1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2018 Intel Corporation 4 * 5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com> 6 * Manasi Navare <manasi.d.navare@intel.com> 7 */ 8 #include <linux/limits.h> 9 10 #include "i915_drv.h" 11 #include "intel_crtc.h" 12 #include "intel_de.h" 13 #include "intel_display_types.h" 14 #include "intel_dsi.h" 15 #include "intel_qp_tables.h" 16 #include "intel_vdsc.h" 17 18 enum ROW_INDEX_BPP { 19 ROW_INDEX_6BPP = 0, 20 ROW_INDEX_8BPP, 21 ROW_INDEX_10BPP, 22 ROW_INDEX_12BPP, 23 ROW_INDEX_15BPP, 24 MAX_ROW_INDEX 25 }; 26 27 enum COLUMN_INDEX_BPC { 28 COLUMN_INDEX_8BPC = 0, 29 COLUMN_INDEX_10BPC, 30 COLUMN_INDEX_12BPC, 31 COLUMN_INDEX_14BPC, 32 COLUMN_INDEX_16BPC, 33 MAX_COLUMN_INDEX 34 }; 35 36 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */ 37 static const u16 rc_buf_thresh[] = { 38 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, 39 7744, 7872, 8000, 8064 40 }; 41 42 struct rc_parameters { 43 u16 initial_xmit_delay; 44 u8 first_line_bpg_offset; 45 u16 initial_offset; 46 u8 flatness_min_qp; 47 u8 flatness_max_qp; 48 u8 rc_quant_incr_limit0; 49 u8 rc_quant_incr_limit1; 50 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; 51 }; 52 53 /* 54 * Selected Rate Control Related Parameter Recommended Values 55 * from DSC_v1.11 spec & C Model release: DSC_model_20161212 56 */ 57 static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { 58 { 59 /* 6BPP/8BPC */ 60 { 768, 15, 6144, 3, 13, 11, 11, { 61 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 }, 62 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 }, 63 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 }, 64 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 } 65 } 66 }, 67 /* 6BPP/10BPC */ 68 { 768, 15, 6144, 7, 17, 15, 15, { 69 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 }, 70 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 }, 71 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 }, 72 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 }, 73 { 17, 18, -12 } 74 } 75 }, 76 /* 6BPP/12BPC */ 77 { 768, 15, 6144, 11, 21, 19, 19, { 78 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 }, 79 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 }, 80 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 }, 81 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 }, 82 { 21, 22, -12 } 83 } 84 }, 85 /* 6BPP/14BPC */ 86 { 768, 15, 6144, 15, 25, 23, 27, { 87 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 }, 88 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 }, 89 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 }, 90 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 }, 91 { 25, 26, -12 } 92 } 93 }, 94 /* 6BPP/16BPC */ 95 { 768, 15, 6144, 19, 29, 27, 27, { 96 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 }, 97 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 }, 98 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 }, 99 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 }, 100 { 29, 30, -12 } 101 } 102 }, 103 }, 104 { 105 /* 8BPP/8BPC */ 106 { 512, 12, 6144, 3, 12, 11, 11, { 107 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, 108 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 109 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, 110 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } 111 } 112 }, 113 /* 8BPP/10BPC */ 114 { 512, 12, 6144, 7, 16, 15, 15, { 115 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, 116 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 117 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, 118 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } 119 } 120 }, 121 /* 8BPP/12BPC */ 122 { 512, 12, 6144, 11, 20, 19, 19, { 123 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, 124 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 125 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, 126 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, 127 { 21, 23, -12 } 128 } 129 }, 130 /* 8BPP/14BPC */ 131 { 512, 12, 6144, 15, 24, 23, 23, { 132 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, 133 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 134 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, 135 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, 136 { 24, 25, -12 } 137 } 138 }, 139 /* 8BPP/16BPC */ 140 { 512, 12, 6144, 19, 28, 27, 27, { 141 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 }, 142 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 143 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 }, 144 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 }, 145 { 28, 29, -12 } 146 } 147 }, 148 }, 149 { 150 /* 10BPP/8BPC */ 151 { 410, 15, 5632, 3, 12, 11, 11, { 152 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, 153 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 154 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 }, 155 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 } 156 } 157 }, 158 /* 10BPP/10BPC */ 159 { 410, 15, 5632, 7, 16, 15, 15, { 160 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, 161 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 162 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 }, 163 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 } 164 } 165 }, 166 /* 10BPP/12BPC */ 167 { 410, 15, 5632, 11, 20, 19, 19, { 168 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, 169 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 170 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 }, 171 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 }, 172 { 19, 20, -12 } 173 } 174 }, 175 /* 10BPP/14BPC */ 176 { 410, 15, 5632, 15, 24, 23, 23, { 177 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 }, 178 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 179 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 }, 180 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 }, 181 { 23, 24, -12 } 182 } 183 }, 184 /* 10BPP/16BPC */ 185 { 410, 15, 5632, 19, 28, 27, 27, { 186 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 }, 187 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 188 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 }, 189 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 }, 190 { 27, 28, -12 } 191 } 192 }, 193 }, 194 { 195 /* 12BPP/8BPC */ 196 { 341, 15, 2048, 3, 12, 11, 11, { 197 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, 198 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 199 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, 200 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } 201 } 202 }, 203 /* 12BPP/10BPC */ 204 { 341, 15, 2048, 7, 16, 15, 15, { 205 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, 206 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 207 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, 208 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } 209 } 210 }, 211 /* 12BPP/12BPC */ 212 { 341, 15, 2048, 11, 20, 19, 19, { 213 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, 214 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 215 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, 216 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, 217 { 21, 23, -12 } 218 } 219 }, 220 /* 12BPP/14BPC */ 221 { 341, 15, 2048, 15, 24, 23, 23, { 222 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 }, 223 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 224 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 }, 225 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 }, 226 { 22, 23, -12 } 227 } 228 }, 229 /* 12BPP/16BPC */ 230 { 341, 15, 2048, 19, 28, 27, 27, { 231 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 }, 232 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 233 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 }, 234 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 }, 235 { 26, 27, -12 } 236 } 237 }, 238 }, 239 { 240 /* 15BPP/8BPC */ 241 { 273, 15, 2048, 3, 12, 11, 11, { 242 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, 243 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 }, 244 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 }, 245 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 } 246 } 247 }, 248 /* 15BPP/10BPC */ 249 { 273, 15, 2048, 7, 16, 15, 15, { 250 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, 251 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 }, 252 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 }, 253 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 } 254 } 255 }, 256 /* 15BPP/12BPC */ 257 { 273, 15, 2048, 11, 20, 19, 19, { 258 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, 259 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 }, 260 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 }, 261 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 }, 262 { 16, 17, -12 } 263 } 264 }, 265 /* 15BPP/14BPC */ 266 { 273, 15, 2048, 15, 24, 23, 23, { 267 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 }, 268 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 }, 269 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 }, 270 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 }, 271 { 20, 21, -12 } 272 } 273 }, 274 /* 15BPP/16BPC */ 275 { 273, 15, 2048, 19, 28, 27, 27, { 276 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 }, 277 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 }, 278 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 }, 279 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 }, 280 { 24, 25, -12 } 281 } 282 } 283 } 284 285 }; 286 287 static int get_row_index_for_rc_params(u16 compressed_bpp) 288 { 289 switch (compressed_bpp) { 290 case 6: 291 return ROW_INDEX_6BPP; 292 case 8: 293 return ROW_INDEX_8BPP; 294 case 10: 295 return ROW_INDEX_10BPP; 296 case 12: 297 return ROW_INDEX_12BPP; 298 case 15: 299 return ROW_INDEX_15BPP; 300 default: 301 return -EINVAL; 302 } 303 } 304 305 static int get_column_index_for_rc_params(u8 bits_per_component) 306 { 307 switch (bits_per_component) { 308 case 8: 309 return COLUMN_INDEX_8BPC; 310 case 10: 311 return COLUMN_INDEX_10BPC; 312 case 12: 313 return COLUMN_INDEX_12BPC; 314 case 14: 315 return COLUMN_INDEX_14BPC; 316 case 16: 317 return COLUMN_INDEX_16BPC; 318 default: 319 return -EINVAL; 320 } 321 } 322 323 static const struct rc_parameters *get_rc_params(u16 compressed_bpp, 324 u8 bits_per_component) 325 { 326 int row_index, column_index; 327 328 row_index = get_row_index_for_rc_params(compressed_bpp); 329 if (row_index < 0) 330 return NULL; 331 332 column_index = get_column_index_for_rc_params(bits_per_component); 333 if (column_index < 0) 334 return NULL; 335 336 return &rc_parameters[row_index][column_index]; 337 } 338 339 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state) 340 { 341 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 342 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 343 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 344 345 if (!INTEL_INFO(i915)->display.has_dsc) 346 return false; 347 348 if (DISPLAY_VER(i915) >= 12) 349 return true; 350 351 if (DISPLAY_VER(i915) >= 11 && cpu_transcoder != TRANSCODER_A) 352 return true; 353 354 return false; 355 } 356 357 static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 358 { 359 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 360 361 if (DISPLAY_VER(i915) >= 12) 362 return true; 363 364 if (cpu_transcoder == TRANSCODER_EDP || 365 cpu_transcoder == TRANSCODER_DSI_0 || 366 cpu_transcoder == TRANSCODER_DSI_1) 367 return false; 368 369 /* There's no pipe A DSC engine on ICL */ 370 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A); 371 372 return true; 373 } 374 375 static void 376 calculate_rc_params(struct rc_parameters *rc, 377 struct drm_dsc_config *vdsc_cfg) 378 { 379 int bpc = vdsc_cfg->bits_per_component; 380 int bpp = vdsc_cfg->bits_per_pixel >> 4; 381 static const s8 ofs_und6[] = { 382 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 383 }; 384 static const s8 ofs_und8[] = { 385 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 386 }; 387 static const s8 ofs_und12[] = { 388 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 389 }; 390 static const s8 ofs_und15[] = { 391 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 392 }; 393 int qp_bpc_modifier = (bpc - 8) * 2; 394 u32 res, buf_i, bpp_i; 395 396 if (vdsc_cfg->slice_height >= 8) 397 rc->first_line_bpg_offset = 398 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100); 399 else 400 rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1); 401 402 /* Our hw supports only 444 modes as of today */ 403 if (bpp >= 12) 404 rc->initial_offset = 2048; 405 else if (bpp >= 10) 406 rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2); 407 else if (bpp >= 8) 408 rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2); 409 else 410 rc->initial_offset = 6144; 411 412 /* initial_xmit_delay = rc_model_size/2/compression_bpp */ 413 rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp); 414 415 rc->flatness_min_qp = 3 + qp_bpc_modifier; 416 rc->flatness_max_qp = 12 + qp_bpc_modifier; 417 418 rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier; 419 rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier; 420 421 bpp_i = (2 * (bpp - 6)); 422 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) { 423 /* Read range_minqp and range_max_qp from qp tables */ 424 rc->rc_range_params[buf_i].range_min_qp = 425 intel_lookup_range_min_qp(bpc, buf_i, bpp_i); 426 rc->rc_range_params[buf_i].range_max_qp = 427 intel_lookup_range_max_qp(bpc, buf_i, bpp_i); 428 429 /* Calculate range_bgp_offset */ 430 if (bpp <= 6) { 431 rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i]; 432 } else if (bpp <= 8) { 433 res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2); 434 rc->rc_range_params[buf_i].range_bpg_offset = 435 ofs_und6[buf_i] + res; 436 } else if (bpp <= 12) { 437 rc->rc_range_params[buf_i].range_bpg_offset = 438 ofs_und8[buf_i]; 439 } else if (bpp <= 15) { 440 res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3); 441 rc->rc_range_params[buf_i].range_bpg_offset = 442 ofs_und12[buf_i] + res; 443 } else { 444 rc->rc_range_params[buf_i].range_bpg_offset = 445 ofs_und15[buf_i]; 446 } 447 } 448 } 449 450 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) 451 { 452 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 453 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 454 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; 455 u16 compressed_bpp = pipe_config->dsc.compressed_bpp; 456 const struct rc_parameters *rc_params; 457 struct rc_parameters *rc = NULL; 458 u8 i = 0; 459 460 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; 461 vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay; 462 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, 463 pipe_config->dsc.slice_count); 464 465 /* Gen 11 does not support YCbCr */ 466 vdsc_cfg->simple_422 = false; 467 /* Gen 11 does not support VBR */ 468 vdsc_cfg->vbr_enable = false; 469 470 /* Gen 11 only supports integral values of bpp */ 471 vdsc_cfg->bits_per_pixel = compressed_bpp << 4; 472 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; 473 474 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { 475 /* 476 * six 0s are appended to the lsb of each threshold value 477 * internally in h/w. 478 * Only 8 bits are allowed for programming RcBufThreshold 479 */ 480 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; 481 } 482 483 /* 484 * For 6bpp, RC Buffer threshold 12 and 13 need a different value 485 * as per C Model 486 */ 487 if (compressed_bpp == 6) { 488 vdsc_cfg->rc_buf_thresh[12] = 0x7C; 489 vdsc_cfg->rc_buf_thresh[13] = 0x7D; 490 } 491 492 /* 493 * From XE_LPD onwards we supports compression bpps in steps of 1 494 * upto uncompressed bpp-1, hence add calculations for all the rc 495 * parameters 496 */ 497 if (DISPLAY_VER(dev_priv) >= 13) { 498 rc = kmalloc(sizeof(*rc), GFP_KERNEL); 499 if (!rc) 500 return -ENOMEM; 501 502 calculate_rc_params(rc, vdsc_cfg); 503 rc_params = rc; 504 } else { 505 rc_params = get_rc_params(compressed_bpp, 506 vdsc_cfg->bits_per_component); 507 if (!rc_params) 508 return -EINVAL; 509 } 510 511 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset; 512 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay; 513 vdsc_cfg->initial_offset = rc_params->initial_offset; 514 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp; 515 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp; 516 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0; 517 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1; 518 519 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 520 vdsc_cfg->rc_range_params[i].range_min_qp = 521 rc_params->rc_range_params[i].range_min_qp; 522 vdsc_cfg->rc_range_params[i].range_max_qp = 523 rc_params->rc_range_params[i].range_max_qp; 524 /* 525 * Range BPG Offset uses 2's complement and is only a 6 bits. So 526 * mask it to get only 6 bits. 527 */ 528 vdsc_cfg->rc_range_params[i].range_bpg_offset = 529 rc_params->rc_range_params[i].range_bpg_offset & 530 DSC_RANGE_BPG_OFFSET_MASK; 531 } 532 533 /* 534 * BitsPerComponent value determines mux_word_size: 535 * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to 536 * 48 bits otherwise 64 537 */ 538 if (vdsc_cfg->bits_per_component <= 10) 539 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; 540 else 541 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; 542 543 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ 544 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / 545 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); 546 547 kfree(rc); 548 549 return 0; 550 } 551 552 enum intel_display_power_domain 553 intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 554 { 555 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 556 enum pipe pipe = crtc->pipe; 557 558 /* 559 * VDSC/joining uses a separate power well, PW2, and requires 560 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases: 561 * 562 * - ICL eDP/DSI transcoder 563 * - Display version 12 (except RKL) pipe A 564 * 565 * For any other pipe, VDSC/joining uses the power well associated with 566 * the pipe in use. Hence another reference on the pipe power domain 567 * will suffice. (Except no VDSC/joining on ICL pipe A.) 568 */ 569 if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A) 570 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 571 else if (is_pipe_dsc(crtc, cpu_transcoder)) 572 return POWER_DOMAIN_PIPE(pipe); 573 else 574 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 575 } 576 577 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) 578 { 579 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 580 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 581 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 582 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 583 enum pipe pipe = crtc->pipe; 584 u32 pps_val = 0; 585 u32 rc_buf_thresh_dword[4]; 586 u32 rc_range_params_dword[8]; 587 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1; 588 int i = 0; 589 590 if (crtc_state->bigjoiner_pipes) 591 num_vdsc_instances *= 2; 592 593 /* Populate PICTURE_PARAMETER_SET_0 registers */ 594 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << 595 DSC_VER_MIN_SHIFT | 596 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | 597 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; 598 if (vdsc_cfg->block_pred_enable) 599 pps_val |= DSC_BLOCK_PREDICTION; 600 if (vdsc_cfg->convert_rgb) 601 pps_val |= DSC_COLOR_SPACE_CONVERSION; 602 if (vdsc_cfg->simple_422) 603 pps_val |= DSC_422_ENABLE; 604 if (vdsc_cfg->vbr_enable) 605 pps_val |= DSC_VBR_ENABLE; 606 drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); 607 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 608 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0, 609 pps_val); 610 /* 611 * If 2 VDSC instances are needed, configure PPS for second 612 * VDSC 613 */ 614 if (crtc_state->dsc.dsc_split) 615 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0, 616 pps_val); 617 } else { 618 intel_de_write(dev_priv, 619 ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), 620 pps_val); 621 if (crtc_state->dsc.dsc_split) 622 intel_de_write(dev_priv, 623 ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), 624 pps_val); 625 } 626 627 /* Populate PICTURE_PARAMETER_SET_1 registers */ 628 pps_val = 0; 629 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); 630 drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); 631 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 632 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1, 633 pps_val); 634 /* 635 * If 2 VDSC instances are needed, configure PPS for second 636 * VDSC 637 */ 638 if (crtc_state->dsc.dsc_split) 639 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1, 640 pps_val); 641 } else { 642 intel_de_write(dev_priv, 643 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), 644 pps_val); 645 if (crtc_state->dsc.dsc_split) 646 intel_de_write(dev_priv, 647 ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), 648 pps_val); 649 } 650 651 /* Populate PICTURE_PARAMETER_SET_2 registers */ 652 pps_val = 0; 653 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | 654 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); 655 drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); 656 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 657 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2, 658 pps_val); 659 /* 660 * If 2 VDSC instances are needed, configure PPS for second 661 * VDSC 662 */ 663 if (crtc_state->dsc.dsc_split) 664 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2, 665 pps_val); 666 } else { 667 intel_de_write(dev_priv, 668 ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), 669 pps_val); 670 if (crtc_state->dsc.dsc_split) 671 intel_de_write(dev_priv, 672 ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), 673 pps_val); 674 } 675 676 /* Populate PICTURE_PARAMETER_SET_3 registers */ 677 pps_val = 0; 678 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | 679 DSC_SLICE_WIDTH(vdsc_cfg->slice_width); 680 drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); 681 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 682 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3, 683 pps_val); 684 /* 685 * If 2 VDSC instances are needed, configure PPS for second 686 * VDSC 687 */ 688 if (crtc_state->dsc.dsc_split) 689 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3, 690 pps_val); 691 } else { 692 intel_de_write(dev_priv, 693 ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), 694 pps_val); 695 if (crtc_state->dsc.dsc_split) 696 intel_de_write(dev_priv, 697 ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), 698 pps_val); 699 } 700 701 /* Populate PICTURE_PARAMETER_SET_4 registers */ 702 pps_val = 0; 703 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | 704 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); 705 drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); 706 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 707 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4, 708 pps_val); 709 /* 710 * If 2 VDSC instances are needed, configure PPS for second 711 * VDSC 712 */ 713 if (crtc_state->dsc.dsc_split) 714 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4, 715 pps_val); 716 } else { 717 intel_de_write(dev_priv, 718 ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), 719 pps_val); 720 if (crtc_state->dsc.dsc_split) 721 intel_de_write(dev_priv, 722 ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), 723 pps_val); 724 } 725 726 /* Populate PICTURE_PARAMETER_SET_5 registers */ 727 pps_val = 0; 728 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | 729 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); 730 drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); 731 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 732 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5, 733 pps_val); 734 /* 735 * If 2 VDSC instances are needed, configure PPS for second 736 * VDSC 737 */ 738 if (crtc_state->dsc.dsc_split) 739 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5, 740 pps_val); 741 } else { 742 intel_de_write(dev_priv, 743 ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), 744 pps_val); 745 if (crtc_state->dsc.dsc_split) 746 intel_de_write(dev_priv, 747 ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), 748 pps_val); 749 } 750 751 /* Populate PICTURE_PARAMETER_SET_6 registers */ 752 pps_val = 0; 753 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | 754 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | 755 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | 756 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); 757 drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); 758 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 759 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6, 760 pps_val); 761 /* 762 * If 2 VDSC instances are needed, configure PPS for second 763 * VDSC 764 */ 765 if (crtc_state->dsc.dsc_split) 766 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6, 767 pps_val); 768 } else { 769 intel_de_write(dev_priv, 770 ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), 771 pps_val); 772 if (crtc_state->dsc.dsc_split) 773 intel_de_write(dev_priv, 774 ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), 775 pps_val); 776 } 777 778 /* Populate PICTURE_PARAMETER_SET_7 registers */ 779 pps_val = 0; 780 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | 781 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); 782 drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); 783 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 784 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7, 785 pps_val); 786 /* 787 * If 2 VDSC instances are needed, configure PPS for second 788 * VDSC 789 */ 790 if (crtc_state->dsc.dsc_split) 791 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7, 792 pps_val); 793 } else { 794 intel_de_write(dev_priv, 795 ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), 796 pps_val); 797 if (crtc_state->dsc.dsc_split) 798 intel_de_write(dev_priv, 799 ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), 800 pps_val); 801 } 802 803 /* Populate PICTURE_PARAMETER_SET_8 registers */ 804 pps_val = 0; 805 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | 806 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); 807 drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); 808 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 809 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8, 810 pps_val); 811 /* 812 * If 2 VDSC instances are needed, configure PPS for second 813 * VDSC 814 */ 815 if (crtc_state->dsc.dsc_split) 816 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8, 817 pps_val); 818 } else { 819 intel_de_write(dev_priv, 820 ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), 821 pps_val); 822 if (crtc_state->dsc.dsc_split) 823 intel_de_write(dev_priv, 824 ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), 825 pps_val); 826 } 827 828 /* Populate PICTURE_PARAMETER_SET_9 registers */ 829 pps_val = 0; 830 pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | 831 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); 832 drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); 833 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 834 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9, 835 pps_val); 836 /* 837 * If 2 VDSC instances are needed, configure PPS for second 838 * VDSC 839 */ 840 if (crtc_state->dsc.dsc_split) 841 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9, 842 pps_val); 843 } else { 844 intel_de_write(dev_priv, 845 ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), 846 pps_val); 847 if (crtc_state->dsc.dsc_split) 848 intel_de_write(dev_priv, 849 ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), 850 pps_val); 851 } 852 853 /* Populate PICTURE_PARAMETER_SET_10 registers */ 854 pps_val = 0; 855 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | 856 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | 857 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | 858 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); 859 drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); 860 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 861 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10, 862 pps_val); 863 /* 864 * If 2 VDSC instances are needed, configure PPS for second 865 * VDSC 866 */ 867 if (crtc_state->dsc.dsc_split) 868 intel_de_write(dev_priv, 869 DSCC_PICTURE_PARAMETER_SET_10, pps_val); 870 } else { 871 intel_de_write(dev_priv, 872 ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), 873 pps_val); 874 if (crtc_state->dsc.dsc_split) 875 intel_de_write(dev_priv, 876 ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), 877 pps_val); 878 } 879 880 /* Populate Picture parameter set 16 */ 881 pps_val = 0; 882 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | 883 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / 884 vdsc_cfg->slice_width) | 885 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / 886 vdsc_cfg->slice_height); 887 drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val); 888 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 889 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16, 890 pps_val); 891 /* 892 * If 2 VDSC instances are needed, configure PPS for second 893 * VDSC 894 */ 895 if (crtc_state->dsc.dsc_split) 896 intel_de_write(dev_priv, 897 DSCC_PICTURE_PARAMETER_SET_16, pps_val); 898 } else { 899 intel_de_write(dev_priv, 900 ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), 901 pps_val); 902 if (crtc_state->dsc.dsc_split) 903 intel_de_write(dev_priv, 904 ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), 905 pps_val); 906 } 907 908 /* Populate the RC_BUF_THRESH registers */ 909 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); 910 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { 911 rc_buf_thresh_dword[i / 4] |= 912 (u32)(vdsc_cfg->rc_buf_thresh[i] << 913 BITS_PER_BYTE * (i % 4)); 914 drm_dbg_kms(&dev_priv->drm, "RC_BUF_THRESH_%d = 0x%08x\n", i, 915 rc_buf_thresh_dword[i / 4]); 916 } 917 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 918 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0, 919 rc_buf_thresh_dword[0]); 920 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW, 921 rc_buf_thresh_dword[1]); 922 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1, 923 rc_buf_thresh_dword[2]); 924 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW, 925 rc_buf_thresh_dword[3]); 926 if (crtc_state->dsc.dsc_split) { 927 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0, 928 rc_buf_thresh_dword[0]); 929 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW, 930 rc_buf_thresh_dword[1]); 931 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1, 932 rc_buf_thresh_dword[2]); 933 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW, 934 rc_buf_thresh_dword[3]); 935 } 936 } else { 937 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe), 938 rc_buf_thresh_dword[0]); 939 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), 940 rc_buf_thresh_dword[1]); 941 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe), 942 rc_buf_thresh_dword[2]); 943 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), 944 rc_buf_thresh_dword[3]); 945 if (crtc_state->dsc.dsc_split) { 946 intel_de_write(dev_priv, 947 ICL_DSC1_RC_BUF_THRESH_0(pipe), 948 rc_buf_thresh_dword[0]); 949 intel_de_write(dev_priv, 950 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), 951 rc_buf_thresh_dword[1]); 952 intel_de_write(dev_priv, 953 ICL_DSC1_RC_BUF_THRESH_1(pipe), 954 rc_buf_thresh_dword[2]); 955 intel_de_write(dev_priv, 956 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), 957 rc_buf_thresh_dword[3]); 958 } 959 } 960 961 /* Populate the RC_RANGE_PARAMETERS registers */ 962 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); 963 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 964 rc_range_params_dword[i / 2] |= 965 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << 966 RC_BPG_OFFSET_SHIFT) | 967 (vdsc_cfg->rc_range_params[i].range_max_qp << 968 RC_MAX_QP_SHIFT) | 969 (vdsc_cfg->rc_range_params[i].range_min_qp << 970 RC_MIN_QP_SHIFT)) << 16 * (i % 2)); 971 drm_dbg_kms(&dev_priv->drm, "RC_RANGE_PARAM_%d = 0x%08x\n", i, 972 rc_range_params_dword[i / 2]); 973 } 974 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 975 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0, 976 rc_range_params_dword[0]); 977 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW, 978 rc_range_params_dword[1]); 979 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1, 980 rc_range_params_dword[2]); 981 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW, 982 rc_range_params_dword[3]); 983 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2, 984 rc_range_params_dword[4]); 985 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW, 986 rc_range_params_dword[5]); 987 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3, 988 rc_range_params_dword[6]); 989 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW, 990 rc_range_params_dword[7]); 991 if (crtc_state->dsc.dsc_split) { 992 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0, 993 rc_range_params_dword[0]); 994 intel_de_write(dev_priv, 995 DSCC_RC_RANGE_PARAMETERS_0_UDW, 996 rc_range_params_dword[1]); 997 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1, 998 rc_range_params_dword[2]); 999 intel_de_write(dev_priv, 1000 DSCC_RC_RANGE_PARAMETERS_1_UDW, 1001 rc_range_params_dword[3]); 1002 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2, 1003 rc_range_params_dword[4]); 1004 intel_de_write(dev_priv, 1005 DSCC_RC_RANGE_PARAMETERS_2_UDW, 1006 rc_range_params_dword[5]); 1007 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3, 1008 rc_range_params_dword[6]); 1009 intel_de_write(dev_priv, 1010 DSCC_RC_RANGE_PARAMETERS_3_UDW, 1011 rc_range_params_dword[7]); 1012 } 1013 } else { 1014 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), 1015 rc_range_params_dword[0]); 1016 intel_de_write(dev_priv, 1017 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), 1018 rc_range_params_dword[1]); 1019 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), 1020 rc_range_params_dword[2]); 1021 intel_de_write(dev_priv, 1022 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), 1023 rc_range_params_dword[3]); 1024 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), 1025 rc_range_params_dword[4]); 1026 intel_de_write(dev_priv, 1027 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), 1028 rc_range_params_dword[5]); 1029 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), 1030 rc_range_params_dword[6]); 1031 intel_de_write(dev_priv, 1032 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), 1033 rc_range_params_dword[7]); 1034 if (crtc_state->dsc.dsc_split) { 1035 intel_de_write(dev_priv, 1036 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), 1037 rc_range_params_dword[0]); 1038 intel_de_write(dev_priv, 1039 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), 1040 rc_range_params_dword[1]); 1041 intel_de_write(dev_priv, 1042 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), 1043 rc_range_params_dword[2]); 1044 intel_de_write(dev_priv, 1045 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), 1046 rc_range_params_dword[3]); 1047 intel_de_write(dev_priv, 1048 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), 1049 rc_range_params_dword[4]); 1050 intel_de_write(dev_priv, 1051 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), 1052 rc_range_params_dword[5]); 1053 intel_de_write(dev_priv, 1054 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), 1055 rc_range_params_dword[6]); 1056 intel_de_write(dev_priv, 1057 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), 1058 rc_range_params_dword[7]); 1059 } 1060 } 1061 } 1062 1063 void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, 1064 const struct intel_crtc_state *crtc_state) 1065 { 1066 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1067 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1068 struct mipi_dsi_device *dsi; 1069 struct drm_dsc_picture_parameter_set pps; 1070 enum port port; 1071 1072 if (!crtc_state->dsc.compression_enable) 1073 return; 1074 1075 drm_dsc_pps_payload_pack(&pps, vdsc_cfg); 1076 1077 for_each_dsi_port(port, intel_dsi->ports) { 1078 dsi = intel_dsi->dsi_hosts[port]->device; 1079 1080 mipi_dsi_picture_parameter_set(dsi, &pps); 1081 mipi_dsi_compression_mode(dsi, true); 1082 } 1083 } 1084 1085 void intel_dsc_dp_pps_write(struct intel_encoder *encoder, 1086 const struct intel_crtc_state *crtc_state) 1087 { 1088 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1089 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1090 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; 1091 1092 if (!crtc_state->dsc.compression_enable) 1093 return; 1094 1095 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ 1096 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header); 1097 1098 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ 1099 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg); 1100 1101 dig_port->write_infoframe(encoder, crtc_state, 1102 DP_SDP_PPS, &dp_dsc_pps_sdp, 1103 sizeof(dp_dsc_pps_sdp)); 1104 } 1105 1106 static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 1107 { 1108 return is_pipe_dsc(crtc, cpu_transcoder) ? 1109 ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1; 1110 } 1111 1112 static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 1113 { 1114 return is_pipe_dsc(crtc, cpu_transcoder) ? 1115 ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2; 1116 } 1117 1118 void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state) 1119 { 1120 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1121 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1122 u32 dss_ctl1_val = 0; 1123 1124 if (crtc_state->bigjoiner_pipes && !crtc_state->dsc.compression_enable) { 1125 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1126 dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE; 1127 else 1128 dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER; 1129 1130 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); 1131 } 1132 } 1133 1134 void intel_dsc_enable(const struct intel_crtc_state *crtc_state) 1135 { 1136 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1137 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1138 u32 dss_ctl1_val = 0; 1139 u32 dss_ctl2_val = 0; 1140 1141 if (!crtc_state->dsc.compression_enable) 1142 return; 1143 1144 intel_dsc_pps_configure(crtc_state); 1145 1146 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; 1147 if (crtc_state->dsc.dsc_split) { 1148 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; 1149 dss_ctl1_val |= JOINER_ENABLE; 1150 } 1151 if (crtc_state->bigjoiner_pipes) { 1152 dss_ctl1_val |= BIG_JOINER_ENABLE; 1153 if (!intel_crtc_is_bigjoiner_slave(crtc_state)) 1154 dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE; 1155 } 1156 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); 1157 intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val); 1158 } 1159 1160 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) 1161 { 1162 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1163 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1164 1165 /* Disable only if either of them is enabled */ 1166 if (old_crtc_state->dsc.compression_enable || 1167 old_crtc_state->bigjoiner_pipes) { 1168 intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0); 1169 intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0); 1170 } 1171 } 1172 1173 void intel_dsc_get_config(struct intel_crtc_state *crtc_state) 1174 { 1175 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1176 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1177 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1178 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1179 enum pipe pipe = crtc->pipe; 1180 enum intel_display_power_domain power_domain; 1181 intel_wakeref_t wakeref; 1182 u32 dss_ctl1, dss_ctl2, val; 1183 1184 if (!intel_dsc_source_support(crtc_state)) 1185 return; 1186 1187 power_domain = intel_dsc_power_domain(crtc, cpu_transcoder); 1188 1189 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 1190 if (!wakeref) 1191 return; 1192 1193 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder)); 1194 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder)); 1195 1196 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; 1197 if (!crtc_state->dsc.compression_enable) 1198 goto out; 1199 1200 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && 1201 (dss_ctl1 & JOINER_ENABLE); 1202 1203 /* FIXME: add more state readout as needed */ 1204 1205 /* PPS1 */ 1206 if (!is_pipe_dsc(crtc, cpu_transcoder)) 1207 val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1); 1208 else 1209 val = intel_de_read(dev_priv, 1210 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); 1211 vdsc_cfg->bits_per_pixel = val; 1212 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; 1213 out: 1214 intel_display_power_put(dev_priv, power_domain, wakeref); 1215 } 1216