1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2018 Intel Corporation 4 * 5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com> 6 * Manasi Navare <manasi.d.navare@intel.com> 7 */ 8 9 #include "i915_drv.h" 10 #include "intel_display_types.h" 11 #include "intel_dsi.h" 12 #include "intel_vdsc.h" 13 14 enum ROW_INDEX_BPP { 15 ROW_INDEX_6BPP = 0, 16 ROW_INDEX_8BPP, 17 ROW_INDEX_10BPP, 18 ROW_INDEX_12BPP, 19 ROW_INDEX_15BPP, 20 MAX_ROW_INDEX 21 }; 22 23 enum COLUMN_INDEX_BPC { 24 COLUMN_INDEX_8BPC = 0, 25 COLUMN_INDEX_10BPC, 26 COLUMN_INDEX_12BPC, 27 COLUMN_INDEX_14BPC, 28 COLUMN_INDEX_16BPC, 29 MAX_COLUMN_INDEX 30 }; 31 32 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */ 33 static const u16 rc_buf_thresh[] = { 34 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, 35 7744, 7872, 8000, 8064 36 }; 37 38 struct rc_parameters { 39 u16 initial_xmit_delay; 40 u8 first_line_bpg_offset; 41 u16 initial_offset; 42 u8 flatness_min_qp; 43 u8 flatness_max_qp; 44 u8 rc_quant_incr_limit0; 45 u8 rc_quant_incr_limit1; 46 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; 47 }; 48 49 /* 50 * Selected Rate Control Related Parameter Recommended Values 51 * from DSC_v1.11 spec & C Model release: DSC_model_20161212 52 */ 53 static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { 54 { 55 /* 6BPP/8BPC */ 56 { 768, 15, 6144, 3, 13, 11, 11, { 57 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 }, 58 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 }, 59 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 }, 60 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 } 61 } 62 }, 63 /* 6BPP/10BPC */ 64 { 768, 15, 6144, 7, 17, 15, 15, { 65 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 }, 66 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 }, 67 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 }, 68 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 }, 69 { 17, 18, -12 } 70 } 71 }, 72 /* 6BPP/12BPC */ 73 { 768, 15, 6144, 11, 21, 19, 19, { 74 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 }, 75 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 }, 76 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 }, 77 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 }, 78 { 21, 22, -12 } 79 } 80 }, 81 /* 6BPP/14BPC */ 82 { 768, 15, 6144, 15, 25, 23, 27, { 83 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 }, 84 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 }, 85 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 }, 86 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 }, 87 { 25, 26, -12 } 88 } 89 }, 90 /* 6BPP/16BPC */ 91 { 768, 15, 6144, 19, 29, 27, 27, { 92 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 }, 93 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 }, 94 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 }, 95 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 }, 96 { 29, 30, -12 } 97 } 98 }, 99 }, 100 { 101 /* 8BPP/8BPC */ 102 { 512, 12, 6144, 3, 12, 11, 11, { 103 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, 104 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 105 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, 106 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } 107 } 108 }, 109 /* 8BPP/10BPC */ 110 { 512, 12, 6144, 7, 16, 15, 15, { 111 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, 112 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 113 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, 114 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } 115 } 116 }, 117 /* 8BPP/12BPC */ 118 { 512, 12, 6144, 11, 20, 19, 19, { 119 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, 120 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 121 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, 122 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, 123 { 21, 23, -12 } 124 } 125 }, 126 /* 8BPP/14BPC */ 127 { 512, 12, 6144, 15, 24, 23, 23, { 128 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, 129 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 130 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, 131 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, 132 { 24, 25, -12 } 133 } 134 }, 135 /* 8BPP/16BPC */ 136 { 512, 12, 6144, 19, 28, 27, 27, { 137 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 }, 138 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 139 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 }, 140 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 }, 141 { 28, 29, -12 } 142 } 143 }, 144 }, 145 { 146 /* 10BPP/8BPC */ 147 { 410, 15, 5632, 3, 12, 11, 11, { 148 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, 149 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 150 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 }, 151 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 } 152 } 153 }, 154 /* 10BPP/10BPC */ 155 { 410, 15, 5632, 7, 16, 15, 15, { 156 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, 157 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 158 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 }, 159 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 } 160 } 161 }, 162 /* 10BPP/12BPC */ 163 { 410, 15, 5632, 11, 20, 19, 19, { 164 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, 165 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 166 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 }, 167 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 }, 168 { 19, 20, -12 } 169 } 170 }, 171 /* 10BPP/14BPC */ 172 { 410, 15, 5632, 15, 24, 23, 23, { 173 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 }, 174 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 175 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 }, 176 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 }, 177 { 23, 24, -12 } 178 } 179 }, 180 /* 10BPP/16BPC */ 181 { 410, 15, 5632, 19, 28, 27, 27, { 182 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 }, 183 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 184 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 }, 185 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 }, 186 { 27, 28, -12 } 187 } 188 }, 189 }, 190 { 191 /* 12BPP/8BPC */ 192 { 341, 15, 2048, 3, 12, 11, 11, { 193 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, 194 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 195 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, 196 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } 197 } 198 }, 199 /* 12BPP/10BPC */ 200 { 341, 15, 2048, 7, 16, 15, 15, { 201 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, 202 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 203 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, 204 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } 205 } 206 }, 207 /* 12BPP/12BPC */ 208 { 341, 15, 2048, 11, 20, 19, 19, { 209 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, 210 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 211 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, 212 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, 213 { 21, 23, -12 } 214 } 215 }, 216 /* 12BPP/14BPC */ 217 { 341, 15, 2048, 15, 24, 23, 23, { 218 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 }, 219 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 220 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 }, 221 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 }, 222 { 22, 23, -12 } 223 } 224 }, 225 /* 12BPP/16BPC */ 226 { 341, 15, 2048, 19, 28, 27, 27, { 227 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 }, 228 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 229 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 }, 230 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 }, 231 { 26, 27, -12 } 232 } 233 }, 234 }, 235 { 236 /* 15BPP/8BPC */ 237 { 273, 15, 2048, 3, 12, 11, 11, { 238 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, 239 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 }, 240 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 }, 241 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 } 242 } 243 }, 244 /* 15BPP/10BPC */ 245 { 273, 15, 2048, 7, 16, 15, 15, { 246 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, 247 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 }, 248 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 }, 249 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 } 250 } 251 }, 252 /* 15BPP/12BPC */ 253 { 273, 15, 2048, 11, 20, 19, 19, { 254 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, 255 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 }, 256 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 }, 257 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 }, 258 { 16, 17, -12 } 259 } 260 }, 261 /* 15BPP/14BPC */ 262 { 273, 15, 2048, 15, 24, 23, 23, { 263 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 }, 264 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 }, 265 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 }, 266 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 }, 267 { 20, 21, -12 } 268 } 269 }, 270 /* 15BPP/16BPC */ 271 { 273, 15, 2048, 19, 28, 27, 27, { 272 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 }, 273 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 }, 274 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 }, 275 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 }, 276 { 24, 25, -12 } 277 } 278 } 279 } 280 281 }; 282 283 static int get_row_index_for_rc_params(u16 compressed_bpp) 284 { 285 switch (compressed_bpp) { 286 case 6: 287 return ROW_INDEX_6BPP; 288 case 8: 289 return ROW_INDEX_8BPP; 290 case 10: 291 return ROW_INDEX_10BPP; 292 case 12: 293 return ROW_INDEX_12BPP; 294 case 15: 295 return ROW_INDEX_15BPP; 296 default: 297 return -EINVAL; 298 } 299 } 300 301 static int get_column_index_for_rc_params(u8 bits_per_component) 302 { 303 switch (bits_per_component) { 304 case 8: 305 return COLUMN_INDEX_8BPC; 306 case 10: 307 return COLUMN_INDEX_10BPC; 308 case 12: 309 return COLUMN_INDEX_12BPC; 310 case 14: 311 return COLUMN_INDEX_14BPC; 312 case 16: 313 return COLUMN_INDEX_16BPC; 314 default: 315 return -EINVAL; 316 } 317 } 318 319 static const struct rc_parameters *get_rc_params(u16 compressed_bpp, 320 u8 bits_per_component) 321 { 322 int row_index, column_index; 323 324 row_index = get_row_index_for_rc_params(compressed_bpp); 325 if (row_index < 0) 326 return NULL; 327 328 column_index = get_column_index_for_rc_params(bits_per_component); 329 if (column_index < 0) 330 return NULL; 331 332 return &rc_parameters[row_index][column_index]; 333 } 334 335 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state) 336 { 337 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 338 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 339 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 340 enum pipe pipe = crtc->pipe; 341 342 if (!INTEL_INFO(i915)->display.has_dsc) 343 return false; 344 345 /* On TGL, DSC is supported on all Pipes */ 346 if (DISPLAY_VER(i915) >= 12) 347 return true; 348 349 if ((DISPLAY_VER(i915) >= 11 || IS_CANNONLAKE(i915)) && (pipe != PIPE_A || (cpu_transcoder == TRANSCODER_EDP || cpu_transcoder == TRANSCODER_DSI_0 || cpu_transcoder == TRANSCODER_DSI_1))) 350 return true; 351 352 return false; 353 } 354 355 static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state) 356 { 357 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 358 const struct drm_i915_private *i915 = to_i915(crtc->base.dev); 359 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 360 361 if (DISPLAY_VER(i915) >= 12) 362 return true; 363 364 if (cpu_transcoder == TRANSCODER_EDP || 365 cpu_transcoder == TRANSCODER_DSI_0 || 366 cpu_transcoder == TRANSCODER_DSI_1) 367 return false; 368 369 /* There's no pipe A DSC engine on ICL */ 370 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A); 371 372 return true; 373 } 374 375 int intel_dsc_compute_params(struct intel_encoder *encoder, 376 struct intel_crtc_state *pipe_config) 377 { 378 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; 379 u16 compressed_bpp = pipe_config->dsc.compressed_bpp; 380 const struct rc_parameters *rc_params; 381 u8 i = 0; 382 383 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; 384 vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay; 385 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, 386 pipe_config->dsc.slice_count); 387 388 /* Gen 11 does not support YCbCr */ 389 vdsc_cfg->simple_422 = false; 390 /* Gen 11 does not support VBR */ 391 vdsc_cfg->vbr_enable = false; 392 393 /* Gen 11 only supports integral values of bpp */ 394 vdsc_cfg->bits_per_pixel = compressed_bpp << 4; 395 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; 396 397 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { 398 /* 399 * six 0s are appended to the lsb of each threshold value 400 * internally in h/w. 401 * Only 8 bits are allowed for programming RcBufThreshold 402 */ 403 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; 404 } 405 406 /* 407 * For 6bpp, RC Buffer threshold 12 and 13 need a different value 408 * as per C Model 409 */ 410 if (compressed_bpp == 6) { 411 vdsc_cfg->rc_buf_thresh[12] = 0x7C; 412 vdsc_cfg->rc_buf_thresh[13] = 0x7D; 413 } 414 415 rc_params = get_rc_params(compressed_bpp, vdsc_cfg->bits_per_component); 416 if (!rc_params) 417 return -EINVAL; 418 419 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset; 420 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay; 421 vdsc_cfg->initial_offset = rc_params->initial_offset; 422 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp; 423 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp; 424 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0; 425 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1; 426 427 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 428 vdsc_cfg->rc_range_params[i].range_min_qp = 429 rc_params->rc_range_params[i].range_min_qp; 430 vdsc_cfg->rc_range_params[i].range_max_qp = 431 rc_params->rc_range_params[i].range_max_qp; 432 /* 433 * Range BPG Offset uses 2's complement and is only a 6 bits. So 434 * mask it to get only 6 bits. 435 */ 436 vdsc_cfg->rc_range_params[i].range_bpg_offset = 437 rc_params->rc_range_params[i].range_bpg_offset & 438 DSC_RANGE_BPG_OFFSET_MASK; 439 } 440 441 /* 442 * BitsPerComponent value determines mux_word_size: 443 * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits 444 * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to 445 * 48 bits 446 */ 447 if (vdsc_cfg->bits_per_component == 8 || 448 vdsc_cfg->bits_per_component == 10) 449 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; 450 else if (vdsc_cfg->bits_per_component == 12) 451 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; 452 453 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ 454 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / 455 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); 456 457 return 0; 458 } 459 460 enum intel_display_power_domain 461 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state) 462 { 463 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 464 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 465 enum pipe pipe = crtc->pipe; 466 467 /* 468 * VDSC/joining uses a separate power well, PW2, and requires 469 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases: 470 * 471 * - ICL eDP/DSI transcoder 472 * - Gen12+ (except RKL) pipe A 473 * 474 * For any other pipe, VDSC/joining uses the power well associated with 475 * the pipe in use. Hence another reference on the pipe power domain 476 * will suffice. (Except no VDSC/joining on ICL pipe A.) 477 */ 478 if (DISPLAY_VER(i915) >= 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A) 479 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 480 else if (is_pipe_dsc(crtc_state)) 481 return POWER_DOMAIN_PIPE(pipe); 482 else 483 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 484 } 485 486 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) 487 { 488 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 489 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 490 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 491 enum pipe pipe = crtc->pipe; 492 u32 pps_val = 0; 493 u32 rc_buf_thresh_dword[4]; 494 u32 rc_range_params_dword[8]; 495 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1; 496 int i = 0; 497 498 if (crtc_state->bigjoiner) 499 num_vdsc_instances *= 2; 500 501 /* Populate PICTURE_PARAMETER_SET_0 registers */ 502 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << 503 DSC_VER_MIN_SHIFT | 504 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | 505 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; 506 if (vdsc_cfg->block_pred_enable) 507 pps_val |= DSC_BLOCK_PREDICTION; 508 if (vdsc_cfg->convert_rgb) 509 pps_val |= DSC_COLOR_SPACE_CONVERSION; 510 if (vdsc_cfg->simple_422) 511 pps_val |= DSC_422_ENABLE; 512 if (vdsc_cfg->vbr_enable) 513 pps_val |= DSC_VBR_ENABLE; 514 drm_info(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); 515 if (!is_pipe_dsc(crtc_state)) { 516 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0, 517 pps_val); 518 /* 519 * If 2 VDSC instances are needed, configure PPS for second 520 * VDSC 521 */ 522 if (crtc_state->dsc.dsc_split) 523 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0, 524 pps_val); 525 } else { 526 intel_de_write(dev_priv, 527 ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), 528 pps_val); 529 if (crtc_state->dsc.dsc_split) 530 intel_de_write(dev_priv, 531 ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), 532 pps_val); 533 } 534 535 /* Populate PICTURE_PARAMETER_SET_1 registers */ 536 pps_val = 0; 537 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); 538 drm_info(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); 539 if (!is_pipe_dsc(crtc_state)) { 540 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1, 541 pps_val); 542 /* 543 * If 2 VDSC instances are needed, configure PPS for second 544 * VDSC 545 */ 546 if (crtc_state->dsc.dsc_split) 547 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1, 548 pps_val); 549 } else { 550 intel_de_write(dev_priv, 551 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), 552 pps_val); 553 if (crtc_state->dsc.dsc_split) 554 intel_de_write(dev_priv, 555 ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), 556 pps_val); 557 } 558 559 /* Populate PICTURE_PARAMETER_SET_2 registers */ 560 pps_val = 0; 561 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | 562 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); 563 drm_info(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); 564 if (!is_pipe_dsc(crtc_state)) { 565 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2, 566 pps_val); 567 /* 568 * If 2 VDSC instances are needed, configure PPS for second 569 * VDSC 570 */ 571 if (crtc_state->dsc.dsc_split) 572 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2, 573 pps_val); 574 } else { 575 intel_de_write(dev_priv, 576 ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), 577 pps_val); 578 if (crtc_state->dsc.dsc_split) 579 intel_de_write(dev_priv, 580 ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), 581 pps_val); 582 } 583 584 /* Populate PICTURE_PARAMETER_SET_3 registers */ 585 pps_val = 0; 586 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | 587 DSC_SLICE_WIDTH(vdsc_cfg->slice_width); 588 drm_info(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); 589 if (!is_pipe_dsc(crtc_state)) { 590 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3, 591 pps_val); 592 /* 593 * If 2 VDSC instances are needed, configure PPS for second 594 * VDSC 595 */ 596 if (crtc_state->dsc.dsc_split) 597 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3, 598 pps_val); 599 } else { 600 intel_de_write(dev_priv, 601 ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), 602 pps_val); 603 if (crtc_state->dsc.dsc_split) 604 intel_de_write(dev_priv, 605 ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), 606 pps_val); 607 } 608 609 /* Populate PICTURE_PARAMETER_SET_4 registers */ 610 pps_val = 0; 611 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | 612 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); 613 drm_info(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); 614 if (!is_pipe_dsc(crtc_state)) { 615 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4, 616 pps_val); 617 /* 618 * If 2 VDSC instances are needed, configure PPS for second 619 * VDSC 620 */ 621 if (crtc_state->dsc.dsc_split) 622 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4, 623 pps_val); 624 } else { 625 intel_de_write(dev_priv, 626 ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), 627 pps_val); 628 if (crtc_state->dsc.dsc_split) 629 intel_de_write(dev_priv, 630 ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), 631 pps_val); 632 } 633 634 /* Populate PICTURE_PARAMETER_SET_5 registers */ 635 pps_val = 0; 636 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | 637 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); 638 drm_info(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); 639 if (!is_pipe_dsc(crtc_state)) { 640 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5, 641 pps_val); 642 /* 643 * If 2 VDSC instances are needed, configure PPS for second 644 * VDSC 645 */ 646 if (crtc_state->dsc.dsc_split) 647 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5, 648 pps_val); 649 } else { 650 intel_de_write(dev_priv, 651 ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), 652 pps_val); 653 if (crtc_state->dsc.dsc_split) 654 intel_de_write(dev_priv, 655 ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), 656 pps_val); 657 } 658 659 /* Populate PICTURE_PARAMETER_SET_6 registers */ 660 pps_val = 0; 661 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | 662 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | 663 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | 664 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); 665 drm_info(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); 666 if (!is_pipe_dsc(crtc_state)) { 667 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6, 668 pps_val); 669 /* 670 * If 2 VDSC instances are needed, configure PPS for second 671 * VDSC 672 */ 673 if (crtc_state->dsc.dsc_split) 674 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6, 675 pps_val); 676 } else { 677 intel_de_write(dev_priv, 678 ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), 679 pps_val); 680 if (crtc_state->dsc.dsc_split) 681 intel_de_write(dev_priv, 682 ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), 683 pps_val); 684 } 685 686 /* Populate PICTURE_PARAMETER_SET_7 registers */ 687 pps_val = 0; 688 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | 689 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); 690 drm_info(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); 691 if (!is_pipe_dsc(crtc_state)) { 692 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7, 693 pps_val); 694 /* 695 * If 2 VDSC instances are needed, configure PPS for second 696 * VDSC 697 */ 698 if (crtc_state->dsc.dsc_split) 699 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7, 700 pps_val); 701 } else { 702 intel_de_write(dev_priv, 703 ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), 704 pps_val); 705 if (crtc_state->dsc.dsc_split) 706 intel_de_write(dev_priv, 707 ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), 708 pps_val); 709 } 710 711 /* Populate PICTURE_PARAMETER_SET_8 registers */ 712 pps_val = 0; 713 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | 714 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); 715 drm_info(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); 716 if (!is_pipe_dsc(crtc_state)) { 717 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8, 718 pps_val); 719 /* 720 * If 2 VDSC instances are needed, configure PPS for second 721 * VDSC 722 */ 723 if (crtc_state->dsc.dsc_split) 724 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8, 725 pps_val); 726 } else { 727 intel_de_write(dev_priv, 728 ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), 729 pps_val); 730 if (crtc_state->dsc.dsc_split) 731 intel_de_write(dev_priv, 732 ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), 733 pps_val); 734 } 735 736 /* Populate PICTURE_PARAMETER_SET_9 registers */ 737 pps_val = 0; 738 pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | 739 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); 740 drm_info(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); 741 if (!is_pipe_dsc(crtc_state)) { 742 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9, 743 pps_val); 744 /* 745 * If 2 VDSC instances are needed, configure PPS for second 746 * VDSC 747 */ 748 if (crtc_state->dsc.dsc_split) 749 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9, 750 pps_val); 751 } else { 752 intel_de_write(dev_priv, 753 ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), 754 pps_val); 755 if (crtc_state->dsc.dsc_split) 756 intel_de_write(dev_priv, 757 ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), 758 pps_val); 759 } 760 761 /* Populate PICTURE_PARAMETER_SET_10 registers */ 762 pps_val = 0; 763 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | 764 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | 765 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | 766 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); 767 drm_info(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); 768 if (!is_pipe_dsc(crtc_state)) { 769 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10, 770 pps_val); 771 /* 772 * If 2 VDSC instances are needed, configure PPS for second 773 * VDSC 774 */ 775 if (crtc_state->dsc.dsc_split) 776 intel_de_write(dev_priv, 777 DSCC_PICTURE_PARAMETER_SET_10, pps_val); 778 } else { 779 intel_de_write(dev_priv, 780 ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), 781 pps_val); 782 if (crtc_state->dsc.dsc_split) 783 intel_de_write(dev_priv, 784 ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), 785 pps_val); 786 } 787 788 /* Populate Picture parameter set 16 */ 789 pps_val = 0; 790 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | 791 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / 792 vdsc_cfg->slice_width) | 793 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / 794 vdsc_cfg->slice_height); 795 drm_info(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val); 796 if (!is_pipe_dsc(crtc_state)) { 797 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16, 798 pps_val); 799 /* 800 * If 2 VDSC instances are needed, configure PPS for second 801 * VDSC 802 */ 803 if (crtc_state->dsc.dsc_split) 804 intel_de_write(dev_priv, 805 DSCC_PICTURE_PARAMETER_SET_16, pps_val); 806 } else { 807 intel_de_write(dev_priv, 808 ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), 809 pps_val); 810 if (crtc_state->dsc.dsc_split) 811 intel_de_write(dev_priv, 812 ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), 813 pps_val); 814 } 815 816 /* Populate the RC_BUF_THRESH registers */ 817 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); 818 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { 819 rc_buf_thresh_dword[i / 4] |= 820 (u32)(vdsc_cfg->rc_buf_thresh[i] << 821 BITS_PER_BYTE * (i % 4)); 822 drm_info(&dev_priv->drm, " RC_BUF_THRESH%d = 0x%08x\n", i, 823 rc_buf_thresh_dword[i / 4]); 824 } 825 if (!is_pipe_dsc(crtc_state)) { 826 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0, 827 rc_buf_thresh_dword[0]); 828 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW, 829 rc_buf_thresh_dword[1]); 830 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1, 831 rc_buf_thresh_dword[2]); 832 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW, 833 rc_buf_thresh_dword[3]); 834 if (crtc_state->dsc.dsc_split) { 835 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0, 836 rc_buf_thresh_dword[0]); 837 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW, 838 rc_buf_thresh_dword[1]); 839 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1, 840 rc_buf_thresh_dword[2]); 841 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW, 842 rc_buf_thresh_dword[3]); 843 } 844 } else { 845 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe), 846 rc_buf_thresh_dword[0]); 847 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), 848 rc_buf_thresh_dword[1]); 849 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe), 850 rc_buf_thresh_dword[2]); 851 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), 852 rc_buf_thresh_dword[3]); 853 if (crtc_state->dsc.dsc_split) { 854 intel_de_write(dev_priv, 855 ICL_DSC1_RC_BUF_THRESH_0(pipe), 856 rc_buf_thresh_dword[0]); 857 intel_de_write(dev_priv, 858 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), 859 rc_buf_thresh_dword[1]); 860 intel_de_write(dev_priv, 861 ICL_DSC1_RC_BUF_THRESH_1(pipe), 862 rc_buf_thresh_dword[2]); 863 intel_de_write(dev_priv, 864 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), 865 rc_buf_thresh_dword[3]); 866 } 867 } 868 869 /* Populate the RC_RANGE_PARAMETERS registers */ 870 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); 871 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 872 rc_range_params_dword[i / 2] |= 873 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << 874 RC_BPG_OFFSET_SHIFT) | 875 (vdsc_cfg->rc_range_params[i].range_max_qp << 876 RC_MAX_QP_SHIFT) | 877 (vdsc_cfg->rc_range_params[i].range_min_qp << 878 RC_MIN_QP_SHIFT)) << 16 * (i % 2)); 879 drm_info(&dev_priv->drm, " RC_RANGE_PARAM_%d = 0x%08x\n", i, 880 rc_range_params_dword[i / 2]); 881 } 882 if (!is_pipe_dsc(crtc_state)) { 883 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0, 884 rc_range_params_dword[0]); 885 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW, 886 rc_range_params_dword[1]); 887 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1, 888 rc_range_params_dword[2]); 889 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW, 890 rc_range_params_dword[3]); 891 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2, 892 rc_range_params_dword[4]); 893 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW, 894 rc_range_params_dword[5]); 895 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3, 896 rc_range_params_dword[6]); 897 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW, 898 rc_range_params_dword[7]); 899 if (crtc_state->dsc.dsc_split) { 900 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0, 901 rc_range_params_dword[0]); 902 intel_de_write(dev_priv, 903 DSCC_RC_RANGE_PARAMETERS_0_UDW, 904 rc_range_params_dword[1]); 905 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1, 906 rc_range_params_dword[2]); 907 intel_de_write(dev_priv, 908 DSCC_RC_RANGE_PARAMETERS_1_UDW, 909 rc_range_params_dword[3]); 910 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2, 911 rc_range_params_dword[4]); 912 intel_de_write(dev_priv, 913 DSCC_RC_RANGE_PARAMETERS_2_UDW, 914 rc_range_params_dword[5]); 915 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3, 916 rc_range_params_dword[6]); 917 intel_de_write(dev_priv, 918 DSCC_RC_RANGE_PARAMETERS_3_UDW, 919 rc_range_params_dword[7]); 920 } 921 } else { 922 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), 923 rc_range_params_dword[0]); 924 intel_de_write(dev_priv, 925 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), 926 rc_range_params_dword[1]); 927 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), 928 rc_range_params_dword[2]); 929 intel_de_write(dev_priv, 930 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), 931 rc_range_params_dword[3]); 932 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), 933 rc_range_params_dword[4]); 934 intel_de_write(dev_priv, 935 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), 936 rc_range_params_dword[5]); 937 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), 938 rc_range_params_dword[6]); 939 intel_de_write(dev_priv, 940 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), 941 rc_range_params_dword[7]); 942 if (crtc_state->dsc.dsc_split) { 943 intel_de_write(dev_priv, 944 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), 945 rc_range_params_dword[0]); 946 intel_de_write(dev_priv, 947 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), 948 rc_range_params_dword[1]); 949 intel_de_write(dev_priv, 950 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), 951 rc_range_params_dword[2]); 952 intel_de_write(dev_priv, 953 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), 954 rc_range_params_dword[3]); 955 intel_de_write(dev_priv, 956 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), 957 rc_range_params_dword[4]); 958 intel_de_write(dev_priv, 959 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), 960 rc_range_params_dword[5]); 961 intel_de_write(dev_priv, 962 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), 963 rc_range_params_dword[6]); 964 intel_de_write(dev_priv, 965 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), 966 rc_range_params_dword[7]); 967 } 968 } 969 } 970 971 static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, 972 const struct intel_crtc_state *crtc_state) 973 { 974 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 975 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 976 struct mipi_dsi_device *dsi; 977 struct drm_dsc_picture_parameter_set pps; 978 enum port port; 979 980 drm_dsc_pps_payload_pack(&pps, vdsc_cfg); 981 982 for_each_dsi_port(port, intel_dsi->ports) { 983 dsi = intel_dsi->dsi_hosts[port]->device; 984 985 mipi_dsi_picture_parameter_set(dsi, &pps); 986 mipi_dsi_compression_mode(dsi, true); 987 } 988 } 989 990 static void intel_dsc_dp_pps_write(struct intel_encoder *encoder, 991 const struct intel_crtc_state *crtc_state) 992 { 993 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 994 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 995 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 996 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; 997 998 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ 999 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header); 1000 1001 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ 1002 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg); 1003 1004 dig_port->write_infoframe(encoder, crtc_state, 1005 DP_SDP_PPS, &dp_dsc_pps_sdp, 1006 sizeof(dp_dsc_pps_sdp)); 1007 } 1008 1009 static i915_reg_t dss_ctl1_reg(const struct intel_crtc_state *crtc_state) 1010 { 1011 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1012 1013 return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL1(pipe) : DSS_CTL1; 1014 } 1015 1016 static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state) 1017 { 1018 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1019 1020 return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) : DSS_CTL2; 1021 } 1022 1023 void intel_dsc_enable(struct intel_encoder *encoder, 1024 const struct intel_crtc_state *crtc_state) 1025 { 1026 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1027 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1028 u32 dss_ctl1_val = 0; 1029 u32 dss_ctl2_val = 0; 1030 1031 if (!crtc_state->dsc.compression_enable) 1032 return; 1033 1034 intel_dsc_pps_configure(crtc_state); 1035 1036 if (!crtc_state->bigjoiner_slave) { 1037 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1038 intel_dsc_dsi_pps_write(encoder, crtc_state); 1039 else 1040 intel_dsc_dp_pps_write(encoder, crtc_state); 1041 } 1042 1043 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; 1044 if (crtc_state->dsc.dsc_split) { 1045 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; 1046 dss_ctl1_val |= JOINER_ENABLE; 1047 } 1048 if (crtc_state->bigjoiner) { 1049 dss_ctl1_val |= BIG_JOINER_ENABLE; 1050 if (!crtc_state->bigjoiner_slave) 1051 dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE; 1052 } 1053 intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val); 1054 intel_de_write(dev_priv, dss_ctl2_reg(crtc_state), dss_ctl2_val); 1055 } 1056 1057 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) 1058 { 1059 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1060 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1061 1062 if (!old_crtc_state->dsc.compression_enable) 1063 return; 1064 1065 intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0); 1066 intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0); 1067 } 1068 1069 void intel_dsc_get_config(struct intel_crtc_state *crtc_state) 1070 { 1071 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1072 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1073 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1074 enum pipe pipe = crtc->pipe; 1075 enum intel_display_power_domain power_domain; 1076 intel_wakeref_t wakeref; 1077 u32 dss_ctl1, dss_ctl2, val; 1078 1079 if (!intel_dsc_source_support(crtc_state)) 1080 return; 1081 1082 power_domain = intel_dsc_power_domain(crtc_state); 1083 1084 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 1085 if (!wakeref) 1086 return; 1087 1088 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state)); 1089 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc_state)); 1090 1091 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; 1092 if (!crtc_state->dsc.compression_enable) 1093 goto out; 1094 1095 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && 1096 (dss_ctl1 & JOINER_ENABLE); 1097 1098 if (dss_ctl1 & BIG_JOINER_ENABLE) { 1099 crtc_state->bigjoiner = true; 1100 1101 if (!(dss_ctl1 & MASTER_BIG_JOINER_ENABLE)) { 1102 crtc_state->bigjoiner_slave = true; 1103 if (!WARN_ON(crtc->pipe == PIPE_A)) 1104 crtc_state->bigjoiner_linked_crtc = 1105 intel_get_crtc_for_pipe(dev_priv, crtc->pipe - 1); 1106 } else { 1107 if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1)) 1108 crtc_state->bigjoiner_linked_crtc = 1109 intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1); 1110 } 1111 } 1112 1113 /* FIXME: add more state readout as needed */ 1114 1115 /* PPS1 */ 1116 if (!is_pipe_dsc(crtc_state)) 1117 val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1); 1118 else 1119 val = intel_de_read(dev_priv, 1120 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); 1121 vdsc_cfg->bits_per_pixel = val; 1122 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; 1123 out: 1124 intel_display_power_put(dev_priv, power_domain, wakeref); 1125 } 1126