1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2018 Intel Corporation 4 * 5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com> 6 * Manasi Navare <manasi.d.navare@intel.com> 7 */ 8 9 #include <drm/i915_drm.h> 10 11 #include "i915_drv.h" 12 #include "intel_display_types.h" 13 #include "intel_dsi.h" 14 #include "intel_vdsc.h" 15 16 enum ROW_INDEX_BPP { 17 ROW_INDEX_6BPP = 0, 18 ROW_INDEX_8BPP, 19 ROW_INDEX_10BPP, 20 ROW_INDEX_12BPP, 21 ROW_INDEX_15BPP, 22 MAX_ROW_INDEX 23 }; 24 25 enum COLUMN_INDEX_BPC { 26 COLUMN_INDEX_8BPC = 0, 27 COLUMN_INDEX_10BPC, 28 COLUMN_INDEX_12BPC, 29 COLUMN_INDEX_14BPC, 30 COLUMN_INDEX_16BPC, 31 MAX_COLUMN_INDEX 32 }; 33 34 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */ 35 static const u16 rc_buf_thresh[] = { 36 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, 37 7744, 7872, 8000, 8064 38 }; 39 40 struct rc_parameters { 41 u16 initial_xmit_delay; 42 u8 first_line_bpg_offset; 43 u16 initial_offset; 44 u8 flatness_min_qp; 45 u8 flatness_max_qp; 46 u8 rc_quant_incr_limit0; 47 u8 rc_quant_incr_limit1; 48 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; 49 }; 50 51 /* 52 * Selected Rate Control Related Parameter Recommended Values 53 * from DSC_v1.11 spec & C Model release: DSC_model_20161212 54 */ 55 static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { 56 { 57 /* 6BPP/8BPC */ 58 { 768, 15, 6144, 3, 13, 11, 11, { 59 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 }, 60 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 }, 61 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 }, 62 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 } 63 } 64 }, 65 /* 6BPP/10BPC */ 66 { 768, 15, 6144, 7, 17, 15, 15, { 67 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 }, 68 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 }, 69 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 }, 70 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 }, 71 { 17, 18, -12 } 72 } 73 }, 74 /* 6BPP/12BPC */ 75 { 768, 15, 6144, 11, 21, 19, 19, { 76 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 }, 77 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 }, 78 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 }, 79 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 }, 80 { 21, 22, -12 } 81 } 82 }, 83 /* 6BPP/14BPC */ 84 { 768, 15, 6144, 15, 25, 23, 27, { 85 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 }, 86 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 }, 87 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 }, 88 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 }, 89 { 25, 26, -12 } 90 } 91 }, 92 /* 6BPP/16BPC */ 93 { 768, 15, 6144, 19, 29, 27, 27, { 94 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 }, 95 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 }, 96 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 }, 97 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 }, 98 { 29, 30, -12 } 99 } 100 }, 101 }, 102 { 103 /* 8BPP/8BPC */ 104 { 512, 12, 6144, 3, 12, 11, 11, { 105 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, 106 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 107 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, 108 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } 109 } 110 }, 111 /* 8BPP/10BPC */ 112 { 512, 12, 6144, 7, 16, 15, 15, { 113 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, 114 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 115 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, 116 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } 117 } 118 }, 119 /* 8BPP/12BPC */ 120 { 512, 12, 6144, 11, 20, 19, 19, { 121 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, 122 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 123 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, 124 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, 125 { 21, 23, -12 } 126 } 127 }, 128 /* 8BPP/14BPC */ 129 { 512, 12, 6144, 15, 24, 23, 23, { 130 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, 131 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 132 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, 133 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, 134 { 24, 25, -12 } 135 } 136 }, 137 /* 8BPP/16BPC */ 138 { 512, 12, 6144, 19, 28, 27, 27, { 139 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 }, 140 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 141 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 }, 142 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 }, 143 { 28, 29, -12 } 144 } 145 }, 146 }, 147 { 148 /* 10BPP/8BPC */ 149 { 410, 15, 5632, 3, 12, 11, 11, { 150 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, 151 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 152 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 }, 153 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 } 154 } 155 }, 156 /* 10BPP/10BPC */ 157 { 410, 15, 5632, 7, 16, 15, 15, { 158 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, 159 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 160 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 }, 161 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 } 162 } 163 }, 164 /* 10BPP/12BPC */ 165 { 410, 15, 5632, 11, 20, 19, 19, { 166 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, 167 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 168 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 }, 169 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 }, 170 { 19, 20, -12 } 171 } 172 }, 173 /* 10BPP/14BPC */ 174 { 410, 15, 5632, 15, 24, 23, 23, { 175 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 }, 176 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 177 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 }, 178 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 }, 179 { 23, 24, -12 } 180 } 181 }, 182 /* 10BPP/16BPC */ 183 { 410, 15, 5632, 19, 28, 27, 27, { 184 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 }, 185 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 186 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 }, 187 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 }, 188 { 27, 28, -12 } 189 } 190 }, 191 }, 192 { 193 /* 12BPP/8BPC */ 194 { 341, 15, 2048, 3, 12, 11, 11, { 195 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, 196 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 197 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, 198 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } 199 } 200 }, 201 /* 12BPP/10BPC */ 202 { 341, 15, 2048, 7, 16, 15, 15, { 203 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, 204 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 205 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, 206 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } 207 } 208 }, 209 /* 12BPP/12BPC */ 210 { 341, 15, 2048, 11, 20, 19, 19, { 211 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, 212 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 213 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, 214 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, 215 { 21, 23, -12 } 216 } 217 }, 218 /* 12BPP/14BPC */ 219 { 341, 15, 2048, 15, 24, 23, 23, { 220 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 }, 221 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 222 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 }, 223 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 }, 224 { 22, 23, -12 } 225 } 226 }, 227 /* 12BPP/16BPC */ 228 { 341, 15, 2048, 19, 28, 27, 27, { 229 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 }, 230 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 231 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 }, 232 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 }, 233 { 26, 27, -12 } 234 } 235 }, 236 }, 237 { 238 /* 15BPP/8BPC */ 239 { 273, 15, 2048, 3, 12, 11, 11, { 240 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, 241 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 }, 242 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 }, 243 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 } 244 } 245 }, 246 /* 15BPP/10BPC */ 247 { 273, 15, 2048, 7, 16, 15, 15, { 248 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, 249 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 }, 250 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 }, 251 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 } 252 } 253 }, 254 /* 15BPP/12BPC */ 255 { 273, 15, 2048, 11, 20, 19, 19, { 256 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, 257 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 }, 258 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 }, 259 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 }, 260 { 16, 17, -12 } 261 } 262 }, 263 /* 15BPP/14BPC */ 264 { 273, 15, 2048, 15, 24, 23, 23, { 265 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 }, 266 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 }, 267 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 }, 268 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 }, 269 { 20, 21, -12 } 270 } 271 }, 272 /* 15BPP/16BPC */ 273 { 273, 15, 2048, 19, 28, 27, 27, { 274 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 }, 275 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 }, 276 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 }, 277 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 }, 278 { 24, 25, -12 } 279 } 280 } 281 } 282 283 }; 284 285 static int get_row_index_for_rc_params(u16 compressed_bpp) 286 { 287 switch (compressed_bpp) { 288 case 6: 289 return ROW_INDEX_6BPP; 290 case 8: 291 return ROW_INDEX_8BPP; 292 case 10: 293 return ROW_INDEX_10BPP; 294 case 12: 295 return ROW_INDEX_12BPP; 296 case 15: 297 return ROW_INDEX_15BPP; 298 default: 299 return -EINVAL; 300 } 301 } 302 303 static int get_column_index_for_rc_params(u8 bits_per_component) 304 { 305 switch (bits_per_component) { 306 case 8: 307 return COLUMN_INDEX_8BPC; 308 case 10: 309 return COLUMN_INDEX_10BPC; 310 case 12: 311 return COLUMN_INDEX_12BPC; 312 case 14: 313 return COLUMN_INDEX_14BPC; 314 case 16: 315 return COLUMN_INDEX_16BPC; 316 default: 317 return -EINVAL; 318 } 319 } 320 321 static const struct rc_parameters *get_rc_params(u16 compressed_bpp, 322 u8 bits_per_component) 323 { 324 int row_index, column_index; 325 326 row_index = get_row_index_for_rc_params(compressed_bpp); 327 if (row_index < 0) 328 return NULL; 329 330 column_index = get_column_index_for_rc_params(bits_per_component); 331 if (column_index < 0) 332 return NULL; 333 334 return &rc_parameters[row_index][column_index]; 335 } 336 337 bool intel_dsc_source_support(struct intel_encoder *encoder, 338 const struct intel_crtc_state *crtc_state) 339 { 340 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 341 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 342 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 343 enum pipe pipe = crtc->pipe; 344 345 if (!INTEL_INFO(i915)->display.has_dsc) 346 return false; 347 348 /* On TGL, DSC is supported on all Pipes */ 349 if (INTEL_GEN(i915) >= 12) 350 return true; 351 352 if (INTEL_GEN(i915) >= 10 && 353 (pipe != PIPE_A || 354 (cpu_transcoder == TRANSCODER_EDP || 355 cpu_transcoder == TRANSCODER_DSI_0 || 356 cpu_transcoder == TRANSCODER_DSI_1))) 357 return true; 358 359 return false; 360 } 361 362 static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state) 363 { 364 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 365 const struct drm_i915_private *i915 = to_i915(crtc->base.dev); 366 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 367 368 if (INTEL_GEN(i915) >= 12) 369 return true; 370 371 if (cpu_transcoder == TRANSCODER_EDP || 372 cpu_transcoder == TRANSCODER_DSI_0 || 373 cpu_transcoder == TRANSCODER_DSI_1) 374 return false; 375 376 /* There's no pipe A DSC engine on ICL */ 377 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A); 378 379 return true; 380 } 381 382 int intel_dsc_compute_params(struct intel_encoder *encoder, 383 struct intel_crtc_state *pipe_config) 384 { 385 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; 386 u16 compressed_bpp = pipe_config->dsc.compressed_bpp; 387 const struct rc_parameters *rc_params; 388 u8 i = 0; 389 390 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; 391 vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay; 392 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, 393 pipe_config->dsc.slice_count); 394 395 /* Gen 11 does not support YCbCr */ 396 vdsc_cfg->simple_422 = false; 397 /* Gen 11 does not support VBR */ 398 vdsc_cfg->vbr_enable = false; 399 400 /* Gen 11 only supports integral values of bpp */ 401 vdsc_cfg->bits_per_pixel = compressed_bpp << 4; 402 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; 403 404 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { 405 /* 406 * six 0s are appended to the lsb of each threshold value 407 * internally in h/w. 408 * Only 8 bits are allowed for programming RcBufThreshold 409 */ 410 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; 411 } 412 413 /* 414 * For 6bpp, RC Buffer threshold 12 and 13 need a different value 415 * as per C Model 416 */ 417 if (compressed_bpp == 6) { 418 vdsc_cfg->rc_buf_thresh[12] = 0x7C; 419 vdsc_cfg->rc_buf_thresh[13] = 0x7D; 420 } 421 422 rc_params = get_rc_params(compressed_bpp, vdsc_cfg->bits_per_component); 423 if (!rc_params) 424 return -EINVAL; 425 426 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset; 427 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay; 428 vdsc_cfg->initial_offset = rc_params->initial_offset; 429 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp; 430 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp; 431 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0; 432 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1; 433 434 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 435 vdsc_cfg->rc_range_params[i].range_min_qp = 436 rc_params->rc_range_params[i].range_min_qp; 437 vdsc_cfg->rc_range_params[i].range_max_qp = 438 rc_params->rc_range_params[i].range_max_qp; 439 /* 440 * Range BPG Offset uses 2's complement and is only a 6 bits. So 441 * mask it to get only 6 bits. 442 */ 443 vdsc_cfg->rc_range_params[i].range_bpg_offset = 444 rc_params->rc_range_params[i].range_bpg_offset & 445 DSC_RANGE_BPG_OFFSET_MASK; 446 } 447 448 /* 449 * BitsPerComponent value determines mux_word_size: 450 * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits 451 * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to 452 * 48 bits 453 */ 454 if (vdsc_cfg->bits_per_component == 8 || 455 vdsc_cfg->bits_per_component == 10) 456 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; 457 else if (vdsc_cfg->bits_per_component == 12) 458 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; 459 460 /* RC_MODEL_SIZE is a constant across all configurations */ 461 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 462 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ 463 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / 464 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); 465 466 return 0; 467 } 468 469 enum intel_display_power_domain 470 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state) 471 { 472 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 473 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 474 enum pipe pipe = crtc->pipe; 475 476 /* 477 * VDSC/joining uses a separate power well, PW2, and requires 478 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases: 479 * 480 * - ICL eDP/DSI transcoder 481 * - TGL pipe A 482 * 483 * For any other pipe, VDSC/joining uses the power well associated with 484 * the pipe in use. Hence another reference on the pipe power domain 485 * will suffice. (Except no VDSC/joining on ICL pipe A.) 486 */ 487 if (INTEL_GEN(i915) >= 12 && pipe == PIPE_A) 488 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 489 else if (is_pipe_dsc(crtc_state)) 490 return POWER_DOMAIN_PIPE(pipe); 491 else 492 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 493 } 494 495 static void intel_dsc_pps_configure(struct intel_encoder *encoder, 496 const struct intel_crtc_state *crtc_state) 497 { 498 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 499 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 500 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 501 enum pipe pipe = crtc->pipe; 502 u32 pps_val = 0; 503 u32 rc_buf_thresh_dword[4]; 504 u32 rc_range_params_dword[8]; 505 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1; 506 int i = 0; 507 508 /* Populate PICTURE_PARAMETER_SET_0 registers */ 509 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << 510 DSC_VER_MIN_SHIFT | 511 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | 512 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; 513 if (vdsc_cfg->block_pred_enable) 514 pps_val |= DSC_BLOCK_PREDICTION; 515 if (vdsc_cfg->convert_rgb) 516 pps_val |= DSC_COLOR_SPACE_CONVERSION; 517 if (vdsc_cfg->simple_422) 518 pps_val |= DSC_422_ENABLE; 519 if (vdsc_cfg->vbr_enable) 520 pps_val |= DSC_VBR_ENABLE; 521 drm_info(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); 522 if (!is_pipe_dsc(crtc_state)) { 523 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0, 524 pps_val); 525 /* 526 * If 2 VDSC instances are needed, configure PPS for second 527 * VDSC 528 */ 529 if (crtc_state->dsc.dsc_split) 530 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0, 531 pps_val); 532 } else { 533 intel_de_write(dev_priv, 534 ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), 535 pps_val); 536 if (crtc_state->dsc.dsc_split) 537 intel_de_write(dev_priv, 538 ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), 539 pps_val); 540 } 541 542 /* Populate PICTURE_PARAMETER_SET_1 registers */ 543 pps_val = 0; 544 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); 545 drm_info(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); 546 if (!is_pipe_dsc(crtc_state)) { 547 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1, 548 pps_val); 549 /* 550 * If 2 VDSC instances are needed, configure PPS for second 551 * VDSC 552 */ 553 if (crtc_state->dsc.dsc_split) 554 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1, 555 pps_val); 556 } else { 557 intel_de_write(dev_priv, 558 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), 559 pps_val); 560 if (crtc_state->dsc.dsc_split) 561 intel_de_write(dev_priv, 562 ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), 563 pps_val); 564 } 565 566 /* Populate PICTURE_PARAMETER_SET_2 registers */ 567 pps_val = 0; 568 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | 569 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); 570 drm_info(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); 571 if (!is_pipe_dsc(crtc_state)) { 572 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2, 573 pps_val); 574 /* 575 * If 2 VDSC instances are needed, configure PPS for second 576 * VDSC 577 */ 578 if (crtc_state->dsc.dsc_split) 579 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2, 580 pps_val); 581 } else { 582 intel_de_write(dev_priv, 583 ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), 584 pps_val); 585 if (crtc_state->dsc.dsc_split) 586 intel_de_write(dev_priv, 587 ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), 588 pps_val); 589 } 590 591 /* Populate PICTURE_PARAMETER_SET_3 registers */ 592 pps_val = 0; 593 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | 594 DSC_SLICE_WIDTH(vdsc_cfg->slice_width); 595 drm_info(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); 596 if (!is_pipe_dsc(crtc_state)) { 597 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3, 598 pps_val); 599 /* 600 * If 2 VDSC instances are needed, configure PPS for second 601 * VDSC 602 */ 603 if (crtc_state->dsc.dsc_split) 604 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3, 605 pps_val); 606 } else { 607 intel_de_write(dev_priv, 608 ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), 609 pps_val); 610 if (crtc_state->dsc.dsc_split) 611 intel_de_write(dev_priv, 612 ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), 613 pps_val); 614 } 615 616 /* Populate PICTURE_PARAMETER_SET_4 registers */ 617 pps_val = 0; 618 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | 619 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); 620 drm_info(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); 621 if (!is_pipe_dsc(crtc_state)) { 622 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4, 623 pps_val); 624 /* 625 * If 2 VDSC instances are needed, configure PPS for second 626 * VDSC 627 */ 628 if (crtc_state->dsc.dsc_split) 629 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4, 630 pps_val); 631 } else { 632 intel_de_write(dev_priv, 633 ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), 634 pps_val); 635 if (crtc_state->dsc.dsc_split) 636 intel_de_write(dev_priv, 637 ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), 638 pps_val); 639 } 640 641 /* Populate PICTURE_PARAMETER_SET_5 registers */ 642 pps_val = 0; 643 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | 644 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); 645 drm_info(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); 646 if (!is_pipe_dsc(crtc_state)) { 647 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5, 648 pps_val); 649 /* 650 * If 2 VDSC instances are needed, configure PPS for second 651 * VDSC 652 */ 653 if (crtc_state->dsc.dsc_split) 654 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5, 655 pps_val); 656 } else { 657 intel_de_write(dev_priv, 658 ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), 659 pps_val); 660 if (crtc_state->dsc.dsc_split) 661 intel_de_write(dev_priv, 662 ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), 663 pps_val); 664 } 665 666 /* Populate PICTURE_PARAMETER_SET_6 registers */ 667 pps_val = 0; 668 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | 669 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | 670 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | 671 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); 672 drm_info(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); 673 if (!is_pipe_dsc(crtc_state)) { 674 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6, 675 pps_val); 676 /* 677 * If 2 VDSC instances are needed, configure PPS for second 678 * VDSC 679 */ 680 if (crtc_state->dsc.dsc_split) 681 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6, 682 pps_val); 683 } else { 684 intel_de_write(dev_priv, 685 ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), 686 pps_val); 687 if (crtc_state->dsc.dsc_split) 688 intel_de_write(dev_priv, 689 ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), 690 pps_val); 691 } 692 693 /* Populate PICTURE_PARAMETER_SET_7 registers */ 694 pps_val = 0; 695 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | 696 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); 697 drm_info(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); 698 if (!is_pipe_dsc(crtc_state)) { 699 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7, 700 pps_val); 701 /* 702 * If 2 VDSC instances are needed, configure PPS for second 703 * VDSC 704 */ 705 if (crtc_state->dsc.dsc_split) 706 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7, 707 pps_val); 708 } else { 709 intel_de_write(dev_priv, 710 ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), 711 pps_val); 712 if (crtc_state->dsc.dsc_split) 713 intel_de_write(dev_priv, 714 ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), 715 pps_val); 716 } 717 718 /* Populate PICTURE_PARAMETER_SET_8 registers */ 719 pps_val = 0; 720 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | 721 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); 722 drm_info(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); 723 if (!is_pipe_dsc(crtc_state)) { 724 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8, 725 pps_val); 726 /* 727 * If 2 VDSC instances are needed, configure PPS for second 728 * VDSC 729 */ 730 if (crtc_state->dsc.dsc_split) 731 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8, 732 pps_val); 733 } else { 734 intel_de_write(dev_priv, 735 ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), 736 pps_val); 737 if (crtc_state->dsc.dsc_split) 738 intel_de_write(dev_priv, 739 ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), 740 pps_val); 741 } 742 743 /* Populate PICTURE_PARAMETER_SET_9 registers */ 744 pps_val = 0; 745 pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) | 746 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); 747 drm_info(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); 748 if (!is_pipe_dsc(crtc_state)) { 749 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9, 750 pps_val); 751 /* 752 * If 2 VDSC instances are needed, configure PPS for second 753 * VDSC 754 */ 755 if (crtc_state->dsc.dsc_split) 756 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9, 757 pps_val); 758 } else { 759 intel_de_write(dev_priv, 760 ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), 761 pps_val); 762 if (crtc_state->dsc.dsc_split) 763 intel_de_write(dev_priv, 764 ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), 765 pps_val); 766 } 767 768 /* Populate PICTURE_PARAMETER_SET_10 registers */ 769 pps_val = 0; 770 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | 771 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | 772 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | 773 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); 774 drm_info(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); 775 if (!is_pipe_dsc(crtc_state)) { 776 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10, 777 pps_val); 778 /* 779 * If 2 VDSC instances are needed, configure PPS for second 780 * VDSC 781 */ 782 if (crtc_state->dsc.dsc_split) 783 intel_de_write(dev_priv, 784 DSCC_PICTURE_PARAMETER_SET_10, pps_val); 785 } else { 786 intel_de_write(dev_priv, 787 ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), 788 pps_val); 789 if (crtc_state->dsc.dsc_split) 790 intel_de_write(dev_priv, 791 ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), 792 pps_val); 793 } 794 795 /* Populate Picture parameter set 16 */ 796 pps_val = 0; 797 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | 798 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / 799 vdsc_cfg->slice_width) | 800 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / 801 vdsc_cfg->slice_height); 802 drm_info(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val); 803 if (!is_pipe_dsc(crtc_state)) { 804 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16, 805 pps_val); 806 /* 807 * If 2 VDSC instances are needed, configure PPS for second 808 * VDSC 809 */ 810 if (crtc_state->dsc.dsc_split) 811 intel_de_write(dev_priv, 812 DSCC_PICTURE_PARAMETER_SET_16, pps_val); 813 } else { 814 intel_de_write(dev_priv, 815 ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), 816 pps_val); 817 if (crtc_state->dsc.dsc_split) 818 intel_de_write(dev_priv, 819 ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), 820 pps_val); 821 } 822 823 /* Populate the RC_BUF_THRESH registers */ 824 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); 825 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { 826 rc_buf_thresh_dword[i / 4] |= 827 (u32)(vdsc_cfg->rc_buf_thresh[i] << 828 BITS_PER_BYTE * (i % 4)); 829 drm_info(&dev_priv->drm, " RC_BUF_THRESH%d = 0x%08x\n", i, 830 rc_buf_thresh_dword[i / 4]); 831 } 832 if (!is_pipe_dsc(crtc_state)) { 833 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0, 834 rc_buf_thresh_dword[0]); 835 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW, 836 rc_buf_thresh_dword[1]); 837 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1, 838 rc_buf_thresh_dword[2]); 839 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW, 840 rc_buf_thresh_dword[3]); 841 if (crtc_state->dsc.dsc_split) { 842 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0, 843 rc_buf_thresh_dword[0]); 844 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW, 845 rc_buf_thresh_dword[1]); 846 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1, 847 rc_buf_thresh_dword[2]); 848 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW, 849 rc_buf_thresh_dword[3]); 850 } 851 } else { 852 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe), 853 rc_buf_thresh_dword[0]); 854 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), 855 rc_buf_thresh_dword[1]); 856 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe), 857 rc_buf_thresh_dword[2]); 858 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), 859 rc_buf_thresh_dword[3]); 860 if (crtc_state->dsc.dsc_split) { 861 intel_de_write(dev_priv, 862 ICL_DSC1_RC_BUF_THRESH_0(pipe), 863 rc_buf_thresh_dword[0]); 864 intel_de_write(dev_priv, 865 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), 866 rc_buf_thresh_dword[1]); 867 intel_de_write(dev_priv, 868 ICL_DSC1_RC_BUF_THRESH_1(pipe), 869 rc_buf_thresh_dword[2]); 870 intel_de_write(dev_priv, 871 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), 872 rc_buf_thresh_dword[3]); 873 } 874 } 875 876 /* Populate the RC_RANGE_PARAMETERS registers */ 877 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); 878 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 879 rc_range_params_dword[i / 2] |= 880 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << 881 RC_BPG_OFFSET_SHIFT) | 882 (vdsc_cfg->rc_range_params[i].range_max_qp << 883 RC_MAX_QP_SHIFT) | 884 (vdsc_cfg->rc_range_params[i].range_min_qp << 885 RC_MIN_QP_SHIFT)) << 16 * (i % 2)); 886 drm_info(&dev_priv->drm, " RC_RANGE_PARAM_%d = 0x%08x\n", i, 887 rc_range_params_dword[i / 2]); 888 } 889 if (!is_pipe_dsc(crtc_state)) { 890 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0, 891 rc_range_params_dword[0]); 892 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW, 893 rc_range_params_dword[1]); 894 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1, 895 rc_range_params_dword[2]); 896 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW, 897 rc_range_params_dword[3]); 898 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2, 899 rc_range_params_dword[4]); 900 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW, 901 rc_range_params_dword[5]); 902 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3, 903 rc_range_params_dword[6]); 904 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW, 905 rc_range_params_dword[7]); 906 if (crtc_state->dsc.dsc_split) { 907 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0, 908 rc_range_params_dword[0]); 909 intel_de_write(dev_priv, 910 DSCC_RC_RANGE_PARAMETERS_0_UDW, 911 rc_range_params_dword[1]); 912 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1, 913 rc_range_params_dword[2]); 914 intel_de_write(dev_priv, 915 DSCC_RC_RANGE_PARAMETERS_1_UDW, 916 rc_range_params_dword[3]); 917 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2, 918 rc_range_params_dword[4]); 919 intel_de_write(dev_priv, 920 DSCC_RC_RANGE_PARAMETERS_2_UDW, 921 rc_range_params_dword[5]); 922 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3, 923 rc_range_params_dword[6]); 924 intel_de_write(dev_priv, 925 DSCC_RC_RANGE_PARAMETERS_3_UDW, 926 rc_range_params_dword[7]); 927 } 928 } else { 929 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), 930 rc_range_params_dword[0]); 931 intel_de_write(dev_priv, 932 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), 933 rc_range_params_dword[1]); 934 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), 935 rc_range_params_dword[2]); 936 intel_de_write(dev_priv, 937 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), 938 rc_range_params_dword[3]); 939 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), 940 rc_range_params_dword[4]); 941 intel_de_write(dev_priv, 942 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), 943 rc_range_params_dword[5]); 944 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), 945 rc_range_params_dword[6]); 946 intel_de_write(dev_priv, 947 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), 948 rc_range_params_dword[7]); 949 if (crtc_state->dsc.dsc_split) { 950 intel_de_write(dev_priv, 951 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), 952 rc_range_params_dword[0]); 953 intel_de_write(dev_priv, 954 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), 955 rc_range_params_dword[1]); 956 intel_de_write(dev_priv, 957 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), 958 rc_range_params_dword[2]); 959 intel_de_write(dev_priv, 960 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), 961 rc_range_params_dword[3]); 962 intel_de_write(dev_priv, 963 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), 964 rc_range_params_dword[4]); 965 intel_de_write(dev_priv, 966 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), 967 rc_range_params_dword[5]); 968 intel_de_write(dev_priv, 969 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), 970 rc_range_params_dword[6]); 971 intel_de_write(dev_priv, 972 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), 973 rc_range_params_dword[7]); 974 } 975 } 976 } 977 978 void intel_dsc_get_config(struct intel_encoder *encoder, 979 struct intel_crtc_state *crtc_state) 980 { 981 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 982 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 983 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 984 enum pipe pipe = crtc->pipe; 985 enum intel_display_power_domain power_domain; 986 intel_wakeref_t wakeref; 987 u32 dss_ctl1, dss_ctl2, val; 988 989 if (!intel_dsc_source_support(encoder, crtc_state)) 990 return; 991 992 power_domain = intel_dsc_power_domain(crtc_state); 993 994 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 995 if (!wakeref) 996 return; 997 998 if (!is_pipe_dsc(crtc_state)) { 999 dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1); 1000 dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2); 1001 } else { 1002 dss_ctl1 = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 1003 dss_ctl2 = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL2(pipe)); 1004 } 1005 1006 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; 1007 if (!crtc_state->dsc.compression_enable) 1008 goto out; 1009 1010 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && 1011 (dss_ctl1 & JOINER_ENABLE); 1012 1013 /* FIXME: add more state readout as needed */ 1014 1015 /* PPS1 */ 1016 if (!is_pipe_dsc(crtc_state)) 1017 val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1); 1018 else 1019 val = intel_de_read(dev_priv, 1020 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); 1021 vdsc_cfg->bits_per_pixel = val; 1022 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; 1023 out: 1024 intel_display_power_put(dev_priv, power_domain, wakeref); 1025 } 1026 1027 static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, 1028 const struct intel_crtc_state *crtc_state) 1029 { 1030 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1031 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1032 struct mipi_dsi_device *dsi; 1033 struct drm_dsc_picture_parameter_set pps; 1034 enum port port; 1035 1036 drm_dsc_pps_payload_pack(&pps, vdsc_cfg); 1037 1038 for_each_dsi_port(port, intel_dsi->ports) { 1039 dsi = intel_dsi->dsi_hosts[port]->device; 1040 1041 mipi_dsi_picture_parameter_set(dsi, &pps); 1042 mipi_dsi_compression_mode(dsi, true); 1043 } 1044 } 1045 1046 static void intel_dsc_dp_pps_write(struct intel_encoder *encoder, 1047 const struct intel_crtc_state *crtc_state) 1048 { 1049 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1050 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1051 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1052 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; 1053 1054 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ 1055 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header); 1056 1057 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ 1058 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg); 1059 1060 intel_dig_port->write_infoframe(encoder, crtc_state, 1061 DP_SDP_PPS, &dp_dsc_pps_sdp, 1062 sizeof(dp_dsc_pps_sdp)); 1063 } 1064 1065 void intel_dsc_enable(struct intel_encoder *encoder, 1066 const struct intel_crtc_state *crtc_state) 1067 { 1068 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1069 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1070 enum pipe pipe = crtc->pipe; 1071 i915_reg_t dss_ctl1_reg, dss_ctl2_reg; 1072 u32 dss_ctl1_val = 0; 1073 u32 dss_ctl2_val = 0; 1074 1075 if (!crtc_state->dsc.compression_enable) 1076 return; 1077 1078 /* Enable Power wells for VDSC/joining */ 1079 intel_display_power_get(dev_priv, 1080 intel_dsc_power_domain(crtc_state)); 1081 1082 intel_dsc_pps_configure(encoder, crtc_state); 1083 1084 if (encoder->type == INTEL_OUTPUT_DSI) 1085 intel_dsc_dsi_pps_write(encoder, crtc_state); 1086 else 1087 intel_dsc_dp_pps_write(encoder, crtc_state); 1088 1089 if (!is_pipe_dsc(crtc_state)) { 1090 dss_ctl1_reg = DSS_CTL1; 1091 dss_ctl2_reg = DSS_CTL2; 1092 } else { 1093 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe); 1094 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe); 1095 } 1096 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; 1097 if (crtc_state->dsc.dsc_split) { 1098 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; 1099 dss_ctl1_val |= JOINER_ENABLE; 1100 } 1101 intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1_val); 1102 intel_de_write(dev_priv, dss_ctl2_reg, dss_ctl2_val); 1103 } 1104 1105 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) 1106 { 1107 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1108 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1109 enum pipe pipe = crtc->pipe; 1110 i915_reg_t dss_ctl1_reg, dss_ctl2_reg; 1111 u32 dss_ctl1_val = 0, dss_ctl2_val = 0; 1112 1113 if (!old_crtc_state->dsc.compression_enable) 1114 return; 1115 1116 if (!is_pipe_dsc(old_crtc_state)) { 1117 dss_ctl1_reg = DSS_CTL1; 1118 dss_ctl2_reg = DSS_CTL2; 1119 } else { 1120 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe); 1121 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe); 1122 } 1123 dss_ctl1_val = intel_de_read(dev_priv, dss_ctl1_reg); 1124 if (dss_ctl1_val & JOINER_ENABLE) 1125 dss_ctl1_val &= ~JOINER_ENABLE; 1126 intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1_val); 1127 1128 dss_ctl2_val = intel_de_read(dev_priv, dss_ctl2_reg); 1129 if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE || 1130 dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE) 1131 dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE | 1132 RIGHT_BRANCH_VDSC_ENABLE); 1133 intel_de_write(dev_priv, dss_ctl2_reg, dss_ctl2_val); 1134 1135 /* Disable Power wells for VDSC/joining */ 1136 intel_display_power_put_unchecked(dev_priv, 1137 intel_dsc_power_domain(old_crtc_state)); 1138 } 1139