1 /* 2 * Copyright © 2006-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28 /* 29 * This information is private to VBT parsing in intel_bios.c. 30 * 31 * Please do NOT include anywhere else. 32 */ 33 #ifndef _INTEL_BIOS_PRIVATE 34 #error "intel_vbt_defs.h is private to intel_bios.c" 35 #endif 36 37 #ifndef _INTEL_VBT_DEFS_H_ 38 #define _INTEL_VBT_DEFS_H_ 39 40 #include "intel_bios.h" 41 42 /** 43 * struct vbt_header - VBT Header structure 44 * @signature: VBT signature, always starts with "$VBT" 45 * @version: Version of this structure 46 * @header_size: Size of this structure 47 * @vbt_size: Size of VBT (VBT Header, BDB Header and data blocks) 48 * @vbt_checksum: Checksum 49 * @reserved0: Reserved 50 * @bdb_offset: Offset of &struct bdb_header from beginning of VBT 51 * @aim_offset: Offsets of add-in data blocks from beginning of VBT 52 */ 53 struct vbt_header { 54 u8 signature[20]; 55 u16 version; 56 u16 header_size; 57 u16 vbt_size; 58 u8 vbt_checksum; 59 u8 reserved0; 60 u32 bdb_offset; 61 u32 aim_offset[4]; 62 } __packed; 63 64 /** 65 * struct bdb_header - BDB Header structure 66 * @signature: BDB signature "BIOS_DATA_BLOCK" 67 * @version: Version of the data block definitions 68 * @header_size: Size of this structure 69 * @bdb_size: Size of BDB (BDB Header and data blocks) 70 */ 71 struct bdb_header { 72 u8 signature[16]; 73 u16 version; 74 u16 header_size; 75 u16 bdb_size; 76 } __packed; 77 78 /* 79 * There are several types of BIOS data blocks (BDBs), each block has 80 * an ID and size in the first 3 bytes (ID in first, size in next 2). 81 * Known types are listed below. 82 */ 83 enum bdb_block_id { 84 BDB_GENERAL_FEATURES = 1, 85 BDB_GENERAL_DEFINITIONS = 2, 86 BDB_OLD_TOGGLE_LIST = 3, 87 BDB_MODE_SUPPORT_LIST = 4, 88 BDB_GENERIC_MODE_TABLE = 5, 89 BDB_EXT_MMIO_REGS = 6, 90 BDB_SWF_IO = 7, 91 BDB_SWF_MMIO = 8, 92 BDB_PSR = 9, 93 BDB_MODE_REMOVAL_TABLE = 10, 94 BDB_CHILD_DEVICE_TABLE = 11, 95 BDB_DRIVER_FEATURES = 12, 96 BDB_DRIVER_PERSISTENCE = 13, 97 BDB_EXT_TABLE_PTRS = 14, 98 BDB_DOT_CLOCK_OVERRIDE = 15, 99 BDB_DISPLAY_SELECT = 16, 100 BDB_DRIVER_ROTATION = 18, 101 BDB_DISPLAY_REMOVE = 19, 102 BDB_OEM_CUSTOM = 20, 103 BDB_EFP_LIST = 21, /* workarounds for VGA hsync/vsync */ 104 BDB_SDVO_LVDS_OPTIONS = 22, 105 BDB_SDVO_PANEL_DTDS = 23, 106 BDB_SDVO_LVDS_PNP_IDS = 24, 107 BDB_SDVO_LVDS_POWER_SEQ = 25, 108 BDB_TV_OPTIONS = 26, 109 BDB_EDP = 27, 110 BDB_LVDS_OPTIONS = 40, 111 BDB_LVDS_LFP_DATA_PTRS = 41, 112 BDB_LVDS_LFP_DATA = 42, 113 BDB_LVDS_BACKLIGHT = 43, 114 BDB_LVDS_POWER = 44, 115 BDB_MIPI_CONFIG = 52, 116 BDB_MIPI_SEQUENCE = 53, 117 BDB_COMPRESSION_PARAMETERS = 56, 118 BDB_SKIP = 254, /* VBIOS private block, ignore */ 119 }; 120 121 /* 122 * Block 1 - General Bit Definitions 123 */ 124 125 struct bdb_general_features { 126 /* bits 1 */ 127 u8 panel_fitting:2; 128 u8 flexaim:1; 129 u8 msg_enable:1; 130 u8 clear_screen:3; 131 u8 color_flip:1; 132 133 /* bits 2 */ 134 u8 download_ext_vbt:1; 135 u8 enable_ssc:1; 136 u8 ssc_freq:1; 137 u8 enable_lfp_on_override:1; 138 u8 disable_ssc_ddt:1; 139 u8 underscan_vga_timings:1; 140 u8 display_clock_mode:1; 141 u8 vbios_hotplug_support:1; 142 143 /* bits 3 */ 144 u8 disable_smooth_vision:1; 145 u8 single_dvi:1; 146 u8 rotate_180:1; /* 181 */ 147 u8 fdi_rx_polarity_inverted:1; 148 u8 vbios_extended_mode:1; /* 160 */ 149 u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160 */ 150 u8 panel_best_fit_timing:1; /* 160 */ 151 u8 ignore_strap_state:1; /* 160 */ 152 153 /* bits 4 */ 154 u8 legacy_monitor_detect; 155 156 /* bits 5 */ 157 u8 int_crt_support:1; 158 u8 int_tv_support:1; 159 u8 int_efp_support:1; 160 u8 dp_ssc_enable:1; /* PCH attached eDP supports SSC */ 161 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ 162 u8 dp_ssc_dongle_supported:1; 163 u8 rsvd11:2; /* finish byte */ 164 } __packed; 165 166 /* 167 * Block 2 - General Bytes Definition 168 */ 169 170 /* pre-915 */ 171 #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ 172 #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ 173 #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ 174 #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ 175 176 /* Pre 915 */ 177 #define DEVICE_TYPE_NONE 0x00 178 #define DEVICE_TYPE_CRT 0x01 179 #define DEVICE_TYPE_TV 0x09 180 #define DEVICE_TYPE_EFP 0x12 181 #define DEVICE_TYPE_LFP 0x22 182 /* On 915+ */ 183 #define DEVICE_TYPE_CRT_DPMS 0x6001 184 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 185 #define DEVICE_TYPE_TV_COMPOSITE 0x0209 186 #define DEVICE_TYPE_TV_MACROVISION 0x0289 187 #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c 188 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 189 #define DEVICE_TYPE_TV_SCART 0x0209 190 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 191 #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 192 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 193 #define DEVICE_TYPE_EFP_DVI_I 0x6053 194 #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 195 #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 196 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 197 #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 198 #define DEVICE_TYPE_LFP_PANELLINK 0x5012 199 #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 200 #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 201 #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 202 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 203 204 /* Add the device class for LFP, TV, HDMI */ 205 #define DEVICE_TYPE_INT_LFP 0x1022 206 #define DEVICE_TYPE_INT_TV 0x1009 207 #define DEVICE_TYPE_HDMI 0x60D2 208 #define DEVICE_TYPE_DP 0x68C6 209 #define DEVICE_TYPE_DP_DUAL_MODE 0x60D6 210 #define DEVICE_TYPE_eDP 0x78C6 211 212 #define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) 213 #define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) 214 #define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) 215 #define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) 216 #define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) 217 #define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) 218 #define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) 219 #define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) 220 #define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) 221 #define DEVICE_TYPE_LVDS_SIGNALING (1 << 5) 222 #define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) 223 #define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) 224 #define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) 225 #define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) 226 #define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) 227 228 /* 229 * Bits we care about when checking for DEVICE_TYPE_eDP. Depending on the 230 * system, the other bits may or may not be set for eDP outputs. 231 */ 232 #define DEVICE_TYPE_eDP_BITS \ 233 (DEVICE_TYPE_INTERNAL_CONNECTOR | \ 234 DEVICE_TYPE_MIPI_OUTPUT | \ 235 DEVICE_TYPE_COMPOSITE_OUTPUT | \ 236 DEVICE_TYPE_DUAL_CHANNEL | \ 237 DEVICE_TYPE_LVDS_SIGNALING | \ 238 DEVICE_TYPE_TMDS_DVI_SIGNALING | \ 239 DEVICE_TYPE_VIDEO_SIGNALING | \ 240 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ 241 DEVICE_TYPE_ANALOG_OUTPUT) 242 243 #define DEVICE_TYPE_DP_DUAL_MODE_BITS \ 244 (DEVICE_TYPE_INTERNAL_CONNECTOR | \ 245 DEVICE_TYPE_MIPI_OUTPUT | \ 246 DEVICE_TYPE_COMPOSITE_OUTPUT | \ 247 DEVICE_TYPE_LVDS_SIGNALING | \ 248 DEVICE_TYPE_TMDS_DVI_SIGNALING | \ 249 DEVICE_TYPE_VIDEO_SIGNALING | \ 250 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ 251 DEVICE_TYPE_DIGITAL_OUTPUT | \ 252 DEVICE_TYPE_ANALOG_OUTPUT) 253 254 #define DEVICE_CFG_NONE 0x00 255 #define DEVICE_CFG_12BIT_DVOB 0x01 256 #define DEVICE_CFG_12BIT_DVOC 0x02 257 #define DEVICE_CFG_24BIT_DVOBC 0x09 258 #define DEVICE_CFG_24BIT_DVOCB 0x0a 259 #define DEVICE_CFG_DUAL_DVOB 0x11 260 #define DEVICE_CFG_DUAL_DVOC 0x12 261 #define DEVICE_CFG_DUAL_DVOBC 0x13 262 #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 263 #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a 264 265 #define DEVICE_WIRE_NONE 0x00 266 #define DEVICE_WIRE_DVOB 0x01 267 #define DEVICE_WIRE_DVOC 0x02 268 #define DEVICE_WIRE_DVOBC 0x03 269 #define DEVICE_WIRE_DVOBB 0x05 270 #define DEVICE_WIRE_DVOCC 0x06 271 #define DEVICE_WIRE_DVOB_MASTER 0x0d 272 #define DEVICE_WIRE_DVOC_MASTER 0x0e 273 274 /* dvo_port pre BDB 155 */ 275 #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ 276 #define DEVICE_PORT_DVOB 0x01 277 #define DEVICE_PORT_DVOC 0x02 278 279 /* dvo_port BDB 155+ */ 280 #define DVO_PORT_HDMIA 0 281 #define DVO_PORT_HDMIB 1 282 #define DVO_PORT_HDMIC 2 283 #define DVO_PORT_HDMID 3 284 #define DVO_PORT_LVDS 4 285 #define DVO_PORT_TV 5 286 #define DVO_PORT_CRT 6 287 #define DVO_PORT_DPB 7 288 #define DVO_PORT_DPC 8 289 #define DVO_PORT_DPD 9 290 #define DVO_PORT_DPA 10 291 #define DVO_PORT_DPE 11 /* 193 */ 292 #define DVO_PORT_HDMIE 12 /* 193 */ 293 #define DVO_PORT_DPF 13 /* N/A */ 294 #define DVO_PORT_HDMIF 14 /* N/A */ 295 #define DVO_PORT_DPG 15 296 #define DVO_PORT_HDMIG 16 297 #define DVO_PORT_MIPIA 21 /* 171 */ 298 #define DVO_PORT_MIPIB 22 /* 171 */ 299 #define DVO_PORT_MIPIC 23 /* 171 */ 300 #define DVO_PORT_MIPID 24 /* 171 */ 301 302 #define HDMI_MAX_DATA_RATE_PLATFORM 0 /* 204 */ 303 #define HDMI_MAX_DATA_RATE_297 1 /* 204 */ 304 #define HDMI_MAX_DATA_RATE_165 2 /* 204 */ 305 306 #define LEGACY_CHILD_DEVICE_CONFIG_SIZE 33 307 308 /* DDC Bus DDI Type 155+ */ 309 enum vbt_gmbus_ddi { 310 DDC_BUS_DDI_B = 0x1, 311 DDC_BUS_DDI_C, 312 DDC_BUS_DDI_D, 313 DDC_BUS_DDI_F, 314 ICL_DDC_BUS_DDI_A = 0x1, 315 ICL_DDC_BUS_DDI_B, 316 TGL_DDC_BUS_DDI_C, 317 ICL_DDC_BUS_PORT_1 = 0x4, 318 ICL_DDC_BUS_PORT_2, 319 ICL_DDC_BUS_PORT_3, 320 ICL_DDC_BUS_PORT_4, 321 TGL_DDC_BUS_PORT_5, 322 TGL_DDC_BUS_PORT_6, 323 }; 324 325 #define DP_AUX_A 0x40 326 #define DP_AUX_B 0x10 327 #define DP_AUX_C 0x20 328 #define DP_AUX_D 0x30 329 #define DP_AUX_E 0x50 330 #define DP_AUX_F 0x60 331 #define DP_AUX_G 0x70 332 333 #define VBT_DP_MAX_LINK_RATE_HBR3 0 334 #define VBT_DP_MAX_LINK_RATE_HBR2 1 335 #define VBT_DP_MAX_LINK_RATE_HBR 2 336 #define VBT_DP_MAX_LINK_RATE_LBR 3 337 338 /* 339 * The child device config, aka the display device data structure, provides a 340 * description of a port and its configuration on the platform. 341 * 342 * The child device config size has been increased, and fields have been added 343 * and their meaning has changed over time. Care must be taken when accessing 344 * basically any of the fields to ensure the correct interpretation for the BDB 345 * version in question. 346 * 347 * When we copy the child device configs to dev_priv->vbt.child_dev, we reserve 348 * space for the full structure below, and initialize the tail not actually 349 * present in VBT to zeros. Accessing those fields is fine, as long as the 350 * default zero is taken into account, again according to the BDB version. 351 * 352 * BDB versions 155 and below are considered legacy, and version 155 seems to be 353 * a baseline for some of the VBT documentation. When adding new fields, please 354 * include the BDB version when the field was added, if it's above that. 355 */ 356 struct child_device_config { 357 u16 handle; 358 u16 device_type; /* See DEVICE_TYPE_* above */ 359 360 union { 361 u8 device_id[10]; /* ascii string */ 362 struct { 363 u8 i2c_speed; 364 u8 dp_onboard_redriver; /* 158 */ 365 u8 dp_ondock_redriver; /* 158 */ 366 u8 hdmi_level_shifter_value:5; /* 169 */ 367 u8 hdmi_max_data_rate:3; /* 204 */ 368 u16 dtd_buf_ptr; /* 161 */ 369 u8 edidless_efp:1; /* 161 */ 370 u8 compression_enable:1; /* 198 */ 371 u8 compression_method:1; /* 198 */ 372 u8 ganged_edp:1; /* 202 */ 373 u8 reserved0:4; 374 u8 compression_structure_index:4; /* 198 */ 375 u8 reserved1:4; 376 u8 slave_port; /* 202 */ 377 u8 reserved2; 378 } __packed; 379 } __packed; 380 381 u16 addin_offset; 382 u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */ 383 u8 i2c_pin; 384 u8 slave_addr; 385 u8 ddc_pin; 386 u16 edid_ptr; 387 u8 dvo_cfg; /* See DEVICE_CFG_* above */ 388 389 union { 390 struct { 391 u8 dvo2_port; 392 u8 i2c2_pin; 393 u8 slave2_addr; 394 u8 ddc2_pin; 395 } __packed; 396 struct { 397 u8 efp_routed:1; /* 158 */ 398 u8 lane_reversal:1; /* 184 */ 399 u8 lspcon:1; /* 192 */ 400 u8 iboost:1; /* 196 */ 401 u8 hpd_invert:1; /* 196 */ 402 u8 use_vbt_vswing:1; /* 218 */ 403 u8 flag_reserved:2; 404 u8 hdmi_support:1; /* 158 */ 405 u8 dp_support:1; /* 158 */ 406 u8 tmds_support:1; /* 158 */ 407 u8 support_reserved:5; 408 u8 aux_channel; 409 u8 dongle_detect; 410 } __packed; 411 } __packed; 412 413 u8 pipe_cap:2; 414 u8 sdvo_stall:1; /* 158 */ 415 u8 hpd_status:2; 416 u8 integrated_encoder:1; 417 u8 capabilities_reserved:2; 418 u8 dvo_wiring; /* See DEVICE_WIRE_* above */ 419 420 union { 421 u8 dvo2_wiring; 422 u8 mipi_bridge_type; /* 171 */ 423 } __packed; 424 425 u16 extended_type; 426 u8 dvo_function; 427 u8 dp_usb_type_c:1; /* 195 */ 428 u8 tbt:1; /* 209 */ 429 u8 flags2_reserved:2; /* 195 */ 430 u8 dp_port_trace_length:4; /* 209 */ 431 u8 dp_gpio_index; /* 195 */ 432 u16 dp_gpio_pin_num; /* 195 */ 433 u8 dp_iboost_level:4; /* 196 */ 434 u8 hdmi_iboost_level:4; /* 196 */ 435 u8 dp_max_link_rate:2; /* 216 CNL+ */ 436 u8 dp_max_link_rate_reserved:6; /* 216 */ 437 } __packed; 438 439 struct bdb_general_definitions { 440 /* DDC GPIO */ 441 u8 crt_ddc_gmbus_pin; 442 443 /* DPMS bits */ 444 u8 dpms_acpi:1; 445 u8 skip_boot_crt_detect:1; 446 u8 dpms_aim:1; 447 u8 rsvd1:5; /* finish byte */ 448 449 /* boot device bits */ 450 u8 boot_display[2]; 451 u8 child_dev_size; 452 453 /* 454 * Device info: 455 * If TV is present, it'll be at devices[0]. 456 * LVDS will be next, either devices[0] or [1], if present. 457 * On some platforms the number of device is 6. But could be as few as 458 * 4 if both TV and LVDS are missing. 459 * And the device num is related with the size of general definition 460 * block. It is obtained by using the following formula: 461 * number = (block_size - sizeof(bdb_general_definitions))/ 462 * defs->child_dev_size; 463 */ 464 u8 devices[0]; 465 } __packed; 466 467 /* 468 * Block 9 - SRD Feature Block 469 */ 470 471 struct psr_table { 472 /* Feature bits */ 473 u8 full_link:1; 474 u8 require_aux_to_wakeup:1; 475 u8 feature_bits_rsvd:6; 476 477 /* Wait times */ 478 u8 idle_frames:4; 479 u8 lines_to_wait:3; 480 u8 wait_times_rsvd:1; 481 482 /* TP wake up time in multiple of 100 */ 483 u16 tp1_wakeup_time; 484 u16 tp2_tp3_wakeup_time; 485 } __packed; 486 487 struct bdb_psr { 488 struct psr_table psr_table[16]; 489 490 /* PSR2 TP2/TP3 wakeup time for 16 panels */ 491 u32 psr2_tp2_tp3_wakeup_time; 492 } __packed; 493 494 /* 495 * Block 12 - Driver Features Data Block 496 */ 497 498 #define BDB_DRIVER_FEATURE_NO_LVDS 0 499 #define BDB_DRIVER_FEATURE_INT_LVDS 1 500 #define BDB_DRIVER_FEATURE_SDVO_LVDS 2 501 #define BDB_DRIVER_FEATURE_INT_SDVO_LVDS 3 502 503 struct bdb_driver_features { 504 u8 boot_dev_algorithm:1; 505 u8 block_display_switch:1; 506 u8 allow_display_switch:1; 507 u8 hotplug_dvo:1; 508 u8 dual_view_zoom:1; 509 u8 int15h_hook:1; 510 u8 sprite_in_clone:1; 511 u8 primary_lfp_id:1; 512 513 u16 boot_mode_x; 514 u16 boot_mode_y; 515 u8 boot_mode_bpp; 516 u8 boot_mode_refresh; 517 518 u16 enable_lfp_primary:1; 519 u16 selective_mode_pruning:1; 520 u16 dual_frequency:1; 521 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ 522 u16 nt_clone_support:1; 523 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ 524 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ 525 u16 cui_aspect_scaling:1; 526 u16 preserve_aspect_ratio:1; 527 u16 sdvo_device_power_down:1; 528 u16 crt_hotplug:1; 529 u16 lvds_config:2; 530 u16 tv_hotplug:1; 531 u16 hdmi_config:2; 532 533 u8 static_display:1; 534 u8 reserved2:7; 535 u16 legacy_crt_max_x; 536 u16 legacy_crt_max_y; 537 u8 legacy_crt_max_refresh; 538 539 u8 hdmi_termination; 540 u8 custom_vbt_version; 541 /* Driver features data block */ 542 u16 rmpm_enabled:1; 543 u16 s2ddt_enabled:1; 544 u16 dpst_enabled:1; 545 u16 bltclt_enabled:1; 546 u16 adb_enabled:1; 547 u16 drrs_enabled:1; 548 u16 grs_enabled:1; 549 u16 gpmt_enabled:1; 550 u16 tbt_enabled:1; 551 u16 psr_enabled:1; 552 u16 ips_enabled:1; 553 u16 reserved3:4; 554 u16 pc_feature_valid:1; 555 } __packed; 556 557 /* 558 * Block 22 - SDVO LVDS General Options 559 */ 560 561 struct bdb_sdvo_lvds_options { 562 u8 panel_backlight; 563 u8 h40_set_panel_type; 564 u8 panel_type; 565 u8 ssc_clk_freq; 566 u16 als_low_trip; 567 u16 als_high_trip; 568 u8 sclalarcoeff_tab_row_num; 569 u8 sclalarcoeff_tab_row_size; 570 u8 coefficient[8]; 571 u8 panel_misc_bits_1; 572 u8 panel_misc_bits_2; 573 u8 panel_misc_bits_3; 574 u8 panel_misc_bits_4; 575 } __packed; 576 577 /* 578 * Block 23 - SDVO LVDS Panel DTDs 579 */ 580 581 struct lvds_dvo_timing { 582 u16 clock; /**< In 10khz */ 583 u8 hactive_lo; 584 u8 hblank_lo; 585 u8 hblank_hi:4; 586 u8 hactive_hi:4; 587 u8 vactive_lo; 588 u8 vblank_lo; 589 u8 vblank_hi:4; 590 u8 vactive_hi:4; 591 u8 hsync_off_lo; 592 u8 hsync_pulse_width_lo; 593 u8 vsync_pulse_width_lo:4; 594 u8 vsync_off_lo:4; 595 u8 vsync_pulse_width_hi:2; 596 u8 vsync_off_hi:2; 597 u8 hsync_pulse_width_hi:2; 598 u8 hsync_off_hi:2; 599 u8 himage_lo; 600 u8 vimage_lo; 601 u8 vimage_hi:4; 602 u8 himage_hi:4; 603 u8 h_border; 604 u8 v_border; 605 u8 rsvd1:3; 606 u8 digital:2; 607 u8 vsync_positive:1; 608 u8 hsync_positive:1; 609 u8 non_interlaced:1; 610 } __packed; 611 612 struct bdb_sdvo_panel_dtds { 613 struct lvds_dvo_timing dtds[4]; 614 } __packed; 615 616 /* 617 * Block 27 - eDP VBT Block 618 */ 619 620 #define EDP_18BPP 0 621 #define EDP_24BPP 1 622 #define EDP_30BPP 2 623 #define EDP_RATE_1_62 0 624 #define EDP_RATE_2_7 1 625 #define EDP_LANE_1 0 626 #define EDP_LANE_2 1 627 #define EDP_LANE_4 3 628 #define EDP_PREEMPHASIS_NONE 0 629 #define EDP_PREEMPHASIS_3_5dB 1 630 #define EDP_PREEMPHASIS_6dB 2 631 #define EDP_PREEMPHASIS_9_5dB 3 632 #define EDP_VSWING_0_4V 0 633 #define EDP_VSWING_0_6V 1 634 #define EDP_VSWING_0_8V 2 635 #define EDP_VSWING_1_2V 3 636 637 638 struct edp_fast_link_params { 639 u8 rate:4; 640 u8 lanes:4; 641 u8 preemphasis:4; 642 u8 vswing:4; 643 } __packed; 644 645 struct edp_pwm_delays { 646 u16 pwm_on_to_backlight_enable; 647 u16 backlight_disable_to_pwm_off; 648 } __packed; 649 650 struct edp_full_link_params { 651 u8 preemphasis:4; 652 u8 vswing:4; 653 } __packed; 654 655 struct bdb_edp { 656 struct edp_power_seq power_seqs[16]; 657 u32 color_depth; 658 struct edp_fast_link_params fast_link_params[16]; 659 u32 sdrrs_msa_timing_delay; 660 661 /* ith bit indicates enabled/disabled for (i+1)th panel */ 662 u16 edp_s3d_feature; /* 162 */ 663 u16 edp_t3_optimization; /* 165 */ 664 u64 edp_vswing_preemph; /* 173 */ 665 u16 fast_link_training; /* 182 */ 666 u16 dpcd_600h_write_required; /* 185 */ 667 struct edp_pwm_delays pwm_delays[16]; /* 186 */ 668 u16 full_link_params_provided; /* 199 */ 669 struct edp_full_link_params full_link_params[16]; /* 199 */ 670 } __packed; 671 672 /* 673 * Block 40 - LFP Data Block 674 */ 675 676 /* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */ 677 #define MODE_MASK 0x3 678 679 struct bdb_lvds_options { 680 u8 panel_type; 681 u8 panel_type2; /* 212 */ 682 /* LVDS capabilities, stored in a dword */ 683 u8 pfit_mode:2; 684 u8 pfit_text_mode_enhanced:1; 685 u8 pfit_gfx_mode_enhanced:1; 686 u8 pfit_ratio_auto:1; 687 u8 pixel_dither:1; 688 u8 lvds_edid:1; 689 u8 rsvd2:1; 690 u8 rsvd4; 691 /* LVDS Panel channel bits stored here */ 692 u32 lvds_panel_channel_bits; 693 /* LVDS SSC (Spread Spectrum Clock) bits stored here. */ 694 u16 ssc_bits; 695 u16 ssc_freq; 696 u16 ssc_ddt; 697 /* Panel color depth defined here */ 698 u16 panel_color_depth; 699 /* LVDS panel type bits stored here */ 700 u32 dps_panel_type_bits; 701 /* LVDS backlight control type bits stored here */ 702 u32 blt_control_type_bits; 703 704 u16 lcdvcc_s0_enable; /* 200 */ 705 u32 rotation; /* 228 */ 706 } __packed; 707 708 /* 709 * Block 41 - LFP Data Table Pointers 710 */ 711 712 /* LFP pointer table contains entries to the struct below */ 713 struct lvds_lfp_data_ptr { 714 u16 fp_timing_offset; /* offsets are from start of bdb */ 715 u8 fp_table_size; 716 u16 dvo_timing_offset; 717 u8 dvo_table_size; 718 u16 panel_pnp_id_offset; 719 u8 pnp_table_size; 720 } __packed; 721 722 struct bdb_lvds_lfp_data_ptrs { 723 u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ 724 struct lvds_lfp_data_ptr ptr[16]; 725 } __packed; 726 727 /* 728 * Block 42 - LFP Data Tables 729 */ 730 731 /* LFP data has 3 blocks per entry */ 732 struct lvds_fp_timing { 733 u16 x_res; 734 u16 y_res; 735 u32 lvds_reg; 736 u32 lvds_reg_val; 737 u32 pp_on_reg; 738 u32 pp_on_reg_val; 739 u32 pp_off_reg; 740 u32 pp_off_reg_val; 741 u32 pp_cycle_reg; 742 u32 pp_cycle_reg_val; 743 u32 pfit_reg; 744 u32 pfit_reg_val; 745 u16 terminator; 746 } __packed; 747 748 struct lvds_pnp_id { 749 u16 mfg_name; 750 u16 product_code; 751 u32 serial; 752 u8 mfg_week; 753 u8 mfg_year; 754 } __packed; 755 756 struct lvds_lfp_data_entry { 757 struct lvds_fp_timing fp_timing; 758 struct lvds_dvo_timing dvo_timing; 759 struct lvds_pnp_id pnp_id; 760 } __packed; 761 762 struct bdb_lvds_lfp_data { 763 struct lvds_lfp_data_entry data[16]; 764 } __packed; 765 766 /* 767 * Block 43 - LFP Backlight Control Data Block 768 */ 769 770 #define BDB_BACKLIGHT_TYPE_NONE 0 771 #define BDB_BACKLIGHT_TYPE_PWM 2 772 773 struct lfp_backlight_data_entry { 774 u8 type:2; 775 u8 active_low_pwm:1; 776 u8 obsolete1:5; 777 u16 pwm_freq_hz; 778 u8 min_brightness; 779 u8 obsolete2; 780 u8 obsolete3; 781 } __packed; 782 783 struct lfp_backlight_control_method { 784 u8 type:4; 785 u8 controller:4; 786 } __packed; 787 788 struct bdb_lfp_backlight_data { 789 u8 entry_size; 790 struct lfp_backlight_data_entry data[16]; 791 u8 level[16]; 792 struct lfp_backlight_control_method backlight_control[16]; 793 } __packed; 794 795 /* 796 * Block 52 - MIPI Configuration Block 797 */ 798 799 #define MAX_MIPI_CONFIGURATIONS 6 800 801 struct bdb_mipi_config { 802 struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; 803 struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; 804 } __packed; 805 806 /* 807 * Block 53 - MIPI Sequence Block 808 */ 809 810 struct bdb_mipi_sequence { 811 u8 version; 812 u8 data[0]; /* up to 6 variable length blocks */ 813 } __packed; 814 815 /* 816 * Block 56 - Compression Parameters 817 */ 818 819 #define VBT_RC_BUFFER_BLOCK_SIZE_1KB 0 820 #define VBT_RC_BUFFER_BLOCK_SIZE_4KB 1 821 #define VBT_RC_BUFFER_BLOCK_SIZE_16KB 2 822 #define VBT_RC_BUFFER_BLOCK_SIZE_64KB 3 823 824 #define VBT_DSC_LINE_BUFFER_DEPTH(vbt_value) ((vbt_value) + 8) /* bits */ 825 #define VBT_DSC_MAX_BPP(vbt_value) (6 + (vbt_value) * 2) 826 827 struct dsc_compression_parameters_entry { 828 u8 version_major:4; 829 u8 version_minor:4; 830 831 u8 rc_buffer_block_size:2; 832 u8 reserved1:6; 833 834 /* 835 * Buffer size in bytes: 836 * 837 * 4 ^ rc_buffer_block_size * 1024 * (rc_buffer_size + 1) bytes 838 */ 839 u8 rc_buffer_size; 840 u32 slices_per_line; 841 842 u8 line_buffer_depth:4; 843 u8 reserved2:4; 844 845 /* Flag Bits 1 */ 846 u8 block_prediction_enable:1; 847 u8 reserved3:7; 848 849 u8 max_bpp; /* mapping */ 850 851 /* Color depth capabilities */ 852 u8 reserved4:1; 853 u8 support_8bpc:1; 854 u8 support_10bpc:1; 855 u8 support_12bpc:1; 856 u8 reserved5:4; 857 858 u16 slice_height; 859 } __packed; 860 861 struct bdb_compression_parameters { 862 u16 entry_size; 863 struct dsc_compression_parameters_entry data[16]; 864 } __packed; 865 866 #endif /* _INTEL_VBT_DEFS_H_ */ 867