1 /*
2  * Copyright © 2006-2016 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *
26  */
27 
28 /*
29  * This information is private to VBT parsing in intel_bios.c.
30  *
31  * Please do NOT include anywhere else.
32  */
33 #ifndef _INTEL_BIOS_PRIVATE
34 #error "intel_vbt_defs.h is private to intel_bios.c"
35 #endif
36 
37 #ifndef _INTEL_VBT_DEFS_H_
38 #define _INTEL_VBT_DEFS_H_
39 
40 #include "intel_bios.h"
41 
42 /**
43  * struct vbt_header - VBT Header structure
44  * @signature:		VBT signature, always starts with "$VBT"
45  * @version:		Version of this structure
46  * @header_size:	Size of this structure
47  * @vbt_size:		Size of VBT (VBT Header, BDB Header and data blocks)
48  * @vbt_checksum:	Checksum
49  * @reserved0:		Reserved
50  * @bdb_offset:		Offset of &struct bdb_header from beginning of VBT
51  * @aim_offset:		Offsets of add-in data blocks from beginning of VBT
52  */
53 struct vbt_header {
54 	u8 signature[20];
55 	u16 version;
56 	u16 header_size;
57 	u16 vbt_size;
58 	u8 vbt_checksum;
59 	u8 reserved0;
60 	u32 bdb_offset;
61 	u32 aim_offset[4];
62 } __packed;
63 
64 /**
65  * struct bdb_header - BDB Header structure
66  * @signature:		BDB signature "BIOS_DATA_BLOCK"
67  * @version:		Version of the data block definitions
68  * @header_size:	Size of this structure
69  * @bdb_size:		Size of BDB (BDB Header and data blocks)
70  */
71 struct bdb_header {
72 	u8 signature[16];
73 	u16 version;
74 	u16 header_size;
75 	u16 bdb_size;
76 } __packed;
77 
78 /*
79  * There are several types of BIOS data blocks (BDBs), each block has
80  * an ID and size in the first 3 bytes (ID in first, size in next 2).
81  * Known types are listed below.
82  */
83 enum bdb_block_id {
84 	BDB_GENERAL_FEATURES		= 1,
85 	BDB_GENERAL_DEFINITIONS		= 2,
86 	BDB_OLD_TOGGLE_LIST		= 3,
87 	BDB_MODE_SUPPORT_LIST		= 4,
88 	BDB_GENERIC_MODE_TABLE		= 5,
89 	BDB_EXT_MMIO_REGS		= 6,
90 	BDB_SWF_IO			= 7,
91 	BDB_SWF_MMIO			= 8,
92 	BDB_PSR				= 9,
93 	BDB_MODE_REMOVAL_TABLE		= 10,
94 	BDB_CHILD_DEVICE_TABLE		= 11,
95 	BDB_DRIVER_FEATURES		= 12,
96 	BDB_DRIVER_PERSISTENCE		= 13,
97 	BDB_EXT_TABLE_PTRS		= 14,
98 	BDB_DOT_CLOCK_OVERRIDE		= 15,
99 	BDB_DISPLAY_SELECT		= 16,
100 	BDB_DRIVER_ROTATION		= 18,
101 	BDB_DISPLAY_REMOVE		= 19,
102 	BDB_OEM_CUSTOM			= 20,
103 	BDB_EFP_LIST			= 21, /* workarounds for VGA hsync/vsync */
104 	BDB_SDVO_LVDS_OPTIONS		= 22,
105 	BDB_SDVO_PANEL_DTDS		= 23,
106 	BDB_SDVO_LVDS_PNP_IDS		= 24,
107 	BDB_SDVO_LVDS_POWER_SEQ		= 25,
108 	BDB_TV_OPTIONS			= 26,
109 	BDB_EDP				= 27,
110 	BDB_LVDS_OPTIONS		= 40,
111 	BDB_LVDS_LFP_DATA_PTRS		= 41,
112 	BDB_LVDS_LFP_DATA		= 42,
113 	BDB_LVDS_BACKLIGHT		= 43,
114 	BDB_LFP_POWER			= 44,
115 	BDB_MIPI_CONFIG			= 52,
116 	BDB_MIPI_SEQUENCE		= 53,
117 	BDB_COMPRESSION_PARAMETERS	= 56,
118 	BDB_GENERIC_DTD			= 58,
119 	BDB_SKIP			= 254, /* VBIOS private block, ignore */
120 };
121 
122 /*
123  * Block 1 - General Bit Definitions
124  */
125 
126 struct bdb_general_features {
127         /* bits 1 */
128 	u8 panel_fitting:2;
129 	u8 flexaim:1;
130 	u8 msg_enable:1;
131 	u8 clear_screen:3;
132 	u8 color_flip:1;
133 
134         /* bits 2 */
135 	u8 download_ext_vbt:1;
136 	u8 enable_ssc:1;
137 	u8 ssc_freq:1;
138 	u8 enable_lfp_on_override:1;
139 	u8 disable_ssc_ddt:1;
140 	u8 underscan_vga_timings:1;
141 	u8 display_clock_mode:1;
142 	u8 vbios_hotplug_support:1;
143 
144         /* bits 3 */
145 	u8 disable_smooth_vision:1;
146 	u8 single_dvi:1;
147 	u8 rotate_180:1;					/* 181 */
148 	u8 fdi_rx_polarity_inverted:1;
149 	u8 vbios_extended_mode:1;				/* 160 */
150 	u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1;			/* 160 */
151 	u8 panel_best_fit_timing:1;				/* 160 */
152 	u8 ignore_strap_state:1;				/* 160 */
153 
154         /* bits 4 */
155 	u8 legacy_monitor_detect;
156 
157         /* bits 5 */
158 	u8 int_crt_support:1;
159 	u8 int_tv_support:1;
160 	u8 int_efp_support:1;
161 	u8 dp_ssc_enable:1;	/* PCH attached eDP supports SSC */
162 	u8 dp_ssc_freq:1;	/* SSC freq for PCH attached eDP */
163 	u8 dp_ssc_dongle_supported:1;
164 	u8 rsvd11:2; /* finish byte */
165 } __packed;
166 
167 /*
168  * Block 2 - General Bytes Definition
169  */
170 
171 /* pre-915 */
172 #define GPIO_PIN_DVI_LVDS	0x03 /* "DVI/LVDS DDC GPIO pins" */
173 #define GPIO_PIN_ADD_I2C	0x05 /* "ADDCARD I2C GPIO pins" */
174 #define GPIO_PIN_ADD_DDC	0x04 /* "ADDCARD DDC GPIO pins" */
175 #define GPIO_PIN_ADD_DDC_I2C	0x06 /* "ADDCARD DDC/I2C GPIO pins" */
176 
177 /* Pre 915 */
178 #define DEVICE_TYPE_NONE	0x00
179 #define DEVICE_TYPE_CRT		0x01
180 #define DEVICE_TYPE_TV		0x09
181 #define DEVICE_TYPE_EFP		0x12
182 #define DEVICE_TYPE_LFP		0x22
183 /* On 915+ */
184 #define DEVICE_TYPE_CRT_DPMS		0x6001
185 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG	0x4001
186 #define DEVICE_TYPE_TV_COMPOSITE	0x0209
187 #define DEVICE_TYPE_TV_MACROVISION	0x0289
188 #define DEVICE_TYPE_TV_RF_COMPOSITE	0x020c
189 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE	0x0609
190 #define DEVICE_TYPE_TV_SCART		0x0209
191 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
192 #define DEVICE_TYPE_EFP_HOTPLUG_PWR	0x6012
193 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR	0x6052
194 #define DEVICE_TYPE_EFP_DVI_I		0x6053
195 #define DEVICE_TYPE_EFP_DVI_D_DUAL	0x6152
196 #define DEVICE_TYPE_EFP_DVI_D_HDCP	0x60d2
197 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR	0x6062
198 #define DEVICE_TYPE_OPENLDI_DUALPIX	0x6162
199 #define DEVICE_TYPE_LFP_PANELLINK	0x5012
200 #define DEVICE_TYPE_LFP_CMOS_PWR	0x5042
201 #define DEVICE_TYPE_LFP_LVDS_PWR	0x5062
202 #define DEVICE_TYPE_LFP_LVDS_DUAL	0x5162
203 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP	0x51e2
204 
205 /* Add the device class for LFP, TV, HDMI */
206 #define DEVICE_TYPE_INT_LFP		0x1022
207 #define DEVICE_TYPE_INT_TV		0x1009
208 #define DEVICE_TYPE_HDMI		0x60D2
209 #define DEVICE_TYPE_DP			0x68C6
210 #define DEVICE_TYPE_DP_DUAL_MODE	0x60D6
211 #define DEVICE_TYPE_eDP			0x78C6
212 
213 #define DEVICE_TYPE_CLASS_EXTENSION	(1 << 15)
214 #define DEVICE_TYPE_POWER_MANAGEMENT	(1 << 14)
215 #define DEVICE_TYPE_HOTPLUG_SIGNALING	(1 << 13)
216 #define DEVICE_TYPE_INTERNAL_CONNECTOR	(1 << 12)
217 #define DEVICE_TYPE_NOT_HDMI_OUTPUT	(1 << 11)
218 #define DEVICE_TYPE_MIPI_OUTPUT		(1 << 10)
219 #define DEVICE_TYPE_COMPOSITE_OUTPUT	(1 << 9)
220 #define DEVICE_TYPE_DUAL_CHANNEL	(1 << 8)
221 #define DEVICE_TYPE_HIGH_SPEED_LINK	(1 << 6)
222 #define DEVICE_TYPE_LVDS_SIGNALING	(1 << 5)
223 #define DEVICE_TYPE_TMDS_DVI_SIGNALING	(1 << 4)
224 #define DEVICE_TYPE_VIDEO_SIGNALING	(1 << 3)
225 #define DEVICE_TYPE_DISPLAYPORT_OUTPUT	(1 << 2)
226 #define DEVICE_TYPE_DIGITAL_OUTPUT	(1 << 1)
227 #define DEVICE_TYPE_ANALOG_OUTPUT	(1 << 0)
228 
229 /*
230  * Bits we care about when checking for DEVICE_TYPE_eDP. Depending on the
231  * system, the other bits may or may not be set for eDP outputs.
232  */
233 #define DEVICE_TYPE_eDP_BITS \
234 	(DEVICE_TYPE_INTERNAL_CONNECTOR |	\
235 	 DEVICE_TYPE_MIPI_OUTPUT |		\
236 	 DEVICE_TYPE_COMPOSITE_OUTPUT |		\
237 	 DEVICE_TYPE_DUAL_CHANNEL |		\
238 	 DEVICE_TYPE_LVDS_SIGNALING |		\
239 	 DEVICE_TYPE_TMDS_DVI_SIGNALING |	\
240 	 DEVICE_TYPE_VIDEO_SIGNALING |		\
241 	 DEVICE_TYPE_DISPLAYPORT_OUTPUT |	\
242 	 DEVICE_TYPE_ANALOG_OUTPUT)
243 
244 #define DEVICE_TYPE_DP_DUAL_MODE_BITS \
245 	(DEVICE_TYPE_INTERNAL_CONNECTOR |	\
246 	 DEVICE_TYPE_MIPI_OUTPUT |		\
247 	 DEVICE_TYPE_COMPOSITE_OUTPUT |		\
248 	 DEVICE_TYPE_LVDS_SIGNALING |		\
249 	 DEVICE_TYPE_TMDS_DVI_SIGNALING |	\
250 	 DEVICE_TYPE_VIDEO_SIGNALING |		\
251 	 DEVICE_TYPE_DISPLAYPORT_OUTPUT |	\
252 	 DEVICE_TYPE_DIGITAL_OUTPUT |		\
253 	 DEVICE_TYPE_ANALOG_OUTPUT)
254 
255 #define DEVICE_CFG_NONE		0x00
256 #define DEVICE_CFG_12BIT_DVOB	0x01
257 #define DEVICE_CFG_12BIT_DVOC	0x02
258 #define DEVICE_CFG_24BIT_DVOBC	0x09
259 #define DEVICE_CFG_24BIT_DVOCB	0x0a
260 #define DEVICE_CFG_DUAL_DVOB	0x11
261 #define DEVICE_CFG_DUAL_DVOC	0x12
262 #define DEVICE_CFG_DUAL_DVOBC	0x13
263 #define DEVICE_CFG_DUAL_LINK_DVOBC	0x19
264 #define DEVICE_CFG_DUAL_LINK_DVOCB	0x1a
265 
266 #define DEVICE_WIRE_NONE	0x00
267 #define DEVICE_WIRE_DVOB	0x01
268 #define DEVICE_WIRE_DVOC	0x02
269 #define DEVICE_WIRE_DVOBC	0x03
270 #define DEVICE_WIRE_DVOBB	0x05
271 #define DEVICE_WIRE_DVOCC	0x06
272 #define DEVICE_WIRE_DVOB_MASTER 0x0d
273 #define DEVICE_WIRE_DVOC_MASTER 0x0e
274 
275 /* dvo_port pre BDB 155 */
276 #define DEVICE_PORT_DVOA	0x00 /* none on 845+ */
277 #define DEVICE_PORT_DVOB	0x01
278 #define DEVICE_PORT_DVOC	0x02
279 
280 /* dvo_port BDB 155+ */
281 #define DVO_PORT_HDMIA		0
282 #define DVO_PORT_HDMIB		1
283 #define DVO_PORT_HDMIC		2
284 #define DVO_PORT_HDMID		3
285 #define DVO_PORT_LVDS		4
286 #define DVO_PORT_TV		5
287 #define DVO_PORT_CRT		6
288 #define DVO_PORT_DPB		7
289 #define DVO_PORT_DPC		8
290 #define DVO_PORT_DPD		9
291 #define DVO_PORT_DPA		10
292 #define DVO_PORT_DPE		11				/* 193 */
293 #define DVO_PORT_HDMIE		12				/* 193 */
294 #define DVO_PORT_DPF		13				/* N/A */
295 #define DVO_PORT_HDMIF		14				/* N/A */
296 #define DVO_PORT_DPG		15
297 #define DVO_PORT_HDMIG		16
298 #define DVO_PORT_MIPIA		21				/* 171 */
299 #define DVO_PORT_MIPIB		22				/* 171 */
300 #define DVO_PORT_MIPIC		23				/* 171 */
301 #define DVO_PORT_MIPID		24				/* 171 */
302 
303 #define HDMI_MAX_DATA_RATE_PLATFORM	0			/* 204 */
304 #define HDMI_MAX_DATA_RATE_297		1			/* 204 */
305 #define HDMI_MAX_DATA_RATE_165		2			/* 204 */
306 
307 #define LEGACY_CHILD_DEVICE_CONFIG_SIZE		33
308 
309 /* DDC Bus DDI Type 155+ */
310 enum vbt_gmbus_ddi {
311 	DDC_BUS_DDI_B = 0x1,
312 	DDC_BUS_DDI_C,
313 	DDC_BUS_DDI_D,
314 	DDC_BUS_DDI_F,
315 	ICL_DDC_BUS_DDI_A = 0x1,
316 	ICL_DDC_BUS_DDI_B,
317 	TGL_DDC_BUS_DDI_C,
318 	ICL_DDC_BUS_PORT_1 = 0x4,
319 	ICL_DDC_BUS_PORT_2,
320 	ICL_DDC_BUS_PORT_3,
321 	ICL_DDC_BUS_PORT_4,
322 	TGL_DDC_BUS_PORT_5,
323 	TGL_DDC_BUS_PORT_6,
324 };
325 
326 #define DP_AUX_A 0x40
327 #define DP_AUX_B 0x10
328 #define DP_AUX_C 0x20
329 #define DP_AUX_D 0x30
330 #define DP_AUX_E 0x50
331 #define DP_AUX_F 0x60
332 #define DP_AUX_G 0x70
333 
334 #define VBT_DP_MAX_LINK_RATE_HBR3	0
335 #define VBT_DP_MAX_LINK_RATE_HBR2	1
336 #define VBT_DP_MAX_LINK_RATE_HBR	2
337 #define VBT_DP_MAX_LINK_RATE_LBR	3
338 
339 /*
340  * The child device config, aka the display device data structure, provides a
341  * description of a port and its configuration on the platform.
342  *
343  * The child device config size has been increased, and fields have been added
344  * and their meaning has changed over time. Care must be taken when accessing
345  * basically any of the fields to ensure the correct interpretation for the BDB
346  * version in question.
347  *
348  * When we copy the child device configs to dev_priv->vbt.child_dev, we reserve
349  * space for the full structure below, and initialize the tail not actually
350  * present in VBT to zeros. Accessing those fields is fine, as long as the
351  * default zero is taken into account, again according to the BDB version.
352  *
353  * BDB versions 155 and below are considered legacy, and version 155 seems to be
354  * a baseline for some of the VBT documentation. When adding new fields, please
355  * include the BDB version when the field was added, if it's above that.
356  */
357 struct child_device_config {
358 	u16 handle;
359 	u16 device_type; /* See DEVICE_TYPE_* above */
360 
361 	union {
362 		u8  device_id[10]; /* ascii string */
363 		struct {
364 			u8 i2c_speed;
365 			u8 dp_onboard_redriver;			/* 158 */
366 			u8 dp_ondock_redriver;			/* 158 */
367 			u8 hdmi_level_shifter_value:5;		/* 169 */
368 			u8 hdmi_max_data_rate:3;		/* 204 */
369 			u16 dtd_buf_ptr;			/* 161 */
370 			u8 edidless_efp:1;			/* 161 */
371 			u8 compression_enable:1;		/* 198 */
372 			u8 compression_method_cps:1;		/* 198 */
373 			u8 ganged_edp:1;			/* 202 */
374 			u8 reserved0:4;
375 			u8 compression_structure_index:4;	/* 198 */
376 			u8 reserved1:4;
377 			u8 slave_port;				/* 202 */
378 			u8 reserved2;
379 		} __packed;
380 	} __packed;
381 
382 	u16 addin_offset;
383 	u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */
384 	u8 i2c_pin;
385 	u8 slave_addr;
386 	u8 ddc_pin;
387 	u16 edid_ptr;
388 	u8 dvo_cfg; /* See DEVICE_CFG_* above */
389 
390 	union {
391 		struct {
392 			u8 dvo2_port;
393 			u8 i2c2_pin;
394 			u8 slave2_addr;
395 			u8 ddc2_pin;
396 		} __packed;
397 		struct {
398 			u8 efp_routed:1;			/* 158 */
399 			u8 lane_reversal:1;			/* 184 */
400 			u8 lspcon:1;				/* 192 */
401 			u8 iboost:1;				/* 196 */
402 			u8 hpd_invert:1;			/* 196 */
403 			u8 use_vbt_vswing:1;			/* 218 */
404 			u8 flag_reserved:2;
405 			u8 hdmi_support:1;			/* 158 */
406 			u8 dp_support:1;			/* 158 */
407 			u8 tmds_support:1;			/* 158 */
408 			u8 support_reserved:5;
409 			u8 aux_channel;
410 			u8 dongle_detect;
411 		} __packed;
412 	} __packed;
413 
414 	u8 pipe_cap:2;
415 	u8 sdvo_stall:1;					/* 158 */
416 	u8 hpd_status:2;
417 	u8 integrated_encoder:1;
418 	u8 capabilities_reserved:2;
419 	u8 dvo_wiring; /* See DEVICE_WIRE_* above */
420 
421 	union {
422 		u8 dvo2_wiring;
423 		u8 mipi_bridge_type;				/* 171 */
424 	} __packed;
425 
426 	u16 extended_type;
427 	u8 dvo_function;
428 	u8 dp_usb_type_c:1;					/* 195 */
429 	u8 tbt:1;						/* 209 */
430 	u8 flags2_reserved:2;					/* 195 */
431 	u8 dp_port_trace_length:4;				/* 209 */
432 	u8 dp_gpio_index;					/* 195 */
433 	u16 dp_gpio_pin_num;					/* 195 */
434 	u8 dp_iboost_level:4;					/* 196 */
435 	u8 hdmi_iboost_level:4;					/* 196 */
436 	u8 dp_max_link_rate:2;					/* 216 CNL+ */
437 	u8 dp_max_link_rate_reserved:6;				/* 216 */
438 } __packed;
439 
440 struct bdb_general_definitions {
441 	/* DDC GPIO */
442 	u8 crt_ddc_gmbus_pin;
443 
444 	/* DPMS bits */
445 	u8 dpms_acpi:1;
446 	u8 skip_boot_crt_detect:1;
447 	u8 dpms_aim:1;
448 	u8 rsvd1:5; /* finish byte */
449 
450 	/* boot device bits */
451 	u8 boot_display[2];
452 	u8 child_dev_size;
453 
454 	/*
455 	 * Device info:
456 	 * If TV is present, it'll be at devices[0].
457 	 * LVDS will be next, either devices[0] or [1], if present.
458 	 * On some platforms the number of device is 6. But could be as few as
459 	 * 4 if both TV and LVDS are missing.
460 	 * And the device num is related with the size of general definition
461 	 * block. It is obtained by using the following formula:
462 	 * number = (block_size - sizeof(bdb_general_definitions))/
463 	 *	     defs->child_dev_size;
464 	 */
465 	u8 devices[];
466 } __packed;
467 
468 /*
469  * Block 9 - SRD Feature Block
470  */
471 
472 struct psr_table {
473 	/* Feature bits */
474 	u8 full_link:1;
475 	u8 require_aux_to_wakeup:1;
476 	u8 feature_bits_rsvd:6;
477 
478 	/* Wait times */
479 	u8 idle_frames:4;
480 	u8 lines_to_wait:3;
481 	u8 wait_times_rsvd:1;
482 
483 	/* TP wake up time in multiple of 100 */
484 	u16 tp1_wakeup_time;
485 	u16 tp2_tp3_wakeup_time;
486 } __packed;
487 
488 struct bdb_psr {
489 	struct psr_table psr_table[16];
490 
491 	/* PSR2 TP2/TP3 wakeup time for 16 panels */
492 	u32 psr2_tp2_tp3_wakeup_time;
493 } __packed;
494 
495 /*
496  * Block 12 - Driver Features Data Block
497  */
498 
499 #define BDB_DRIVER_FEATURE_NO_LVDS		0
500 #define BDB_DRIVER_FEATURE_INT_LVDS		1
501 #define BDB_DRIVER_FEATURE_SDVO_LVDS		2
502 #define BDB_DRIVER_FEATURE_INT_SDVO_LVDS	3
503 
504 struct bdb_driver_features {
505 	u8 boot_dev_algorithm:1;
506 	u8 block_display_switch:1;
507 	u8 allow_display_switch:1;
508 	u8 hotplug_dvo:1;
509 	u8 dual_view_zoom:1;
510 	u8 int15h_hook:1;
511 	u8 sprite_in_clone:1;
512 	u8 primary_lfp_id:1;
513 
514 	u16 boot_mode_x;
515 	u16 boot_mode_y;
516 	u8 boot_mode_bpp;
517 	u8 boot_mode_refresh;
518 
519 	u16 enable_lfp_primary:1;
520 	u16 selective_mode_pruning:1;
521 	u16 dual_frequency:1;
522 	u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
523 	u16 nt_clone_support:1;
524 	u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
525 	u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
526 	u16 cui_aspect_scaling:1;
527 	u16 preserve_aspect_ratio:1;
528 	u16 sdvo_device_power_down:1;
529 	u16 crt_hotplug:1;
530 	u16 lvds_config:2;
531 	u16 tv_hotplug:1;
532 	u16 hdmi_config:2;
533 
534 	u8 static_display:1;
535 	u8 reserved2:7;
536 	u16 legacy_crt_max_x;
537 	u16 legacy_crt_max_y;
538 	u8 legacy_crt_max_refresh;
539 
540 	u8 hdmi_termination;
541 	u8 custom_vbt_version;
542 	/* Driver features data block */
543 	u16 rmpm_enabled:1;
544 	u16 s2ddt_enabled:1;
545 	u16 dpst_enabled:1;
546 	u16 bltclt_enabled:1;
547 	u16 adb_enabled:1;
548 	u16 drrs_enabled:1;
549 	u16 grs_enabled:1;
550 	u16 gpmt_enabled:1;
551 	u16 tbt_enabled:1;
552 	u16 psr_enabled:1;
553 	u16 ips_enabled:1;
554 	u16 reserved3:4;
555 	u16 pc_feature_valid:1;
556 } __packed;
557 
558 /*
559  * Block 22 - SDVO LVDS General Options
560  */
561 
562 struct bdb_sdvo_lvds_options {
563 	u8 panel_backlight;
564 	u8 h40_set_panel_type;
565 	u8 panel_type;
566 	u8 ssc_clk_freq;
567 	u16 als_low_trip;
568 	u16 als_high_trip;
569 	u8 sclalarcoeff_tab_row_num;
570 	u8 sclalarcoeff_tab_row_size;
571 	u8 coefficient[8];
572 	u8 panel_misc_bits_1;
573 	u8 panel_misc_bits_2;
574 	u8 panel_misc_bits_3;
575 	u8 panel_misc_bits_4;
576 } __packed;
577 
578 /*
579  * Block 23 - SDVO LVDS Panel DTDs
580  */
581 
582 struct lvds_dvo_timing {
583 	u16 clock;		/**< In 10khz */
584 	u8 hactive_lo;
585 	u8 hblank_lo;
586 	u8 hblank_hi:4;
587 	u8 hactive_hi:4;
588 	u8 vactive_lo;
589 	u8 vblank_lo;
590 	u8 vblank_hi:4;
591 	u8 vactive_hi:4;
592 	u8 hsync_off_lo;
593 	u8 hsync_pulse_width_lo;
594 	u8 vsync_pulse_width_lo:4;
595 	u8 vsync_off_lo:4;
596 	u8 vsync_pulse_width_hi:2;
597 	u8 vsync_off_hi:2;
598 	u8 hsync_pulse_width_hi:2;
599 	u8 hsync_off_hi:2;
600 	u8 himage_lo;
601 	u8 vimage_lo;
602 	u8 vimage_hi:4;
603 	u8 himage_hi:4;
604 	u8 h_border;
605 	u8 v_border;
606 	u8 rsvd1:3;
607 	u8 digital:2;
608 	u8 vsync_positive:1;
609 	u8 hsync_positive:1;
610 	u8 non_interlaced:1;
611 } __packed;
612 
613 struct bdb_sdvo_panel_dtds {
614 	struct lvds_dvo_timing dtds[4];
615 } __packed;
616 
617 /*
618  * Block 27 - eDP VBT Block
619  */
620 
621 #define EDP_18BPP	0
622 #define EDP_24BPP	1
623 #define EDP_30BPP	2
624 #define EDP_RATE_1_62	0
625 #define EDP_RATE_2_7	1
626 #define EDP_LANE_1	0
627 #define EDP_LANE_2	1
628 #define EDP_LANE_4	3
629 #define EDP_PREEMPHASIS_NONE	0
630 #define EDP_PREEMPHASIS_3_5dB	1
631 #define EDP_PREEMPHASIS_6dB	2
632 #define EDP_PREEMPHASIS_9_5dB	3
633 #define EDP_VSWING_0_4V		0
634 #define EDP_VSWING_0_6V		1
635 #define EDP_VSWING_0_8V		2
636 #define EDP_VSWING_1_2V		3
637 
638 
639 struct edp_fast_link_params {
640 	u8 rate:4;
641 	u8 lanes:4;
642 	u8 preemphasis:4;
643 	u8 vswing:4;
644 } __packed;
645 
646 struct edp_pwm_delays {
647 	u16 pwm_on_to_backlight_enable;
648 	u16 backlight_disable_to_pwm_off;
649 } __packed;
650 
651 struct edp_full_link_params {
652 	u8 preemphasis:4;
653 	u8 vswing:4;
654 } __packed;
655 
656 struct bdb_edp {
657 	struct edp_power_seq power_seqs[16];
658 	u32 color_depth;
659 	struct edp_fast_link_params fast_link_params[16];
660 	u32 sdrrs_msa_timing_delay;
661 
662 	/* ith bit indicates enabled/disabled for (i+1)th panel */
663 	u16 edp_s3d_feature;					/* 162 */
664 	u16 edp_t3_optimization;				/* 165 */
665 	u64 edp_vswing_preemph;					/* 173 */
666 	u16 fast_link_training;					/* 182 */
667 	u16 dpcd_600h_write_required;				/* 185 */
668 	struct edp_pwm_delays pwm_delays[16];			/* 186 */
669 	u16 full_link_params_provided;				/* 199 */
670 	struct edp_full_link_params full_link_params[16];	/* 199 */
671 } __packed;
672 
673 /*
674  * Block 40 - LFP Data Block
675  */
676 
677 /* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
678 #define MODE_MASK		0x3
679 
680 struct bdb_lvds_options {
681 	u8 panel_type;
682 	u8 panel_type2;						/* 212 */
683 	/* LVDS capabilities, stored in a dword */
684 	u8 pfit_mode:2;
685 	u8 pfit_text_mode_enhanced:1;
686 	u8 pfit_gfx_mode_enhanced:1;
687 	u8 pfit_ratio_auto:1;
688 	u8 pixel_dither:1;
689 	u8 lvds_edid:1;
690 	u8 rsvd2:1;
691 	u8 rsvd4;
692 	/* LVDS Panel channel bits stored here */
693 	u32 lvds_panel_channel_bits;
694 	/* LVDS SSC (Spread Spectrum Clock) bits stored here. */
695 	u16 ssc_bits;
696 	u16 ssc_freq;
697 	u16 ssc_ddt;
698 	/* Panel color depth defined here */
699 	u16 panel_color_depth;
700 	/* LVDS panel type bits stored here */
701 	u32 dps_panel_type_bits;
702 	/* LVDS backlight control type bits stored here */
703 	u32 blt_control_type_bits;
704 
705 	u16 lcdvcc_s0_enable;					/* 200 */
706 	u32 rotation;						/* 228 */
707 } __packed;
708 
709 /*
710  * Block 41 - LFP Data Table Pointers
711  */
712 
713 /* LFP pointer table contains entries to the struct below */
714 struct lvds_lfp_data_ptr {
715 	u16 fp_timing_offset; /* offsets are from start of bdb */
716 	u8 fp_table_size;
717 	u16 dvo_timing_offset;
718 	u8 dvo_table_size;
719 	u16 panel_pnp_id_offset;
720 	u8 pnp_table_size;
721 } __packed;
722 
723 struct bdb_lvds_lfp_data_ptrs {
724 	u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
725 	struct lvds_lfp_data_ptr ptr[16];
726 } __packed;
727 
728 /*
729  * Block 42 - LFP Data Tables
730  */
731 
732 /* LFP data has 3 blocks per entry */
733 struct lvds_fp_timing {
734 	u16 x_res;
735 	u16 y_res;
736 	u32 lvds_reg;
737 	u32 lvds_reg_val;
738 	u32 pp_on_reg;
739 	u32 pp_on_reg_val;
740 	u32 pp_off_reg;
741 	u32 pp_off_reg_val;
742 	u32 pp_cycle_reg;
743 	u32 pp_cycle_reg_val;
744 	u32 pfit_reg;
745 	u32 pfit_reg_val;
746 	u16 terminator;
747 } __packed;
748 
749 struct lvds_pnp_id {
750 	u16 mfg_name;
751 	u16 product_code;
752 	u32 serial;
753 	u8 mfg_week;
754 	u8 mfg_year;
755 } __packed;
756 
757 struct lvds_lfp_data_entry {
758 	struct lvds_fp_timing fp_timing;
759 	struct lvds_dvo_timing dvo_timing;
760 	struct lvds_pnp_id pnp_id;
761 } __packed;
762 
763 struct bdb_lvds_lfp_data {
764 	struct lvds_lfp_data_entry data[16];
765 } __packed;
766 
767 /*
768  * Block 43 - LFP Backlight Control Data Block
769  */
770 
771 #define BDB_BACKLIGHT_TYPE_NONE	0
772 #define BDB_BACKLIGHT_TYPE_PWM	2
773 
774 struct lfp_backlight_data_entry {
775 	u8 type:2;
776 	u8 active_low_pwm:1;
777 	u8 obsolete1:5;
778 	u16 pwm_freq_hz;
779 	u8 min_brightness;
780 	u8 obsolete2;
781 	u8 obsolete3;
782 } __packed;
783 
784 struct lfp_backlight_control_method {
785 	u8 type:4;
786 	u8 controller:4;
787 } __packed;
788 
789 struct bdb_lfp_backlight_data {
790 	u8 entry_size;
791 	struct lfp_backlight_data_entry data[16];
792 	u8 level[16];
793 	struct lfp_backlight_control_method backlight_control[16];
794 } __packed;
795 
796 /*
797  * Block 44 - LFP Power Conservation Features Block
798  */
799 
800 struct als_data_entry {
801 	u16 backlight_adjust;
802 	u16 lux;
803 } __packed;
804 
805 struct agressiveness_profile_entry {
806 	u8 dpst_agressiveness : 4;
807 	u8 lace_agressiveness : 4;
808 } __packed;
809 
810 struct bdb_lfp_power {
811 	u8 lfp_feature_bits;
812 	struct als_data_entry als[5];
813 	u8 lace_aggressiveness_profile;
814 	u16 dpst;
815 	u16 psr;
816 	u16 drrs;
817 	u16 lace_support;
818 	u16 adt;
819 	u16 dmrrs;
820 	u16 adb;
821 	u16 lace_enabled_status;
822 	struct agressiveness_profile_entry aggressivenes[16];
823 } __packed;
824 
825 /*
826  * Block 52 - MIPI Configuration Block
827  */
828 
829 #define MAX_MIPI_CONFIGURATIONS	6
830 
831 struct bdb_mipi_config {
832 	struct mipi_config config[MAX_MIPI_CONFIGURATIONS];
833 	struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];
834 } __packed;
835 
836 /*
837  * Block 53 - MIPI Sequence Block
838  */
839 
840 struct bdb_mipi_sequence {
841 	u8 version;
842 	u8 data[]; /* up to 6 variable length blocks */
843 } __packed;
844 
845 /*
846  * Block 56 - Compression Parameters
847  */
848 
849 #define VBT_RC_BUFFER_BLOCK_SIZE_1KB	0
850 #define VBT_RC_BUFFER_BLOCK_SIZE_4KB	1
851 #define VBT_RC_BUFFER_BLOCK_SIZE_16KB	2
852 #define VBT_RC_BUFFER_BLOCK_SIZE_64KB	3
853 
854 #define VBT_DSC_LINE_BUFFER_DEPTH(vbt_value)	((vbt_value) + 8) /* bits */
855 #define VBT_DSC_MAX_BPP(vbt_value)		(6 + (vbt_value) * 2)
856 
857 struct dsc_compression_parameters_entry {
858 	u8 version_major:4;
859 	u8 version_minor:4;
860 
861 	u8 rc_buffer_block_size:2;
862 	u8 reserved1:6;
863 
864 	/*
865 	 * Buffer size in bytes:
866 	 *
867 	 * 4 ^ rc_buffer_block_size * 1024 * (rc_buffer_size + 1) bytes
868 	 */
869 	u8 rc_buffer_size;
870 	u32 slices_per_line;
871 
872 	u8 line_buffer_depth:4;
873 	u8 reserved2:4;
874 
875 	/* Flag Bits 1 */
876 	u8 block_prediction_enable:1;
877 	u8 reserved3:7;
878 
879 	u8 max_bpp; /* mapping */
880 
881 	/* Color depth capabilities */
882 	u8 reserved4:1;
883 	u8 support_8bpc:1;
884 	u8 support_10bpc:1;
885 	u8 support_12bpc:1;
886 	u8 reserved5:4;
887 
888 	u16 slice_height;
889 } __packed;
890 
891 struct bdb_compression_parameters {
892 	u16 entry_size;
893 	struct dsc_compression_parameters_entry data[16];
894 } __packed;
895 
896 /*
897  * Block 58 - Generic DTD Block
898  */
899 
900 struct generic_dtd_entry {
901 	u32 pixel_clock;
902 	u16 hactive;
903 	u16 hblank;
904 	u16 hfront_porch;
905 	u16 hsync;
906 	u16 vactive;
907 	u16 vblank;
908 	u16 vfront_porch;
909 	u16 vsync;
910 	u16 width_mm;
911 	u16 height_mm;
912 
913 	/* Flags */
914 	u8 rsvd_flags:6;
915 	u8 vsync_positive_polarity:1;
916 	u8 hsync_positive_polarity:1;
917 
918 	u8 rsvd[3];
919 } __packed;
920 
921 struct bdb_generic_dtd {
922 	u16 gdtd_size;
923 	struct generic_dtd_entry dtd[];	/* up to 24 DTD's */
924 } __packed;
925 
926 #endif /* _INTEL_VBT_DEFS_H_ */
927