1 /* 2 * Copyright © 2006-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28 /* 29 * This information is private to VBT parsing in intel_bios.c. 30 * 31 * Please do NOT include anywhere else. 32 */ 33 #ifndef _INTEL_BIOS_PRIVATE 34 #error "intel_vbt_defs.h is private to intel_bios.c" 35 #endif 36 37 #ifndef _INTEL_VBT_DEFS_H_ 38 #define _INTEL_VBT_DEFS_H_ 39 40 #include "intel_bios.h" 41 42 /** 43 * struct vbt_header - VBT Header structure 44 * @signature: VBT signature, always starts with "$VBT" 45 * @version: Version of this structure 46 * @header_size: Size of this structure 47 * @vbt_size: Size of VBT (VBT Header, BDB Header and data blocks) 48 * @vbt_checksum: Checksum 49 * @reserved0: Reserved 50 * @bdb_offset: Offset of &struct bdb_header from beginning of VBT 51 * @aim_offset: Offsets of add-in data blocks from beginning of VBT 52 */ 53 struct vbt_header { 54 u8 signature[20]; 55 u16 version; 56 u16 header_size; 57 u16 vbt_size; 58 u8 vbt_checksum; 59 u8 reserved0; 60 u32 bdb_offset; 61 u32 aim_offset[4]; 62 } __packed; 63 64 /** 65 * struct bdb_header - BDB Header structure 66 * @signature: BDB signature "BIOS_DATA_BLOCK" 67 * @version: Version of the data block definitions 68 * @header_size: Size of this structure 69 * @bdb_size: Size of BDB (BDB Header and data blocks) 70 */ 71 struct bdb_header { 72 u8 signature[16]; 73 u16 version; 74 u16 header_size; 75 u16 bdb_size; 76 } __packed; 77 78 /* 79 * There are several types of BIOS data blocks (BDBs), each block has 80 * an ID and size in the first 3 bytes (ID in first, size in next 2). 81 * Known types are listed below. 82 */ 83 enum bdb_block_id { 84 BDB_GENERAL_FEATURES = 1, 85 BDB_GENERAL_DEFINITIONS = 2, 86 BDB_OLD_TOGGLE_LIST = 3, 87 BDB_MODE_SUPPORT_LIST = 4, 88 BDB_GENERIC_MODE_TABLE = 5, 89 BDB_EXT_MMIO_REGS = 6, 90 BDB_SWF_IO = 7, 91 BDB_SWF_MMIO = 8, 92 BDB_PSR = 9, 93 BDB_MODE_REMOVAL_TABLE = 10, 94 BDB_CHILD_DEVICE_TABLE = 11, 95 BDB_DRIVER_FEATURES = 12, 96 BDB_DRIVER_PERSISTENCE = 13, 97 BDB_EXT_TABLE_PTRS = 14, 98 BDB_DOT_CLOCK_OVERRIDE = 15, 99 BDB_DISPLAY_SELECT = 16, 100 BDB_DRIVER_ROTATION = 18, 101 BDB_DISPLAY_REMOVE = 19, 102 BDB_OEM_CUSTOM = 20, 103 BDB_EFP_LIST = 21, /* workarounds for VGA hsync/vsync */ 104 BDB_SDVO_LVDS_OPTIONS = 22, 105 BDB_SDVO_PANEL_DTDS = 23, 106 BDB_SDVO_LVDS_PNP_IDS = 24, 107 BDB_SDVO_LVDS_POWER_SEQ = 25, 108 BDB_TV_OPTIONS = 26, 109 BDB_EDP = 27, 110 BDB_LVDS_OPTIONS = 40, 111 BDB_LVDS_LFP_DATA_PTRS = 41, 112 BDB_LVDS_LFP_DATA = 42, 113 BDB_LVDS_BACKLIGHT = 43, 114 BDB_LFP_POWER = 44, 115 BDB_MIPI_CONFIG = 52, 116 BDB_MIPI_SEQUENCE = 53, 117 BDB_COMPRESSION_PARAMETERS = 56, 118 BDB_GENERIC_DTD = 58, 119 BDB_SKIP = 254, /* VBIOS private block, ignore */ 120 }; 121 122 /* 123 * Block 1 - General Bit Definitions 124 */ 125 126 struct bdb_general_features { 127 /* bits 1 */ 128 u8 panel_fitting:2; 129 u8 flexaim:1; 130 u8 msg_enable:1; 131 u8 clear_screen:3; 132 u8 color_flip:1; 133 134 /* bits 2 */ 135 u8 download_ext_vbt:1; 136 u8 enable_ssc:1; 137 u8 ssc_freq:1; 138 u8 enable_lfp_on_override:1; 139 u8 disable_ssc_ddt:1; 140 u8 underscan_vga_timings:1; 141 u8 display_clock_mode:1; 142 u8 vbios_hotplug_support:1; 143 144 /* bits 3 */ 145 u8 disable_smooth_vision:1; 146 u8 single_dvi:1; 147 u8 rotate_180:1; /* 181 */ 148 u8 fdi_rx_polarity_inverted:1; 149 u8 vbios_extended_mode:1; /* 160 */ 150 u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160 */ 151 u8 panel_best_fit_timing:1; /* 160 */ 152 u8 ignore_strap_state:1; /* 160 */ 153 154 /* bits 4 */ 155 u8 legacy_monitor_detect; 156 157 /* bits 5 */ 158 u8 int_crt_support:1; 159 u8 int_tv_support:1; 160 u8 int_efp_support:1; 161 u8 dp_ssc_enable:1; /* PCH attached eDP supports SSC */ 162 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ 163 u8 dp_ssc_dongle_supported:1; 164 u8 rsvd11:2; /* finish byte */ 165 166 /* bits 6 */ 167 u8 tc_hpd_retry_timeout:7; /* 242 */ 168 u8 rsvd12:1; 169 170 /* bits 7 */ 171 u8 afc_startup_config:2;/* 249 */ 172 u8 rsvd13:6; 173 } __packed; 174 175 /* 176 * Block 2 - General Bytes Definition 177 */ 178 179 /* pre-915 */ 180 #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ 181 #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ 182 #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ 183 #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ 184 185 /* Device handle */ 186 #define DEVICE_HANDLE_LFP1 0x0008 187 #define DEVICE_HANDLE_LFP2 0x0080 188 189 /* Pre 915 */ 190 #define DEVICE_TYPE_NONE 0x00 191 #define DEVICE_TYPE_CRT 0x01 192 #define DEVICE_TYPE_TV 0x09 193 #define DEVICE_TYPE_EFP 0x12 194 #define DEVICE_TYPE_LFP 0x22 195 /* On 915+ */ 196 #define DEVICE_TYPE_CRT_DPMS 0x6001 197 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 198 #define DEVICE_TYPE_TV_COMPOSITE 0x0209 199 #define DEVICE_TYPE_TV_MACROVISION 0x0289 200 #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c 201 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 202 #define DEVICE_TYPE_TV_SCART 0x0209 203 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 204 #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 205 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 206 #define DEVICE_TYPE_EFP_DVI_I 0x6053 207 #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 208 #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 209 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 210 #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 211 #define DEVICE_TYPE_LFP_PANELLINK 0x5012 212 #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 213 #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 214 #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 215 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 216 217 /* Add the device class for LFP, TV, HDMI */ 218 #define DEVICE_TYPE_INT_LFP 0x1022 219 #define DEVICE_TYPE_INT_TV 0x1009 220 #define DEVICE_TYPE_HDMI 0x60D2 221 #define DEVICE_TYPE_DP 0x68C6 222 #define DEVICE_TYPE_DP_DUAL_MODE 0x60D6 223 #define DEVICE_TYPE_eDP 0x78C6 224 225 #define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) 226 #define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) 227 #define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) 228 #define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) 229 #define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) 230 #define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) 231 #define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) 232 #define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) 233 #define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) 234 #define DEVICE_TYPE_LVDS_SIGNALING (1 << 5) 235 #define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) 236 #define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) 237 #define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) 238 #define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) 239 #define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) 240 241 #define DEVICE_CFG_NONE 0x00 242 #define DEVICE_CFG_12BIT_DVOB 0x01 243 #define DEVICE_CFG_12BIT_DVOC 0x02 244 #define DEVICE_CFG_24BIT_DVOBC 0x09 245 #define DEVICE_CFG_24BIT_DVOCB 0x0a 246 #define DEVICE_CFG_DUAL_DVOB 0x11 247 #define DEVICE_CFG_DUAL_DVOC 0x12 248 #define DEVICE_CFG_DUAL_DVOBC 0x13 249 #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 250 #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a 251 252 #define DEVICE_WIRE_NONE 0x00 253 #define DEVICE_WIRE_DVOB 0x01 254 #define DEVICE_WIRE_DVOC 0x02 255 #define DEVICE_WIRE_DVOBC 0x03 256 #define DEVICE_WIRE_DVOBB 0x05 257 #define DEVICE_WIRE_DVOCC 0x06 258 #define DEVICE_WIRE_DVOB_MASTER 0x0d 259 #define DEVICE_WIRE_DVOC_MASTER 0x0e 260 261 /* dvo_port pre BDB 155 */ 262 #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ 263 #define DEVICE_PORT_DVOB 0x01 264 #define DEVICE_PORT_DVOC 0x02 265 266 /* dvo_port BDB 155+ */ 267 #define DVO_PORT_HDMIA 0 268 #define DVO_PORT_HDMIB 1 269 #define DVO_PORT_HDMIC 2 270 #define DVO_PORT_HDMID 3 271 #define DVO_PORT_LVDS 4 272 #define DVO_PORT_TV 5 273 #define DVO_PORT_CRT 6 274 #define DVO_PORT_DPB 7 275 #define DVO_PORT_DPC 8 276 #define DVO_PORT_DPD 9 277 #define DVO_PORT_DPA 10 278 #define DVO_PORT_DPE 11 /* 193 */ 279 #define DVO_PORT_HDMIE 12 /* 193 */ 280 #define DVO_PORT_DPF 13 /* N/A */ 281 #define DVO_PORT_HDMIF 14 /* N/A */ 282 #define DVO_PORT_DPG 15 /* 217 */ 283 #define DVO_PORT_HDMIG 16 /* 217 */ 284 #define DVO_PORT_DPH 17 /* 217 */ 285 #define DVO_PORT_HDMIH 18 /* 217 */ 286 #define DVO_PORT_DPI 19 /* 217 */ 287 #define DVO_PORT_HDMII 20 /* 217 */ 288 #define DVO_PORT_MIPIA 21 /* 171 */ 289 #define DVO_PORT_MIPIB 22 /* 171 */ 290 #define DVO_PORT_MIPIC 23 /* 171 */ 291 #define DVO_PORT_MIPID 24 /* 171 */ 292 293 #define HDMI_MAX_DATA_RATE_PLATFORM 0 /* 204 */ 294 #define HDMI_MAX_DATA_RATE_297 1 /* 204 */ 295 #define HDMI_MAX_DATA_RATE_165 2 /* 204 */ 296 #define HDMI_MAX_DATA_RATE_594 3 /* 249 */ 297 #define HDMI_MAX_DATA_RATE_340 4 /* 249 */ 298 #define HDMI_MAX_DATA_RATE_300 5 /* 249 */ 299 300 #define LEGACY_CHILD_DEVICE_CONFIG_SIZE 33 301 302 /* DDC Bus DDI Type 155+ */ 303 enum vbt_gmbus_ddi { 304 DDC_BUS_DDI_B = 0x1, 305 DDC_BUS_DDI_C, 306 DDC_BUS_DDI_D, 307 DDC_BUS_DDI_F, 308 ICL_DDC_BUS_DDI_A = 0x1, 309 ICL_DDC_BUS_DDI_B, 310 TGL_DDC_BUS_DDI_C, 311 RKL_DDC_BUS_DDI_D = 0x3, 312 RKL_DDC_BUS_DDI_E, 313 ICL_DDC_BUS_PORT_1 = 0x4, 314 ICL_DDC_BUS_PORT_2, 315 ICL_DDC_BUS_PORT_3, 316 ICL_DDC_BUS_PORT_4, 317 TGL_DDC_BUS_PORT_5, 318 TGL_DDC_BUS_PORT_6, 319 ADLS_DDC_BUS_PORT_TC1 = 0x2, 320 ADLS_DDC_BUS_PORT_TC2, 321 ADLS_DDC_BUS_PORT_TC3, 322 ADLS_DDC_BUS_PORT_TC4, 323 ADLP_DDC_BUS_PORT_TC1 = 0x3, 324 ADLP_DDC_BUS_PORT_TC2, 325 ADLP_DDC_BUS_PORT_TC3, 326 ADLP_DDC_BUS_PORT_TC4 327 328 }; 329 330 #define DP_AUX_A 0x40 331 #define DP_AUX_B 0x10 332 #define DP_AUX_C 0x20 333 #define DP_AUX_D 0x30 334 #define DP_AUX_E 0x50 335 #define DP_AUX_F 0x60 336 #define DP_AUX_G 0x70 337 #define DP_AUX_H 0x80 338 #define DP_AUX_I 0x90 339 340 /* DP max link rate 216+ */ 341 #define BDB_216_VBT_DP_MAX_LINK_RATE_HBR3 0 342 #define BDB_216_VBT_DP_MAX_LINK_RATE_HBR2 1 343 #define BDB_216_VBT_DP_MAX_LINK_RATE_HBR 2 344 #define BDB_216_VBT_DP_MAX_LINK_RATE_LBR 3 345 346 /* DP max link rate 230+ */ 347 #define BDB_230_VBT_DP_MAX_LINK_RATE_DEF 0 348 #define BDB_230_VBT_DP_MAX_LINK_RATE_LBR 1 349 #define BDB_230_VBT_DP_MAX_LINK_RATE_HBR 2 350 #define BDB_230_VBT_DP_MAX_LINK_RATE_HBR2 3 351 #define BDB_230_VBT_DP_MAX_LINK_RATE_HBR3 4 352 #define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR10 5 353 #define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR13P5 6 354 #define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR20 7 355 356 /* 357 * The child device config, aka the display device data structure, provides a 358 * description of a port and its configuration on the platform. 359 * 360 * The child device config size has been increased, and fields have been added 361 * and their meaning has changed over time. Care must be taken when accessing 362 * basically any of the fields to ensure the correct interpretation for the BDB 363 * version in question. 364 * 365 * When we copy the child device configs to dev_priv->vbt.child_dev, we reserve 366 * space for the full structure below, and initialize the tail not actually 367 * present in VBT to zeros. Accessing those fields is fine, as long as the 368 * default zero is taken into account, again according to the BDB version. 369 * 370 * BDB versions 155 and below are considered legacy, and version 155 seems to be 371 * a baseline for some of the VBT documentation. When adding new fields, please 372 * include the BDB version when the field was added, if it's above that. 373 */ 374 struct child_device_config { 375 u16 handle; 376 u16 device_type; /* See DEVICE_TYPE_* above */ 377 378 union { 379 u8 device_id[10]; /* ascii string */ 380 struct { 381 u8 i2c_speed; 382 u8 dp_onboard_redriver; /* 158 */ 383 u8 dp_ondock_redriver; /* 158 */ 384 u8 hdmi_level_shifter_value:5; /* 169 */ 385 u8 hdmi_max_data_rate:3; /* 204 */ 386 u16 dtd_buf_ptr; /* 161 */ 387 u8 edidless_efp:1; /* 161 */ 388 u8 compression_enable:1; /* 198 */ 389 u8 compression_method_cps:1; /* 198 */ 390 u8 ganged_edp:1; /* 202 */ 391 u8 reserved0:4; 392 u8 compression_structure_index:4; /* 198 */ 393 u8 reserved1:4; 394 u8 slave_port; /* 202 */ 395 u8 reserved2; 396 } __packed; 397 } __packed; 398 399 u16 addin_offset; 400 u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */ 401 u8 i2c_pin; 402 u8 slave_addr; 403 u8 ddc_pin; 404 u16 edid_ptr; 405 u8 dvo_cfg; /* See DEVICE_CFG_* above */ 406 407 union { 408 struct { 409 u8 dvo2_port; 410 u8 i2c2_pin; 411 u8 slave2_addr; 412 u8 ddc2_pin; 413 } __packed; 414 struct { 415 u8 efp_routed:1; /* 158 */ 416 u8 lane_reversal:1; /* 184 */ 417 u8 lspcon:1; /* 192 */ 418 u8 iboost:1; /* 196 */ 419 u8 hpd_invert:1; /* 196 */ 420 u8 use_vbt_vswing:1; /* 218 */ 421 u8 flag_reserved:2; 422 u8 hdmi_support:1; /* 158 */ 423 u8 dp_support:1; /* 158 */ 424 u8 tmds_support:1; /* 158 */ 425 u8 support_reserved:5; 426 u8 aux_channel; 427 u8 dongle_detect; 428 } __packed; 429 } __packed; 430 431 u8 pipe_cap:2; 432 u8 sdvo_stall:1; /* 158 */ 433 u8 hpd_status:2; 434 u8 integrated_encoder:1; 435 u8 capabilities_reserved:2; 436 u8 dvo_wiring; /* See DEVICE_WIRE_* above */ 437 438 union { 439 u8 dvo2_wiring; 440 u8 mipi_bridge_type; /* 171 */ 441 } __packed; 442 443 u16 extended_type; 444 u8 dvo_function; 445 u8 dp_usb_type_c:1; /* 195 */ 446 u8 tbt:1; /* 209 */ 447 u8 flags2_reserved:2; /* 195 */ 448 u8 dp_port_trace_length:4; /* 209 */ 449 u8 dp_gpio_index; /* 195 */ 450 u16 dp_gpio_pin_num; /* 195 */ 451 u8 dp_iboost_level:4; /* 196 */ 452 u8 hdmi_iboost_level:4; /* 196 */ 453 u8 dp_max_link_rate:3; /* 216/230 GLK+ */ 454 u8 dp_max_link_rate_reserved:5; /* 216/230 */ 455 } __packed; 456 457 struct bdb_general_definitions { 458 /* DDC GPIO */ 459 u8 crt_ddc_gmbus_pin; 460 461 /* DPMS bits */ 462 u8 dpms_acpi:1; 463 u8 skip_boot_crt_detect:1; 464 u8 dpms_aim:1; 465 u8 rsvd1:5; /* finish byte */ 466 467 /* boot device bits */ 468 u8 boot_display[2]; 469 u8 child_dev_size; 470 471 /* 472 * Device info: 473 * If TV is present, it'll be at devices[0]. 474 * LVDS will be next, either devices[0] or [1], if present. 475 * On some platforms the number of device is 6. But could be as few as 476 * 4 if both TV and LVDS are missing. 477 * And the device num is related with the size of general definition 478 * block. It is obtained by using the following formula: 479 * number = (block_size - sizeof(bdb_general_definitions))/ 480 * defs->child_dev_size; 481 */ 482 u8 devices[]; 483 } __packed; 484 485 /* 486 * Block 9 - SRD Feature Block 487 */ 488 489 struct psr_table { 490 /* Feature bits */ 491 u8 full_link:1; 492 u8 require_aux_to_wakeup:1; 493 u8 feature_bits_rsvd:6; 494 495 /* Wait times */ 496 u8 idle_frames:4; 497 u8 lines_to_wait:3; 498 u8 wait_times_rsvd:1; 499 500 /* TP wake up time in multiple of 100 */ 501 u16 tp1_wakeup_time; 502 u16 tp2_tp3_wakeup_time; 503 } __packed; 504 505 struct bdb_psr { 506 struct psr_table psr_table[16]; 507 508 /* PSR2 TP2/TP3 wakeup time for 16 panels */ 509 u32 psr2_tp2_tp3_wakeup_time; 510 } __packed; 511 512 /* 513 * Block 12 - Driver Features Data Block 514 */ 515 516 #define BDB_DRIVER_FEATURE_NO_LVDS 0 517 #define BDB_DRIVER_FEATURE_INT_LVDS 1 518 #define BDB_DRIVER_FEATURE_SDVO_LVDS 2 519 #define BDB_DRIVER_FEATURE_INT_SDVO_LVDS 3 520 521 struct bdb_driver_features { 522 u8 boot_dev_algorithm:1; 523 u8 block_display_switch:1; 524 u8 allow_display_switch:1; 525 u8 hotplug_dvo:1; 526 u8 dual_view_zoom:1; 527 u8 int15h_hook:1; 528 u8 sprite_in_clone:1; 529 u8 primary_lfp_id:1; 530 531 u16 boot_mode_x; 532 u16 boot_mode_y; 533 u8 boot_mode_bpp; 534 u8 boot_mode_refresh; 535 536 u16 enable_lfp_primary:1; 537 u16 selective_mode_pruning:1; 538 u16 dual_frequency:1; 539 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ 540 u16 nt_clone_support:1; 541 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ 542 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ 543 u16 cui_aspect_scaling:1; 544 u16 preserve_aspect_ratio:1; 545 u16 sdvo_device_power_down:1; 546 u16 crt_hotplug:1; 547 u16 lvds_config:2; 548 u16 tv_hotplug:1; 549 u16 hdmi_config:2; 550 551 u8 static_display:1; 552 u8 reserved2:7; 553 u16 legacy_crt_max_x; 554 u16 legacy_crt_max_y; 555 u8 legacy_crt_max_refresh; 556 557 u8 hdmi_termination; 558 u8 custom_vbt_version; 559 /* Driver features data block */ 560 u16 rmpm_enabled:1; 561 u16 s2ddt_enabled:1; 562 u16 dpst_enabled:1; 563 u16 bltclt_enabled:1; 564 u16 adb_enabled:1; 565 u16 drrs_enabled:1; 566 u16 grs_enabled:1; 567 u16 gpmt_enabled:1; 568 u16 tbt_enabled:1; 569 u16 psr_enabled:1; 570 u16 ips_enabled:1; 571 u16 reserved3:1; 572 u16 dmrrs_enabled:1; 573 u16 reserved4:2; 574 u16 pc_feature_valid:1; 575 } __packed; 576 577 /* 578 * Block 22 - SDVO LVDS General Options 579 */ 580 581 struct bdb_sdvo_lvds_options { 582 u8 panel_backlight; 583 u8 h40_set_panel_type; 584 u8 panel_type; 585 u8 ssc_clk_freq; 586 u16 als_low_trip; 587 u16 als_high_trip; 588 u8 sclalarcoeff_tab_row_num; 589 u8 sclalarcoeff_tab_row_size; 590 u8 coefficient[8]; 591 u8 panel_misc_bits_1; 592 u8 panel_misc_bits_2; 593 u8 panel_misc_bits_3; 594 u8 panel_misc_bits_4; 595 } __packed; 596 597 /* 598 * Block 23 - SDVO LVDS Panel DTDs 599 */ 600 601 struct lvds_dvo_timing { 602 u16 clock; /**< In 10khz */ 603 u8 hactive_lo; 604 u8 hblank_lo; 605 u8 hblank_hi:4; 606 u8 hactive_hi:4; 607 u8 vactive_lo; 608 u8 vblank_lo; 609 u8 vblank_hi:4; 610 u8 vactive_hi:4; 611 u8 hsync_off_lo; 612 u8 hsync_pulse_width_lo; 613 u8 vsync_pulse_width_lo:4; 614 u8 vsync_off_lo:4; 615 u8 vsync_pulse_width_hi:2; 616 u8 vsync_off_hi:2; 617 u8 hsync_pulse_width_hi:2; 618 u8 hsync_off_hi:2; 619 u8 himage_lo; 620 u8 vimage_lo; 621 u8 vimage_hi:4; 622 u8 himage_hi:4; 623 u8 h_border; 624 u8 v_border; 625 u8 rsvd1:3; 626 u8 digital:2; 627 u8 vsync_positive:1; 628 u8 hsync_positive:1; 629 u8 non_interlaced:1; 630 } __packed; 631 632 struct bdb_sdvo_panel_dtds { 633 struct lvds_dvo_timing dtds[4]; 634 } __packed; 635 636 /* 637 * Block 27 - eDP VBT Block 638 */ 639 640 #define EDP_18BPP 0 641 #define EDP_24BPP 1 642 #define EDP_30BPP 2 643 #define EDP_RATE_1_62 0 644 #define EDP_RATE_2_7 1 645 #define EDP_RATE_5_4 2 646 #define EDP_LANE_1 0 647 #define EDP_LANE_2 1 648 #define EDP_LANE_4 3 649 #define EDP_PREEMPHASIS_NONE 0 650 #define EDP_PREEMPHASIS_3_5dB 1 651 #define EDP_PREEMPHASIS_6dB 2 652 #define EDP_PREEMPHASIS_9_5dB 3 653 #define EDP_VSWING_0_4V 0 654 #define EDP_VSWING_0_6V 1 655 #define EDP_VSWING_0_8V 2 656 #define EDP_VSWING_1_2V 3 657 658 659 struct edp_fast_link_params { 660 u8 rate:4; 661 u8 lanes:4; 662 u8 preemphasis:4; 663 u8 vswing:4; 664 } __packed; 665 666 struct edp_pwm_delays { 667 u16 pwm_on_to_backlight_enable; 668 u16 backlight_disable_to_pwm_off; 669 } __packed; 670 671 struct edp_full_link_params { 672 u8 preemphasis:4; 673 u8 vswing:4; 674 } __packed; 675 676 struct edp_apical_params { 677 u32 panel_oui; 678 u32 dpcd_base_address; 679 u32 dpcd_idridix_control_0; 680 u32 dpcd_option_select; 681 u32 dpcd_backlight; 682 u32 ambient_light; 683 u32 backlight_scale; 684 } __packed; 685 686 struct bdb_edp { 687 struct edp_power_seq power_seqs[16]; 688 u32 color_depth; 689 struct edp_fast_link_params fast_link_params[16]; 690 u32 sdrrs_msa_timing_delay; 691 692 /* ith bit indicates enabled/disabled for (i+1)th panel */ 693 u16 edp_s3d_feature; /* 162 */ 694 u16 edp_t3_optimization; /* 165 */ 695 u64 edp_vswing_preemph; /* 173 */ 696 u16 fast_link_training; /* 182 */ 697 u16 dpcd_600h_write_required; /* 185 */ 698 struct edp_pwm_delays pwm_delays[16]; /* 186 */ 699 u16 full_link_params_provided; /* 199 */ 700 struct edp_full_link_params full_link_params[16]; /* 199 */ 701 u16 apical_enable; /* 203 */ 702 struct edp_apical_params apical_params[16]; /* 203 */ 703 u16 edp_fast_link_training_rate[16]; /* 224 */ 704 u16 edp_max_port_link_rate[16]; /* 244 */ 705 } __packed; 706 707 /* 708 * Block 40 - LFP Data Block 709 */ 710 711 struct bdb_lvds_options { 712 u8 panel_type; 713 u8 panel_type2; /* 212 */ 714 /* LVDS capabilities, stored in a dword */ 715 u8 pfit_mode:2; 716 u8 pfit_text_mode_enhanced:1; 717 u8 pfit_gfx_mode_enhanced:1; 718 u8 pfit_ratio_auto:1; 719 u8 pixel_dither:1; 720 u8 lvds_edid:1; 721 u8 rsvd2:1; 722 u8 rsvd4; 723 /* LVDS Panel channel bits stored here */ 724 u32 lvds_panel_channel_bits; 725 /* LVDS SSC (Spread Spectrum Clock) bits stored here. */ 726 u16 ssc_bits; 727 u16 ssc_freq; 728 u16 ssc_ddt; 729 /* Panel color depth defined here */ 730 u16 panel_color_depth; 731 /* LVDS panel type bits stored here */ 732 u32 dps_panel_type_bits; 733 /* LVDS backlight control type bits stored here */ 734 u32 blt_control_type_bits; 735 736 u16 lcdvcc_s0_enable; /* 200 */ 737 u32 rotation; /* 228 */ 738 u32 position; /* 240 */ 739 } __packed; 740 741 /* 742 * Block 41 - LFP Data Table Pointers 743 */ 744 struct lvds_lfp_data_ptr_table { 745 u16 offset; /* offsets are from start of bdb */ 746 u8 table_size; 747 } __packed; 748 749 /* LFP pointer table contains entries to the struct below */ 750 struct lvds_lfp_data_ptr { 751 struct lvds_lfp_data_ptr_table fp_timing; 752 struct lvds_lfp_data_ptr_table dvo_timing; 753 struct lvds_lfp_data_ptr_table panel_pnp_id; 754 } __packed; 755 756 struct bdb_lvds_lfp_data_ptrs { 757 u8 lvds_entries; 758 struct lvds_lfp_data_ptr ptr[16]; 759 struct lvds_lfp_data_ptr_table panel_name; /* 156-163? */ 760 } __packed; 761 762 /* 763 * Block 42 - LFP Data Tables 764 */ 765 766 /* LFP data has 3 blocks per entry */ 767 struct lvds_fp_timing { 768 u16 x_res; 769 u16 y_res; 770 u32 lvds_reg; 771 u32 lvds_reg_val; 772 u32 pp_on_reg; 773 u32 pp_on_reg_val; 774 u32 pp_off_reg; 775 u32 pp_off_reg_val; 776 u32 pp_cycle_reg; 777 u32 pp_cycle_reg_val; 778 u32 pfit_reg; 779 u32 pfit_reg_val; 780 u16 terminator; 781 } __packed; 782 783 struct lvds_pnp_id { 784 u16 mfg_name; 785 u16 product_code; 786 u32 serial; 787 u8 mfg_week; 788 u8 mfg_year; 789 } __packed; 790 791 /* 792 * For reference only. fp_timing has variable size so 793 * the data must be accessed using the data table pointers. 794 * Do not use this directly! 795 */ 796 struct lvds_lfp_data_entry { 797 struct lvds_fp_timing fp_timing; 798 struct lvds_dvo_timing dvo_timing; 799 struct lvds_pnp_id pnp_id; 800 } __packed; 801 802 struct bdb_lvds_lfp_data { 803 struct lvds_lfp_data_entry data[16]; 804 } __packed; 805 806 struct lvds_lfp_panel_name { 807 u8 name[13]; 808 } __packed; 809 810 struct lvds_lfp_black_border { 811 u8 top; /* 227 */ 812 u8 bottom; /* 227 */ 813 u8 left; /* 238 */ 814 u8 right; /* 238 */ 815 } __packed; 816 817 struct bdb_lvds_lfp_data_tail { 818 struct lvds_lfp_panel_name panel_name[16]; /* 156-163? */ 819 u16 scaling_enable; /* 187 */ 820 u8 seamless_drrs_min_refresh_rate[16]; /* 188 */ 821 u8 pixel_overlap_count[16]; /* 208 */ 822 struct lvds_lfp_black_border black_border[16]; /* 227 */ 823 u16 dual_lfp_port_sync_enable; /* 231 */ 824 u16 gpu_dithering_for_banding_artifacts; /* 245 */ 825 } __packed; 826 827 /* 828 * Block 43 - LFP Backlight Control Data Block 829 */ 830 831 #define BDB_BACKLIGHT_TYPE_NONE 0 832 #define BDB_BACKLIGHT_TYPE_PWM 2 833 834 struct lfp_backlight_data_entry { 835 u8 type:2; 836 u8 active_low_pwm:1; 837 u8 obsolete1:5; 838 u16 pwm_freq_hz; 839 u8 min_brightness; /* Obsolete from 234+ */ 840 u8 obsolete2; 841 u8 obsolete3; 842 } __packed; 843 844 struct lfp_backlight_control_method { 845 u8 type:4; 846 u8 controller:4; 847 } __packed; 848 849 struct lfp_brightness_level { 850 u16 level; 851 u16 reserved; 852 } __packed; 853 854 #define EXP_BDB_LFP_BL_DATA_SIZE_REV_191 \ 855 offsetof(struct bdb_lfp_backlight_data, brightness_level) 856 #define EXP_BDB_LFP_BL_DATA_SIZE_REV_234 \ 857 offsetof(struct bdb_lfp_backlight_data, brightness_precision_bits) 858 859 struct bdb_lfp_backlight_data { 860 u8 entry_size; 861 struct lfp_backlight_data_entry data[16]; 862 u8 level[16]; /* Obsolete from 234+ */ 863 struct lfp_backlight_control_method backlight_control[16]; 864 struct lfp_brightness_level brightness_level[16]; /* 234+ */ 865 struct lfp_brightness_level brightness_min_level[16]; /* 234+ */ 866 u8 brightness_precision_bits[16]; /* 236+ */ 867 u16 hdr_dpcd_refresh_timeout[16]; /* 239+ */ 868 } __packed; 869 870 /* 871 * Block 44 - LFP Power Conservation Features Block 872 */ 873 struct lfp_power_features { 874 u8 reserved1:1; 875 u8 power_conservation_pref:3; 876 u8 reserved2:1; 877 u8 lace_enabled_status:1; 878 u8 lace_support:1; 879 u8 als_enable:1; 880 } __packed; 881 882 struct als_data_entry { 883 u16 backlight_adjust; 884 u16 lux; 885 } __packed; 886 887 struct aggressiveness_profile_entry { 888 u8 dpst_aggressiveness : 4; 889 u8 lace_aggressiveness : 4; 890 } __packed; 891 892 struct aggressiveness_profile2_entry { 893 u8 opst_aggressiveness : 4; 894 u8 elp_aggressiveness : 4; 895 } __packed; 896 897 struct bdb_lfp_power { 898 struct lfp_power_features features; 899 struct als_data_entry als[5]; 900 u8 lace_aggressiveness_profile:3; 901 u8 reserved1:5; 902 u16 dpst; 903 u16 psr; 904 u16 drrs; 905 u16 lace_support; 906 u16 adt; 907 u16 dmrrs; 908 u16 adb; 909 u16 lace_enabled_status; 910 struct aggressiveness_profile_entry aggressiveness[16]; 911 u16 hobl; /* 232+ */ 912 u16 vrr_feature_enabled; /* 233+ */ 913 u16 elp; /* 247+ */ 914 u16 opst; /* 247+ */ 915 struct aggressiveness_profile2_entry aggressiveness2[16]; /* 247+ */ 916 } __packed; 917 918 /* 919 * Block 52 - MIPI Configuration Block 920 */ 921 922 #define MAX_MIPI_CONFIGURATIONS 6 923 924 struct bdb_mipi_config { 925 struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; /* 175 */ 926 struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; /* 177 */ 927 struct edp_pwm_delays pwm_delays[MAX_MIPI_CONFIGURATIONS]; /* 186 */ 928 u8 pmic_i2c_bus_number[MAX_MIPI_CONFIGURATIONS]; /* 190 */ 929 } __packed; 930 931 /* 932 * Block 53 - MIPI Sequence Block 933 */ 934 935 struct bdb_mipi_sequence { 936 u8 version; 937 u8 data[]; /* up to 6 variable length blocks */ 938 } __packed; 939 940 /* 941 * Block 56 - Compression Parameters 942 */ 943 944 #define VBT_RC_BUFFER_BLOCK_SIZE_1KB 0 945 #define VBT_RC_BUFFER_BLOCK_SIZE_4KB 1 946 #define VBT_RC_BUFFER_BLOCK_SIZE_16KB 2 947 #define VBT_RC_BUFFER_BLOCK_SIZE_64KB 3 948 949 #define VBT_DSC_LINE_BUFFER_DEPTH(vbt_value) ((vbt_value) + 8) /* bits */ 950 #define VBT_DSC_MAX_BPP(vbt_value) (6 + (vbt_value) * 2) 951 952 struct dsc_compression_parameters_entry { 953 u8 version_major:4; 954 u8 version_minor:4; 955 956 u8 rc_buffer_block_size:2; 957 u8 reserved1:6; 958 959 /* 960 * Buffer size in bytes: 961 * 962 * 4 ^ rc_buffer_block_size * 1024 * (rc_buffer_size + 1) bytes 963 */ 964 u8 rc_buffer_size; 965 u32 slices_per_line; 966 967 u8 line_buffer_depth:4; 968 u8 reserved2:4; 969 970 /* Flag Bits 1 */ 971 u8 block_prediction_enable:1; 972 u8 reserved3:7; 973 974 u8 max_bpp; /* mapping */ 975 976 /* Color depth capabilities */ 977 u8 reserved4:1; 978 u8 support_8bpc:1; 979 u8 support_10bpc:1; 980 u8 support_12bpc:1; 981 u8 reserved5:4; 982 983 u16 slice_height; 984 } __packed; 985 986 struct bdb_compression_parameters { 987 u16 entry_size; 988 struct dsc_compression_parameters_entry data[16]; 989 } __packed; 990 991 /* 992 * Block 58 - Generic DTD Block 993 */ 994 995 struct generic_dtd_entry { 996 u32 pixel_clock; 997 u16 hactive; 998 u16 hblank; 999 u16 hfront_porch; 1000 u16 hsync; 1001 u16 vactive; 1002 u16 vblank; 1003 u16 vfront_porch; 1004 u16 vsync; 1005 u16 width_mm; 1006 u16 height_mm; 1007 1008 /* Flags */ 1009 u8 rsvd_flags:6; 1010 u8 vsync_positive_polarity:1; 1011 u8 hsync_positive_polarity:1; 1012 1013 u8 rsvd[3]; 1014 } __packed; 1015 1016 struct bdb_generic_dtd { 1017 u16 gdtd_size; 1018 struct generic_dtd_entry dtd[]; /* up to 24 DTD's */ 1019 } __packed; 1020 1021 #endif /* _INTEL_VBT_DEFS_H_ */ 1022