1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022-2023 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 #include "intel_de.h" 9 #include "intel_display_types.h" 10 #include "intel_vblank.h" 11 12 /* 13 * This timing diagram depicts the video signal in and 14 * around the vertical blanking period. 15 * 16 * Assumptions about the fictitious mode used in this example: 17 * vblank_start >= 3 18 * vsync_start = vblank_start + 1 19 * vsync_end = vblank_start + 2 20 * vtotal = vblank_start + 3 21 * 22 * start of vblank: 23 * latch double buffered registers 24 * increment frame counter (ctg+) 25 * generate start of vblank interrupt (gen4+) 26 * | 27 * | frame start: 28 * | generate frame start interrupt (aka. vblank interrupt) (gmch) 29 * | may be shifted forward 1-3 extra lines via PIPECONF 30 * | | 31 * | | start of vsync: 32 * | | generate vsync interrupt 33 * | | | 34 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx 35 * . \hs/ . \hs/ \hs/ \hs/ . \hs/ 36 * ----va---> <-----------------vb--------------------> <--------va------------- 37 * | | <----vs-----> | 38 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) 39 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) 40 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) 41 * | | | 42 * last visible pixel first visible pixel 43 * | increment frame counter (gen3/4) 44 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) 45 * 46 * x = horizontal active 47 * _ = horizontal blanking 48 * hs = horizontal sync 49 * va = vertical active 50 * vb = vertical blanking 51 * vs = vertical sync 52 * vbs = vblank_start (number) 53 * 54 * Summary: 55 * - most events happen at the start of horizontal sync 56 * - frame start happens at the start of horizontal blank, 1-4 lines 57 * (depending on PIPECONF settings) after the start of vblank 58 * - gen3/4 pixel and frame counter are synchronized with the start 59 * of horizontal active on the first line of vertical active 60 */ 61 62 /* 63 * Called from drm generic code, passed a 'crtc', which we use as a pipe index. 64 */ 65 u32 i915_get_vblank_counter(struct drm_crtc *crtc) 66 { 67 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 68 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)]; 69 const struct drm_display_mode *mode = &vblank->hwmode; 70 enum pipe pipe = to_intel_crtc(crtc)->pipe; 71 u32 pixel, vbl_start, hsync_start, htotal; 72 u64 frame; 73 74 /* 75 * On i965gm TV output the frame counter only works up to 76 * the point when we enable the TV encoder. After that the 77 * frame counter ceases to work and reads zero. We need a 78 * vblank wait before enabling the TV encoder and so we 79 * have to enable vblank interrupts while the frame counter 80 * is still in a working state. However the core vblank code 81 * does not like us returning non-zero frame counter values 82 * when we've told it that we don't have a working frame 83 * counter. Thus we must stop non-zero values leaking out. 84 */ 85 if (!vblank->max_vblank_count) 86 return 0; 87 88 htotal = mode->crtc_htotal; 89 hsync_start = mode->crtc_hsync_start; 90 vbl_start = mode->crtc_vblank_start; 91 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 92 vbl_start = DIV_ROUND_UP(vbl_start, 2); 93 94 /* Convert to pixel count */ 95 vbl_start *= htotal; 96 97 /* Start of vblank event occurs at start of hsync */ 98 vbl_start -= htotal - hsync_start; 99 100 /* 101 * High & low register fields aren't synchronized, so make sure 102 * we get a low value that's stable across two reads of the high 103 * register. 104 */ 105 frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(pipe), PIPEFRAME(pipe)); 106 107 pixel = frame & PIPE_PIXEL_MASK; 108 frame = (frame >> PIPE_FRAME_LOW_SHIFT) & 0xffffff; 109 110 /* 111 * The frame counter increments at beginning of active. 112 * Cook up a vblank counter by also checking the pixel 113 * counter against vblank start. 114 */ 115 return (frame + (pixel >= vbl_start)) & 0xffffff; 116 } 117 118 u32 g4x_get_vblank_counter(struct drm_crtc *crtc) 119 { 120 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 121 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)]; 122 enum pipe pipe = to_intel_crtc(crtc)->pipe; 123 124 if (!vblank->max_vblank_count) 125 return 0; 126 127 return intel_de_read(dev_priv, PIPE_FRMCOUNT_G4X(pipe)); 128 } 129 130 static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc) 131 { 132 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 133 struct drm_vblank_crtc *vblank = 134 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; 135 const struct drm_display_mode *mode = &vblank->hwmode; 136 u32 htotal = mode->crtc_htotal; 137 u32 clock = mode->crtc_clock; 138 u32 scan_prev_time, scan_curr_time, scan_post_time; 139 140 /* 141 * To avoid the race condition where we might cross into the 142 * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR 143 * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR 144 * during the same frame. 145 */ 146 do { 147 /* 148 * This field provides read back of the display 149 * pipe frame time stamp. The time stamp value 150 * is sampled at every start of vertical blank. 151 */ 152 scan_prev_time = intel_de_read_fw(dev_priv, 153 PIPE_FRMTMSTMP(crtc->pipe)); 154 155 /* 156 * The TIMESTAMP_CTR register has the current 157 * time stamp value. 158 */ 159 scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR); 160 161 scan_post_time = intel_de_read_fw(dev_priv, 162 PIPE_FRMTMSTMP(crtc->pipe)); 163 } while (scan_post_time != scan_prev_time); 164 165 return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time, 166 clock), 1000 * htotal); 167 } 168 169 /* 170 * On certain encoders on certain platforms, pipe 171 * scanline register will not work to get the scanline, 172 * since the timings are driven from the PORT or issues 173 * with scanline register updates. 174 * This function will use Framestamp and current 175 * timestamp registers to calculate the scanline. 176 */ 177 static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) 178 { 179 struct drm_vblank_crtc *vblank = 180 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; 181 const struct drm_display_mode *mode = &vblank->hwmode; 182 u32 vblank_start = mode->crtc_vblank_start; 183 u32 vtotal = mode->crtc_vtotal; 184 u32 scanline; 185 186 scanline = intel_crtc_scanlines_since_frame_timestamp(crtc); 187 scanline = min(scanline, vtotal - 1); 188 scanline = (scanline + vblank_start) % vtotal; 189 190 return scanline; 191 } 192 193 /* 194 * intel_de_read_fw(), only for fast reads of display block, no need for 195 * forcewake etc. 196 */ 197 static int __intel_get_crtc_scanline(struct intel_crtc *crtc) 198 { 199 struct drm_device *dev = crtc->base.dev; 200 struct drm_i915_private *dev_priv = to_i915(dev); 201 const struct drm_display_mode *mode; 202 struct drm_vblank_crtc *vblank; 203 enum pipe pipe = crtc->pipe; 204 int position, vtotal; 205 206 if (!crtc->active) 207 return 0; 208 209 vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; 210 mode = &vblank->hwmode; 211 212 if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP) 213 return __intel_get_crtc_scanline_from_timestamp(crtc); 214 215 vtotal = mode->crtc_vtotal; 216 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 217 vtotal /= 2; 218 219 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK; 220 221 /* 222 * On HSW, the DSL reg (0x70000) appears to return 0 if we 223 * read it just before the start of vblank. So try it again 224 * so we don't accidentally end up spanning a vblank frame 225 * increment, causing the pipe_update_end() code to squak at us. 226 * 227 * The nature of this problem means we can't simply check the ISR 228 * bit and return the vblank start value; nor can we use the scanline 229 * debug register in the transcoder as it appears to have the same 230 * problem. We may need to extend this to include other platforms, 231 * but so far testing only shows the problem on HSW. 232 */ 233 if (HAS_DDI(dev_priv) && !position) { 234 int i, temp; 235 236 for (i = 0; i < 100; i++) { 237 udelay(1); 238 temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK; 239 if (temp != position) { 240 position = temp; 241 break; 242 } 243 } 244 } 245 246 /* 247 * See update_scanline_offset() for the details on the 248 * scanline_offset adjustment. 249 */ 250 return (position + crtc->scanline_offset) % vtotal; 251 } 252 253 static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, 254 bool in_vblank_irq, 255 int *vpos, int *hpos, 256 ktime_t *stime, ktime_t *etime, 257 const struct drm_display_mode *mode) 258 { 259 struct drm_device *dev = _crtc->dev; 260 struct drm_i915_private *dev_priv = to_i915(dev); 261 struct intel_crtc *crtc = to_intel_crtc(_crtc); 262 enum pipe pipe = crtc->pipe; 263 int position; 264 int vbl_start, vbl_end, hsync_start, htotal, vtotal; 265 unsigned long irqflags; 266 bool use_scanline_counter = DISPLAY_VER(dev_priv) >= 5 || 267 IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) == 2 || 268 crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER; 269 270 if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) { 271 drm_dbg(&dev_priv->drm, 272 "trying to get scanoutpos for disabled pipe %c\n", 273 pipe_name(pipe)); 274 return false; 275 } 276 277 htotal = mode->crtc_htotal; 278 hsync_start = mode->crtc_hsync_start; 279 vtotal = mode->crtc_vtotal; 280 vbl_start = mode->crtc_vblank_start; 281 vbl_end = mode->crtc_vblank_end; 282 283 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 284 vbl_start = DIV_ROUND_UP(vbl_start, 2); 285 vbl_end /= 2; 286 vtotal /= 2; 287 } 288 289 /* 290 * Lock uncore.lock, as we will do multiple timing critical raw 291 * register reads, potentially with preemption disabled, so the 292 * following code must not block on uncore.lock. 293 */ 294 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 295 296 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 297 298 /* Get optional system timestamp before query. */ 299 if (stime) 300 *stime = ktime_get(); 301 302 if (crtc->mode_flags & I915_MODE_FLAG_VRR) { 303 int scanlines = intel_crtc_scanlines_since_frame_timestamp(crtc); 304 305 position = __intel_get_crtc_scanline(crtc); 306 307 /* 308 * Already exiting vblank? If so, shift our position 309 * so it looks like we're already apporaching the full 310 * vblank end. This should make the generated timestamp 311 * more or less match when the active portion will start. 312 */ 313 if (position >= vbl_start && scanlines < position) 314 position = min(crtc->vmax_vblank_start + scanlines, vtotal - 1); 315 } else if (use_scanline_counter) { 316 /* No obvious pixelcount register. Only query vertical 317 * scanout position from Display scan line register. 318 */ 319 position = __intel_get_crtc_scanline(crtc); 320 } else { 321 /* 322 * Have access to pixelcount since start of frame. 323 * We can split this into vertical and horizontal 324 * scanout position. 325 */ 326 position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; 327 328 /* convert to pixel counts */ 329 vbl_start *= htotal; 330 vbl_end *= htotal; 331 vtotal *= htotal; 332 333 /* 334 * In interlaced modes, the pixel counter counts all pixels, 335 * so one field will have htotal more pixels. In order to avoid 336 * the reported position from jumping backwards when the pixel 337 * counter is beyond the length of the shorter field, just 338 * clamp the position the length of the shorter field. This 339 * matches how the scanline counter based position works since 340 * the scanline counter doesn't count the two half lines. 341 */ 342 if (position >= vtotal) 343 position = vtotal - 1; 344 345 /* 346 * Start of vblank interrupt is triggered at start of hsync, 347 * just prior to the first active line of vblank. However we 348 * consider lines to start at the leading edge of horizontal 349 * active. So, should we get here before we've crossed into 350 * the horizontal active of the first line in vblank, we would 351 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, 352 * always add htotal-hsync_start to the current pixel position. 353 */ 354 position = (position + htotal - hsync_start) % vtotal; 355 } 356 357 /* Get optional system timestamp after query. */ 358 if (etime) 359 *etime = ktime_get(); 360 361 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 362 363 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 364 365 /* 366 * While in vblank, position will be negative 367 * counting up towards 0 at vbl_end. And outside 368 * vblank, position will be positive counting 369 * up since vbl_end. 370 */ 371 if (position >= vbl_start) 372 position -= vbl_end; 373 else 374 position += vtotal - vbl_end; 375 376 if (use_scanline_counter) { 377 *vpos = position; 378 *hpos = 0; 379 } else { 380 *vpos = position / htotal; 381 *hpos = position - (*vpos * htotal); 382 } 383 384 return true; 385 } 386 387 bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error, 388 ktime_t *vblank_time, bool in_vblank_irq) 389 { 390 return drm_crtc_vblank_helper_get_vblank_timestamp_internal( 391 crtc, max_error, vblank_time, in_vblank_irq, 392 i915_get_crtc_scanoutpos); 393 } 394 395 int intel_get_crtc_scanline(struct intel_crtc *crtc) 396 { 397 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 398 unsigned long irqflags; 399 int position; 400 401 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 402 position = __intel_get_crtc_scanline(crtc); 403 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 404 405 return position; 406 } 407 408 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, 409 enum pipe pipe) 410 { 411 i915_reg_t reg = PIPEDSL(pipe); 412 u32 line1, line2; 413 414 line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 415 msleep(5); 416 line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 417 418 return line1 != line2; 419 } 420 421 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state) 422 { 423 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 424 enum pipe pipe = crtc->pipe; 425 426 /* Wait for the display line to settle/start moving */ 427 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) 428 drm_err(&dev_priv->drm, 429 "pipe %c scanline %s wait timed out\n", 430 pipe_name(pipe), str_on_off(state)); 431 } 432 433 void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc) 434 { 435 wait_for_pipe_scanline_moving(crtc, false); 436 } 437 438 void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) 439 { 440 wait_for_pipe_scanline_moving(crtc, true); 441 } 442