1 /* 2 * Copyright © 2006-2008 Intel Corporation 3 * Jesse Barnes <jesse.barnes@intel.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * 27 */ 28 29 /** @file 30 * Integrated TV-out support for the 915GM and 945GM. 31 */ 32 33 #include <drm/drm_atomic_helper.h> 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_edid.h> 36 37 #include "i915_drv.h" 38 #include "i915_irq.h" 39 #include "i915_reg.h" 40 #include "intel_connector.h" 41 #include "intel_crtc.h" 42 #include "intel_de.h" 43 #include "intel_display_types.h" 44 #include "intel_dpll.h" 45 #include "intel_hotplug.h" 46 #include "intel_tv.h" 47 #include "intel_tv_regs.h" 48 49 enum tv_margin { 50 TV_MARGIN_LEFT, TV_MARGIN_TOP, 51 TV_MARGIN_RIGHT, TV_MARGIN_BOTTOM 52 }; 53 54 struct intel_tv { 55 struct intel_encoder base; 56 57 int type; 58 }; 59 60 struct video_levels { 61 u16 blank, black; 62 u8 burst; 63 }; 64 65 struct color_conversion { 66 u16 ry, gy, by, ay; 67 u16 ru, gu, bu, au; 68 u16 rv, gv, bv, av; 69 }; 70 71 static const u32 filter_table[] = { 72 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140, 73 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000, 74 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160, 75 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780, 76 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50, 77 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20, 78 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0, 79 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0, 80 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020, 81 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140, 82 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20, 83 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848, 84 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900, 85 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080, 86 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060, 87 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140, 88 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000, 89 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160, 90 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780, 91 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50, 92 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20, 93 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0, 94 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0, 95 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020, 96 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140, 97 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20, 98 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848, 99 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900, 100 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080, 101 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060, 102 0x36403000, 0x2D002CC0, 0x30003640, 0x2D0036C0, 103 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540, 104 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00, 105 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000, 106 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00, 107 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40, 108 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240, 109 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00, 110 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0, 111 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840, 112 0x28003100, 0x28002F00, 0x00003100, 0x36403000, 113 0x2D002CC0, 0x30003640, 0x2D0036C0, 114 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540, 115 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00, 116 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000, 117 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00, 118 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40, 119 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240, 120 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00, 121 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0, 122 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840, 123 0x28003100, 0x28002F00, 0x00003100, 124 }; 125 126 /* 127 * Color conversion values have 3 separate fixed point formats: 128 * 129 * 10 bit fields (ay, au) 130 * 1.9 fixed point (b.bbbbbbbbb) 131 * 11 bit fields (ry, by, ru, gu, gv) 132 * exp.mantissa (ee.mmmmmmmmm) 133 * ee = 00 = 10^-1 (0.mmmmmmmmm) 134 * ee = 01 = 10^-2 (0.0mmmmmmmmm) 135 * ee = 10 = 10^-3 (0.00mmmmmmmmm) 136 * ee = 11 = 10^-4 (0.000mmmmmmmmm) 137 * 12 bit fields (gy, rv, bu) 138 * exp.mantissa (eee.mmmmmmmmm) 139 * eee = 000 = 10^-1 (0.mmmmmmmmm) 140 * eee = 001 = 10^-2 (0.0mmmmmmmmm) 141 * eee = 010 = 10^-3 (0.00mmmmmmmmm) 142 * eee = 011 = 10^-4 (0.000mmmmmmmmm) 143 * eee = 100 = reserved 144 * eee = 101 = reserved 145 * eee = 110 = reserved 146 * eee = 111 = 10^0 (m.mmmmmmmm) (only usable for 1.0 representation) 147 * 148 * Saturation and contrast are 8 bits, with their own representation: 149 * 8 bit field (saturation, contrast) 150 * exp.mantissa (ee.mmmmmm) 151 * ee = 00 = 10^-1 (0.mmmmmm) 152 * ee = 01 = 10^0 (m.mmmmm) 153 * ee = 10 = 10^1 (mm.mmmm) 154 * ee = 11 = 10^2 (mmm.mmm) 155 * 156 * Simple conversion function: 157 * 158 * static u32 159 * float_to_csc_11(float f) 160 * { 161 * u32 exp; 162 * u32 mant; 163 * u32 ret; 164 * 165 * if (f < 0) 166 * f = -f; 167 * 168 * if (f >= 1) { 169 * exp = 0x7; 170 * mant = 1 << 8; 171 * } else { 172 * for (exp = 0; exp < 3 && f < 0.5; exp++) 173 * f *= 2.0; 174 * mant = (f * (1 << 9) + 0.5); 175 * if (mant >= (1 << 9)) 176 * mant = (1 << 9) - 1; 177 * } 178 * ret = (exp << 9) | mant; 179 * return ret; 180 * } 181 */ 182 183 /* 184 * Behold, magic numbers! If we plant them they might grow a big 185 * s-video cable to the sky... or something. 186 * 187 * Pre-converted to appropriate hex value. 188 */ 189 190 /* 191 * PAL & NTSC values for composite & s-video connections 192 */ 193 static const struct color_conversion ntsc_m_csc_composite = { 194 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104, 195 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200, 196 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200, 197 }; 198 199 static const struct video_levels ntsc_m_levels_composite = { 200 .blank = 225, .black = 267, .burst = 113, 201 }; 202 203 static const struct color_conversion ntsc_m_csc_svideo = { 204 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133, 205 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200, 206 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200, 207 }; 208 209 static const struct video_levels ntsc_m_levels_svideo = { 210 .blank = 266, .black = 316, .burst = 133, 211 }; 212 213 static const struct color_conversion ntsc_j_csc_composite = { 214 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0119, 215 .ru = 0x074c, .gu = 0x0546, .bu = 0x05ec, .au = 0x0200, 216 .rv = 0x035a, .gv = 0x0322, .bv = 0x06e1, .av = 0x0200, 217 }; 218 219 static const struct video_levels ntsc_j_levels_composite = { 220 .blank = 225, .black = 225, .burst = 113, 221 }; 222 223 static const struct color_conversion ntsc_j_csc_svideo = { 224 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x014c, 225 .ru = 0x0788, .gu = 0x0581, .bu = 0x0322, .au = 0x0200, 226 .rv = 0x0399, .gv = 0x0356, .bv = 0x070a, .av = 0x0200, 227 }; 228 229 static const struct video_levels ntsc_j_levels_svideo = { 230 .blank = 266, .black = 266, .burst = 133, 231 }; 232 233 static const struct color_conversion pal_csc_composite = { 234 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0113, 235 .ru = 0x0745, .gu = 0x053f, .bu = 0x05e1, .au = 0x0200, 236 .rv = 0x0353, .gv = 0x031c, .bv = 0x06dc, .av = 0x0200, 237 }; 238 239 static const struct video_levels pal_levels_composite = { 240 .blank = 237, .black = 237, .burst = 118, 241 }; 242 243 static const struct color_conversion pal_csc_svideo = { 244 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145, 245 .ru = 0x0780, .gu = 0x0579, .bu = 0x031c, .au = 0x0200, 246 .rv = 0x0390, .gv = 0x034f, .bv = 0x0705, .av = 0x0200, 247 }; 248 249 static const struct video_levels pal_levels_svideo = { 250 .blank = 280, .black = 280, .burst = 139, 251 }; 252 253 static const struct color_conversion pal_m_csc_composite = { 254 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104, 255 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200, 256 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200, 257 }; 258 259 static const struct video_levels pal_m_levels_composite = { 260 .blank = 225, .black = 267, .burst = 113, 261 }; 262 263 static const struct color_conversion pal_m_csc_svideo = { 264 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133, 265 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200, 266 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200, 267 }; 268 269 static const struct video_levels pal_m_levels_svideo = { 270 .blank = 266, .black = 316, .burst = 133, 271 }; 272 273 static const struct color_conversion pal_n_csc_composite = { 274 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104, 275 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200, 276 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200, 277 }; 278 279 static const struct video_levels pal_n_levels_composite = { 280 .blank = 225, .black = 267, .burst = 118, 281 }; 282 283 static const struct color_conversion pal_n_csc_svideo = { 284 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133, 285 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200, 286 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200, 287 }; 288 289 static const struct video_levels pal_n_levels_svideo = { 290 .blank = 266, .black = 316, .burst = 139, 291 }; 292 293 /* 294 * Component connections 295 */ 296 static const struct color_conversion sdtv_csc_yprpb = { 297 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145, 298 .ru = 0x0559, .gu = 0x0353, .bu = 0x0100, .au = 0x0200, 299 .rv = 0x0100, .gv = 0x03ad, .bv = 0x074d, .av = 0x0200, 300 }; 301 302 static const struct color_conversion hdtv_csc_yprpb = { 303 .ry = 0x05b3, .gy = 0x016e, .by = 0x0728, .ay = 0x0145, 304 .ru = 0x07d5, .gu = 0x038b, .bu = 0x0100, .au = 0x0200, 305 .rv = 0x0100, .gv = 0x03d1, .bv = 0x06bc, .av = 0x0200, 306 }; 307 308 static const struct video_levels component_levels = { 309 .blank = 279, .black = 279, .burst = 0, 310 }; 311 312 313 struct tv_mode { 314 const char *name; 315 316 u32 clock; 317 u16 refresh; /* in millihertz (for precision) */ 318 u8 oversample; 319 u8 hsync_end; 320 u16 hblank_start, hblank_end, htotal; 321 bool progressive : 1, trilevel_sync : 1, component_only : 1; 322 u8 vsync_start_f1, vsync_start_f2, vsync_len; 323 bool veq_ena : 1; 324 u8 veq_start_f1, veq_start_f2, veq_len; 325 u8 vi_end_f1, vi_end_f2; 326 u16 nbr_end; 327 bool burst_ena : 1; 328 u8 hburst_start, hburst_len; 329 u8 vburst_start_f1; 330 u16 vburst_end_f1; 331 u8 vburst_start_f2; 332 u16 vburst_end_f2; 333 u8 vburst_start_f3; 334 u16 vburst_end_f3; 335 u8 vburst_start_f4; 336 u16 vburst_end_f4; 337 /* 338 * subcarrier programming 339 */ 340 u16 dda2_size, dda3_size; 341 u8 dda1_inc; 342 u16 dda2_inc, dda3_inc; 343 u32 sc_reset; 344 bool pal_burst : 1; 345 /* 346 * blank/black levels 347 */ 348 const struct video_levels *composite_levels, *svideo_levels; 349 const struct color_conversion *composite_color, *svideo_color; 350 const u32 *filter_table; 351 }; 352 353 354 /* 355 * Sub carrier DDA 356 * 357 * I think this works as follows: 358 * 359 * subcarrier freq = pixel_clock * (dda1_inc + dda2_inc / dda2_size) / 4096 360 * 361 * Presumably, when dda3 is added in, it gets to adjust the dda2_inc value 362 * 363 * So, 364 * dda1_ideal = subcarrier/pixel * 4096 365 * dda1_inc = floor (dda1_ideal) 366 * dda2 = dda1_ideal - dda1_inc 367 * 368 * then pick a ratio for dda2 that gives the closest approximation. If 369 * you can't get close enough, you can play with dda3 as well. This 370 * seems likely to happen when dda2 is small as the jumps would be larger 371 * 372 * To invert this, 373 * 374 * pixel_clock = subcarrier * 4096 / (dda1_inc + dda2_inc / dda2_size) 375 * 376 * The constants below were all computed using a 107.520MHz clock 377 */ 378 379 /* 380 * Register programming values for TV modes. 381 * 382 * These values account for -1s required. 383 */ 384 static const struct tv_mode tv_modes[] = { 385 { 386 .name = "NTSC-M", 387 .clock = 108000, 388 .refresh = 59940, 389 .oversample = 8, 390 .component_only = false, 391 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */ 392 393 .hsync_end = 64, .hblank_end = 124, 394 .hblank_start = 836, .htotal = 857, 395 396 .progressive = false, .trilevel_sync = false, 397 398 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 399 .vsync_len = 6, 400 401 .veq_ena = true, .veq_start_f1 = 0, 402 .veq_start_f2 = 1, .veq_len = 18, 403 404 .vi_end_f1 = 20, .vi_end_f2 = 21, 405 .nbr_end = 240, 406 407 .burst_ena = true, 408 .hburst_start = 72, .hburst_len = 34, 409 .vburst_start_f1 = 9, .vburst_end_f1 = 240, 410 .vburst_start_f2 = 10, .vburst_end_f2 = 240, 411 .vburst_start_f3 = 9, .vburst_end_f3 = 240, 412 .vburst_start_f4 = 10, .vburst_end_f4 = 240, 413 414 /* desired 3.5800000 actual 3.5800000 clock 107.52 */ 415 .dda1_inc = 135, 416 .dda2_inc = 20800, .dda2_size = 27456, 417 .dda3_inc = 0, .dda3_size = 0, 418 .sc_reset = TV_SC_RESET_EVERY_4, 419 .pal_burst = false, 420 421 .composite_levels = &ntsc_m_levels_composite, 422 .composite_color = &ntsc_m_csc_composite, 423 .svideo_levels = &ntsc_m_levels_svideo, 424 .svideo_color = &ntsc_m_csc_svideo, 425 426 .filter_table = filter_table, 427 }, 428 { 429 .name = "NTSC-443", 430 .clock = 108000, 431 .refresh = 59940, 432 .oversample = 8, 433 .component_only = false, 434 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */ 435 .hsync_end = 64, .hblank_end = 124, 436 .hblank_start = 836, .htotal = 857, 437 438 .progressive = false, .trilevel_sync = false, 439 440 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 441 .vsync_len = 6, 442 443 .veq_ena = true, .veq_start_f1 = 0, 444 .veq_start_f2 = 1, .veq_len = 18, 445 446 .vi_end_f1 = 20, .vi_end_f2 = 21, 447 .nbr_end = 240, 448 449 .burst_ena = true, 450 .hburst_start = 72, .hburst_len = 34, 451 .vburst_start_f1 = 9, .vburst_end_f1 = 240, 452 .vburst_start_f2 = 10, .vburst_end_f2 = 240, 453 .vburst_start_f3 = 9, .vburst_end_f3 = 240, 454 .vburst_start_f4 = 10, .vburst_end_f4 = 240, 455 456 /* desired 4.4336180 actual 4.4336180 clock 107.52 */ 457 .dda1_inc = 168, 458 .dda2_inc = 4093, .dda2_size = 27456, 459 .dda3_inc = 310, .dda3_size = 525, 460 .sc_reset = TV_SC_RESET_NEVER, 461 .pal_burst = false, 462 463 .composite_levels = &ntsc_m_levels_composite, 464 .composite_color = &ntsc_m_csc_composite, 465 .svideo_levels = &ntsc_m_levels_svideo, 466 .svideo_color = &ntsc_m_csc_svideo, 467 468 .filter_table = filter_table, 469 }, 470 { 471 .name = "NTSC-J", 472 .clock = 108000, 473 .refresh = 59940, 474 .oversample = 8, 475 .component_only = false, 476 477 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */ 478 .hsync_end = 64, .hblank_end = 124, 479 .hblank_start = 836, .htotal = 857, 480 481 .progressive = false, .trilevel_sync = false, 482 483 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 484 .vsync_len = 6, 485 486 .veq_ena = true, .veq_start_f1 = 0, 487 .veq_start_f2 = 1, .veq_len = 18, 488 489 .vi_end_f1 = 20, .vi_end_f2 = 21, 490 .nbr_end = 240, 491 492 .burst_ena = true, 493 .hburst_start = 72, .hburst_len = 34, 494 .vburst_start_f1 = 9, .vburst_end_f1 = 240, 495 .vburst_start_f2 = 10, .vburst_end_f2 = 240, 496 .vburst_start_f3 = 9, .vburst_end_f3 = 240, 497 .vburst_start_f4 = 10, .vburst_end_f4 = 240, 498 499 /* desired 3.5800000 actual 3.5800000 clock 107.52 */ 500 .dda1_inc = 135, 501 .dda2_inc = 20800, .dda2_size = 27456, 502 .dda3_inc = 0, .dda3_size = 0, 503 .sc_reset = TV_SC_RESET_EVERY_4, 504 .pal_burst = false, 505 506 .composite_levels = &ntsc_j_levels_composite, 507 .composite_color = &ntsc_j_csc_composite, 508 .svideo_levels = &ntsc_j_levels_svideo, 509 .svideo_color = &ntsc_j_csc_svideo, 510 511 .filter_table = filter_table, 512 }, 513 { 514 .name = "PAL-M", 515 .clock = 108000, 516 .refresh = 59940, 517 .oversample = 8, 518 .component_only = false, 519 520 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */ 521 .hsync_end = 64, .hblank_end = 124, 522 .hblank_start = 836, .htotal = 857, 523 524 .progressive = false, .trilevel_sync = false, 525 526 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 527 .vsync_len = 6, 528 529 .veq_ena = true, .veq_start_f1 = 0, 530 .veq_start_f2 = 1, .veq_len = 18, 531 532 .vi_end_f1 = 20, .vi_end_f2 = 21, 533 .nbr_end = 240, 534 535 .burst_ena = true, 536 .hburst_start = 72, .hburst_len = 34, 537 .vburst_start_f1 = 9, .vburst_end_f1 = 240, 538 .vburst_start_f2 = 10, .vburst_end_f2 = 240, 539 .vburst_start_f3 = 9, .vburst_end_f3 = 240, 540 .vburst_start_f4 = 10, .vburst_end_f4 = 240, 541 542 /* desired 3.5800000 actual 3.5800000 clock 107.52 */ 543 .dda1_inc = 135, 544 .dda2_inc = 16704, .dda2_size = 27456, 545 .dda3_inc = 0, .dda3_size = 0, 546 .sc_reset = TV_SC_RESET_EVERY_8, 547 .pal_burst = true, 548 549 .composite_levels = &pal_m_levels_composite, 550 .composite_color = &pal_m_csc_composite, 551 .svideo_levels = &pal_m_levels_svideo, 552 .svideo_color = &pal_m_csc_svideo, 553 554 .filter_table = filter_table, 555 }, 556 { 557 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */ 558 .name = "PAL-N", 559 .clock = 108000, 560 .refresh = 50000, 561 .oversample = 8, 562 .component_only = false, 563 564 .hsync_end = 64, .hblank_end = 128, 565 .hblank_start = 844, .htotal = 863, 566 567 .progressive = false, .trilevel_sync = false, 568 569 570 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 571 .vsync_len = 6, 572 573 .veq_ena = true, .veq_start_f1 = 0, 574 .veq_start_f2 = 1, .veq_len = 18, 575 576 .vi_end_f1 = 24, .vi_end_f2 = 25, 577 .nbr_end = 286, 578 579 .burst_ena = true, 580 .hburst_start = 73, .hburst_len = 34, 581 .vburst_start_f1 = 8, .vburst_end_f1 = 285, 582 .vburst_start_f2 = 8, .vburst_end_f2 = 286, 583 .vburst_start_f3 = 9, .vburst_end_f3 = 286, 584 .vburst_start_f4 = 9, .vburst_end_f4 = 285, 585 586 587 /* desired 4.4336180 actual 4.4336180 clock 107.52 */ 588 .dda1_inc = 135, 589 .dda2_inc = 23578, .dda2_size = 27648, 590 .dda3_inc = 134, .dda3_size = 625, 591 .sc_reset = TV_SC_RESET_EVERY_8, 592 .pal_burst = true, 593 594 .composite_levels = &pal_n_levels_composite, 595 .composite_color = &pal_n_csc_composite, 596 .svideo_levels = &pal_n_levels_svideo, 597 .svideo_color = &pal_n_csc_svideo, 598 599 .filter_table = filter_table, 600 }, 601 { 602 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */ 603 .name = "PAL", 604 .clock = 108000, 605 .refresh = 50000, 606 .oversample = 8, 607 .component_only = false, 608 609 .hsync_end = 64, .hblank_end = 142, 610 .hblank_start = 844, .htotal = 863, 611 612 .progressive = false, .trilevel_sync = false, 613 614 .vsync_start_f1 = 5, .vsync_start_f2 = 6, 615 .vsync_len = 5, 616 617 .veq_ena = true, .veq_start_f1 = 0, 618 .veq_start_f2 = 1, .veq_len = 15, 619 620 .vi_end_f1 = 24, .vi_end_f2 = 25, 621 .nbr_end = 286, 622 623 .burst_ena = true, 624 .hburst_start = 73, .hburst_len = 32, 625 .vburst_start_f1 = 8, .vburst_end_f1 = 285, 626 .vburst_start_f2 = 8, .vburst_end_f2 = 286, 627 .vburst_start_f3 = 9, .vburst_end_f3 = 286, 628 .vburst_start_f4 = 9, .vburst_end_f4 = 285, 629 630 /* desired 4.4336180 actual 4.4336180 clock 107.52 */ 631 .dda1_inc = 168, 632 .dda2_inc = 4122, .dda2_size = 27648, 633 .dda3_inc = 67, .dda3_size = 625, 634 .sc_reset = TV_SC_RESET_EVERY_8, 635 .pal_burst = true, 636 637 .composite_levels = &pal_levels_composite, 638 .composite_color = &pal_csc_composite, 639 .svideo_levels = &pal_levels_svideo, 640 .svideo_color = &pal_csc_svideo, 641 642 .filter_table = filter_table, 643 }, 644 { 645 .name = "480p", 646 .clock = 108000, 647 .refresh = 59940, 648 .oversample = 4, 649 .component_only = true, 650 651 .hsync_end = 64, .hblank_end = 122, 652 .hblank_start = 842, .htotal = 857, 653 654 .progressive = true, .trilevel_sync = false, 655 656 .vsync_start_f1 = 12, .vsync_start_f2 = 12, 657 .vsync_len = 12, 658 659 .veq_ena = false, 660 661 .vi_end_f1 = 44, .vi_end_f2 = 44, 662 .nbr_end = 479, 663 664 .burst_ena = false, 665 666 .filter_table = filter_table, 667 }, 668 { 669 .name = "576p", 670 .clock = 108000, 671 .refresh = 50000, 672 .oversample = 4, 673 .component_only = true, 674 675 .hsync_end = 64, .hblank_end = 139, 676 .hblank_start = 859, .htotal = 863, 677 678 .progressive = true, .trilevel_sync = false, 679 680 .vsync_start_f1 = 10, .vsync_start_f2 = 10, 681 .vsync_len = 10, 682 683 .veq_ena = false, 684 685 .vi_end_f1 = 48, .vi_end_f2 = 48, 686 .nbr_end = 575, 687 688 .burst_ena = false, 689 690 .filter_table = filter_table, 691 }, 692 { 693 .name = "720p@60Hz", 694 .clock = 148500, 695 .refresh = 60000, 696 .oversample = 2, 697 .component_only = true, 698 699 .hsync_end = 80, .hblank_end = 300, 700 .hblank_start = 1580, .htotal = 1649, 701 702 .progressive = true, .trilevel_sync = true, 703 704 .vsync_start_f1 = 10, .vsync_start_f2 = 10, 705 .vsync_len = 10, 706 707 .veq_ena = false, 708 709 .vi_end_f1 = 29, .vi_end_f2 = 29, 710 .nbr_end = 719, 711 712 .burst_ena = false, 713 714 .filter_table = filter_table, 715 }, 716 { 717 .name = "720p@50Hz", 718 .clock = 148500, 719 .refresh = 50000, 720 .oversample = 2, 721 .component_only = true, 722 723 .hsync_end = 80, .hblank_end = 300, 724 .hblank_start = 1580, .htotal = 1979, 725 726 .progressive = true, .trilevel_sync = true, 727 728 .vsync_start_f1 = 10, .vsync_start_f2 = 10, 729 .vsync_len = 10, 730 731 .veq_ena = false, 732 733 .vi_end_f1 = 29, .vi_end_f2 = 29, 734 .nbr_end = 719, 735 736 .burst_ena = false, 737 738 .filter_table = filter_table, 739 }, 740 { 741 .name = "1080i@50Hz", 742 .clock = 148500, 743 .refresh = 50000, 744 .oversample = 2, 745 .component_only = true, 746 747 .hsync_end = 88, .hblank_end = 235, 748 .hblank_start = 2155, .htotal = 2639, 749 750 .progressive = false, .trilevel_sync = true, 751 752 .vsync_start_f1 = 4, .vsync_start_f2 = 5, 753 .vsync_len = 10, 754 755 .veq_ena = true, .veq_start_f1 = 4, 756 .veq_start_f2 = 4, .veq_len = 10, 757 758 759 .vi_end_f1 = 21, .vi_end_f2 = 22, 760 .nbr_end = 539, 761 762 .burst_ena = false, 763 764 .filter_table = filter_table, 765 }, 766 { 767 .name = "1080i@60Hz", 768 .clock = 148500, 769 .refresh = 60000, 770 .oversample = 2, 771 .component_only = true, 772 773 .hsync_end = 88, .hblank_end = 235, 774 .hblank_start = 2155, .htotal = 2199, 775 776 .progressive = false, .trilevel_sync = true, 777 778 .vsync_start_f1 = 4, .vsync_start_f2 = 5, 779 .vsync_len = 10, 780 781 .veq_ena = true, .veq_start_f1 = 4, 782 .veq_start_f2 = 4, .veq_len = 10, 783 784 785 .vi_end_f1 = 21, .vi_end_f2 = 22, 786 .nbr_end = 539, 787 788 .burst_ena = false, 789 790 .filter_table = filter_table, 791 }, 792 793 { 794 .name = "1080p@30Hz", 795 .clock = 148500, 796 .refresh = 30000, 797 .oversample = 2, 798 .component_only = true, 799 800 .hsync_end = 88, .hblank_end = 235, 801 .hblank_start = 2155, .htotal = 2199, 802 803 .progressive = true, .trilevel_sync = true, 804 805 .vsync_start_f1 = 8, .vsync_start_f2 = 8, 806 .vsync_len = 10, 807 808 .veq_ena = false, .veq_start_f1 = 0, 809 .veq_start_f2 = 0, .veq_len = 0, 810 811 .vi_end_f1 = 44, .vi_end_f2 = 44, 812 .nbr_end = 1079, 813 814 .burst_ena = false, 815 816 .filter_table = filter_table, 817 }, 818 819 { 820 .name = "1080p@50Hz", 821 .clock = 148500, 822 .refresh = 50000, 823 .oversample = 1, 824 .component_only = true, 825 826 .hsync_end = 88, .hblank_end = 235, 827 .hblank_start = 2155, .htotal = 2639, 828 829 .progressive = true, .trilevel_sync = true, 830 831 .vsync_start_f1 = 8, .vsync_start_f2 = 8, 832 .vsync_len = 10, 833 834 .veq_ena = false, .veq_start_f1 = 0, 835 .veq_start_f2 = 0, .veq_len = 0, 836 837 .vi_end_f1 = 44, .vi_end_f2 = 44, 838 .nbr_end = 1079, 839 840 .burst_ena = false, 841 842 .filter_table = filter_table, 843 }, 844 845 { 846 .name = "1080p@60Hz", 847 .clock = 148500, 848 .refresh = 60000, 849 .oversample = 1, 850 .component_only = true, 851 852 .hsync_end = 88, .hblank_end = 235, 853 .hblank_start = 2155, .htotal = 2199, 854 855 .progressive = true, .trilevel_sync = true, 856 857 .vsync_start_f1 = 8, .vsync_start_f2 = 8, 858 .vsync_len = 10, 859 860 .veq_ena = false, .veq_start_f1 = 0, 861 .veq_start_f2 = 0, .veq_len = 0, 862 863 .vi_end_f1 = 44, .vi_end_f2 = 44, 864 .nbr_end = 1079, 865 866 .burst_ena = false, 867 868 .filter_table = filter_table, 869 }, 870 }; 871 872 struct intel_tv_connector_state { 873 struct drm_connector_state base; 874 875 /* 876 * May need to override the user margins for 877 * gen3 >1024 wide source vertical centering. 878 */ 879 struct { 880 u16 top, bottom; 881 } margins; 882 883 bool bypass_vfilter; 884 }; 885 886 #define to_intel_tv_connector_state(x) container_of(x, struct intel_tv_connector_state, base) 887 888 static struct drm_connector_state * 889 intel_tv_connector_duplicate_state(struct drm_connector *connector) 890 { 891 struct intel_tv_connector_state *state; 892 893 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL); 894 if (!state) 895 return NULL; 896 897 __drm_atomic_helper_connector_duplicate_state(connector, &state->base); 898 return &state->base; 899 } 900 901 static struct intel_tv *enc_to_tv(struct intel_encoder *encoder) 902 { 903 return container_of(encoder, struct intel_tv, base); 904 } 905 906 static struct intel_tv *intel_attached_tv(struct intel_connector *connector) 907 { 908 return enc_to_tv(intel_attached_encoder(connector)); 909 } 910 911 static bool 912 intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe) 913 { 914 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 915 u32 tmp = intel_de_read(dev_priv, TV_CTL); 916 917 *pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT; 918 919 return tmp & TV_ENC_ENABLE; 920 } 921 922 static void 923 intel_enable_tv(struct intel_atomic_state *state, 924 struct intel_encoder *encoder, 925 const struct intel_crtc_state *pipe_config, 926 const struct drm_connector_state *conn_state) 927 { 928 struct drm_device *dev = encoder->base.dev; 929 struct drm_i915_private *dev_priv = to_i915(dev); 930 931 /* Prevents vblank waits from timing out in intel_tv_detect_type() */ 932 intel_crtc_wait_for_next_vblank(to_intel_crtc(pipe_config->uapi.crtc)); 933 934 intel_de_rmw(dev_priv, TV_CTL, 0, TV_ENC_ENABLE); 935 } 936 937 static void 938 intel_disable_tv(struct intel_atomic_state *state, 939 struct intel_encoder *encoder, 940 const struct intel_crtc_state *old_crtc_state, 941 const struct drm_connector_state *old_conn_state) 942 { 943 struct drm_device *dev = encoder->base.dev; 944 struct drm_i915_private *dev_priv = to_i915(dev); 945 946 intel_de_rmw(dev_priv, TV_CTL, TV_ENC_ENABLE, 0); 947 } 948 949 static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state) 950 { 951 int format = conn_state->tv.mode; 952 953 return &tv_modes[format]; 954 } 955 956 static enum drm_mode_status 957 intel_tv_mode_valid(struct drm_connector *connector, 958 struct drm_display_mode *mode) 959 { 960 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state); 961 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 962 963 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 964 return MODE_NO_DBLESCAN; 965 966 if (mode->clock > max_dotclk) 967 return MODE_CLOCK_HIGH; 968 969 /* Ensure TV refresh is close to desired refresh */ 970 if (abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000) >= 1000) 971 return MODE_CLOCK_RANGE; 972 973 return MODE_OK; 974 } 975 976 static int 977 intel_tv_mode_vdisplay(const struct tv_mode *tv_mode) 978 { 979 if (tv_mode->progressive) 980 return tv_mode->nbr_end + 1; 981 else 982 return 2 * (tv_mode->nbr_end + 1); 983 } 984 985 static void 986 intel_tv_mode_to_mode(struct drm_display_mode *mode, 987 const struct tv_mode *tv_mode, 988 int clock) 989 { 990 mode->clock = clock / (tv_mode->oversample >> !tv_mode->progressive); 991 992 /* 993 * tv_mode horizontal timings: 994 * 995 * hsync_end 996 * | hblank_end 997 * | | hblank_start 998 * | | | htotal 999 * | _______ | 1000 * ____/ \___ 1001 * \__/ \ 1002 */ 1003 mode->hdisplay = 1004 tv_mode->hblank_start - tv_mode->hblank_end; 1005 mode->hsync_start = mode->hdisplay + 1006 tv_mode->htotal - tv_mode->hblank_start; 1007 mode->hsync_end = mode->hsync_start + 1008 tv_mode->hsync_end; 1009 mode->htotal = tv_mode->htotal + 1; 1010 1011 /* 1012 * tv_mode vertical timings: 1013 * 1014 * vsync_start 1015 * | vsync_end 1016 * | | vi_end nbr_end 1017 * | | | | 1018 * | | _______ 1019 * \__ ____/ \ 1020 * \__/ 1021 */ 1022 mode->vdisplay = intel_tv_mode_vdisplay(tv_mode); 1023 if (tv_mode->progressive) { 1024 mode->vsync_start = mode->vdisplay + 1025 tv_mode->vsync_start_f1 + 1; 1026 mode->vsync_end = mode->vsync_start + 1027 tv_mode->vsync_len; 1028 mode->vtotal = mode->vdisplay + 1029 tv_mode->vi_end_f1 + 1; 1030 } else { 1031 mode->vsync_start = mode->vdisplay + 1032 tv_mode->vsync_start_f1 + 1 + 1033 tv_mode->vsync_start_f2 + 1; 1034 mode->vsync_end = mode->vsync_start + 1035 2 * tv_mode->vsync_len; 1036 mode->vtotal = mode->vdisplay + 1037 tv_mode->vi_end_f1 + 1 + 1038 tv_mode->vi_end_f2 + 1; 1039 } 1040 1041 /* TV has it's own notion of sync and other mode flags, so clear them. */ 1042 mode->flags = 0; 1043 1044 snprintf(mode->name, sizeof(mode->name), 1045 "%dx%d%c (%s)", 1046 mode->hdisplay, mode->vdisplay, 1047 tv_mode->progressive ? 'p' : 'i', 1048 tv_mode->name); 1049 } 1050 1051 static void intel_tv_scale_mode_horiz(struct drm_display_mode *mode, 1052 int hdisplay, int left_margin, 1053 int right_margin) 1054 { 1055 int hsync_start = mode->hsync_start - mode->hdisplay + right_margin; 1056 int hsync_end = mode->hsync_end - mode->hdisplay + right_margin; 1057 int new_htotal = mode->htotal * hdisplay / 1058 (mode->hdisplay - left_margin - right_margin); 1059 1060 mode->clock = mode->clock * new_htotal / mode->htotal; 1061 1062 mode->hdisplay = hdisplay; 1063 mode->hsync_start = hdisplay + hsync_start * new_htotal / mode->htotal; 1064 mode->hsync_end = hdisplay + hsync_end * new_htotal / mode->htotal; 1065 mode->htotal = new_htotal; 1066 } 1067 1068 static void intel_tv_scale_mode_vert(struct drm_display_mode *mode, 1069 int vdisplay, int top_margin, 1070 int bottom_margin) 1071 { 1072 int vsync_start = mode->vsync_start - mode->vdisplay + bottom_margin; 1073 int vsync_end = mode->vsync_end - mode->vdisplay + bottom_margin; 1074 int new_vtotal = mode->vtotal * vdisplay / 1075 (mode->vdisplay - top_margin - bottom_margin); 1076 1077 mode->clock = mode->clock * new_vtotal / mode->vtotal; 1078 1079 mode->vdisplay = vdisplay; 1080 mode->vsync_start = vdisplay + vsync_start * new_vtotal / mode->vtotal; 1081 mode->vsync_end = vdisplay + vsync_end * new_vtotal / mode->vtotal; 1082 mode->vtotal = new_vtotal; 1083 } 1084 1085 static void 1086 intel_tv_get_config(struct intel_encoder *encoder, 1087 struct intel_crtc_state *pipe_config) 1088 { 1089 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1090 struct drm_display_mode *adjusted_mode = 1091 &pipe_config->hw.adjusted_mode; 1092 struct drm_display_mode mode = {}; 1093 u32 tv_ctl, hctl1, hctl3, vctl1, vctl2, tmp; 1094 struct tv_mode tv_mode = {}; 1095 int hdisplay = adjusted_mode->crtc_hdisplay; 1096 int vdisplay = adjusted_mode->crtc_vdisplay; 1097 int xsize, ysize, xpos, ypos; 1098 1099 pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT); 1100 1101 tv_ctl = intel_de_read(dev_priv, TV_CTL); 1102 hctl1 = intel_de_read(dev_priv, TV_H_CTL_1); 1103 hctl3 = intel_de_read(dev_priv, TV_H_CTL_3); 1104 vctl1 = intel_de_read(dev_priv, TV_V_CTL_1); 1105 vctl2 = intel_de_read(dev_priv, TV_V_CTL_2); 1106 1107 tv_mode.htotal = (hctl1 & TV_HTOTAL_MASK) >> TV_HTOTAL_SHIFT; 1108 tv_mode.hsync_end = (hctl1 & TV_HSYNC_END_MASK) >> TV_HSYNC_END_SHIFT; 1109 1110 tv_mode.hblank_start = (hctl3 & TV_HBLANK_START_MASK) >> TV_HBLANK_START_SHIFT; 1111 tv_mode.hblank_end = (hctl3 & TV_HSYNC_END_MASK) >> TV_HBLANK_END_SHIFT; 1112 1113 tv_mode.nbr_end = (vctl1 & TV_NBR_END_MASK) >> TV_NBR_END_SHIFT; 1114 tv_mode.vi_end_f1 = (vctl1 & TV_VI_END_F1_MASK) >> TV_VI_END_F1_SHIFT; 1115 tv_mode.vi_end_f2 = (vctl1 & TV_VI_END_F2_MASK) >> TV_VI_END_F2_SHIFT; 1116 1117 tv_mode.vsync_len = (vctl2 & TV_VSYNC_LEN_MASK) >> TV_VSYNC_LEN_SHIFT; 1118 tv_mode.vsync_start_f1 = (vctl2 & TV_VSYNC_START_F1_MASK) >> TV_VSYNC_START_F1_SHIFT; 1119 tv_mode.vsync_start_f2 = (vctl2 & TV_VSYNC_START_F2_MASK) >> TV_VSYNC_START_F2_SHIFT; 1120 1121 tv_mode.clock = pipe_config->port_clock; 1122 1123 tv_mode.progressive = tv_ctl & TV_PROGRESSIVE; 1124 1125 switch (tv_ctl & TV_OVERSAMPLE_MASK) { 1126 case TV_OVERSAMPLE_8X: 1127 tv_mode.oversample = 8; 1128 break; 1129 case TV_OVERSAMPLE_4X: 1130 tv_mode.oversample = 4; 1131 break; 1132 case TV_OVERSAMPLE_2X: 1133 tv_mode.oversample = 2; 1134 break; 1135 default: 1136 tv_mode.oversample = 1; 1137 break; 1138 } 1139 1140 tmp = intel_de_read(dev_priv, TV_WIN_POS); 1141 xpos = tmp >> 16; 1142 ypos = tmp & 0xffff; 1143 1144 tmp = intel_de_read(dev_priv, TV_WIN_SIZE); 1145 xsize = tmp >> 16; 1146 ysize = tmp & 0xffff; 1147 1148 intel_tv_mode_to_mode(&mode, &tv_mode, pipe_config->port_clock); 1149 1150 drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n", 1151 DRM_MODE_ARG(&mode)); 1152 1153 intel_tv_scale_mode_horiz(&mode, hdisplay, 1154 xpos, mode.hdisplay - xsize - xpos); 1155 intel_tv_scale_mode_vert(&mode, vdisplay, 1156 ypos, mode.vdisplay - ysize - ypos); 1157 1158 adjusted_mode->crtc_clock = mode.clock; 1159 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 1160 adjusted_mode->crtc_clock /= 2; 1161 1162 /* pixel counter doesn't work on i965gm TV output */ 1163 if (IS_I965GM(dev_priv)) 1164 pipe_config->mode_flags |= 1165 I915_MODE_FLAG_USE_SCANLINE_COUNTER; 1166 } 1167 1168 static bool intel_tv_source_too_wide(struct drm_i915_private *dev_priv, 1169 int hdisplay) 1170 { 1171 return DISPLAY_VER(dev_priv) == 3 && hdisplay > 1024; 1172 } 1173 1174 static bool intel_tv_vert_scaling(const struct drm_display_mode *tv_mode, 1175 const struct drm_connector_state *conn_state, 1176 int vdisplay) 1177 { 1178 return tv_mode->crtc_vdisplay - 1179 conn_state->tv.margins.top - 1180 conn_state->tv.margins.bottom != 1181 vdisplay; 1182 } 1183 1184 static int 1185 intel_tv_compute_config(struct intel_encoder *encoder, 1186 struct intel_crtc_state *pipe_config, 1187 struct drm_connector_state *conn_state) 1188 { 1189 struct intel_atomic_state *state = 1190 to_intel_atomic_state(pipe_config->uapi.state); 1191 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1192 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1193 struct intel_tv_connector_state *tv_conn_state = 1194 to_intel_tv_connector_state(conn_state); 1195 const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state); 1196 struct drm_display_mode *adjusted_mode = 1197 &pipe_config->hw.adjusted_mode; 1198 int hdisplay = adjusted_mode->crtc_hdisplay; 1199 int vdisplay = adjusted_mode->crtc_vdisplay; 1200 int ret; 1201 1202 if (!tv_mode) 1203 return -EINVAL; 1204 1205 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 1206 return -EINVAL; 1207 1208 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1209 1210 drm_dbg_kms(&dev_priv->drm, "forcing bpc to 8 for TV\n"); 1211 pipe_config->pipe_bpp = 8*3; 1212 1213 pipe_config->port_clock = tv_mode->clock; 1214 1215 ret = intel_dpll_crtc_compute_clock(state, crtc); 1216 if (ret) 1217 return ret; 1218 1219 pipe_config->clock_set = true; 1220 1221 intel_tv_mode_to_mode(adjusted_mode, tv_mode, pipe_config->port_clock); 1222 drm_mode_set_crtcinfo(adjusted_mode, 0); 1223 1224 if (intel_tv_source_too_wide(dev_priv, hdisplay) || 1225 !intel_tv_vert_scaling(adjusted_mode, conn_state, vdisplay)) { 1226 int extra, top, bottom; 1227 1228 extra = adjusted_mode->crtc_vdisplay - vdisplay; 1229 1230 if (extra < 0) { 1231 drm_dbg_kms(&dev_priv->drm, 1232 "No vertical scaling for >1024 pixel wide modes\n"); 1233 return -EINVAL; 1234 } 1235 1236 /* Need to turn off the vertical filter and center the image */ 1237 1238 /* Attempt to maintain the relative sizes of the margins */ 1239 top = conn_state->tv.margins.top; 1240 bottom = conn_state->tv.margins.bottom; 1241 1242 if (top + bottom) 1243 top = extra * top / (top + bottom); 1244 else 1245 top = extra / 2; 1246 bottom = extra - top; 1247 1248 tv_conn_state->margins.top = top; 1249 tv_conn_state->margins.bottom = bottom; 1250 1251 tv_conn_state->bypass_vfilter = true; 1252 1253 if (!tv_mode->progressive) { 1254 adjusted_mode->clock /= 2; 1255 adjusted_mode->crtc_clock /= 2; 1256 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE; 1257 } 1258 } else { 1259 tv_conn_state->margins.top = conn_state->tv.margins.top; 1260 tv_conn_state->margins.bottom = conn_state->tv.margins.bottom; 1261 1262 tv_conn_state->bypass_vfilter = false; 1263 } 1264 1265 drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n", 1266 DRM_MODE_ARG(adjusted_mode)); 1267 1268 /* 1269 * The pipe scanline counter behaviour looks as follows when 1270 * using the TV encoder: 1271 * 1272 * time -> 1273 * 1274 * dsl=vtotal-1 | | 1275 * || || 1276 * ___| | ___| | 1277 * / | / | 1278 * / | / | 1279 * dsl=0 ___/ |_____/ | 1280 * | | | | | | 1281 * ^ ^ ^ ^ ^ 1282 * | | | | pipe vblank/first part of tv vblank 1283 * | | | bottom margin 1284 * | | active 1285 * | top margin 1286 * remainder of tv vblank 1287 * 1288 * When the TV encoder is used the pipe wants to run faster 1289 * than expected rate. During the active portion the TV 1290 * encoder stalls the pipe every few lines to keep it in 1291 * check. When the TV encoder reaches the bottom margin the 1292 * pipe simply stops. Once we reach the TV vblank the pipe is 1293 * no longer stalled and it runs at the max rate (apparently 1294 * oversample clock on gen3, cdclk on gen4). Once the pipe 1295 * reaches the pipe vtotal the pipe stops for the remainder 1296 * of the TV vblank/top margin. The pipe starts up again when 1297 * the TV encoder exits the top margin. 1298 * 1299 * To avoid huge hassles for vblank timestamping we scale 1300 * the pipe timings as if the pipe always runs at the average 1301 * rate it maintains during the active period. This also 1302 * gives us a reasonable guesstimate as to the pixel rate. 1303 * Due to the variation in the actual pipe speed the scanline 1304 * counter will give us slightly erroneous results during the 1305 * TV vblank/margins. But since vtotal was selected such that 1306 * it matches the average rate of the pipe during the active 1307 * portion the error shouldn't cause any serious grief to 1308 * vblank timestamps. 1309 * 1310 * For posterity here is the empirically derived formula 1311 * that gives us the maximum length of the pipe vblank 1312 * we can use without causing display corruption. Following 1313 * this would allow us to have a ticking scanline counter 1314 * everywhere except during the bottom margin (there the 1315 * pipe always stops). Ie. this would eliminate the second 1316 * flat portion of the above graph. However this would also 1317 * complicate vblank timestamping as the pipe vtotal would 1318 * no longer match the average rate the pipe runs at during 1319 * the active portion. Hence following this formula seems 1320 * more trouble that it's worth. 1321 * 1322 * if (GRAPHICS_VER(dev_priv) == 4) { 1323 * num = cdclk * (tv_mode->oversample >> !tv_mode->progressive); 1324 * den = tv_mode->clock; 1325 * } else { 1326 * num = tv_mode->oversample >> !tv_mode->progressive; 1327 * den = 1; 1328 * } 1329 * max_pipe_vblank_len ~= 1330 * (num * tv_htotal * (tv_vblank_len + top_margin)) / 1331 * (den * pipe_htotal); 1332 */ 1333 intel_tv_scale_mode_horiz(adjusted_mode, hdisplay, 1334 conn_state->tv.margins.left, 1335 conn_state->tv.margins.right); 1336 intel_tv_scale_mode_vert(adjusted_mode, vdisplay, 1337 tv_conn_state->margins.top, 1338 tv_conn_state->margins.bottom); 1339 drm_mode_set_crtcinfo(adjusted_mode, 0); 1340 adjusted_mode->name[0] = '\0'; 1341 1342 /* pixel counter doesn't work on i965gm TV output */ 1343 if (IS_I965GM(dev_priv)) 1344 pipe_config->mode_flags |= 1345 I915_MODE_FLAG_USE_SCANLINE_COUNTER; 1346 1347 return 0; 1348 } 1349 1350 static void 1351 set_tv_mode_timings(struct drm_i915_private *dev_priv, 1352 const struct tv_mode *tv_mode, 1353 bool burst_ena) 1354 { 1355 u32 hctl1, hctl2, hctl3; 1356 u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7; 1357 1358 hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) | 1359 (tv_mode->htotal << TV_HTOTAL_SHIFT); 1360 1361 hctl2 = (tv_mode->hburst_start << 16) | 1362 (tv_mode->hburst_len << TV_HBURST_LEN_SHIFT); 1363 1364 if (burst_ena) 1365 hctl2 |= TV_BURST_ENA; 1366 1367 hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) | 1368 (tv_mode->hblank_end << TV_HBLANK_END_SHIFT); 1369 1370 vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) | 1371 (tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) | 1372 (tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT); 1373 1374 vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) | 1375 (tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) | 1376 (tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT); 1377 1378 vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) | 1379 (tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) | 1380 (tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT); 1381 1382 if (tv_mode->veq_ena) 1383 vctl3 |= TV_EQUAL_ENA; 1384 1385 vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) | 1386 (tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT); 1387 1388 vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) | 1389 (tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT); 1390 1391 vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) | 1392 (tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT); 1393 1394 vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) | 1395 (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT); 1396 1397 intel_de_write(dev_priv, TV_H_CTL_1, hctl1); 1398 intel_de_write(dev_priv, TV_H_CTL_2, hctl2); 1399 intel_de_write(dev_priv, TV_H_CTL_3, hctl3); 1400 intel_de_write(dev_priv, TV_V_CTL_1, vctl1); 1401 intel_de_write(dev_priv, TV_V_CTL_2, vctl2); 1402 intel_de_write(dev_priv, TV_V_CTL_3, vctl3); 1403 intel_de_write(dev_priv, TV_V_CTL_4, vctl4); 1404 intel_de_write(dev_priv, TV_V_CTL_5, vctl5); 1405 intel_de_write(dev_priv, TV_V_CTL_6, vctl6); 1406 intel_de_write(dev_priv, TV_V_CTL_7, vctl7); 1407 } 1408 1409 static void set_color_conversion(struct drm_i915_private *dev_priv, 1410 const struct color_conversion *color_conversion) 1411 { 1412 if (!color_conversion) 1413 return; 1414 1415 intel_de_write(dev_priv, TV_CSC_Y, 1416 (color_conversion->ry << 16) | color_conversion->gy); 1417 intel_de_write(dev_priv, TV_CSC_Y2, 1418 (color_conversion->by << 16) | color_conversion->ay); 1419 intel_de_write(dev_priv, TV_CSC_U, 1420 (color_conversion->ru << 16) | color_conversion->gu); 1421 intel_de_write(dev_priv, TV_CSC_U2, 1422 (color_conversion->bu << 16) | color_conversion->au); 1423 intel_de_write(dev_priv, TV_CSC_V, 1424 (color_conversion->rv << 16) | color_conversion->gv); 1425 intel_de_write(dev_priv, TV_CSC_V2, 1426 (color_conversion->bv << 16) | color_conversion->av); 1427 } 1428 1429 static void intel_tv_pre_enable(struct intel_atomic_state *state, 1430 struct intel_encoder *encoder, 1431 const struct intel_crtc_state *pipe_config, 1432 const struct drm_connector_state *conn_state) 1433 { 1434 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1435 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1436 struct intel_tv *intel_tv = enc_to_tv(encoder); 1437 const struct intel_tv_connector_state *tv_conn_state = 1438 to_intel_tv_connector_state(conn_state); 1439 const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state); 1440 u32 tv_ctl, tv_filter_ctl; 1441 u32 scctl1, scctl2, scctl3; 1442 int i, j; 1443 const struct video_levels *video_levels; 1444 const struct color_conversion *color_conversion; 1445 bool burst_ena; 1446 int xpos, ypos; 1447 unsigned int xsize, ysize; 1448 1449 if (!tv_mode) 1450 return; /* can't happen (mode_prepare prevents this) */ 1451 1452 tv_ctl = intel_de_read(dev_priv, TV_CTL); 1453 tv_ctl &= TV_CTL_SAVE; 1454 1455 switch (intel_tv->type) { 1456 default: 1457 case DRM_MODE_CONNECTOR_Unknown: 1458 case DRM_MODE_CONNECTOR_Composite: 1459 tv_ctl |= TV_ENC_OUTPUT_COMPOSITE; 1460 video_levels = tv_mode->composite_levels; 1461 color_conversion = tv_mode->composite_color; 1462 burst_ena = tv_mode->burst_ena; 1463 break; 1464 case DRM_MODE_CONNECTOR_Component: 1465 tv_ctl |= TV_ENC_OUTPUT_COMPONENT; 1466 video_levels = &component_levels; 1467 if (tv_mode->burst_ena) 1468 color_conversion = &sdtv_csc_yprpb; 1469 else 1470 color_conversion = &hdtv_csc_yprpb; 1471 burst_ena = false; 1472 break; 1473 case DRM_MODE_CONNECTOR_SVIDEO: 1474 tv_ctl |= TV_ENC_OUTPUT_SVIDEO; 1475 video_levels = tv_mode->svideo_levels; 1476 color_conversion = tv_mode->svideo_color; 1477 burst_ena = tv_mode->burst_ena; 1478 break; 1479 } 1480 1481 tv_ctl |= TV_ENC_PIPE_SEL(crtc->pipe); 1482 1483 switch (tv_mode->oversample) { 1484 case 8: 1485 tv_ctl |= TV_OVERSAMPLE_8X; 1486 break; 1487 case 4: 1488 tv_ctl |= TV_OVERSAMPLE_4X; 1489 break; 1490 case 2: 1491 tv_ctl |= TV_OVERSAMPLE_2X; 1492 break; 1493 default: 1494 tv_ctl |= TV_OVERSAMPLE_NONE; 1495 break; 1496 } 1497 1498 if (tv_mode->progressive) 1499 tv_ctl |= TV_PROGRESSIVE; 1500 if (tv_mode->trilevel_sync) 1501 tv_ctl |= TV_TRILEVEL_SYNC; 1502 if (tv_mode->pal_burst) 1503 tv_ctl |= TV_PAL_BURST; 1504 1505 scctl1 = 0; 1506 if (tv_mode->dda1_inc) 1507 scctl1 |= TV_SC_DDA1_EN; 1508 if (tv_mode->dda2_inc) 1509 scctl1 |= TV_SC_DDA2_EN; 1510 if (tv_mode->dda3_inc) 1511 scctl1 |= TV_SC_DDA3_EN; 1512 scctl1 |= tv_mode->sc_reset; 1513 if (video_levels) 1514 scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT; 1515 scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT; 1516 1517 scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT | 1518 tv_mode->dda2_inc << TV_SCDDA2_INC_SHIFT; 1519 1520 scctl3 = tv_mode->dda3_size << TV_SCDDA3_SIZE_SHIFT | 1521 tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT; 1522 1523 /* Enable two fixes for the chips that need them. */ 1524 if (IS_I915GM(dev_priv)) 1525 tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX; 1526 1527 set_tv_mode_timings(dev_priv, tv_mode, burst_ena); 1528 1529 intel_de_write(dev_priv, TV_SC_CTL_1, scctl1); 1530 intel_de_write(dev_priv, TV_SC_CTL_2, scctl2); 1531 intel_de_write(dev_priv, TV_SC_CTL_3, scctl3); 1532 1533 set_color_conversion(dev_priv, color_conversion); 1534 1535 if (DISPLAY_VER(dev_priv) >= 4) 1536 intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00404000); 1537 else 1538 intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00606000); 1539 1540 if (video_levels) 1541 intel_de_write(dev_priv, TV_CLR_LEVEL, 1542 ((video_levels->black << TV_BLACK_LEVEL_SHIFT) | (video_levels->blank << TV_BLANK_LEVEL_SHIFT))); 1543 1544 assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder); 1545 1546 /* Filter ctl must be set before TV_WIN_SIZE */ 1547 tv_filter_ctl = TV_AUTO_SCALE; 1548 if (tv_conn_state->bypass_vfilter) 1549 tv_filter_ctl |= TV_V_FILTER_BYPASS; 1550 intel_de_write(dev_priv, TV_FILTER_CTL_1, tv_filter_ctl); 1551 1552 xsize = tv_mode->hblank_start - tv_mode->hblank_end; 1553 ysize = intel_tv_mode_vdisplay(tv_mode); 1554 1555 xpos = conn_state->tv.margins.left; 1556 ypos = tv_conn_state->margins.top; 1557 xsize -= (conn_state->tv.margins.left + 1558 conn_state->tv.margins.right); 1559 ysize -= (tv_conn_state->margins.top + 1560 tv_conn_state->margins.bottom); 1561 intel_de_write(dev_priv, TV_WIN_POS, (xpos << 16) | ypos); 1562 intel_de_write(dev_priv, TV_WIN_SIZE, (xsize << 16) | ysize); 1563 1564 j = 0; 1565 for (i = 0; i < 60; i++) 1566 intel_de_write(dev_priv, TV_H_LUMA(i), 1567 tv_mode->filter_table[j++]); 1568 for (i = 0; i < 60; i++) 1569 intel_de_write(dev_priv, TV_H_CHROMA(i), 1570 tv_mode->filter_table[j++]); 1571 for (i = 0; i < 43; i++) 1572 intel_de_write(dev_priv, TV_V_LUMA(i), 1573 tv_mode->filter_table[j++]); 1574 for (i = 0; i < 43; i++) 1575 intel_de_write(dev_priv, TV_V_CHROMA(i), 1576 tv_mode->filter_table[j++]); 1577 intel_de_write(dev_priv, TV_DAC, 1578 intel_de_read(dev_priv, TV_DAC) & TV_DAC_SAVE); 1579 intel_de_write(dev_priv, TV_CTL, tv_ctl); 1580 } 1581 1582 static int 1583 intel_tv_detect_type(struct intel_tv *intel_tv, 1584 struct drm_connector *connector) 1585 { 1586 struct intel_crtc *crtc = to_intel_crtc(connector->state->crtc); 1587 struct drm_device *dev = connector->dev; 1588 struct drm_i915_private *dev_priv = to_i915(dev); 1589 u32 tv_ctl, save_tv_ctl; 1590 u32 tv_dac, save_tv_dac; 1591 int type; 1592 1593 /* Disable TV interrupts around load detect or we'll recurse */ 1594 if (connector->polled & DRM_CONNECTOR_POLL_HPD) { 1595 spin_lock_irq(&dev_priv->irq_lock); 1596 i915_disable_pipestat(dev_priv, 0, 1597 PIPE_HOTPLUG_INTERRUPT_STATUS | 1598 PIPE_HOTPLUG_TV_INTERRUPT_STATUS); 1599 spin_unlock_irq(&dev_priv->irq_lock); 1600 } 1601 1602 save_tv_dac = tv_dac = intel_de_read(dev_priv, TV_DAC); 1603 save_tv_ctl = tv_ctl = intel_de_read(dev_priv, TV_CTL); 1604 1605 /* Poll for TV detection */ 1606 tv_ctl &= ~(TV_ENC_ENABLE | TV_ENC_PIPE_SEL_MASK | TV_TEST_MODE_MASK); 1607 tv_ctl |= TV_TEST_MODE_MONITOR_DETECT; 1608 tv_ctl |= TV_ENC_PIPE_SEL(crtc->pipe); 1609 1610 tv_dac &= ~(TVDAC_SENSE_MASK | DAC_A_MASK | DAC_B_MASK | DAC_C_MASK); 1611 tv_dac |= (TVDAC_STATE_CHG_EN | 1612 TVDAC_A_SENSE_CTL | 1613 TVDAC_B_SENSE_CTL | 1614 TVDAC_C_SENSE_CTL | 1615 DAC_CTL_OVERRIDE | 1616 DAC_A_0_7_V | 1617 DAC_B_0_7_V | 1618 DAC_C_0_7_V); 1619 1620 1621 /* 1622 * The TV sense state should be cleared to zero on cantiga platform. Otherwise 1623 * the TV is misdetected. This is hardware requirement. 1624 */ 1625 if (IS_GM45(dev_priv)) 1626 tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL | 1627 TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL); 1628 1629 intel_de_write(dev_priv, TV_CTL, tv_ctl); 1630 intel_de_write(dev_priv, TV_DAC, tv_dac); 1631 intel_de_posting_read(dev_priv, TV_DAC); 1632 1633 intel_crtc_wait_for_next_vblank(crtc); 1634 1635 type = -1; 1636 tv_dac = intel_de_read(dev_priv, TV_DAC); 1637 drm_dbg_kms(&dev_priv->drm, "TV detected: %x, %x\n", tv_ctl, tv_dac); 1638 /* 1639 * A B C 1640 * 0 1 1 Composite 1641 * 1 0 X svideo 1642 * 0 0 0 Component 1643 */ 1644 if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) { 1645 drm_dbg_kms(&dev_priv->drm, 1646 "Detected Composite TV connection\n"); 1647 type = DRM_MODE_CONNECTOR_Composite; 1648 } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) { 1649 drm_dbg_kms(&dev_priv->drm, 1650 "Detected S-Video TV connection\n"); 1651 type = DRM_MODE_CONNECTOR_SVIDEO; 1652 } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) { 1653 drm_dbg_kms(&dev_priv->drm, 1654 "Detected Component TV connection\n"); 1655 type = DRM_MODE_CONNECTOR_Component; 1656 } else { 1657 drm_dbg_kms(&dev_priv->drm, "Unrecognised TV connection\n"); 1658 type = -1; 1659 } 1660 1661 intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN); 1662 intel_de_write(dev_priv, TV_CTL, save_tv_ctl); 1663 intel_de_posting_read(dev_priv, TV_CTL); 1664 1665 /* For unknown reasons the hw barfs if we don't do this vblank wait. */ 1666 intel_crtc_wait_for_next_vblank(crtc); 1667 1668 /* Restore interrupt config */ 1669 if (connector->polled & DRM_CONNECTOR_POLL_HPD) { 1670 spin_lock_irq(&dev_priv->irq_lock); 1671 i915_enable_pipestat(dev_priv, 0, 1672 PIPE_HOTPLUG_INTERRUPT_STATUS | 1673 PIPE_HOTPLUG_TV_INTERRUPT_STATUS); 1674 spin_unlock_irq(&dev_priv->irq_lock); 1675 } 1676 1677 return type; 1678 } 1679 1680 /* 1681 * Here we set accurate tv format according to connector type 1682 * i.e Component TV should not be assigned by NTSC or PAL 1683 */ 1684 static void intel_tv_find_better_format(struct drm_connector *connector) 1685 { 1686 struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector)); 1687 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state); 1688 int i; 1689 1690 /* Component supports everything so we can keep the current mode */ 1691 if (intel_tv->type == DRM_MODE_CONNECTOR_Component) 1692 return; 1693 1694 /* If the current mode is fine don't change it */ 1695 if (!tv_mode->component_only) 1696 return; 1697 1698 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) { 1699 tv_mode = &tv_modes[i]; 1700 1701 if (!tv_mode->component_only) 1702 break; 1703 } 1704 1705 connector->state->tv.mode = i; 1706 } 1707 1708 static int 1709 intel_tv_detect(struct drm_connector *connector, 1710 struct drm_modeset_acquire_ctx *ctx, 1711 bool force) 1712 { 1713 struct drm_i915_private *i915 = to_i915(connector->dev); 1714 struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector)); 1715 enum drm_connector_status status; 1716 int type; 1717 1718 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] force=%d\n", 1719 connector->base.id, connector->name, force); 1720 1721 if (!INTEL_DISPLAY_ENABLED(i915)) 1722 return connector_status_disconnected; 1723 1724 if (force) { 1725 struct intel_load_detect_pipe tmp; 1726 int ret; 1727 1728 ret = intel_get_load_detect_pipe(connector, &tmp, ctx); 1729 if (ret < 0) 1730 return ret; 1731 1732 if (ret > 0) { 1733 type = intel_tv_detect_type(intel_tv, connector); 1734 intel_release_load_detect_pipe(connector, &tmp, ctx); 1735 status = type < 0 ? 1736 connector_status_disconnected : 1737 connector_status_connected; 1738 } else 1739 status = connector_status_unknown; 1740 1741 if (status == connector_status_connected) { 1742 intel_tv->type = type; 1743 intel_tv_find_better_format(connector); 1744 } 1745 1746 return status; 1747 } else 1748 return connector->status; 1749 } 1750 1751 static const struct input_res { 1752 u16 w, h; 1753 } input_res_table[] = { 1754 { 640, 480 }, 1755 { 800, 600 }, 1756 { 1024, 768 }, 1757 { 1280, 1024 }, 1758 { 848, 480 }, 1759 { 1280, 720 }, 1760 { 1920, 1080 }, 1761 }; 1762 1763 /* Choose preferred mode according to line number of TV format */ 1764 static bool 1765 intel_tv_is_preferred_mode(const struct drm_display_mode *mode, 1766 const struct tv_mode *tv_mode) 1767 { 1768 int vdisplay = intel_tv_mode_vdisplay(tv_mode); 1769 1770 /* prefer 480 line modes for all SD TV modes */ 1771 if (vdisplay <= 576) 1772 vdisplay = 480; 1773 1774 return vdisplay == mode->vdisplay; 1775 } 1776 1777 static void 1778 intel_tv_set_mode_type(struct drm_display_mode *mode, 1779 const struct tv_mode *tv_mode) 1780 { 1781 mode->type = DRM_MODE_TYPE_DRIVER; 1782 1783 if (intel_tv_is_preferred_mode(mode, tv_mode)) 1784 mode->type |= DRM_MODE_TYPE_PREFERRED; 1785 } 1786 1787 static int 1788 intel_tv_get_modes(struct drm_connector *connector) 1789 { 1790 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1791 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state); 1792 int i, count = 0; 1793 1794 for (i = 0; i < ARRAY_SIZE(input_res_table); i++) { 1795 const struct input_res *input = &input_res_table[i]; 1796 struct drm_display_mode *mode; 1797 1798 if (input->w > 1024 && 1799 !tv_mode->progressive && 1800 !tv_mode->component_only) 1801 continue; 1802 1803 /* no vertical scaling with wide sources on gen3 */ 1804 if (DISPLAY_VER(dev_priv) == 3 && input->w > 1024 && 1805 input->h > intel_tv_mode_vdisplay(tv_mode)) 1806 continue; 1807 1808 mode = drm_mode_create(connector->dev); 1809 if (!mode) 1810 continue; 1811 1812 /* 1813 * We take the TV mode and scale it to look 1814 * like it had the expected h/vdisplay. This 1815 * provides the most information to userspace 1816 * about the actual timings of the mode. We 1817 * do ignore the margins though. 1818 */ 1819 intel_tv_mode_to_mode(mode, tv_mode, tv_mode->clock); 1820 if (count == 0) { 1821 drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n", 1822 DRM_MODE_ARG(mode)); 1823 } 1824 intel_tv_scale_mode_horiz(mode, input->w, 0, 0); 1825 intel_tv_scale_mode_vert(mode, input->h, 0, 0); 1826 intel_tv_set_mode_type(mode, tv_mode); 1827 1828 drm_mode_set_name(mode); 1829 1830 drm_mode_probed_add(connector, mode); 1831 count++; 1832 } 1833 1834 return count; 1835 } 1836 1837 static const struct drm_connector_funcs intel_tv_connector_funcs = { 1838 .late_register = intel_connector_register, 1839 .early_unregister = intel_connector_unregister, 1840 .destroy = intel_connector_destroy, 1841 .fill_modes = drm_helper_probe_single_connector_modes, 1842 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1843 .atomic_duplicate_state = intel_tv_connector_duplicate_state, 1844 }; 1845 1846 static int intel_tv_atomic_check(struct drm_connector *connector, 1847 struct drm_atomic_state *state) 1848 { 1849 struct drm_connector_state *new_state; 1850 struct drm_crtc_state *new_crtc_state; 1851 struct drm_connector_state *old_state; 1852 1853 new_state = drm_atomic_get_new_connector_state(state, connector); 1854 if (!new_state->crtc) 1855 return 0; 1856 1857 old_state = drm_atomic_get_old_connector_state(state, connector); 1858 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc); 1859 1860 if (old_state->tv.mode != new_state->tv.mode || 1861 old_state->tv.margins.left != new_state->tv.margins.left || 1862 old_state->tv.margins.right != new_state->tv.margins.right || 1863 old_state->tv.margins.top != new_state->tv.margins.top || 1864 old_state->tv.margins.bottom != new_state->tv.margins.bottom) { 1865 /* Force a modeset. */ 1866 1867 new_crtc_state->connectors_changed = true; 1868 } 1869 1870 return 0; 1871 } 1872 1873 static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs = { 1874 .detect_ctx = intel_tv_detect, 1875 .mode_valid = intel_tv_mode_valid, 1876 .get_modes = intel_tv_get_modes, 1877 .atomic_check = intel_tv_atomic_check, 1878 }; 1879 1880 static const struct drm_encoder_funcs intel_tv_enc_funcs = { 1881 .destroy = intel_encoder_destroy, 1882 }; 1883 1884 static void intel_tv_add_properties(struct drm_connector *connector) 1885 { 1886 struct drm_i915_private *i915 = to_i915(connector->dev); 1887 struct drm_connector_state *conn_state = connector->state; 1888 const char *tv_format_names[ARRAY_SIZE(tv_modes)]; 1889 int i; 1890 1891 /* BIOS margin values */ 1892 conn_state->tv.margins.left = 54; 1893 conn_state->tv.margins.top = 36; 1894 conn_state->tv.margins.right = 46; 1895 conn_state->tv.margins.bottom = 37; 1896 1897 conn_state->tv.mode = 0; 1898 1899 /* Create TV properties then attach current values */ 1900 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) { 1901 /* 1080p50/1080p60 not supported on gen3 */ 1902 if (DISPLAY_VER(i915) == 3 && tv_modes[i].oversample == 1) 1903 break; 1904 1905 tv_format_names[i] = tv_modes[i].name; 1906 } 1907 drm_mode_create_tv_properties_legacy(&i915->drm, i, tv_format_names); 1908 1909 drm_object_attach_property(&connector->base, 1910 i915->drm.mode_config.legacy_tv_mode_property, 1911 conn_state->tv.mode); 1912 drm_object_attach_property(&connector->base, 1913 i915->drm.mode_config.tv_left_margin_property, 1914 conn_state->tv.margins.left); 1915 drm_object_attach_property(&connector->base, 1916 i915->drm.mode_config.tv_top_margin_property, 1917 conn_state->tv.margins.top); 1918 drm_object_attach_property(&connector->base, 1919 i915->drm.mode_config.tv_right_margin_property, 1920 conn_state->tv.margins.right); 1921 drm_object_attach_property(&connector->base, 1922 i915->drm.mode_config.tv_bottom_margin_property, 1923 conn_state->tv.margins.bottom); 1924 } 1925 1926 void 1927 intel_tv_init(struct drm_i915_private *dev_priv) 1928 { 1929 struct drm_connector *connector; 1930 struct intel_tv *intel_tv; 1931 struct intel_encoder *intel_encoder; 1932 struct intel_connector *intel_connector; 1933 u32 tv_dac_on, tv_dac_off, save_tv_dac; 1934 1935 if ((intel_de_read(dev_priv, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED) 1936 return; 1937 1938 if (!intel_bios_is_tv_present(dev_priv)) { 1939 drm_dbg_kms(&dev_priv->drm, "Integrated TV is not present.\n"); 1940 return; 1941 } 1942 1943 /* 1944 * Sanity check the TV output by checking to see if the 1945 * DAC register holds a value 1946 */ 1947 save_tv_dac = intel_de_read(dev_priv, TV_DAC); 1948 1949 intel_de_write(dev_priv, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN); 1950 tv_dac_on = intel_de_read(dev_priv, TV_DAC); 1951 1952 intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN); 1953 tv_dac_off = intel_de_read(dev_priv, TV_DAC); 1954 1955 intel_de_write(dev_priv, TV_DAC, save_tv_dac); 1956 1957 /* 1958 * If the register does not hold the state change enable 1959 * bit, (either as a 0 or a 1), assume it doesn't really 1960 * exist 1961 */ 1962 if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 || 1963 (tv_dac_off & TVDAC_STATE_CHG_EN) != 0) 1964 return; 1965 1966 intel_tv = kzalloc(sizeof(*intel_tv), GFP_KERNEL); 1967 if (!intel_tv) { 1968 return; 1969 } 1970 1971 intel_connector = intel_connector_alloc(); 1972 if (!intel_connector) { 1973 kfree(intel_tv); 1974 return; 1975 } 1976 1977 intel_encoder = &intel_tv->base; 1978 connector = &intel_connector->base; 1979 1980 /* 1981 * The documentation, for the older chipsets at least, recommend 1982 * using a polling method rather than hotplug detection for TVs. 1983 * This is because in order to perform the hotplug detection, the PLLs 1984 * for the TV must be kept alive increasing power drain and starving 1985 * bandwidth from other encoders. Notably for instance, it causes 1986 * pipe underruns on Crestline when this encoder is supposedly idle. 1987 * 1988 * More recent chipsets favour HDMI rather than integrated S-Video. 1989 */ 1990 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1991 1992 drm_connector_init(&dev_priv->drm, connector, &intel_tv_connector_funcs, 1993 DRM_MODE_CONNECTOR_SVIDEO); 1994 1995 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, &intel_tv_enc_funcs, 1996 DRM_MODE_ENCODER_TVDAC, "TV"); 1997 1998 intel_encoder->compute_config = intel_tv_compute_config; 1999 intel_encoder->get_config = intel_tv_get_config; 2000 intel_encoder->pre_enable = intel_tv_pre_enable; 2001 intel_encoder->enable = intel_enable_tv; 2002 intel_encoder->disable = intel_disable_tv; 2003 intel_encoder->get_hw_state = intel_tv_get_hw_state; 2004 intel_connector->get_hw_state = intel_connector_get_hw_state; 2005 2006 intel_connector_attach_encoder(intel_connector, intel_encoder); 2007 2008 intel_encoder->type = INTEL_OUTPUT_TVOUT; 2009 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 2010 intel_encoder->port = PORT_NONE; 2011 intel_encoder->pipe_mask = ~0; 2012 intel_encoder->cloneable = 0; 2013 intel_tv->type = DRM_MODE_CONNECTOR_Unknown; 2014 2015 drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs); 2016 2017 intel_tv_add_properties(connector); 2018 } 2019