1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "intel_display.h" 8 #include "intel_display_types.h" 9 #include "intel_dp_mst.h" 10 #include "intel_tc.h" 11 12 static const char *tc_port_mode_name(enum tc_port_mode mode) 13 { 14 static const char * const names[] = { 15 [TC_PORT_DISCONNECTED] = "disconnected", 16 [TC_PORT_TBT_ALT] = "tbt-alt", 17 [TC_PORT_DP_ALT] = "dp-alt", 18 [TC_PORT_LEGACY] = "legacy", 19 }; 20 21 if (WARN_ON(mode >= ARRAY_SIZE(names))) 22 mode = TC_PORT_DISCONNECTED; 23 24 return names[mode]; 25 } 26 27 static bool intel_tc_port_in_mode(struct intel_digital_port *dig_port, 28 enum tc_port_mode mode) 29 { 30 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 31 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 32 33 return intel_phy_is_tc(i915, phy) && dig_port->tc_mode == mode; 34 } 35 36 bool intel_tc_port_in_tbt_alt_mode(struct intel_digital_port *dig_port) 37 { 38 return intel_tc_port_in_mode(dig_port, TC_PORT_TBT_ALT); 39 } 40 41 bool intel_tc_port_in_dp_alt_mode(struct intel_digital_port *dig_port) 42 { 43 return intel_tc_port_in_mode(dig_port, TC_PORT_DP_ALT); 44 } 45 46 bool intel_tc_port_in_legacy_mode(struct intel_digital_port *dig_port) 47 { 48 return intel_tc_port_in_mode(dig_port, TC_PORT_LEGACY); 49 } 50 51 bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port) 52 { 53 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 54 55 return (DISPLAY_VER(i915) == 11 && dig_port->tc_legacy_port) || 56 IS_ALDERLAKE_P(i915); 57 } 58 59 static enum intel_display_power_domain 60 tc_cold_get_power_domain(struct intel_digital_port *dig_port, enum tc_port_mode mode) 61 { 62 if (mode == TC_PORT_TBT_ALT || !intel_tc_cold_requires_aux_pw(dig_port)) 63 return POWER_DOMAIN_TC_COLD_OFF; 64 65 return intel_legacy_aux_to_power_domain(dig_port->aux_ch); 66 } 67 68 static intel_wakeref_t 69 tc_cold_block_in_mode(struct intel_digital_port *dig_port, enum tc_port_mode mode, 70 enum intel_display_power_domain *domain) 71 { 72 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 73 74 *domain = tc_cold_get_power_domain(dig_port, mode); 75 76 return intel_display_power_get(i915, *domain); 77 } 78 79 static intel_wakeref_t 80 tc_cold_block(struct intel_digital_port *dig_port, enum intel_display_power_domain *domain) 81 { 82 return tc_cold_block_in_mode(dig_port, dig_port->tc_mode, domain); 83 } 84 85 static void 86 tc_cold_unblock(struct intel_digital_port *dig_port, enum intel_display_power_domain domain, 87 intel_wakeref_t wakeref) 88 { 89 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 90 91 /* 92 * wakeref == -1, means some error happened saving save_depot_stack but 93 * power should still be put down and 0 is a invalid save_depot_stack 94 * id so can be used to skip it for non TC legacy ports. 95 */ 96 if (wakeref == 0) 97 return; 98 99 intel_display_power_put(i915, domain, wakeref); 100 } 101 102 static void 103 assert_tc_cold_blocked(struct intel_digital_port *dig_port) 104 { 105 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 106 bool enabled; 107 108 enabled = intel_display_power_is_enabled(i915, 109 tc_cold_get_power_domain(dig_port, 110 dig_port->tc_mode)); 111 drm_WARN_ON(&i915->drm, !enabled); 112 } 113 114 u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port) 115 { 116 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 117 struct intel_uncore *uncore = &i915->uncore; 118 u32 lane_mask; 119 120 lane_mask = intel_uncore_read(uncore, 121 PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia)); 122 123 drm_WARN_ON(&i915->drm, lane_mask == 0xffffffff); 124 assert_tc_cold_blocked(dig_port); 125 126 lane_mask &= DP_LANE_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx); 127 return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx); 128 } 129 130 u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) 131 { 132 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 133 struct intel_uncore *uncore = &i915->uncore; 134 u32 pin_mask; 135 136 pin_mask = intel_uncore_read(uncore, 137 PORT_TX_DFLEXPA1(dig_port->tc_phy_fia)); 138 139 drm_WARN_ON(&i915->drm, pin_mask == 0xffffffff); 140 assert_tc_cold_blocked(dig_port); 141 142 return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx)) >> 143 DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx); 144 } 145 146 int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port) 147 { 148 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 149 intel_wakeref_t wakeref; 150 u32 lane_mask; 151 152 if (dig_port->tc_mode != TC_PORT_DP_ALT) 153 return 4; 154 155 assert_tc_cold_blocked(dig_port); 156 157 lane_mask = 0; 158 with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) 159 lane_mask = intel_tc_port_get_lane_mask(dig_port); 160 161 switch (lane_mask) { 162 default: 163 MISSING_CASE(lane_mask); 164 fallthrough; 165 case 0x1: 166 case 0x2: 167 case 0x4: 168 case 0x8: 169 return 1; 170 case 0x3: 171 case 0xc: 172 return 2; 173 case 0xf: 174 return 4; 175 } 176 } 177 178 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port, 179 int required_lanes) 180 { 181 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 182 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 183 struct intel_uncore *uncore = &i915->uncore; 184 u32 val; 185 186 drm_WARN_ON(&i915->drm, 187 lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY); 188 189 assert_tc_cold_blocked(dig_port); 190 191 val = intel_uncore_read(uncore, 192 PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia)); 193 val &= ~DFLEXDPMLE1_DPMLETC_MASK(dig_port->tc_phy_fia_idx); 194 195 switch (required_lanes) { 196 case 1: 197 val |= lane_reversal ? 198 DFLEXDPMLE1_DPMLETC_ML3(dig_port->tc_phy_fia_idx) : 199 DFLEXDPMLE1_DPMLETC_ML0(dig_port->tc_phy_fia_idx); 200 break; 201 case 2: 202 val |= lane_reversal ? 203 DFLEXDPMLE1_DPMLETC_ML3_2(dig_port->tc_phy_fia_idx) : 204 DFLEXDPMLE1_DPMLETC_ML1_0(dig_port->tc_phy_fia_idx); 205 break; 206 case 4: 207 val |= DFLEXDPMLE1_DPMLETC_ML3_0(dig_port->tc_phy_fia_idx); 208 break; 209 default: 210 MISSING_CASE(required_lanes); 211 } 212 213 intel_uncore_write(uncore, 214 PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val); 215 } 216 217 static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port, 218 u32 live_status_mask) 219 { 220 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 221 u32 valid_hpd_mask; 222 223 if (dig_port->tc_legacy_port) 224 valid_hpd_mask = BIT(TC_PORT_LEGACY); 225 else 226 valid_hpd_mask = BIT(TC_PORT_DP_ALT) | 227 BIT(TC_PORT_TBT_ALT); 228 229 if (!(live_status_mask & ~valid_hpd_mask)) 230 return; 231 232 /* If live status mismatches the VBT flag, trust the live status. */ 233 drm_dbg_kms(&i915->drm, 234 "Port %s: live status %08x mismatches the legacy port flag %08x, fixing flag\n", 235 dig_port->tc_port_name, live_status_mask, valid_hpd_mask); 236 237 dig_port->tc_legacy_port = !dig_port->tc_legacy_port; 238 } 239 240 static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port) 241 { 242 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 243 struct intel_uncore *uncore = &i915->uncore; 244 u32 isr_bit = i915->hotplug.pch_hpd[dig_port->base.hpd_pin]; 245 u32 mask = 0; 246 u32 val; 247 248 val = intel_uncore_read(uncore, 249 PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia)); 250 251 if (val == 0xffffffff) { 252 drm_dbg_kms(&i915->drm, 253 "Port %s: PHY in TCCOLD, nothing connected\n", 254 dig_port->tc_port_name); 255 return mask; 256 } 257 258 if (val & TC_LIVE_STATE_TBT(dig_port->tc_phy_fia_idx)) 259 mask |= BIT(TC_PORT_TBT_ALT); 260 if (val & TC_LIVE_STATE_TC(dig_port->tc_phy_fia_idx)) 261 mask |= BIT(TC_PORT_DP_ALT); 262 263 if (intel_uncore_read(uncore, SDEISR) & isr_bit) 264 mask |= BIT(TC_PORT_LEGACY); 265 266 /* The sink can be connected only in a single mode. */ 267 if (!drm_WARN_ON_ONCE(&i915->drm, hweight32(mask) > 1)) 268 tc_port_fixup_legacy_flag(dig_port, mask); 269 270 return mask; 271 } 272 273 static u32 adl_tc_port_live_status_mask(struct intel_digital_port *dig_port) 274 { 275 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 276 enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); 277 u32 isr_bit = i915->hotplug.pch_hpd[dig_port->base.hpd_pin]; 278 struct intel_uncore *uncore = &i915->uncore; 279 u32 val, mask = 0; 280 281 /* 282 * On ADL-P HW/FW will wake from TCCOLD to complete the read access of 283 * registers in IOM. Note that this doesn't apply to PHY and FIA 284 * registers. 285 */ 286 val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port)); 287 if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT) 288 mask |= BIT(TC_PORT_DP_ALT); 289 if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT) 290 mask |= BIT(TC_PORT_TBT_ALT); 291 292 if (intel_uncore_read(uncore, SDEISR) & isr_bit) 293 mask |= BIT(TC_PORT_LEGACY); 294 295 /* The sink can be connected only in a single mode. */ 296 if (!drm_WARN_ON(&i915->drm, hweight32(mask) > 1)) 297 tc_port_fixup_legacy_flag(dig_port, mask); 298 299 return mask; 300 } 301 302 static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port) 303 { 304 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 305 306 if (IS_ALDERLAKE_P(i915)) 307 return adl_tc_port_live_status_mask(dig_port); 308 309 return icl_tc_port_live_status_mask(dig_port); 310 } 311 312 /* 313 * Return the PHY status complete flag indicating that display can acquire the 314 * PHY ownership. The IOM firmware sets this flag when a DP-alt or legacy sink 315 * is connected and it's ready to switch the ownership to display. The flag 316 * will be left cleared when a TBT-alt sink is connected, where the PHY is 317 * owned by the TBT subsystem and so switching the ownership to display is not 318 * required. 319 */ 320 static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port) 321 { 322 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 323 struct intel_uncore *uncore = &i915->uncore; 324 u32 val; 325 326 val = intel_uncore_read(uncore, 327 PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia)); 328 if (val == 0xffffffff) { 329 drm_dbg_kms(&i915->drm, 330 "Port %s: PHY in TCCOLD, assuming not complete\n", 331 dig_port->tc_port_name); 332 return false; 333 } 334 335 return val & DP_PHY_MODE_STATUS_COMPLETED(dig_port->tc_phy_fia_idx); 336 } 337 338 /* 339 * Return the PHY status complete flag indicating that display can acquire the 340 * PHY ownership. The IOM firmware sets this flag when it's ready to switch 341 * the ownership to display, regardless of what sink is connected (TBT-alt, 342 * DP-alt, legacy or nothing). For TBT-alt sinks the PHY is owned by the TBT 343 * subsystem and so switching the ownership to display is not required. 344 */ 345 static bool adl_tc_phy_status_complete(struct intel_digital_port *dig_port) 346 { 347 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 348 enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); 349 struct intel_uncore *uncore = &i915->uncore; 350 u32 val; 351 352 val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port)); 353 if (val == 0xffffffff) { 354 drm_dbg_kms(&i915->drm, 355 "Port %s: PHY in TCCOLD, assuming not complete\n", 356 dig_port->tc_port_name); 357 return false; 358 } 359 360 return val & TCSS_DDI_STATUS_READY; 361 } 362 363 static bool tc_phy_status_complete(struct intel_digital_port *dig_port) 364 { 365 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 366 367 if (IS_ALDERLAKE_P(i915)) 368 return adl_tc_phy_status_complete(dig_port); 369 370 return icl_tc_phy_status_complete(dig_port); 371 } 372 373 static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port, 374 bool take) 375 { 376 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 377 struct intel_uncore *uncore = &i915->uncore; 378 u32 val; 379 380 val = intel_uncore_read(uncore, 381 PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia)); 382 if (val == 0xffffffff) { 383 drm_dbg_kms(&i915->drm, 384 "Port %s: PHY in TCCOLD, can't %s ownership\n", 385 dig_port->tc_port_name, take ? "take" : "release"); 386 387 return false; 388 } 389 390 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx); 391 if (take) 392 val |= DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx); 393 394 intel_uncore_write(uncore, 395 PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val); 396 397 return true; 398 } 399 400 static bool adl_tc_phy_take_ownership(struct intel_digital_port *dig_port, 401 bool take) 402 { 403 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 404 struct intel_uncore *uncore = &i915->uncore; 405 enum port port = dig_port->base.port; 406 u32 val; 407 408 val = intel_uncore_read(uncore, DDI_BUF_CTL(port)); 409 if (take) 410 val |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 411 else 412 val &= ~DDI_BUF_CTL_TC_PHY_OWNERSHIP; 413 intel_uncore_write(uncore, DDI_BUF_CTL(port), val); 414 415 return true; 416 } 417 418 static bool tc_phy_take_ownership(struct intel_digital_port *dig_port, bool take) 419 { 420 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 421 422 if (IS_ALDERLAKE_P(i915)) 423 return adl_tc_phy_take_ownership(dig_port, take); 424 425 return icl_tc_phy_take_ownership(dig_port, take); 426 } 427 428 static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port) 429 { 430 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 431 struct intel_uncore *uncore = &i915->uncore; 432 u32 val; 433 434 val = intel_uncore_read(uncore, 435 PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia)); 436 if (val == 0xffffffff) { 437 drm_dbg_kms(&i915->drm, 438 "Port %s: PHY in TCCOLD, assume safe mode\n", 439 dig_port->tc_port_name); 440 return true; 441 } 442 443 return val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx); 444 } 445 446 static bool adl_tc_phy_is_owned(struct intel_digital_port *dig_port) 447 { 448 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 449 struct intel_uncore *uncore = &i915->uncore; 450 enum port port = dig_port->base.port; 451 u32 val; 452 453 val = intel_uncore_read(uncore, DDI_BUF_CTL(port)); 454 return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP; 455 } 456 457 static bool tc_phy_is_owned(struct intel_digital_port *dig_port) 458 { 459 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 460 461 if (IS_ALDERLAKE_P(i915)) 462 return adl_tc_phy_is_owned(dig_port); 463 464 return icl_tc_phy_is_owned(dig_port); 465 } 466 467 /* 468 * This function implements the first part of the Connect Flow described by our 469 * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading 470 * lanes, EDID, etc) is done as needed in the typical places. 471 * 472 * Unlike the other ports, type-C ports are not available to use as soon as we 473 * get a hotplug. The type-C PHYs can be shared between multiple controllers: 474 * display, USB, etc. As a result, handshaking through FIA is required around 475 * connect and disconnect to cleanly transfer ownership with the controller and 476 * set the type-C power state. 477 */ 478 static void icl_tc_phy_connect(struct intel_digital_port *dig_port, 479 int required_lanes) 480 { 481 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 482 u32 live_status_mask; 483 int max_lanes; 484 485 if (!tc_phy_status_complete(dig_port)) { 486 drm_dbg_kms(&i915->drm, "Port %s: PHY not ready\n", 487 dig_port->tc_port_name); 488 goto out_set_tbt_alt_mode; 489 } 490 491 live_status_mask = tc_port_live_status_mask(dig_port); 492 if (!(live_status_mask & (BIT(TC_PORT_DP_ALT) | BIT(TC_PORT_LEGACY)))) { 493 drm_dbg_kms(&i915->drm, "Port %s: PHY ownership not required (live status %02x)\n", 494 dig_port->tc_port_name, live_status_mask); 495 goto out_set_tbt_alt_mode; 496 } 497 498 if (!tc_phy_take_ownership(dig_port, true) && 499 !drm_WARN_ON(&i915->drm, dig_port->tc_legacy_port)) 500 goto out_set_tbt_alt_mode; 501 502 max_lanes = intel_tc_port_fia_max_lane_count(dig_port); 503 if (dig_port->tc_legacy_port) { 504 drm_WARN_ON(&i915->drm, max_lanes != 4); 505 dig_port->tc_mode = TC_PORT_LEGACY; 506 507 return; 508 } 509 510 /* 511 * Now we have to re-check the live state, in case the port recently 512 * became disconnected. Not necessary for legacy mode. 513 */ 514 if (!(tc_port_live_status_mask(dig_port) & BIT(TC_PORT_DP_ALT))) { 515 drm_dbg_kms(&i915->drm, "Port %s: PHY sudden disconnect\n", 516 dig_port->tc_port_name); 517 goto out_release_phy; 518 } 519 520 if (max_lanes < required_lanes) { 521 drm_dbg_kms(&i915->drm, 522 "Port %s: PHY max lanes %d < required lanes %d\n", 523 dig_port->tc_port_name, 524 max_lanes, required_lanes); 525 goto out_release_phy; 526 } 527 528 dig_port->tc_mode = TC_PORT_DP_ALT; 529 530 return; 531 532 out_release_phy: 533 tc_phy_take_ownership(dig_port, false); 534 out_set_tbt_alt_mode: 535 dig_port->tc_mode = TC_PORT_TBT_ALT; 536 } 537 538 /* 539 * See the comment at the connect function. This implements the Disconnect 540 * Flow. 541 */ 542 static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port) 543 { 544 switch (dig_port->tc_mode) { 545 case TC_PORT_LEGACY: 546 case TC_PORT_DP_ALT: 547 tc_phy_take_ownership(dig_port, false); 548 fallthrough; 549 case TC_PORT_TBT_ALT: 550 dig_port->tc_mode = TC_PORT_DISCONNECTED; 551 fallthrough; 552 case TC_PORT_DISCONNECTED: 553 break; 554 default: 555 MISSING_CASE(dig_port->tc_mode); 556 } 557 } 558 559 static bool icl_tc_phy_is_connected(struct intel_digital_port *dig_port) 560 { 561 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 562 563 if (!tc_phy_status_complete(dig_port)) { 564 drm_dbg_kms(&i915->drm, "Port %s: PHY status not complete\n", 565 dig_port->tc_port_name); 566 return dig_port->tc_mode == TC_PORT_TBT_ALT; 567 } 568 569 /* On ADL-P the PHY complete flag is set in TBT mode as well. */ 570 if (IS_ALDERLAKE_P(i915) && dig_port->tc_mode == TC_PORT_TBT_ALT) 571 return true; 572 573 if (!tc_phy_is_owned(dig_port)) { 574 drm_dbg_kms(&i915->drm, "Port %s: PHY not owned\n", 575 dig_port->tc_port_name); 576 577 return false; 578 } 579 580 return dig_port->tc_mode == TC_PORT_DP_ALT || 581 dig_port->tc_mode == TC_PORT_LEGACY; 582 } 583 584 static enum tc_port_mode 585 intel_tc_port_get_current_mode(struct intel_digital_port *dig_port) 586 { 587 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 588 u32 live_status_mask = tc_port_live_status_mask(dig_port); 589 enum tc_port_mode mode; 590 591 if (!tc_phy_is_owned(dig_port) || 592 drm_WARN_ON(&i915->drm, !tc_phy_status_complete(dig_port))) 593 return TC_PORT_TBT_ALT; 594 595 mode = dig_port->tc_legacy_port ? TC_PORT_LEGACY : TC_PORT_DP_ALT; 596 if (live_status_mask) { 597 enum tc_port_mode live_mode = fls(live_status_mask) - 1; 598 599 if (!drm_WARN_ON(&i915->drm, live_mode == TC_PORT_TBT_ALT)) 600 mode = live_mode; 601 } 602 603 return mode; 604 } 605 606 static enum tc_port_mode 607 intel_tc_port_get_target_mode(struct intel_digital_port *dig_port) 608 { 609 u32 live_status_mask = tc_port_live_status_mask(dig_port); 610 611 if (live_status_mask) 612 return fls(live_status_mask) - 1; 613 614 return TC_PORT_TBT_ALT; 615 } 616 617 static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port, 618 int required_lanes, bool force_disconnect) 619 { 620 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 621 enum tc_port_mode old_tc_mode = dig_port->tc_mode; 622 623 intel_display_power_flush_work(i915); 624 if (!intel_tc_cold_requires_aux_pw(dig_port)) { 625 enum intel_display_power_domain aux_domain; 626 bool aux_powered; 627 628 aux_domain = intel_aux_power_domain(dig_port); 629 aux_powered = intel_display_power_is_enabled(i915, aux_domain); 630 drm_WARN_ON(&i915->drm, aux_powered); 631 } 632 633 icl_tc_phy_disconnect(dig_port); 634 if (!force_disconnect) 635 icl_tc_phy_connect(dig_port, required_lanes); 636 637 drm_dbg_kms(&i915->drm, "Port %s: TC port mode reset (%s -> %s)\n", 638 dig_port->tc_port_name, 639 tc_port_mode_name(old_tc_mode), 640 tc_port_mode_name(dig_port->tc_mode)); 641 } 642 643 static bool intel_tc_port_needs_reset(struct intel_digital_port *dig_port) 644 { 645 return intel_tc_port_get_target_mode(dig_port) != dig_port->tc_mode; 646 } 647 648 static void intel_tc_port_update_mode(struct intel_digital_port *dig_port, 649 int required_lanes, bool force_disconnect) 650 { 651 enum intel_display_power_domain domain; 652 intel_wakeref_t wref; 653 bool needs_reset = force_disconnect; 654 655 if (!needs_reset) { 656 /* Get power domain required to check the hotplug live status. */ 657 wref = tc_cold_block(dig_port, &domain); 658 needs_reset = intel_tc_port_needs_reset(dig_port); 659 tc_cold_unblock(dig_port, domain, wref); 660 } 661 662 if (!needs_reset) 663 return; 664 665 /* Get power domain required for resetting the mode. */ 666 wref = tc_cold_block_in_mode(dig_port, TC_PORT_DISCONNECTED, &domain); 667 668 intel_tc_port_reset_mode(dig_port, required_lanes, force_disconnect); 669 670 /* Get power domain matching the new mode after reset. */ 671 tc_cold_unblock(dig_port, dig_port->tc_lock_power_domain, 672 fetch_and_zero(&dig_port->tc_lock_wakeref)); 673 if (dig_port->tc_mode != TC_PORT_DISCONNECTED) 674 dig_port->tc_lock_wakeref = tc_cold_block(dig_port, 675 &dig_port->tc_lock_power_domain); 676 677 tc_cold_unblock(dig_port, domain, wref); 678 } 679 680 static void 681 intel_tc_port_link_init_refcount(struct intel_digital_port *dig_port, 682 int refcount) 683 { 684 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 685 686 drm_WARN_ON(&i915->drm, dig_port->tc_link_refcount); 687 dig_port->tc_link_refcount = refcount; 688 } 689 690 void intel_tc_port_sanitize(struct intel_digital_port *dig_port) 691 { 692 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 693 struct intel_encoder *encoder = &dig_port->base; 694 intel_wakeref_t tc_cold_wref; 695 enum intel_display_power_domain domain; 696 int active_links = 0; 697 698 mutex_lock(&dig_port->tc_lock); 699 700 if (dig_port->dp.is_mst) 701 active_links = intel_dp_mst_encoder_active_links(dig_port); 702 else if (encoder->base.crtc) 703 active_links = to_intel_crtc(encoder->base.crtc)->active; 704 705 drm_WARN_ON(&i915->drm, dig_port->tc_mode != TC_PORT_DISCONNECTED); 706 drm_WARN_ON(&i915->drm, dig_port->tc_lock_wakeref); 707 708 tc_cold_wref = tc_cold_block(dig_port, &domain); 709 710 dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port); 711 if (active_links) { 712 if (!icl_tc_phy_is_connected(dig_port)) 713 drm_dbg_kms(&i915->drm, 714 "Port %s: PHY disconnected with %d active link(s)\n", 715 dig_port->tc_port_name, active_links); 716 intel_tc_port_link_init_refcount(dig_port, active_links); 717 718 dig_port->tc_lock_wakeref = tc_cold_block(dig_port, 719 &dig_port->tc_lock_power_domain); 720 } else { 721 /* 722 * TBT-alt is the default mode in any case the PHY ownership is not 723 * held (regardless of the sink's connected live state), so 724 * we'll just switch to disconnected mode from it here without 725 * a note. 726 */ 727 if (dig_port->tc_mode != TC_PORT_TBT_ALT) 728 drm_dbg_kms(&i915->drm, 729 "Port %s: PHY left in %s mode on disabled port, disconnecting it\n", 730 dig_port->tc_port_name, 731 tc_port_mode_name(dig_port->tc_mode)); 732 icl_tc_phy_disconnect(dig_port); 733 } 734 735 tc_cold_unblock(dig_port, domain, tc_cold_wref); 736 737 drm_dbg_kms(&i915->drm, "Port %s: sanitize mode (%s)\n", 738 dig_port->tc_port_name, 739 tc_port_mode_name(dig_port->tc_mode)); 740 741 mutex_unlock(&dig_port->tc_lock); 742 } 743 744 /* 745 * The type-C ports are different because even when they are connected, they may 746 * not be available/usable by the graphics driver: see the comment on 747 * icl_tc_phy_connect(). So in our driver instead of adding the additional 748 * concept of "usable" and make everything check for "connected and usable" we 749 * define a port as "connected" when it is not only connected, but also when it 750 * is usable by the rest of the driver. That maintains the old assumption that 751 * connected ports are usable, and avoids exposing to the users objects they 752 * can't really use. 753 */ 754 bool intel_tc_port_connected(struct intel_encoder *encoder) 755 { 756 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 757 bool is_connected; 758 759 intel_tc_port_lock(dig_port); 760 761 is_connected = tc_port_live_status_mask(dig_port) & 762 BIT(dig_port->tc_mode); 763 764 intel_tc_port_unlock(dig_port); 765 766 return is_connected; 767 } 768 769 static void __intel_tc_port_lock(struct intel_digital_port *dig_port, 770 int required_lanes) 771 { 772 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 773 774 mutex_lock(&dig_port->tc_lock); 775 776 cancel_delayed_work(&dig_port->tc_disconnect_phy_work); 777 778 if (!dig_port->tc_link_refcount) 779 intel_tc_port_update_mode(dig_port, required_lanes, 780 false); 781 782 drm_WARN_ON(&i915->drm, dig_port->tc_mode == TC_PORT_DISCONNECTED); 783 drm_WARN_ON(&i915->drm, dig_port->tc_mode != TC_PORT_TBT_ALT && 784 !tc_phy_is_owned(dig_port)); 785 } 786 787 void intel_tc_port_lock(struct intel_digital_port *dig_port) 788 { 789 __intel_tc_port_lock(dig_port, 1); 790 } 791 792 /** 793 * intel_tc_port_disconnect_phy_work: disconnect TypeC PHY from display port 794 * @dig_port: digital port 795 * 796 * Disconnect the given digital port from its TypeC PHY (handing back the 797 * control of the PHY to the TypeC subsystem). This will happen in a delayed 798 * manner after each aux transactions and modeset disables. 799 */ 800 static void intel_tc_port_disconnect_phy_work(struct work_struct *work) 801 { 802 struct intel_digital_port *dig_port = 803 container_of(work, struct intel_digital_port, tc_disconnect_phy_work.work); 804 805 mutex_lock(&dig_port->tc_lock); 806 807 if (!dig_port->tc_link_refcount) 808 intel_tc_port_update_mode(dig_port, 1, true); 809 810 mutex_unlock(&dig_port->tc_lock); 811 } 812 813 /** 814 * intel_tc_port_flush_work: flush the work disconnecting the PHY 815 * @dig_port: digital port 816 * 817 * Flush the delayed work disconnecting an idle PHY. 818 */ 819 void intel_tc_port_flush_work(struct intel_digital_port *dig_port) 820 { 821 flush_delayed_work(&dig_port->tc_disconnect_phy_work); 822 } 823 824 void intel_tc_port_unlock(struct intel_digital_port *dig_port) 825 { 826 if (!dig_port->tc_link_refcount && dig_port->tc_mode != TC_PORT_DISCONNECTED) 827 queue_delayed_work(system_unbound_wq, &dig_port->tc_disconnect_phy_work, 828 msecs_to_jiffies(1000)); 829 830 mutex_unlock(&dig_port->tc_lock); 831 } 832 833 bool intel_tc_port_ref_held(struct intel_digital_port *dig_port) 834 { 835 return mutex_is_locked(&dig_port->tc_lock) || 836 dig_port->tc_link_refcount; 837 } 838 839 void intel_tc_port_get_link(struct intel_digital_port *dig_port, 840 int required_lanes) 841 { 842 __intel_tc_port_lock(dig_port, required_lanes); 843 dig_port->tc_link_refcount++; 844 intel_tc_port_unlock(dig_port); 845 } 846 847 void intel_tc_port_put_link(struct intel_digital_port *dig_port) 848 { 849 intel_tc_port_lock(dig_port); 850 --dig_port->tc_link_refcount; 851 intel_tc_port_unlock(dig_port); 852 853 /* 854 * Disconnecting the PHY after the PHY's PLL gets disabled may 855 * hang the system on ADL-P, so disconnect the PHY here synchronously. 856 * TODO: remove this once the root cause of the ordering requirement 857 * is found/fixed. 858 */ 859 intel_tc_port_flush_work(dig_port); 860 } 861 862 static bool 863 tc_has_modular_fia(struct drm_i915_private *i915, struct intel_digital_port *dig_port) 864 { 865 enum intel_display_power_domain domain; 866 intel_wakeref_t wakeref; 867 u32 val; 868 869 if (!INTEL_INFO(i915)->display.has_modular_fia) 870 return false; 871 872 mutex_lock(&dig_port->tc_lock); 873 wakeref = tc_cold_block(dig_port, &domain); 874 val = intel_uncore_read(&i915->uncore, PORT_TX_DFLEXDPSP(FIA1)); 875 tc_cold_unblock(dig_port, domain, wakeref); 876 mutex_unlock(&dig_port->tc_lock); 877 878 drm_WARN_ON(&i915->drm, val == 0xffffffff); 879 880 return val & MODULAR_FIA_MASK; 881 } 882 883 static void 884 tc_port_load_fia_params(struct drm_i915_private *i915, struct intel_digital_port *dig_port) 885 { 886 enum port port = dig_port->base.port; 887 enum tc_port tc_port = intel_port_to_tc(i915, port); 888 889 /* 890 * Each Modular FIA instance houses 2 TC ports. In SOC that has more 891 * than two TC ports, there are multiple instances of Modular FIA. 892 */ 893 if (tc_has_modular_fia(i915, dig_port)) { 894 dig_port->tc_phy_fia = tc_port / 2; 895 dig_port->tc_phy_fia_idx = tc_port % 2; 896 } else { 897 dig_port->tc_phy_fia = FIA1; 898 dig_port->tc_phy_fia_idx = tc_port; 899 } 900 } 901 902 void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy) 903 { 904 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 905 enum port port = dig_port->base.port; 906 enum tc_port tc_port = intel_port_to_tc(i915, port); 907 908 if (drm_WARN_ON(&i915->drm, tc_port == TC_PORT_NONE)) 909 return; 910 911 snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name), 912 "%c/TC#%d", port_name(port), tc_port + 1); 913 914 mutex_init(&dig_port->tc_lock); 915 INIT_DELAYED_WORK(&dig_port->tc_disconnect_phy_work, intel_tc_port_disconnect_phy_work); 916 dig_port->tc_legacy_port = is_legacy; 917 dig_port->tc_mode = TC_PORT_DISCONNECTED; 918 dig_port->tc_link_refcount = 0; 919 tc_port_load_fia_params(i915, dig_port); 920 } 921