1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "intel_display.h" 8 #include "intel_dp_mst.h" 9 #include "intel_tc.h" 10 11 static const char *tc_port_mode_name(enum tc_port_mode mode) 12 { 13 static const char * const names[] = { 14 [TC_PORT_TBT_ALT] = "tbt-alt", 15 [TC_PORT_DP_ALT] = "dp-alt", 16 [TC_PORT_LEGACY] = "legacy", 17 }; 18 19 if (WARN_ON(mode >= ARRAY_SIZE(names))) 20 mode = TC_PORT_TBT_ALT; 21 22 return names[mode]; 23 } 24 25 static bool has_modular_fia(struct drm_i915_private *i915) 26 { 27 if (!INTEL_INFO(i915)->display.has_modular_fia) 28 return false; 29 30 return intel_uncore_read(&i915->uncore, 31 PORT_TX_DFLEXDPSP(FIA1)) & MODULAR_FIA_MASK; 32 } 33 34 static enum phy_fia tc_port_to_fia(struct drm_i915_private *i915, 35 enum tc_port tc_port) 36 { 37 if (!has_modular_fia(i915)) 38 return FIA1; 39 40 /* 41 * Each Modular FIA instance houses 2 TC ports. In SOC that has more 42 * than two TC ports, there are multiple instances of Modular FIA. 43 */ 44 return tc_port / 2; 45 } 46 47 u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port) 48 { 49 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 50 enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); 51 struct intel_uncore *uncore = &i915->uncore; 52 u32 lane_mask; 53 54 lane_mask = intel_uncore_read(uncore, 55 PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia)); 56 57 WARN_ON(lane_mask == 0xffffffff); 58 59 return (lane_mask & DP_LANE_ASSIGNMENT_MASK(tc_port)) >> 60 DP_LANE_ASSIGNMENT_SHIFT(tc_port); 61 } 62 63 int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port) 64 { 65 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 66 intel_wakeref_t wakeref; 67 u32 lane_mask; 68 69 if (dig_port->tc_mode != TC_PORT_DP_ALT) 70 return 4; 71 72 lane_mask = 0; 73 with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) 74 lane_mask = intel_tc_port_get_lane_mask(dig_port); 75 76 switch (lane_mask) { 77 default: 78 MISSING_CASE(lane_mask); 79 /* fall-through */ 80 case 0x1: 81 case 0x2: 82 case 0x4: 83 case 0x8: 84 return 1; 85 case 0x3: 86 case 0xc: 87 return 2; 88 case 0xf: 89 return 4; 90 } 91 } 92 93 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port, 94 int required_lanes) 95 { 96 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 97 enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); 98 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 99 struct intel_uncore *uncore = &i915->uncore; 100 u32 val; 101 102 WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY); 103 104 val = intel_uncore_read(uncore, 105 PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia)); 106 val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port); 107 108 switch (required_lanes) { 109 case 1: 110 val |= lane_reversal ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) : 111 DFLEXDPMLE1_DPMLETC_ML0(tc_port); 112 break; 113 case 2: 114 val |= lane_reversal ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) : 115 DFLEXDPMLE1_DPMLETC_ML1_0(tc_port); 116 break; 117 case 4: 118 val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port); 119 break; 120 default: 121 MISSING_CASE(required_lanes); 122 } 123 124 intel_uncore_write(uncore, 125 PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val); 126 } 127 128 static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port, 129 u32 live_status_mask) 130 { 131 u32 valid_hpd_mask; 132 133 if (dig_port->tc_legacy_port) 134 valid_hpd_mask = BIT(TC_PORT_LEGACY); 135 else 136 valid_hpd_mask = BIT(TC_PORT_DP_ALT) | 137 BIT(TC_PORT_TBT_ALT); 138 139 if (!(live_status_mask & ~valid_hpd_mask)) 140 return; 141 142 /* If live status mismatches the VBT flag, trust the live status. */ 143 DRM_ERROR("Port %s: live status %08x mismatches the legacy port flag, fix flag\n", 144 dig_port->tc_port_name, live_status_mask); 145 146 dig_port->tc_legacy_port = !dig_port->tc_legacy_port; 147 } 148 149 static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port) 150 { 151 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 152 enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); 153 struct intel_uncore *uncore = &i915->uncore; 154 u32 mask = 0; 155 u32 val; 156 157 val = intel_uncore_read(uncore, 158 PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia)); 159 160 if (val == 0xffffffff) { 161 DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, nothing connected\n", 162 dig_port->tc_port_name); 163 return mask; 164 } 165 166 if (val & TC_LIVE_STATE_TBT(tc_port)) 167 mask |= BIT(TC_PORT_TBT_ALT); 168 if (val & TC_LIVE_STATE_TC(tc_port)) 169 mask |= BIT(TC_PORT_DP_ALT); 170 171 if (intel_uncore_read(uncore, SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port)) 172 mask |= BIT(TC_PORT_LEGACY); 173 174 /* The sink can be connected only in a single mode. */ 175 if (!WARN_ON(hweight32(mask) > 1)) 176 tc_port_fixup_legacy_flag(dig_port, mask); 177 178 return mask; 179 } 180 181 static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port) 182 { 183 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 184 enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); 185 struct intel_uncore *uncore = &i915->uncore; 186 u32 val; 187 188 val = intel_uncore_read(uncore, 189 PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia)); 190 if (val == 0xffffffff) { 191 DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assuming not complete\n", 192 dig_port->tc_port_name); 193 return false; 194 } 195 196 return val & DP_PHY_MODE_STATUS_COMPLETED(tc_port); 197 } 198 199 static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port, 200 bool enable) 201 { 202 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 203 enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); 204 struct intel_uncore *uncore = &i915->uncore; 205 u32 val; 206 207 val = intel_uncore_read(uncore, 208 PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia)); 209 if (val == 0xffffffff) { 210 DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, can't set safe-mode to %s\n", 211 dig_port->tc_port_name, 212 enableddisabled(enable)); 213 214 return false; 215 } 216 217 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port); 218 if (!enable) 219 val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port); 220 221 intel_uncore_write(uncore, 222 PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val); 223 224 if (enable && wait_for(!icl_tc_phy_status_complete(dig_port), 10)) 225 DRM_DEBUG_KMS("Port %s: PHY complete clear timed out\n", 226 dig_port->tc_port_name); 227 228 return true; 229 } 230 231 static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port) 232 { 233 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 234 enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); 235 struct intel_uncore *uncore = &i915->uncore; 236 u32 val; 237 238 val = intel_uncore_read(uncore, 239 PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia)); 240 if (val == 0xffffffff) { 241 DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assume safe mode\n", 242 dig_port->tc_port_name); 243 return true; 244 } 245 246 return !(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)); 247 } 248 249 /* 250 * This function implements the first part of the Connect Flow described by our 251 * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading 252 * lanes, EDID, etc) is done as needed in the typical places. 253 * 254 * Unlike the other ports, type-C ports are not available to use as soon as we 255 * get a hotplug. The type-C PHYs can be shared between multiple controllers: 256 * display, USB, etc. As a result, handshaking through FIA is required around 257 * connect and disconnect to cleanly transfer ownership with the controller and 258 * set the type-C power state. 259 */ 260 static void icl_tc_phy_connect(struct intel_digital_port *dig_port, 261 int required_lanes) 262 { 263 int max_lanes; 264 265 if (!icl_tc_phy_status_complete(dig_port)) { 266 DRM_DEBUG_KMS("Port %s: PHY not ready\n", 267 dig_port->tc_port_name); 268 goto out_set_tbt_alt_mode; 269 } 270 271 if (!icl_tc_phy_set_safe_mode(dig_port, false) && 272 !WARN_ON(dig_port->tc_legacy_port)) 273 goto out_set_tbt_alt_mode; 274 275 max_lanes = intel_tc_port_fia_max_lane_count(dig_port); 276 if (dig_port->tc_legacy_port) { 277 WARN_ON(max_lanes != 4); 278 dig_port->tc_mode = TC_PORT_LEGACY; 279 280 return; 281 } 282 283 /* 284 * Now we have to re-check the live state, in case the port recently 285 * became disconnected. Not necessary for legacy mode. 286 */ 287 if (!(tc_port_live_status_mask(dig_port) & BIT(TC_PORT_DP_ALT))) { 288 DRM_DEBUG_KMS("Port %s: PHY sudden disconnect\n", 289 dig_port->tc_port_name); 290 goto out_set_safe_mode; 291 } 292 293 if (max_lanes < required_lanes) { 294 DRM_DEBUG_KMS("Port %s: PHY max lanes %d < required lanes %d\n", 295 dig_port->tc_port_name, 296 max_lanes, required_lanes); 297 goto out_set_safe_mode; 298 } 299 300 dig_port->tc_mode = TC_PORT_DP_ALT; 301 302 return; 303 304 out_set_safe_mode: 305 icl_tc_phy_set_safe_mode(dig_port, true); 306 out_set_tbt_alt_mode: 307 dig_port->tc_mode = TC_PORT_TBT_ALT; 308 } 309 310 /* 311 * See the comment at the connect function. This implements the Disconnect 312 * Flow. 313 */ 314 static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port) 315 { 316 switch (dig_port->tc_mode) { 317 case TC_PORT_LEGACY: 318 /* Nothing to do, we never disconnect from legacy mode */ 319 break; 320 case TC_PORT_DP_ALT: 321 icl_tc_phy_set_safe_mode(dig_port, true); 322 dig_port->tc_mode = TC_PORT_TBT_ALT; 323 break; 324 case TC_PORT_TBT_ALT: 325 /* Nothing to do, we stay in TBT-alt mode */ 326 break; 327 default: 328 MISSING_CASE(dig_port->tc_mode); 329 } 330 } 331 332 static bool icl_tc_phy_is_connected(struct intel_digital_port *dig_port) 333 { 334 if (!icl_tc_phy_status_complete(dig_port)) { 335 DRM_DEBUG_KMS("Port %s: PHY status not complete\n", 336 dig_port->tc_port_name); 337 return dig_port->tc_mode == TC_PORT_TBT_ALT; 338 } 339 340 if (icl_tc_phy_is_in_safe_mode(dig_port)) { 341 DRM_DEBUG_KMS("Port %s: PHY still in safe mode\n", 342 dig_port->tc_port_name); 343 344 return false; 345 } 346 347 return dig_port->tc_mode == TC_PORT_DP_ALT || 348 dig_port->tc_mode == TC_PORT_LEGACY; 349 } 350 351 static enum tc_port_mode 352 intel_tc_port_get_current_mode(struct intel_digital_port *dig_port) 353 { 354 u32 live_status_mask = tc_port_live_status_mask(dig_port); 355 bool in_safe_mode = icl_tc_phy_is_in_safe_mode(dig_port); 356 enum tc_port_mode mode; 357 358 if (in_safe_mode || WARN_ON(!icl_tc_phy_status_complete(dig_port))) 359 return TC_PORT_TBT_ALT; 360 361 mode = dig_port->tc_legacy_port ? TC_PORT_LEGACY : TC_PORT_DP_ALT; 362 if (live_status_mask) { 363 enum tc_port_mode live_mode = fls(live_status_mask) - 1; 364 365 if (!WARN_ON(live_mode == TC_PORT_TBT_ALT)) 366 mode = live_mode; 367 } 368 369 return mode; 370 } 371 372 static enum tc_port_mode 373 intel_tc_port_get_target_mode(struct intel_digital_port *dig_port) 374 { 375 u32 live_status_mask = tc_port_live_status_mask(dig_port); 376 377 if (live_status_mask) 378 return fls(live_status_mask) - 1; 379 380 return icl_tc_phy_status_complete(dig_port) && 381 dig_port->tc_legacy_port ? TC_PORT_LEGACY : 382 TC_PORT_TBT_ALT; 383 } 384 385 static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port, 386 int required_lanes) 387 { 388 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 389 enum tc_port_mode old_tc_mode = dig_port->tc_mode; 390 391 intel_display_power_flush_work(i915); 392 WARN_ON(intel_display_power_is_enabled(i915, 393 intel_aux_power_domain(dig_port))); 394 395 icl_tc_phy_disconnect(dig_port); 396 icl_tc_phy_connect(dig_port, required_lanes); 397 398 DRM_DEBUG_KMS("Port %s: TC port mode reset (%s -> %s)\n", 399 dig_port->tc_port_name, 400 tc_port_mode_name(old_tc_mode), 401 tc_port_mode_name(dig_port->tc_mode)); 402 } 403 404 static void 405 intel_tc_port_link_init_refcount(struct intel_digital_port *dig_port, 406 int refcount) 407 { 408 WARN_ON(dig_port->tc_link_refcount); 409 dig_port->tc_link_refcount = refcount; 410 } 411 412 void intel_tc_port_sanitize(struct intel_digital_port *dig_port) 413 { 414 struct intel_encoder *encoder = &dig_port->base; 415 int active_links = 0; 416 417 mutex_lock(&dig_port->tc_lock); 418 419 dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port); 420 if (dig_port->dp.is_mst) 421 active_links = intel_dp_mst_encoder_active_links(dig_port); 422 else if (encoder->base.crtc) 423 active_links = to_intel_crtc(encoder->base.crtc)->active; 424 425 if (active_links) { 426 if (!icl_tc_phy_is_connected(dig_port)) 427 DRM_DEBUG_KMS("Port %s: PHY disconnected with %d active link(s)\n", 428 dig_port->tc_port_name, active_links); 429 intel_tc_port_link_init_refcount(dig_port, active_links); 430 431 goto out; 432 } 433 434 if (dig_port->tc_legacy_port) 435 icl_tc_phy_connect(dig_port, 1); 436 437 out: 438 DRM_DEBUG_KMS("Port %s: sanitize mode (%s)\n", 439 dig_port->tc_port_name, 440 tc_port_mode_name(dig_port->tc_mode)); 441 442 mutex_unlock(&dig_port->tc_lock); 443 } 444 445 static bool intel_tc_port_needs_reset(struct intel_digital_port *dig_port) 446 { 447 return intel_tc_port_get_target_mode(dig_port) != dig_port->tc_mode; 448 } 449 450 /* 451 * The type-C ports are different because even when they are connected, they may 452 * not be available/usable by the graphics driver: see the comment on 453 * icl_tc_phy_connect(). So in our driver instead of adding the additional 454 * concept of "usable" and make everything check for "connected and usable" we 455 * define a port as "connected" when it is not only connected, but also when it 456 * is usable by the rest of the driver. That maintains the old assumption that 457 * connected ports are usable, and avoids exposing to the users objects they 458 * can't really use. 459 */ 460 bool intel_tc_port_connected(struct intel_digital_port *dig_port) 461 { 462 bool is_connected; 463 464 intel_tc_port_lock(dig_port); 465 is_connected = tc_port_live_status_mask(dig_port) & 466 BIT(dig_port->tc_mode); 467 intel_tc_port_unlock(dig_port); 468 469 return is_connected; 470 } 471 472 static void __intel_tc_port_lock(struct intel_digital_port *dig_port, 473 int required_lanes) 474 { 475 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 476 intel_wakeref_t wakeref; 477 478 wakeref = intel_display_power_get(i915, POWER_DOMAIN_DISPLAY_CORE); 479 480 mutex_lock(&dig_port->tc_lock); 481 482 if (!dig_port->tc_link_refcount && 483 intel_tc_port_needs_reset(dig_port)) 484 intel_tc_port_reset_mode(dig_port, required_lanes); 485 486 WARN_ON(dig_port->tc_lock_wakeref); 487 dig_port->tc_lock_wakeref = wakeref; 488 } 489 490 void intel_tc_port_lock(struct intel_digital_port *dig_port) 491 { 492 __intel_tc_port_lock(dig_port, 1); 493 } 494 495 void intel_tc_port_unlock(struct intel_digital_port *dig_port) 496 { 497 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 498 intel_wakeref_t wakeref = fetch_and_zero(&dig_port->tc_lock_wakeref); 499 500 mutex_unlock(&dig_port->tc_lock); 501 502 intel_display_power_put_async(i915, POWER_DOMAIN_DISPLAY_CORE, 503 wakeref); 504 } 505 506 void intel_tc_port_get_link(struct intel_digital_port *dig_port, 507 int required_lanes) 508 { 509 __intel_tc_port_lock(dig_port, required_lanes); 510 dig_port->tc_link_refcount++; 511 intel_tc_port_unlock(dig_port); 512 } 513 514 void intel_tc_port_put_link(struct intel_digital_port *dig_port) 515 { 516 mutex_lock(&dig_port->tc_lock); 517 dig_port->tc_link_refcount--; 518 mutex_unlock(&dig_port->tc_lock); 519 } 520 521 void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy) 522 { 523 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 524 enum port port = dig_port->base.port; 525 enum tc_port tc_port = intel_port_to_tc(i915, port); 526 527 if (WARN_ON(tc_port == PORT_TC_NONE)) 528 return; 529 530 snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name), 531 "%c/TC#%d", port_name(port), tc_port + 1); 532 533 mutex_init(&dig_port->tc_lock); 534 dig_port->tc_legacy_port = is_legacy; 535 dig_port->tc_link_refcount = 0; 536 dig_port->tc_phy_fia = tc_port_to_fia(i915, tc_port); 537 } 538