1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2019 Intel Corporation
4  */
5 
6 #include "i915_drv.h"
7 #include "intel_display.h"
8 #include "intel_display_types.h"
9 #include "intel_dp_mst.h"
10 #include "intel_tc.h"
11 
12 static const char *tc_port_mode_name(enum tc_port_mode mode)
13 {
14 	static const char * const names[] = {
15 		[TC_PORT_TBT_ALT] = "tbt-alt",
16 		[TC_PORT_DP_ALT] = "dp-alt",
17 		[TC_PORT_LEGACY] = "legacy",
18 	};
19 
20 	if (WARN_ON(mode >= ARRAY_SIZE(names)))
21 		mode = TC_PORT_TBT_ALT;
22 
23 	return names[mode];
24 }
25 
26 static enum intel_display_power_domain
27 tc_cold_get_power_domain(struct intel_digital_port *dig_port)
28 {
29 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
30 
31 	if (INTEL_GEN(i915) == 11)
32 		return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
33 	else
34 		return POWER_DOMAIN_TC_COLD_OFF;
35 }
36 
37 static intel_wakeref_t
38 tc_cold_block(struct intel_digital_port *dig_port)
39 {
40 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
41 	enum intel_display_power_domain domain;
42 
43 	if (INTEL_GEN(i915) == 11 && !dig_port->tc_legacy_port)
44 		return 0;
45 
46 	domain = tc_cold_get_power_domain(dig_port);
47 	return intel_display_power_get(i915, domain);
48 }
49 
50 static void
51 tc_cold_unblock(struct intel_digital_port *dig_port, intel_wakeref_t wakeref)
52 {
53 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
54 	enum intel_display_power_domain domain;
55 
56 	/*
57 	 * wakeref == -1, means some error happened saving save_depot_stack but
58 	 * power should still be put down and 0 is a invalid save_depot_stack
59 	 * id so can be used to skip it for non TC legacy ports.
60 	 */
61 	if (wakeref == 0)
62 		return;
63 
64 	domain = tc_cold_get_power_domain(dig_port);
65 	intel_display_power_put_async(i915, domain, wakeref);
66 }
67 
68 static void
69 assert_tc_cold_blocked(struct intel_digital_port *dig_port)
70 {
71 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
72 	bool enabled;
73 
74 	if (INTEL_GEN(i915) == 11 && !dig_port->tc_legacy_port)
75 		return;
76 
77 	enabled = intel_display_power_is_enabled(i915,
78 						 tc_cold_get_power_domain(dig_port));
79 	drm_WARN_ON(&i915->drm, !enabled);
80 }
81 
82 u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
83 {
84 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
85 	struct intel_uncore *uncore = &i915->uncore;
86 	u32 lane_mask;
87 
88 	lane_mask = intel_uncore_read(uncore,
89 				      PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
90 
91 	drm_WARN_ON(&i915->drm, lane_mask == 0xffffffff);
92 	assert_tc_cold_blocked(dig_port);
93 
94 	lane_mask &= DP_LANE_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx);
95 	return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
96 }
97 
98 u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
99 {
100 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
101 	struct intel_uncore *uncore = &i915->uncore;
102 	u32 pin_mask;
103 
104 	pin_mask = intel_uncore_read(uncore,
105 				     PORT_TX_DFLEXPA1(dig_port->tc_phy_fia));
106 
107 	drm_WARN_ON(&i915->drm, pin_mask == 0xffffffff);
108 	assert_tc_cold_blocked(dig_port);
109 
110 	return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx)) >>
111 	       DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
112 }
113 
114 int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
115 {
116 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
117 	intel_wakeref_t wakeref;
118 	u32 lane_mask;
119 
120 	if (dig_port->tc_mode != TC_PORT_DP_ALT)
121 		return 4;
122 
123 	assert_tc_cold_blocked(dig_port);
124 
125 	lane_mask = 0;
126 	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
127 		lane_mask = intel_tc_port_get_lane_mask(dig_port);
128 
129 	switch (lane_mask) {
130 	default:
131 		MISSING_CASE(lane_mask);
132 		fallthrough;
133 	case 0x1:
134 	case 0x2:
135 	case 0x4:
136 	case 0x8:
137 		return 1;
138 	case 0x3:
139 	case 0xc:
140 		return 2;
141 	case 0xf:
142 		return 4;
143 	}
144 }
145 
146 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
147 				      int required_lanes)
148 {
149 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
150 	bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
151 	struct intel_uncore *uncore = &i915->uncore;
152 	u32 val;
153 
154 	drm_WARN_ON(&i915->drm,
155 		    lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
156 
157 	assert_tc_cold_blocked(dig_port);
158 
159 	val = intel_uncore_read(uncore,
160 				PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
161 	val &= ~DFLEXDPMLE1_DPMLETC_MASK(dig_port->tc_phy_fia_idx);
162 
163 	switch (required_lanes) {
164 	case 1:
165 		val |= lane_reversal ?
166 			DFLEXDPMLE1_DPMLETC_ML3(dig_port->tc_phy_fia_idx) :
167 			DFLEXDPMLE1_DPMLETC_ML0(dig_port->tc_phy_fia_idx);
168 		break;
169 	case 2:
170 		val |= lane_reversal ?
171 			DFLEXDPMLE1_DPMLETC_ML3_2(dig_port->tc_phy_fia_idx) :
172 			DFLEXDPMLE1_DPMLETC_ML1_0(dig_port->tc_phy_fia_idx);
173 		break;
174 	case 4:
175 		val |= DFLEXDPMLE1_DPMLETC_ML3_0(dig_port->tc_phy_fia_idx);
176 		break;
177 	default:
178 		MISSING_CASE(required_lanes);
179 	}
180 
181 	intel_uncore_write(uncore,
182 			   PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
183 }
184 
185 static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
186 				      u32 live_status_mask)
187 {
188 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
189 	u32 valid_hpd_mask;
190 
191 	if (dig_port->tc_legacy_port)
192 		valid_hpd_mask = BIT(TC_PORT_LEGACY);
193 	else
194 		valid_hpd_mask = BIT(TC_PORT_DP_ALT) |
195 				 BIT(TC_PORT_TBT_ALT);
196 
197 	if (!(live_status_mask & ~valid_hpd_mask))
198 		return;
199 
200 	/* If live status mismatches the VBT flag, trust the live status. */
201 	drm_dbg_kms(&i915->drm,
202 		    "Port %s: live status %08x mismatches the legacy port flag %08x, fixing flag\n",
203 		    dig_port->tc_port_name, live_status_mask, valid_hpd_mask);
204 
205 	dig_port->tc_legacy_port = !dig_port->tc_legacy_port;
206 }
207 
208 static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
209 {
210 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
211 	struct intel_uncore *uncore = &i915->uncore;
212 	u32 isr_bit = i915->hotplug.pch_hpd[dig_port->base.hpd_pin];
213 	u32 mask = 0;
214 	u32 val;
215 
216 	val = intel_uncore_read(uncore,
217 				PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
218 
219 	if (val == 0xffffffff) {
220 		drm_dbg_kms(&i915->drm,
221 			    "Port %s: PHY in TCCOLD, nothing connected\n",
222 			    dig_port->tc_port_name);
223 		return mask;
224 	}
225 
226 	if (val & TC_LIVE_STATE_TBT(dig_port->tc_phy_fia_idx))
227 		mask |= BIT(TC_PORT_TBT_ALT);
228 	if (val & TC_LIVE_STATE_TC(dig_port->tc_phy_fia_idx))
229 		mask |= BIT(TC_PORT_DP_ALT);
230 
231 	if (intel_uncore_read(uncore, SDEISR) & isr_bit)
232 		mask |= BIT(TC_PORT_LEGACY);
233 
234 	/* The sink can be connected only in a single mode. */
235 	if (!drm_WARN_ON_ONCE(&i915->drm, hweight32(mask) > 1))
236 		tc_port_fixup_legacy_flag(dig_port, mask);
237 
238 	return mask;
239 }
240 
241 static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
242 {
243 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
244 	struct intel_uncore *uncore = &i915->uncore;
245 	u32 val;
246 
247 	val = intel_uncore_read(uncore,
248 				PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia));
249 	if (val == 0xffffffff) {
250 		drm_dbg_kms(&i915->drm,
251 			    "Port %s: PHY in TCCOLD, assuming not complete\n",
252 			    dig_port->tc_port_name);
253 		return false;
254 	}
255 
256 	return val & DP_PHY_MODE_STATUS_COMPLETED(dig_port->tc_phy_fia_idx);
257 }
258 
259 static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
260 				     bool enable)
261 {
262 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
263 	struct intel_uncore *uncore = &i915->uncore;
264 	u32 val;
265 
266 	val = intel_uncore_read(uncore,
267 				PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
268 	if (val == 0xffffffff) {
269 		drm_dbg_kms(&i915->drm,
270 			    "Port %s: PHY in TCCOLD, can't set safe-mode to %s\n",
271 			    dig_port->tc_port_name, enableddisabled(enable));
272 
273 		return false;
274 	}
275 
276 	val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
277 	if (!enable)
278 		val |= DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
279 
280 	intel_uncore_write(uncore,
281 			   PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
282 
283 	if (enable && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
284 		drm_dbg_kms(&i915->drm,
285 			    "Port %s: PHY complete clear timed out\n",
286 			    dig_port->tc_port_name);
287 
288 	return true;
289 }
290 
291 static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port)
292 {
293 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
294 	struct intel_uncore *uncore = &i915->uncore;
295 	u32 val;
296 
297 	val = intel_uncore_read(uncore,
298 				PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
299 	if (val == 0xffffffff) {
300 		drm_dbg_kms(&i915->drm,
301 			    "Port %s: PHY in TCCOLD, assume safe mode\n",
302 			    dig_port->tc_port_name);
303 		return true;
304 	}
305 
306 	return !(val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx));
307 }
308 
309 /*
310  * This function implements the first part of the Connect Flow described by our
311  * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
312  * lanes, EDID, etc) is done as needed in the typical places.
313  *
314  * Unlike the other ports, type-C ports are not available to use as soon as we
315  * get a hotplug. The type-C PHYs can be shared between multiple controllers:
316  * display, USB, etc. As a result, handshaking through FIA is required around
317  * connect and disconnect to cleanly transfer ownership with the controller and
318  * set the type-C power state.
319  */
320 static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
321 			       int required_lanes)
322 {
323 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
324 	int max_lanes;
325 
326 	if (!icl_tc_phy_status_complete(dig_port)) {
327 		drm_dbg_kms(&i915->drm, "Port %s: PHY not ready\n",
328 			    dig_port->tc_port_name);
329 		goto out_set_tbt_alt_mode;
330 	}
331 
332 	if (!icl_tc_phy_set_safe_mode(dig_port, false) &&
333 	    !drm_WARN_ON(&i915->drm, dig_port->tc_legacy_port))
334 		goto out_set_tbt_alt_mode;
335 
336 	max_lanes = intel_tc_port_fia_max_lane_count(dig_port);
337 	if (dig_port->tc_legacy_port) {
338 		drm_WARN_ON(&i915->drm, max_lanes != 4);
339 		dig_port->tc_mode = TC_PORT_LEGACY;
340 
341 		return;
342 	}
343 
344 	/*
345 	 * Now we have to re-check the live state, in case the port recently
346 	 * became disconnected. Not necessary for legacy mode.
347 	 */
348 	if (!(tc_port_live_status_mask(dig_port) & BIT(TC_PORT_DP_ALT))) {
349 		drm_dbg_kms(&i915->drm, "Port %s: PHY sudden disconnect\n",
350 			    dig_port->tc_port_name);
351 		goto out_set_safe_mode;
352 	}
353 
354 	if (max_lanes < required_lanes) {
355 		drm_dbg_kms(&i915->drm,
356 			    "Port %s: PHY max lanes %d < required lanes %d\n",
357 			    dig_port->tc_port_name,
358 			    max_lanes, required_lanes);
359 		goto out_set_safe_mode;
360 	}
361 
362 	dig_port->tc_mode = TC_PORT_DP_ALT;
363 
364 	return;
365 
366 out_set_safe_mode:
367 	icl_tc_phy_set_safe_mode(dig_port, true);
368 out_set_tbt_alt_mode:
369 	dig_port->tc_mode = TC_PORT_TBT_ALT;
370 }
371 
372 /*
373  * See the comment at the connect function. This implements the Disconnect
374  * Flow.
375  */
376 static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port)
377 {
378 	switch (dig_port->tc_mode) {
379 	case TC_PORT_LEGACY:
380 		/* Nothing to do, we never disconnect from legacy mode */
381 		break;
382 	case TC_PORT_DP_ALT:
383 		icl_tc_phy_set_safe_mode(dig_port, true);
384 		dig_port->tc_mode = TC_PORT_TBT_ALT;
385 		break;
386 	case TC_PORT_TBT_ALT:
387 		/* Nothing to do, we stay in TBT-alt mode */
388 		break;
389 	default:
390 		MISSING_CASE(dig_port->tc_mode);
391 	}
392 }
393 
394 static bool icl_tc_phy_is_connected(struct intel_digital_port *dig_port)
395 {
396 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
397 
398 	if (!icl_tc_phy_status_complete(dig_port)) {
399 		drm_dbg_kms(&i915->drm, "Port %s: PHY status not complete\n",
400 			    dig_port->tc_port_name);
401 		return dig_port->tc_mode == TC_PORT_TBT_ALT;
402 	}
403 
404 	if (icl_tc_phy_is_in_safe_mode(dig_port)) {
405 		drm_dbg_kms(&i915->drm, "Port %s: PHY still in safe mode\n",
406 			    dig_port->tc_port_name);
407 
408 		return false;
409 	}
410 
411 	return dig_port->tc_mode == TC_PORT_DP_ALT ||
412 	       dig_port->tc_mode == TC_PORT_LEGACY;
413 }
414 
415 static enum tc_port_mode
416 intel_tc_port_get_current_mode(struct intel_digital_port *dig_port)
417 {
418 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
419 	u32 live_status_mask = tc_port_live_status_mask(dig_port);
420 	bool in_safe_mode = icl_tc_phy_is_in_safe_mode(dig_port);
421 	enum tc_port_mode mode;
422 
423 	if (in_safe_mode ||
424 	    drm_WARN_ON(&i915->drm, !icl_tc_phy_status_complete(dig_port)))
425 		return TC_PORT_TBT_ALT;
426 
427 	mode = dig_port->tc_legacy_port ? TC_PORT_LEGACY : TC_PORT_DP_ALT;
428 	if (live_status_mask) {
429 		enum tc_port_mode live_mode = fls(live_status_mask) - 1;
430 
431 		if (!drm_WARN_ON(&i915->drm, live_mode == TC_PORT_TBT_ALT))
432 			mode = live_mode;
433 	}
434 
435 	return mode;
436 }
437 
438 static enum tc_port_mode
439 intel_tc_port_get_target_mode(struct intel_digital_port *dig_port)
440 {
441 	u32 live_status_mask = tc_port_live_status_mask(dig_port);
442 
443 	if (live_status_mask)
444 		return fls(live_status_mask) - 1;
445 
446 	return icl_tc_phy_status_complete(dig_port) &&
447 	       dig_port->tc_legacy_port ? TC_PORT_LEGACY :
448 					  TC_PORT_TBT_ALT;
449 }
450 
451 static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port,
452 				     int required_lanes)
453 {
454 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
455 	enum tc_port_mode old_tc_mode = dig_port->tc_mode;
456 
457 	intel_display_power_flush_work(i915);
458 	if (INTEL_GEN(i915) != 11 || !dig_port->tc_legacy_port) {
459 		enum intel_display_power_domain aux_domain;
460 		bool aux_powered;
461 
462 		aux_domain = intel_aux_power_domain(dig_port);
463 		aux_powered = intel_display_power_is_enabled(i915, aux_domain);
464 		drm_WARN_ON(&i915->drm, aux_powered);
465 	}
466 
467 	icl_tc_phy_disconnect(dig_port);
468 	icl_tc_phy_connect(dig_port, required_lanes);
469 
470 	drm_dbg_kms(&i915->drm, "Port %s: TC port mode reset (%s -> %s)\n",
471 		    dig_port->tc_port_name,
472 		    tc_port_mode_name(old_tc_mode),
473 		    tc_port_mode_name(dig_port->tc_mode));
474 }
475 
476 static void
477 intel_tc_port_link_init_refcount(struct intel_digital_port *dig_port,
478 				 int refcount)
479 {
480 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
481 
482 	drm_WARN_ON(&i915->drm, dig_port->tc_link_refcount);
483 	dig_port->tc_link_refcount = refcount;
484 }
485 
486 void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
487 {
488 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
489 	struct intel_encoder *encoder = &dig_port->base;
490 	intel_wakeref_t tc_cold_wref;
491 	int active_links = 0;
492 
493 	mutex_lock(&dig_port->tc_lock);
494 	tc_cold_wref = tc_cold_block(dig_port);
495 
496 	dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port);
497 	if (dig_port->dp.is_mst)
498 		active_links = intel_dp_mst_encoder_active_links(dig_port);
499 	else if (encoder->base.crtc)
500 		active_links = to_intel_crtc(encoder->base.crtc)->active;
501 
502 	if (active_links) {
503 		if (!icl_tc_phy_is_connected(dig_port))
504 			drm_dbg_kms(&i915->drm,
505 				    "Port %s: PHY disconnected with %d active link(s)\n",
506 				    dig_port->tc_port_name, active_links);
507 		intel_tc_port_link_init_refcount(dig_port, active_links);
508 
509 		goto out;
510 	}
511 
512 	if (dig_port->tc_legacy_port)
513 		icl_tc_phy_connect(dig_port, 1);
514 
515 out:
516 	drm_dbg_kms(&i915->drm, "Port %s: sanitize mode (%s)\n",
517 		    dig_port->tc_port_name,
518 		    tc_port_mode_name(dig_port->tc_mode));
519 
520 	tc_cold_unblock(dig_port, tc_cold_wref);
521 	mutex_unlock(&dig_port->tc_lock);
522 }
523 
524 static bool intel_tc_port_needs_reset(struct intel_digital_port *dig_port)
525 {
526 	return intel_tc_port_get_target_mode(dig_port) != dig_port->tc_mode;
527 }
528 
529 /*
530  * The type-C ports are different because even when they are connected, they may
531  * not be available/usable by the graphics driver: see the comment on
532  * icl_tc_phy_connect(). So in our driver instead of adding the additional
533  * concept of "usable" and make everything check for "connected and usable" we
534  * define a port as "connected" when it is not only connected, but also when it
535  * is usable by the rest of the driver. That maintains the old assumption that
536  * connected ports are usable, and avoids exposing to the users objects they
537  * can't really use.
538  */
539 bool intel_tc_port_connected(struct intel_encoder *encoder)
540 {
541 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
542 	bool is_connected;
543 	intel_wakeref_t tc_cold_wref;
544 
545 	intel_tc_port_lock(dig_port);
546 	tc_cold_wref = tc_cold_block(dig_port);
547 
548 	is_connected = tc_port_live_status_mask(dig_port) &
549 		       BIT(dig_port->tc_mode);
550 
551 	tc_cold_unblock(dig_port, tc_cold_wref);
552 	intel_tc_port_unlock(dig_port);
553 
554 	return is_connected;
555 }
556 
557 static void __intel_tc_port_lock(struct intel_digital_port *dig_port,
558 				 int required_lanes)
559 {
560 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
561 	intel_wakeref_t wakeref;
562 
563 	wakeref = intel_display_power_get(i915, POWER_DOMAIN_DISPLAY_CORE);
564 
565 	mutex_lock(&dig_port->tc_lock);
566 
567 	if (!dig_port->tc_link_refcount) {
568 		intel_wakeref_t tc_cold_wref;
569 
570 		tc_cold_wref = tc_cold_block(dig_port);
571 
572 		if (intel_tc_port_needs_reset(dig_port))
573 			intel_tc_port_reset_mode(dig_port, required_lanes);
574 
575 		tc_cold_unblock(dig_port, tc_cold_wref);
576 	}
577 
578 	drm_WARN_ON(&i915->drm, dig_port->tc_lock_wakeref);
579 	dig_port->tc_lock_wakeref = wakeref;
580 }
581 
582 void intel_tc_port_lock(struct intel_digital_port *dig_port)
583 {
584 	__intel_tc_port_lock(dig_port, 1);
585 }
586 
587 void intel_tc_port_unlock(struct intel_digital_port *dig_port)
588 {
589 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
590 	intel_wakeref_t wakeref = fetch_and_zero(&dig_port->tc_lock_wakeref);
591 
592 	mutex_unlock(&dig_port->tc_lock);
593 
594 	intel_display_power_put_async(i915, POWER_DOMAIN_DISPLAY_CORE,
595 				      wakeref);
596 }
597 
598 bool intel_tc_port_ref_held(struct intel_digital_port *dig_port)
599 {
600 	return mutex_is_locked(&dig_port->tc_lock) ||
601 	       dig_port->tc_link_refcount;
602 }
603 
604 void intel_tc_port_get_link(struct intel_digital_port *dig_port,
605 			    int required_lanes)
606 {
607 	__intel_tc_port_lock(dig_port, required_lanes);
608 	dig_port->tc_link_refcount++;
609 	intel_tc_port_unlock(dig_port);
610 }
611 
612 void intel_tc_port_put_link(struct intel_digital_port *dig_port)
613 {
614 	mutex_lock(&dig_port->tc_lock);
615 	dig_port->tc_link_refcount--;
616 	mutex_unlock(&dig_port->tc_lock);
617 }
618 
619 static bool
620 tc_has_modular_fia(struct drm_i915_private *i915, struct intel_digital_port *dig_port)
621 {
622 	intel_wakeref_t wakeref;
623 	u32 val;
624 
625 	if (!INTEL_INFO(i915)->display.has_modular_fia)
626 		return false;
627 
628 	wakeref = tc_cold_block(dig_port);
629 	val = intel_uncore_read(&i915->uncore, PORT_TX_DFLEXDPSP(FIA1));
630 	tc_cold_unblock(dig_port, wakeref);
631 
632 	drm_WARN_ON(&i915->drm, val == 0xffffffff);
633 
634 	return val & MODULAR_FIA_MASK;
635 }
636 
637 static void
638 tc_port_load_fia_params(struct drm_i915_private *i915, struct intel_digital_port *dig_port)
639 {
640 	enum port port = dig_port->base.port;
641 	enum tc_port tc_port = intel_port_to_tc(i915, port);
642 
643 	/*
644 	 * Each Modular FIA instance houses 2 TC ports. In SOC that has more
645 	 * than two TC ports, there are multiple instances of Modular FIA.
646 	 */
647 	if (tc_has_modular_fia(i915, dig_port)) {
648 		dig_port->tc_phy_fia = tc_port / 2;
649 		dig_port->tc_phy_fia_idx = tc_port % 2;
650 	} else {
651 		dig_port->tc_phy_fia = FIA1;
652 		dig_port->tc_phy_fia_idx = tc_port;
653 	}
654 }
655 
656 void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
657 {
658 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
659 	enum port port = dig_port->base.port;
660 	enum tc_port tc_port = intel_port_to_tc(i915, port);
661 
662 	if (drm_WARN_ON(&i915->drm, tc_port == TC_PORT_NONE))
663 		return;
664 
665 	snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name),
666 		 "%c/TC#%d", port_name(port), tc_port + 1);
667 
668 	mutex_init(&dig_port->tc_lock);
669 	dig_port->tc_legacy_port = is_legacy;
670 	dig_port->tc_link_refcount = 0;
671 	tc_port_load_fia_params(i915, dig_port);
672 }
673