1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "intel_display.h" 8 #include "intel_display_types.h" 9 #include "intel_dp_mst.h" 10 #include "intel_tc.h" 11 12 static const char *tc_port_mode_name(enum tc_port_mode mode) 13 { 14 static const char * const names[] = { 15 [TC_PORT_DISCONNECTED] = "disconnected", 16 [TC_PORT_TBT_ALT] = "tbt-alt", 17 [TC_PORT_DP_ALT] = "dp-alt", 18 [TC_PORT_LEGACY] = "legacy", 19 }; 20 21 if (WARN_ON(mode >= ARRAY_SIZE(names))) 22 mode = TC_PORT_DISCONNECTED; 23 24 return names[mode]; 25 } 26 27 static bool intel_tc_port_in_mode(struct intel_digital_port *dig_port, 28 enum tc_port_mode mode) 29 { 30 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 31 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 32 33 return intel_phy_is_tc(i915, phy) && dig_port->tc_mode == mode; 34 } 35 36 bool intel_tc_port_in_tbt_alt_mode(struct intel_digital_port *dig_port) 37 { 38 return intel_tc_port_in_mode(dig_port, TC_PORT_TBT_ALT); 39 } 40 41 bool intel_tc_port_in_dp_alt_mode(struct intel_digital_port *dig_port) 42 { 43 return intel_tc_port_in_mode(dig_port, TC_PORT_DP_ALT); 44 } 45 46 bool intel_tc_port_in_legacy_mode(struct intel_digital_port *dig_port) 47 { 48 return intel_tc_port_in_mode(dig_port, TC_PORT_LEGACY); 49 } 50 51 bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port) 52 { 53 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 54 55 return (DISPLAY_VER(i915) == 11 && dig_port->tc_legacy_port) || 56 IS_ALDERLAKE_P(i915); 57 } 58 59 static enum intel_display_power_domain 60 tc_cold_get_power_domain(struct intel_digital_port *dig_port, enum tc_port_mode mode) 61 { 62 if (mode == TC_PORT_TBT_ALT || !intel_tc_cold_requires_aux_pw(dig_port)) 63 return POWER_DOMAIN_TC_COLD_OFF; 64 65 return intel_legacy_aux_to_power_domain(dig_port->aux_ch); 66 } 67 68 static intel_wakeref_t 69 tc_cold_block_in_mode(struct intel_digital_port *dig_port, enum tc_port_mode mode, 70 enum intel_display_power_domain *domain) 71 { 72 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 73 74 *domain = tc_cold_get_power_domain(dig_port, mode); 75 76 return intel_display_power_get(i915, *domain); 77 } 78 79 static intel_wakeref_t 80 tc_cold_block(struct intel_digital_port *dig_port, enum intel_display_power_domain *domain) 81 { 82 return tc_cold_block_in_mode(dig_port, dig_port->tc_mode, domain); 83 } 84 85 static void 86 tc_cold_unblock(struct intel_digital_port *dig_port, enum intel_display_power_domain domain, 87 intel_wakeref_t wakeref) 88 { 89 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 90 91 /* 92 * wakeref == -1, means some error happened saving save_depot_stack but 93 * power should still be put down and 0 is a invalid save_depot_stack 94 * id so can be used to skip it for non TC legacy ports. 95 */ 96 if (wakeref == 0) 97 return; 98 99 intel_display_power_put(i915, domain, wakeref); 100 } 101 102 static void 103 assert_tc_cold_blocked(struct intel_digital_port *dig_port) 104 { 105 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 106 bool enabled; 107 108 enabled = intel_display_power_is_enabled(i915, 109 tc_cold_get_power_domain(dig_port, 110 dig_port->tc_mode)); 111 drm_WARN_ON(&i915->drm, !enabled); 112 } 113 114 u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port) 115 { 116 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 117 struct intel_uncore *uncore = &i915->uncore; 118 u32 lane_mask; 119 120 lane_mask = intel_uncore_read(uncore, 121 PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia)); 122 123 drm_WARN_ON(&i915->drm, lane_mask == 0xffffffff); 124 assert_tc_cold_blocked(dig_port); 125 126 lane_mask &= DP_LANE_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx); 127 return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx); 128 } 129 130 u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) 131 { 132 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 133 struct intel_uncore *uncore = &i915->uncore; 134 u32 pin_mask; 135 136 pin_mask = intel_uncore_read(uncore, 137 PORT_TX_DFLEXPA1(dig_port->tc_phy_fia)); 138 139 drm_WARN_ON(&i915->drm, pin_mask == 0xffffffff); 140 assert_tc_cold_blocked(dig_port); 141 142 return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx)) >> 143 DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx); 144 } 145 146 int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port) 147 { 148 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 149 intel_wakeref_t wakeref; 150 u32 lane_mask; 151 152 if (dig_port->tc_mode != TC_PORT_DP_ALT) 153 return 4; 154 155 assert_tc_cold_blocked(dig_port); 156 157 lane_mask = 0; 158 with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) 159 lane_mask = intel_tc_port_get_lane_mask(dig_port); 160 161 switch (lane_mask) { 162 default: 163 MISSING_CASE(lane_mask); 164 fallthrough; 165 case 0x1: 166 case 0x2: 167 case 0x4: 168 case 0x8: 169 return 1; 170 case 0x3: 171 case 0xc: 172 return 2; 173 case 0xf: 174 return 4; 175 } 176 } 177 178 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port, 179 int required_lanes) 180 { 181 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 182 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 183 struct intel_uncore *uncore = &i915->uncore; 184 u32 val; 185 186 drm_WARN_ON(&i915->drm, 187 lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY); 188 189 assert_tc_cold_blocked(dig_port); 190 191 val = intel_uncore_read(uncore, 192 PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia)); 193 val &= ~DFLEXDPMLE1_DPMLETC_MASK(dig_port->tc_phy_fia_idx); 194 195 switch (required_lanes) { 196 case 1: 197 val |= lane_reversal ? 198 DFLEXDPMLE1_DPMLETC_ML3(dig_port->tc_phy_fia_idx) : 199 DFLEXDPMLE1_DPMLETC_ML0(dig_port->tc_phy_fia_idx); 200 break; 201 case 2: 202 val |= lane_reversal ? 203 DFLEXDPMLE1_DPMLETC_ML3_2(dig_port->tc_phy_fia_idx) : 204 DFLEXDPMLE1_DPMLETC_ML1_0(dig_port->tc_phy_fia_idx); 205 break; 206 case 4: 207 val |= DFLEXDPMLE1_DPMLETC_ML3_0(dig_port->tc_phy_fia_idx); 208 break; 209 default: 210 MISSING_CASE(required_lanes); 211 } 212 213 intel_uncore_write(uncore, 214 PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val); 215 } 216 217 static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port, 218 u32 live_status_mask) 219 { 220 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 221 u32 valid_hpd_mask; 222 223 if (dig_port->tc_legacy_port) 224 valid_hpd_mask = BIT(TC_PORT_LEGACY); 225 else 226 valid_hpd_mask = BIT(TC_PORT_DP_ALT) | 227 BIT(TC_PORT_TBT_ALT); 228 229 if (!(live_status_mask & ~valid_hpd_mask)) 230 return; 231 232 /* If live status mismatches the VBT flag, trust the live status. */ 233 drm_dbg_kms(&i915->drm, 234 "Port %s: live status %08x mismatches the legacy port flag %08x, fixing flag\n", 235 dig_port->tc_port_name, live_status_mask, valid_hpd_mask); 236 237 dig_port->tc_legacy_port = !dig_port->tc_legacy_port; 238 } 239 240 static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port) 241 { 242 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 243 struct intel_uncore *uncore = &i915->uncore; 244 u32 isr_bit = i915->hotplug.pch_hpd[dig_port->base.hpd_pin]; 245 u32 mask = 0; 246 u32 val; 247 248 val = intel_uncore_read(uncore, 249 PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia)); 250 251 if (val == 0xffffffff) { 252 drm_dbg_kms(&i915->drm, 253 "Port %s: PHY in TCCOLD, nothing connected\n", 254 dig_port->tc_port_name); 255 return mask; 256 } 257 258 if (val & TC_LIVE_STATE_TBT(dig_port->tc_phy_fia_idx)) 259 mask |= BIT(TC_PORT_TBT_ALT); 260 if (val & TC_LIVE_STATE_TC(dig_port->tc_phy_fia_idx)) 261 mask |= BIT(TC_PORT_DP_ALT); 262 263 if (intel_uncore_read(uncore, SDEISR) & isr_bit) 264 mask |= BIT(TC_PORT_LEGACY); 265 266 /* The sink can be connected only in a single mode. */ 267 if (!drm_WARN_ON_ONCE(&i915->drm, hweight32(mask) > 1)) 268 tc_port_fixup_legacy_flag(dig_port, mask); 269 270 return mask; 271 } 272 273 static u32 adl_tc_port_live_status_mask(struct intel_digital_port *dig_port) 274 { 275 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 276 enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); 277 u32 isr_bit = i915->hotplug.pch_hpd[dig_port->base.hpd_pin]; 278 struct intel_uncore *uncore = &i915->uncore; 279 u32 val, mask = 0; 280 281 /* 282 * On ADL-P HW/FW will wake from TCCOLD to complete the read access of 283 * registers in IOM. Note that this doesn't apply to PHY and FIA 284 * registers. 285 */ 286 val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port)); 287 if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT) 288 mask |= BIT(TC_PORT_DP_ALT); 289 if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT) 290 mask |= BIT(TC_PORT_TBT_ALT); 291 292 if (intel_uncore_read(uncore, SDEISR) & isr_bit) 293 mask |= BIT(TC_PORT_LEGACY); 294 295 /* The sink can be connected only in a single mode. */ 296 if (!drm_WARN_ON(&i915->drm, hweight32(mask) > 1)) 297 tc_port_fixup_legacy_flag(dig_port, mask); 298 299 return mask; 300 } 301 302 static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port) 303 { 304 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 305 306 if (IS_ALDERLAKE_P(i915)) 307 return adl_tc_port_live_status_mask(dig_port); 308 309 return icl_tc_port_live_status_mask(dig_port); 310 } 311 312 /* 313 * Return the PHY status complete flag indicating that display can acquire the 314 * PHY ownership. The IOM firmware sets this flag when a DP-alt or legacy sink 315 * is connected and it's ready to switch the ownership to display. The flag 316 * will be left cleared when a TBT-alt sink is connected, where the PHY is 317 * owned by the TBT subsystem and so switching the ownership to display is not 318 * required. 319 */ 320 static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port) 321 { 322 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 323 struct intel_uncore *uncore = &i915->uncore; 324 u32 val; 325 326 val = intel_uncore_read(uncore, 327 PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia)); 328 if (val == 0xffffffff) { 329 drm_dbg_kms(&i915->drm, 330 "Port %s: PHY in TCCOLD, assuming not complete\n", 331 dig_port->tc_port_name); 332 return false; 333 } 334 335 return val & DP_PHY_MODE_STATUS_COMPLETED(dig_port->tc_phy_fia_idx); 336 } 337 338 /* 339 * Return the PHY status complete flag indicating that display can acquire the 340 * PHY ownership. The IOM firmware sets this flag when it's ready to switch 341 * the ownership to display, regardless of what sink is connected (TBT-alt, 342 * DP-alt, legacy or nothing). For TBT-alt sinks the PHY is owned by the TBT 343 * subsystem and so switching the ownership to display is not required. 344 */ 345 static bool adl_tc_phy_status_complete(struct intel_digital_port *dig_port) 346 { 347 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 348 struct intel_uncore *uncore = &i915->uncore; 349 u32 val; 350 351 val = intel_uncore_read(uncore, TCSS_DDI_STATUS(dig_port->tc_phy_fia_idx)); 352 if (val == 0xffffffff) { 353 drm_dbg_kms(&i915->drm, 354 "Port %s: PHY in TCCOLD, assuming not complete\n", 355 dig_port->tc_port_name); 356 return false; 357 } 358 359 return val & TCSS_DDI_STATUS_READY; 360 } 361 362 static bool tc_phy_status_complete(struct intel_digital_port *dig_port) 363 { 364 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 365 366 if (IS_ALDERLAKE_P(i915)) 367 return adl_tc_phy_status_complete(dig_port); 368 369 return icl_tc_phy_status_complete(dig_port); 370 } 371 372 static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port, 373 bool take) 374 { 375 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 376 struct intel_uncore *uncore = &i915->uncore; 377 u32 val; 378 379 val = intel_uncore_read(uncore, 380 PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia)); 381 if (val == 0xffffffff) { 382 drm_dbg_kms(&i915->drm, 383 "Port %s: PHY in TCCOLD, can't %s ownership\n", 384 dig_port->tc_port_name, take ? "take" : "release"); 385 386 return false; 387 } 388 389 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx); 390 if (take) 391 val |= DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx); 392 393 intel_uncore_write(uncore, 394 PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val); 395 396 return true; 397 } 398 399 static bool adl_tc_phy_take_ownership(struct intel_digital_port *dig_port, 400 bool take) 401 { 402 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 403 struct intel_uncore *uncore = &i915->uncore; 404 enum port port = dig_port->base.port; 405 u32 val; 406 407 val = intel_uncore_read(uncore, DDI_BUF_CTL(port)); 408 if (take) 409 val |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 410 else 411 val &= ~DDI_BUF_CTL_TC_PHY_OWNERSHIP; 412 intel_uncore_write(uncore, DDI_BUF_CTL(port), val); 413 414 return true; 415 } 416 417 static bool tc_phy_take_ownership(struct intel_digital_port *dig_port, bool take) 418 { 419 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 420 421 if (IS_ALDERLAKE_P(i915)) 422 return adl_tc_phy_take_ownership(dig_port, take); 423 424 return icl_tc_phy_take_ownership(dig_port, take); 425 } 426 427 static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port) 428 { 429 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 430 struct intel_uncore *uncore = &i915->uncore; 431 u32 val; 432 433 val = intel_uncore_read(uncore, 434 PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia)); 435 if (val == 0xffffffff) { 436 drm_dbg_kms(&i915->drm, 437 "Port %s: PHY in TCCOLD, assume safe mode\n", 438 dig_port->tc_port_name); 439 return true; 440 } 441 442 return val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx); 443 } 444 445 static bool adl_tc_phy_is_owned(struct intel_digital_port *dig_port) 446 { 447 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 448 struct intel_uncore *uncore = &i915->uncore; 449 enum port port = dig_port->base.port; 450 u32 val; 451 452 val = intel_uncore_read(uncore, DDI_BUF_CTL(port)); 453 return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP; 454 } 455 456 static bool tc_phy_is_owned(struct intel_digital_port *dig_port) 457 { 458 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 459 460 if (IS_ALDERLAKE_P(i915)) 461 return adl_tc_phy_is_owned(dig_port); 462 463 return icl_tc_phy_is_owned(dig_port); 464 } 465 466 /* 467 * This function implements the first part of the Connect Flow described by our 468 * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading 469 * lanes, EDID, etc) is done as needed in the typical places. 470 * 471 * Unlike the other ports, type-C ports are not available to use as soon as we 472 * get a hotplug. The type-C PHYs can be shared between multiple controllers: 473 * display, USB, etc. As a result, handshaking through FIA is required around 474 * connect and disconnect to cleanly transfer ownership with the controller and 475 * set the type-C power state. 476 */ 477 static void icl_tc_phy_connect(struct intel_digital_port *dig_port, 478 int required_lanes) 479 { 480 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 481 u32 live_status_mask; 482 int max_lanes; 483 484 if (!tc_phy_status_complete(dig_port)) { 485 drm_dbg_kms(&i915->drm, "Port %s: PHY not ready\n", 486 dig_port->tc_port_name); 487 goto out_set_tbt_alt_mode; 488 } 489 490 live_status_mask = tc_port_live_status_mask(dig_port); 491 if (!(live_status_mask & (BIT(TC_PORT_DP_ALT) | BIT(TC_PORT_LEGACY)))) { 492 drm_dbg_kms(&i915->drm, "Port %s: PHY ownership not required (live status %02x)\n", 493 dig_port->tc_port_name, live_status_mask); 494 goto out_set_tbt_alt_mode; 495 } 496 497 if (!tc_phy_take_ownership(dig_port, true) && 498 !drm_WARN_ON(&i915->drm, dig_port->tc_legacy_port)) 499 goto out_set_tbt_alt_mode; 500 501 max_lanes = intel_tc_port_fia_max_lane_count(dig_port); 502 if (dig_port->tc_legacy_port) { 503 drm_WARN_ON(&i915->drm, max_lanes != 4); 504 dig_port->tc_mode = TC_PORT_LEGACY; 505 506 return; 507 } 508 509 /* 510 * Now we have to re-check the live state, in case the port recently 511 * became disconnected. Not necessary for legacy mode. 512 */ 513 if (!(tc_port_live_status_mask(dig_port) & BIT(TC_PORT_DP_ALT))) { 514 drm_dbg_kms(&i915->drm, "Port %s: PHY sudden disconnect\n", 515 dig_port->tc_port_name); 516 goto out_release_phy; 517 } 518 519 if (max_lanes < required_lanes) { 520 drm_dbg_kms(&i915->drm, 521 "Port %s: PHY max lanes %d < required lanes %d\n", 522 dig_port->tc_port_name, 523 max_lanes, required_lanes); 524 goto out_release_phy; 525 } 526 527 dig_port->tc_mode = TC_PORT_DP_ALT; 528 529 return; 530 531 out_release_phy: 532 tc_phy_take_ownership(dig_port, false); 533 out_set_tbt_alt_mode: 534 dig_port->tc_mode = TC_PORT_TBT_ALT; 535 } 536 537 /* 538 * See the comment at the connect function. This implements the Disconnect 539 * Flow. 540 */ 541 static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port) 542 { 543 switch (dig_port->tc_mode) { 544 case TC_PORT_LEGACY: 545 case TC_PORT_DP_ALT: 546 tc_phy_take_ownership(dig_port, false); 547 fallthrough; 548 case TC_PORT_TBT_ALT: 549 dig_port->tc_mode = TC_PORT_DISCONNECTED; 550 fallthrough; 551 case TC_PORT_DISCONNECTED: 552 break; 553 default: 554 MISSING_CASE(dig_port->tc_mode); 555 } 556 } 557 558 static bool icl_tc_phy_is_connected(struct intel_digital_port *dig_port) 559 { 560 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 561 562 if (!tc_phy_status_complete(dig_port)) { 563 drm_dbg_kms(&i915->drm, "Port %s: PHY status not complete\n", 564 dig_port->tc_port_name); 565 return dig_port->tc_mode == TC_PORT_TBT_ALT; 566 } 567 568 /* On ADL-P the PHY complete flag is set in TBT mode as well. */ 569 if (IS_ALDERLAKE_P(i915) && dig_port->tc_mode == TC_PORT_TBT_ALT) 570 return true; 571 572 if (!tc_phy_is_owned(dig_port)) { 573 drm_dbg_kms(&i915->drm, "Port %s: PHY not owned\n", 574 dig_port->tc_port_name); 575 576 return false; 577 } 578 579 return dig_port->tc_mode == TC_PORT_DP_ALT || 580 dig_port->tc_mode == TC_PORT_LEGACY; 581 } 582 583 static enum tc_port_mode 584 intel_tc_port_get_current_mode(struct intel_digital_port *dig_port) 585 { 586 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 587 u32 live_status_mask = tc_port_live_status_mask(dig_port); 588 enum tc_port_mode mode; 589 590 if (!tc_phy_is_owned(dig_port) || 591 drm_WARN_ON(&i915->drm, !tc_phy_status_complete(dig_port))) 592 return TC_PORT_TBT_ALT; 593 594 mode = dig_port->tc_legacy_port ? TC_PORT_LEGACY : TC_PORT_DP_ALT; 595 if (live_status_mask) { 596 enum tc_port_mode live_mode = fls(live_status_mask) - 1; 597 598 if (!drm_WARN_ON(&i915->drm, live_mode == TC_PORT_TBT_ALT)) 599 mode = live_mode; 600 } 601 602 return mode; 603 } 604 605 static enum tc_port_mode 606 intel_tc_port_get_target_mode(struct intel_digital_port *dig_port) 607 { 608 u32 live_status_mask = tc_port_live_status_mask(dig_port); 609 610 if (live_status_mask) 611 return fls(live_status_mask) - 1; 612 613 return TC_PORT_TBT_ALT; 614 } 615 616 static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port, 617 int required_lanes, bool force_disconnect) 618 { 619 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 620 enum tc_port_mode old_tc_mode = dig_port->tc_mode; 621 622 intel_display_power_flush_work(i915); 623 if (!intel_tc_cold_requires_aux_pw(dig_port)) { 624 enum intel_display_power_domain aux_domain; 625 bool aux_powered; 626 627 aux_domain = intel_aux_power_domain(dig_port); 628 aux_powered = intel_display_power_is_enabled(i915, aux_domain); 629 drm_WARN_ON(&i915->drm, aux_powered); 630 } 631 632 icl_tc_phy_disconnect(dig_port); 633 if (!force_disconnect) 634 icl_tc_phy_connect(dig_port, required_lanes); 635 636 drm_dbg_kms(&i915->drm, "Port %s: TC port mode reset (%s -> %s)\n", 637 dig_port->tc_port_name, 638 tc_port_mode_name(old_tc_mode), 639 tc_port_mode_name(dig_port->tc_mode)); 640 } 641 642 static bool intel_tc_port_needs_reset(struct intel_digital_port *dig_port) 643 { 644 return intel_tc_port_get_target_mode(dig_port) != dig_port->tc_mode; 645 } 646 647 static void intel_tc_port_update_mode(struct intel_digital_port *dig_port, 648 int required_lanes, bool force_disconnect) 649 { 650 enum intel_display_power_domain domain; 651 intel_wakeref_t wref; 652 bool needs_reset = force_disconnect; 653 654 if (!needs_reset) { 655 /* Get power domain required to check the hotplug live status. */ 656 wref = tc_cold_block(dig_port, &domain); 657 needs_reset = intel_tc_port_needs_reset(dig_port); 658 tc_cold_unblock(dig_port, domain, wref); 659 } 660 661 if (!needs_reset) 662 return; 663 664 /* Get power domain required for resetting the mode. */ 665 wref = tc_cold_block_in_mode(dig_port, TC_PORT_DISCONNECTED, &domain); 666 667 intel_tc_port_reset_mode(dig_port, required_lanes, force_disconnect); 668 669 /* Get power domain matching the new mode after reset. */ 670 tc_cold_unblock(dig_port, dig_port->tc_lock_power_domain, 671 fetch_and_zero(&dig_port->tc_lock_wakeref)); 672 if (dig_port->tc_mode != TC_PORT_DISCONNECTED) 673 dig_port->tc_lock_wakeref = tc_cold_block(dig_port, 674 &dig_port->tc_lock_power_domain); 675 676 tc_cold_unblock(dig_port, domain, wref); 677 } 678 679 static void 680 intel_tc_port_link_init_refcount(struct intel_digital_port *dig_port, 681 int refcount) 682 { 683 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 684 685 drm_WARN_ON(&i915->drm, dig_port->tc_link_refcount); 686 dig_port->tc_link_refcount = refcount; 687 } 688 689 void intel_tc_port_sanitize(struct intel_digital_port *dig_port) 690 { 691 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 692 struct intel_encoder *encoder = &dig_port->base; 693 int active_links = 0; 694 695 mutex_lock(&dig_port->tc_lock); 696 697 if (dig_port->dp.is_mst) 698 active_links = intel_dp_mst_encoder_active_links(dig_port); 699 else if (encoder->base.crtc) 700 active_links = to_intel_crtc(encoder->base.crtc)->active; 701 702 drm_WARN_ON(&i915->drm, dig_port->tc_mode != TC_PORT_DISCONNECTED); 703 drm_WARN_ON(&i915->drm, dig_port->tc_lock_wakeref); 704 if (active_links) { 705 enum intel_display_power_domain domain; 706 intel_wakeref_t tc_cold_wref = tc_cold_block(dig_port, &domain); 707 708 dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port); 709 710 if (!icl_tc_phy_is_connected(dig_port)) 711 drm_dbg_kms(&i915->drm, 712 "Port %s: PHY disconnected with %d active link(s)\n", 713 dig_port->tc_port_name, active_links); 714 intel_tc_port_link_init_refcount(dig_port, active_links); 715 716 dig_port->tc_lock_wakeref = tc_cold_block(dig_port, 717 &dig_port->tc_lock_power_domain); 718 719 tc_cold_unblock(dig_port, domain, tc_cold_wref); 720 } 721 722 drm_dbg_kms(&i915->drm, "Port %s: sanitize mode (%s)\n", 723 dig_port->tc_port_name, 724 tc_port_mode_name(dig_port->tc_mode)); 725 726 mutex_unlock(&dig_port->tc_lock); 727 } 728 729 /* 730 * The type-C ports are different because even when they are connected, they may 731 * not be available/usable by the graphics driver: see the comment on 732 * icl_tc_phy_connect(). So in our driver instead of adding the additional 733 * concept of "usable" and make everything check for "connected and usable" we 734 * define a port as "connected" when it is not only connected, but also when it 735 * is usable by the rest of the driver. That maintains the old assumption that 736 * connected ports are usable, and avoids exposing to the users objects they 737 * can't really use. 738 */ 739 bool intel_tc_port_connected(struct intel_encoder *encoder) 740 { 741 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 742 bool is_connected; 743 744 intel_tc_port_lock(dig_port); 745 746 is_connected = tc_port_live_status_mask(dig_port) & 747 BIT(dig_port->tc_mode); 748 749 intel_tc_port_unlock(dig_port); 750 751 return is_connected; 752 } 753 754 static void __intel_tc_port_lock(struct intel_digital_port *dig_port, 755 int required_lanes) 756 { 757 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 758 759 mutex_lock(&dig_port->tc_lock); 760 761 cancel_delayed_work(&dig_port->tc_disconnect_phy_work); 762 763 if (!dig_port->tc_link_refcount) 764 intel_tc_port_update_mode(dig_port, required_lanes, 765 false); 766 767 drm_WARN_ON(&i915->drm, dig_port->tc_mode == TC_PORT_DISCONNECTED); 768 drm_WARN_ON(&i915->drm, dig_port->tc_mode != TC_PORT_TBT_ALT && 769 !tc_phy_is_owned(dig_port)); 770 } 771 772 void intel_tc_port_lock(struct intel_digital_port *dig_port) 773 { 774 __intel_tc_port_lock(dig_port, 1); 775 } 776 777 /** 778 * intel_tc_port_disconnect_phy_work: disconnect TypeC PHY from display port 779 * @dig_port: digital port 780 * 781 * Disconnect the given digital port from its TypeC PHY (handing back the 782 * control of the PHY to the TypeC subsystem). This will happen in a delayed 783 * manner after each aux transactions and modeset disables. 784 */ 785 static void intel_tc_port_disconnect_phy_work(struct work_struct *work) 786 { 787 struct intel_digital_port *dig_port = 788 container_of(work, struct intel_digital_port, tc_disconnect_phy_work.work); 789 790 mutex_lock(&dig_port->tc_lock); 791 792 if (!dig_port->tc_link_refcount) 793 intel_tc_port_update_mode(dig_port, 1, true); 794 795 mutex_unlock(&dig_port->tc_lock); 796 } 797 798 /** 799 * intel_tc_port_flush_work: flush the work disconnecting the PHY 800 * @dig_port: digital port 801 * 802 * Flush the delayed work disconnecting an idle PHY. 803 */ 804 void intel_tc_port_flush_work(struct intel_digital_port *dig_port) 805 { 806 flush_delayed_work(&dig_port->tc_disconnect_phy_work); 807 } 808 809 void intel_tc_port_unlock(struct intel_digital_port *dig_port) 810 { 811 if (!dig_port->tc_link_refcount && dig_port->tc_mode != TC_PORT_DISCONNECTED) 812 queue_delayed_work(system_unbound_wq, &dig_port->tc_disconnect_phy_work, 813 msecs_to_jiffies(1000)); 814 815 mutex_unlock(&dig_port->tc_lock); 816 } 817 818 bool intel_tc_port_ref_held(struct intel_digital_port *dig_port) 819 { 820 return mutex_is_locked(&dig_port->tc_lock) || 821 dig_port->tc_link_refcount; 822 } 823 824 void intel_tc_port_get_link(struct intel_digital_port *dig_port, 825 int required_lanes) 826 { 827 __intel_tc_port_lock(dig_port, required_lanes); 828 dig_port->tc_link_refcount++; 829 intel_tc_port_unlock(dig_port); 830 } 831 832 void intel_tc_port_put_link(struct intel_digital_port *dig_port) 833 { 834 intel_tc_port_lock(dig_port); 835 --dig_port->tc_link_refcount; 836 intel_tc_port_unlock(dig_port); 837 838 /* 839 * Disconnecting the PHY after the PHY's PLL gets disabled may 840 * hang the system on ADL-P, so disconnect the PHY here synchronously. 841 * TODO: remove this once the root cause of the ordering requirement 842 * is found/fixed. 843 */ 844 intel_tc_port_flush_work(dig_port); 845 } 846 847 static bool 848 tc_has_modular_fia(struct drm_i915_private *i915, struct intel_digital_port *dig_port) 849 { 850 enum intel_display_power_domain domain; 851 intel_wakeref_t wakeref; 852 u32 val; 853 854 if (!INTEL_INFO(i915)->display.has_modular_fia) 855 return false; 856 857 mutex_lock(&dig_port->tc_lock); 858 wakeref = tc_cold_block(dig_port, &domain); 859 val = intel_uncore_read(&i915->uncore, PORT_TX_DFLEXDPSP(FIA1)); 860 tc_cold_unblock(dig_port, domain, wakeref); 861 mutex_unlock(&dig_port->tc_lock); 862 863 drm_WARN_ON(&i915->drm, val == 0xffffffff); 864 865 return val & MODULAR_FIA_MASK; 866 } 867 868 static void 869 tc_port_load_fia_params(struct drm_i915_private *i915, struct intel_digital_port *dig_port) 870 { 871 enum port port = dig_port->base.port; 872 enum tc_port tc_port = intel_port_to_tc(i915, port); 873 874 /* 875 * Each Modular FIA instance houses 2 TC ports. In SOC that has more 876 * than two TC ports, there are multiple instances of Modular FIA. 877 */ 878 if (tc_has_modular_fia(i915, dig_port)) { 879 dig_port->tc_phy_fia = tc_port / 2; 880 dig_port->tc_phy_fia_idx = tc_port % 2; 881 } else { 882 dig_port->tc_phy_fia = FIA1; 883 dig_port->tc_phy_fia_idx = tc_port; 884 } 885 } 886 887 void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy) 888 { 889 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 890 enum port port = dig_port->base.port; 891 enum tc_port tc_port = intel_port_to_tc(i915, port); 892 893 if (drm_WARN_ON(&i915->drm, tc_port == TC_PORT_NONE)) 894 return; 895 896 snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name), 897 "%c/TC#%d", port_name(port), tc_port + 1); 898 899 mutex_init(&dig_port->tc_lock); 900 INIT_DELAYED_WORK(&dig_port->tc_disconnect_phy_work, intel_tc_port_disconnect_phy_work); 901 dig_port->tc_legacy_port = is_legacy; 902 dig_port->tc_mode = TC_PORT_DISCONNECTED; 903 dig_port->tc_link_refcount = 0; 904 tc_port_load_fia_params(i915, dig_port); 905 } 906