1 /* 2 * Copyright © 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Jesse Barnes <jbarnes@virtuousgeek.org> 25 * 26 * New plane/sprite handling. 27 * 28 * The older chips had a separate interface for programming plane related 29 * registers; newer ones are much simpler and we can use the new DRM plane 30 * support. 31 */ 32 33 #include <drm/drm_atomic.h> 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_color_mgmt.h> 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_damage_helper.h> 38 #include <drm/drm_fourcc.h> 39 #include <drm/drm_plane_helper.h> 40 #include <drm/drm_rect.h> 41 42 #include "i915_drv.h" 43 #include "i915_trace.h" 44 #include "i915_vgpu.h" 45 #include "intel_atomic_plane.h" 46 #include "intel_display_types.h" 47 #include "intel_frontbuffer.h" 48 #include "intel_pm.h" 49 #include "intel_psr.h" 50 #include "intel_dsi.h" 51 #include "intel_sprite.h" 52 #include "i9xx_plane.h" 53 #include "intel_vrr.h" 54 55 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, 56 int usecs) 57 { 58 /* paranoia */ 59 if (!adjusted_mode->crtc_htotal) 60 return 1; 61 62 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock, 63 1000 * adjusted_mode->crtc_htotal); 64 } 65 66 static int intel_mode_vblank_start(const struct drm_display_mode *mode) 67 { 68 int vblank_start = mode->crtc_vblank_start; 69 70 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 71 vblank_start = DIV_ROUND_UP(vblank_start, 2); 72 73 return vblank_start; 74 } 75 76 /** 77 * intel_pipe_update_start() - start update of a set of display registers 78 * @new_crtc_state: the new crtc state 79 * 80 * Mark the start of an update to pipe registers that should be updated 81 * atomically regarding vblank. If the next vblank will happens within 82 * the next 100 us, this function waits until the vblank passes. 83 * 84 * After a successful call to this function, interrupts will be disabled 85 * until a subsequent call to intel_pipe_update_end(). That is done to 86 * avoid random delays. 87 */ 88 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state) 89 { 90 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 91 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 92 const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode; 93 long timeout = msecs_to_jiffies_timeout(1); 94 int scanline, min, max, vblank_start; 95 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); 96 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 97 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI); 98 DEFINE_WAIT(wait); 99 u32 psr_status; 100 101 if (new_crtc_state->uapi.async_flip) 102 return; 103 104 if (new_crtc_state->vrr.enable) 105 vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state); 106 else 107 vblank_start = intel_mode_vblank_start(adjusted_mode); 108 109 /* FIXME needs to be calibrated sensibly */ 110 min = vblank_start - intel_usecs_to_scanlines(adjusted_mode, 111 VBLANK_EVASION_TIME_US); 112 max = vblank_start - 1; 113 114 if (min <= 0 || max <= 0) 115 goto irq_disable; 116 117 if (drm_WARN_ON(&dev_priv->drm, drm_crtc_vblank_get(&crtc->base))) 118 goto irq_disable; 119 120 /* 121 * Wait for psr to idle out after enabling the VBL interrupts 122 * VBL interrupts will start the PSR exit and prevent a PSR 123 * re-entry as well. 124 */ 125 if (intel_psr_wait_for_idle(new_crtc_state, &psr_status)) 126 drm_err(&dev_priv->drm, 127 "PSR idle timed out 0x%x, atomic update may fail\n", 128 psr_status); 129 130 local_irq_disable(); 131 132 crtc->debug.min_vbl = min; 133 crtc->debug.max_vbl = max; 134 trace_intel_pipe_update_start(crtc); 135 136 for (;;) { 137 /* 138 * prepare_to_wait() has a memory barrier, which guarantees 139 * other CPUs can see the task state update by the time we 140 * read the scanline. 141 */ 142 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); 143 144 scanline = intel_get_crtc_scanline(crtc); 145 if (scanline < min || scanline > max) 146 break; 147 148 if (!timeout) { 149 drm_err(&dev_priv->drm, 150 "Potential atomic update failure on pipe %c\n", 151 pipe_name(crtc->pipe)); 152 break; 153 } 154 155 local_irq_enable(); 156 157 timeout = schedule_timeout(timeout); 158 159 local_irq_disable(); 160 } 161 162 finish_wait(wq, &wait); 163 164 drm_crtc_vblank_put(&crtc->base); 165 166 /* 167 * On VLV/CHV DSI the scanline counter would appear to 168 * increment approx. 1/3 of a scanline before start of vblank. 169 * The registers still get latched at start of vblank however. 170 * This means we must not write any registers on the first 171 * line of vblank (since not the whole line is actually in 172 * vblank). And unfortunately we can't use the interrupt to 173 * wait here since it will fire too soon. We could use the 174 * frame start interrupt instead since it will fire after the 175 * critical scanline, but that would require more changes 176 * in the interrupt code. So for now we'll just do the nasty 177 * thing and poll for the bad scanline to pass us by. 178 * 179 * FIXME figure out if BXT+ DSI suffers from this as well 180 */ 181 while (need_vlv_dsi_wa && scanline == vblank_start) 182 scanline = intel_get_crtc_scanline(crtc); 183 184 crtc->debug.scanline_start = scanline; 185 crtc->debug.start_vbl_time = ktime_get(); 186 crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc); 187 188 trace_intel_pipe_update_vblank_evaded(crtc); 189 return; 190 191 irq_disable: 192 local_irq_disable(); 193 } 194 195 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE) 196 static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end) 197 { 198 u64 delta = ktime_to_ns(ktime_sub(end, crtc->debug.start_vbl_time)); 199 unsigned int h; 200 201 h = ilog2(delta >> 9); 202 if (h >= ARRAY_SIZE(crtc->debug.vbl.times)) 203 h = ARRAY_SIZE(crtc->debug.vbl.times) - 1; 204 crtc->debug.vbl.times[h]++; 205 206 crtc->debug.vbl.sum += delta; 207 if (!crtc->debug.vbl.min || delta < crtc->debug.vbl.min) 208 crtc->debug.vbl.min = delta; 209 if (delta > crtc->debug.vbl.max) 210 crtc->debug.vbl.max = delta; 211 212 if (delta > 1000 * VBLANK_EVASION_TIME_US) { 213 drm_dbg_kms(crtc->base.dev, 214 "Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n", 215 pipe_name(crtc->pipe), 216 div_u64(delta, 1000), 217 VBLANK_EVASION_TIME_US); 218 crtc->debug.vbl.over++; 219 } 220 } 221 #else 222 static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end) {} 223 #endif 224 225 /** 226 * intel_pipe_update_end() - end update of a set of display registers 227 * @new_crtc_state: the new crtc state 228 * 229 * Mark the end of an update started with intel_pipe_update_start(). This 230 * re-enables interrupts and verifies the update was actually completed 231 * before a vblank. 232 */ 233 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state) 234 { 235 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 236 enum pipe pipe = crtc->pipe; 237 int scanline_end = intel_get_crtc_scanline(crtc); 238 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc); 239 ktime_t end_vbl_time = ktime_get(); 240 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 241 242 if (new_crtc_state->uapi.async_flip) 243 return; 244 245 trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end); 246 247 /* 248 * Incase of mipi dsi command mode, we need to set frame update 249 * request for every commit. 250 */ 251 if (INTEL_GEN(dev_priv) >= 11 && 252 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 253 icl_dsi_frame_update(new_crtc_state); 254 255 /* We're still in the vblank-evade critical section, this can't race. 256 * Would be slightly nice to just grab the vblank count and arm the 257 * event outside of the critical section - the spinlock might spin for a 258 * while ... */ 259 if (new_crtc_state->uapi.event) { 260 drm_WARN_ON(&dev_priv->drm, 261 drm_crtc_vblank_get(&crtc->base) != 0); 262 263 spin_lock(&crtc->base.dev->event_lock); 264 drm_crtc_arm_vblank_event(&crtc->base, 265 new_crtc_state->uapi.event); 266 spin_unlock(&crtc->base.dev->event_lock); 267 268 new_crtc_state->uapi.event = NULL; 269 } 270 271 local_irq_enable(); 272 273 /* Send VRR Push to terminate Vblank */ 274 intel_vrr_send_push(new_crtc_state); 275 276 if (intel_vgpu_active(dev_priv)) 277 return; 278 279 if (crtc->debug.start_vbl_count && 280 crtc->debug.start_vbl_count != end_vbl_count) { 281 drm_err(&dev_priv->drm, 282 "Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n", 283 pipe_name(pipe), crtc->debug.start_vbl_count, 284 end_vbl_count, 285 ktime_us_delta(end_vbl_time, 286 crtc->debug.start_vbl_time), 287 crtc->debug.min_vbl, crtc->debug.max_vbl, 288 crtc->debug.scanline_start, scanline_end); 289 } 290 291 dbg_vblank_evade(crtc, end_vbl_time); 292 } 293 294 int intel_plane_check_stride(const struct intel_plane_state *plane_state) 295 { 296 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 297 const struct drm_framebuffer *fb = plane_state->hw.fb; 298 unsigned int rotation = plane_state->hw.rotation; 299 u32 stride, max_stride; 300 301 /* 302 * We ignore stride for all invisible planes that 303 * can be remapped. Otherwise we could end up 304 * with a false positive when the remapping didn't 305 * kick in due the plane being invisible. 306 */ 307 if (intel_plane_can_remap(plane_state) && 308 !plane_state->uapi.visible) 309 return 0; 310 311 /* FIXME other color planes? */ 312 stride = plane_state->color_plane[0].stride; 313 max_stride = plane->max_stride(plane, fb->format->format, 314 fb->modifier, rotation); 315 316 if (stride > max_stride) { 317 DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n", 318 fb->base.id, stride, 319 plane->base.base.id, plane->base.name, max_stride); 320 return -EINVAL; 321 } 322 323 return 0; 324 } 325 326 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state) 327 { 328 const struct drm_framebuffer *fb = plane_state->hw.fb; 329 struct drm_rect *src = &plane_state->uapi.src; 330 u32 src_x, src_y, src_w, src_h, hsub, vsub; 331 bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation); 332 333 /* 334 * FIXME hsub/vsub vs. block size is a mess. Pre-tgl CCS 335 * abuses hsub/vsub so we can't use them here. But as they 336 * are limited to 32bpp RGB formats we don't actually need 337 * to check anything. 338 */ 339 if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || 340 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) 341 return 0; 342 343 /* 344 * Hardware doesn't handle subpixel coordinates. 345 * Adjust to (macro)pixel boundary, but be careful not to 346 * increase the source viewport size, because that could 347 * push the downscaling factor out of bounds. 348 */ 349 src_x = src->x1 >> 16; 350 src_w = drm_rect_width(src) >> 16; 351 src_y = src->y1 >> 16; 352 src_h = drm_rect_height(src) >> 16; 353 354 drm_rect_init(src, src_x << 16, src_y << 16, 355 src_w << 16, src_h << 16); 356 357 if (fb->format->format == DRM_FORMAT_RGB565 && rotated) { 358 hsub = 2; 359 vsub = 2; 360 } else { 361 hsub = fb->format->hsub; 362 vsub = fb->format->vsub; 363 } 364 365 if (rotated) 366 hsub = vsub = max(hsub, vsub); 367 368 if (src_x % hsub || src_w % hsub) { 369 DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n", 370 src_x, src_w, hsub, yesno(rotated)); 371 return -EINVAL; 372 } 373 374 if (src_y % vsub || src_h % vsub) { 375 DRM_DEBUG_KMS("src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n", 376 src_y, src_h, vsub, yesno(rotated)); 377 return -EINVAL; 378 } 379 380 return 0; 381 } 382 383 static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915) 384 { 385 if (IS_ROCKETLAKE(i915)) 386 return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3); 387 else 388 return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5); 389 } 390 391 bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv, 392 enum plane_id plane_id) 393 { 394 return INTEL_GEN(dev_priv) >= 11 && 395 icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id); 396 } 397 398 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id) 399 { 400 return INTEL_GEN(dev_priv) >= 11 && 401 icl_hdr_plane_mask() & BIT(plane_id); 402 } 403 404 static void 405 skl_plane_ratio(const struct intel_crtc_state *crtc_state, 406 const struct intel_plane_state *plane_state, 407 unsigned int *num, unsigned int *den) 408 { 409 struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev); 410 const struct drm_framebuffer *fb = plane_state->hw.fb; 411 412 if (fb->format->cpp[0] == 8) { 413 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { 414 *num = 10; 415 *den = 8; 416 } else { 417 *num = 9; 418 *den = 8; 419 } 420 } else { 421 *num = 1; 422 *den = 1; 423 } 424 } 425 426 static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 427 const struct intel_plane_state *plane_state) 428 { 429 struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev); 430 unsigned int num, den; 431 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 432 433 skl_plane_ratio(crtc_state, plane_state, &num, &den); 434 435 /* two pixels per clock on glk+ */ 436 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 437 den *= 2; 438 439 return DIV_ROUND_UP(pixel_rate * num, den); 440 } 441 442 static int skl_plane_max_width(const struct drm_framebuffer *fb, 443 int color_plane, 444 unsigned int rotation) 445 { 446 int cpp = fb->format->cpp[color_plane]; 447 448 switch (fb->modifier) { 449 case DRM_FORMAT_MOD_LINEAR: 450 case I915_FORMAT_MOD_X_TILED: 451 /* 452 * Validated limit is 4k, but has 5k should 453 * work apart from the following features: 454 * - Ytile (already limited to 4k) 455 * - FP16 (already limited to 4k) 456 * - render compression (already limited to 4k) 457 * - KVMR sprite and cursor (don't care) 458 * - horizontal panning (TODO verify this) 459 * - pipe and plane scaling (TODO verify this) 460 */ 461 if (cpp == 8) 462 return 4096; 463 else 464 return 5120; 465 case I915_FORMAT_MOD_Y_TILED_CCS: 466 case I915_FORMAT_MOD_Yf_TILED_CCS: 467 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 468 /* FIXME AUX plane? */ 469 case I915_FORMAT_MOD_Y_TILED: 470 case I915_FORMAT_MOD_Yf_TILED: 471 if (cpp == 8) 472 return 2048; 473 else 474 return 4096; 475 default: 476 MISSING_CASE(fb->modifier); 477 return 2048; 478 } 479 } 480 481 static int glk_plane_max_width(const struct drm_framebuffer *fb, 482 int color_plane, 483 unsigned int rotation) 484 { 485 int cpp = fb->format->cpp[color_plane]; 486 487 switch (fb->modifier) { 488 case DRM_FORMAT_MOD_LINEAR: 489 case I915_FORMAT_MOD_X_TILED: 490 if (cpp == 8) 491 return 4096; 492 else 493 return 5120; 494 case I915_FORMAT_MOD_Y_TILED_CCS: 495 case I915_FORMAT_MOD_Yf_TILED_CCS: 496 /* FIXME AUX plane? */ 497 case I915_FORMAT_MOD_Y_TILED: 498 case I915_FORMAT_MOD_Yf_TILED: 499 if (cpp == 8) 500 return 2048; 501 else 502 return 5120; 503 default: 504 MISSING_CASE(fb->modifier); 505 return 2048; 506 } 507 } 508 509 static int icl_plane_min_width(const struct drm_framebuffer *fb, 510 int color_plane, 511 unsigned int rotation) 512 { 513 /* Wa_14011264657, Wa_14011050563: gen11+ */ 514 switch (fb->format->format) { 515 case DRM_FORMAT_C8: 516 return 18; 517 case DRM_FORMAT_RGB565: 518 return 10; 519 case DRM_FORMAT_XRGB8888: 520 case DRM_FORMAT_XBGR8888: 521 case DRM_FORMAT_ARGB8888: 522 case DRM_FORMAT_ABGR8888: 523 case DRM_FORMAT_XRGB2101010: 524 case DRM_FORMAT_XBGR2101010: 525 case DRM_FORMAT_ARGB2101010: 526 case DRM_FORMAT_ABGR2101010: 527 case DRM_FORMAT_XVYU2101010: 528 case DRM_FORMAT_Y212: 529 case DRM_FORMAT_Y216: 530 return 6; 531 case DRM_FORMAT_NV12: 532 return 20; 533 case DRM_FORMAT_P010: 534 case DRM_FORMAT_P012: 535 case DRM_FORMAT_P016: 536 return 12; 537 case DRM_FORMAT_XRGB16161616F: 538 case DRM_FORMAT_XBGR16161616F: 539 case DRM_FORMAT_ARGB16161616F: 540 case DRM_FORMAT_ABGR16161616F: 541 case DRM_FORMAT_XVYU12_16161616: 542 case DRM_FORMAT_XVYU16161616: 543 return 4; 544 default: 545 return 1; 546 } 547 } 548 549 static int icl_plane_max_width(const struct drm_framebuffer *fb, 550 int color_plane, 551 unsigned int rotation) 552 { 553 return 5120; 554 } 555 556 static int skl_plane_max_height(const struct drm_framebuffer *fb, 557 int color_plane, 558 unsigned int rotation) 559 { 560 return 4096; 561 } 562 563 static int icl_plane_max_height(const struct drm_framebuffer *fb, 564 int color_plane, 565 unsigned int rotation) 566 { 567 return 4320; 568 } 569 570 static unsigned int 571 skl_plane_max_stride(struct intel_plane *plane, 572 u32 pixel_format, u64 modifier, 573 unsigned int rotation) 574 { 575 const struct drm_format_info *info = drm_format_info(pixel_format); 576 int cpp = info->cpp[0]; 577 578 /* 579 * "The stride in bytes must not exceed the 580 * of the size of 8K pixels and 32K bytes." 581 */ 582 if (drm_rotation_90_or_270(rotation)) 583 return min(8192, 32768 / cpp); 584 else 585 return min(8192 * cpp, 32768); 586 } 587 588 static void 589 skl_program_scaler(struct intel_plane *plane, 590 const struct intel_crtc_state *crtc_state, 591 const struct intel_plane_state *plane_state) 592 { 593 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 594 const struct drm_framebuffer *fb = plane_state->hw.fb; 595 enum pipe pipe = plane->pipe; 596 int scaler_id = plane_state->scaler_id; 597 const struct intel_scaler *scaler = 598 &crtc_state->scaler_state.scalers[scaler_id]; 599 int crtc_x = plane_state->uapi.dst.x1; 600 int crtc_y = plane_state->uapi.dst.y1; 601 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 602 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 603 u16 y_hphase, uv_rgb_hphase; 604 u16 y_vphase, uv_rgb_vphase; 605 int hscale, vscale; 606 u32 ps_ctrl; 607 608 hscale = drm_rect_calc_hscale(&plane_state->uapi.src, 609 &plane_state->uapi.dst, 610 0, INT_MAX); 611 vscale = drm_rect_calc_vscale(&plane_state->uapi.src, 612 &plane_state->uapi.dst, 613 0, INT_MAX); 614 615 /* TODO: handle sub-pixel coordinates */ 616 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 617 !icl_is_hdr_plane(dev_priv, plane->id)) { 618 y_hphase = skl_scaler_calc_phase(1, hscale, false); 619 y_vphase = skl_scaler_calc_phase(1, vscale, false); 620 621 /* MPEG2 chroma siting convention */ 622 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true); 623 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false); 624 } else { 625 /* not used */ 626 y_hphase = 0; 627 y_vphase = 0; 628 629 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false); 630 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); 631 } 632 633 ps_ctrl = skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0); 634 ps_ctrl |= PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode; 635 636 skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0, 637 plane_state->hw.scaling_filter); 638 639 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); 640 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id), 641 PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); 642 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id), 643 PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); 644 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id), 645 (crtc_x << 16) | crtc_y); 646 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id), 647 (crtc_w << 16) | crtc_h); 648 } 649 650 /* Preoffset values for YUV to RGB Conversion */ 651 #define PREOFF_YUV_TO_RGB_HI 0x1800 652 #define PREOFF_YUV_TO_RGB_ME 0x0000 653 #define PREOFF_YUV_TO_RGB_LO 0x1800 654 655 #define ROFF(x) (((x) & 0xffff) << 16) 656 #define GOFF(x) (((x) & 0xffff) << 0) 657 #define BOFF(x) (((x) & 0xffff) << 16) 658 659 /* 660 * Programs the input color space conversion stage for ICL HDR planes. 661 * Note that it is assumed that this stage always happens after YUV 662 * range correction. Thus, the input to this stage is assumed to be 663 * in full-range YCbCr. 664 */ 665 static void 666 icl_program_input_csc(struct intel_plane *plane, 667 const struct intel_crtc_state *crtc_state, 668 const struct intel_plane_state *plane_state) 669 { 670 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 671 enum pipe pipe = plane->pipe; 672 enum plane_id plane_id = plane->id; 673 674 static const u16 input_csc_matrix[][9] = { 675 /* 676 * BT.601 full range YCbCr -> full range RGB 677 * The matrix required is : 678 * [1.000, 0.000, 1.371, 679 * 1.000, -0.336, -0.698, 680 * 1.000, 1.732, 0.0000] 681 */ 682 [DRM_COLOR_YCBCR_BT601] = { 683 0x7AF8, 0x7800, 0x0, 684 0x8B28, 0x7800, 0x9AC0, 685 0x0, 0x7800, 0x7DD8, 686 }, 687 /* 688 * BT.709 full range YCbCr -> full range RGB 689 * The matrix required is : 690 * [1.000, 0.000, 1.574, 691 * 1.000, -0.187, -0.468, 692 * 1.000, 1.855, 0.0000] 693 */ 694 [DRM_COLOR_YCBCR_BT709] = { 695 0x7C98, 0x7800, 0x0, 696 0x9EF8, 0x7800, 0xAC00, 697 0x0, 0x7800, 0x7ED8, 698 }, 699 /* 700 * BT.2020 full range YCbCr -> full range RGB 701 * The matrix required is : 702 * [1.000, 0.000, 1.474, 703 * 1.000, -0.1645, -0.5713, 704 * 1.000, 1.8814, 0.0000] 705 */ 706 [DRM_COLOR_YCBCR_BT2020] = { 707 0x7BC8, 0x7800, 0x0, 708 0x8928, 0x7800, 0xAA88, 709 0x0, 0x7800, 0x7F10, 710 }, 711 }; 712 const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding]; 713 714 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), 715 ROFF(csc[0]) | GOFF(csc[1])); 716 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), 717 BOFF(csc[2])); 718 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), 719 ROFF(csc[3]) | GOFF(csc[4])); 720 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), 721 BOFF(csc[5])); 722 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), 723 ROFF(csc[6]) | GOFF(csc[7])); 724 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), 725 BOFF(csc[8])); 726 727 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0), 728 PREOFF_YUV_TO_RGB_HI); 729 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 730 PREOFF_YUV_TO_RGB_ME); 731 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2), 732 PREOFF_YUV_TO_RGB_LO); 733 intel_de_write_fw(dev_priv, 734 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0); 735 intel_de_write_fw(dev_priv, 736 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0); 737 intel_de_write_fw(dev_priv, 738 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); 739 } 740 741 static void 742 skl_plane_async_flip(struct intel_plane *plane, 743 const struct intel_crtc_state *crtc_state, 744 const struct intel_plane_state *plane_state, 745 bool async_flip) 746 { 747 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 748 unsigned long irqflags; 749 enum plane_id plane_id = plane->id; 750 enum pipe pipe = plane->pipe; 751 u32 surf_addr = plane_state->color_plane[0].offset; 752 u32 plane_ctl = plane_state->ctl; 753 754 plane_ctl |= skl_plane_ctl_crtc(crtc_state); 755 756 if (async_flip) 757 plane_ctl |= PLANE_CTL_ASYNC_FLIP; 758 759 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 760 761 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); 762 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 763 intel_plane_ggtt_offset(plane_state) + surf_addr); 764 765 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 766 } 767 768 static void 769 skl_program_plane(struct intel_plane *plane, 770 const struct intel_crtc_state *crtc_state, 771 const struct intel_plane_state *plane_state, 772 int color_plane) 773 { 774 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 775 enum plane_id plane_id = plane->id; 776 enum pipe pipe = plane->pipe; 777 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 778 u32 surf_addr = plane_state->color_plane[color_plane].offset; 779 u32 stride = skl_plane_stride(plane_state, color_plane); 780 const struct drm_framebuffer *fb = plane_state->hw.fb; 781 int aux_plane = intel_main_to_aux_plane(fb, color_plane); 782 int crtc_x = plane_state->uapi.dst.x1; 783 int crtc_y = plane_state->uapi.dst.y1; 784 u32 x = plane_state->color_plane[color_plane].x; 785 u32 y = plane_state->color_plane[color_plane].y; 786 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 787 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 788 u8 alpha = plane_state->hw.alpha >> 8; 789 u32 plane_color_ctl = 0, aux_dist = 0; 790 unsigned long irqflags; 791 u32 keymsk, keymax; 792 u32 plane_ctl = plane_state->ctl; 793 794 plane_ctl |= skl_plane_ctl_crtc(crtc_state); 795 796 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 797 plane_color_ctl = plane_state->color_ctl | 798 glk_plane_color_ctl_crtc(crtc_state); 799 800 /* Sizes are 0 based */ 801 src_w--; 802 src_h--; 803 804 keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha); 805 806 keymsk = key->channel_mask & 0x7ffffff; 807 if (alpha < 0xff) 808 keymsk |= PLANE_KEYMSK_ALPHA_ENABLE; 809 810 /* The scaler will handle the output position */ 811 if (plane_state->scaler_id >= 0) { 812 crtc_x = 0; 813 crtc_y = 0; 814 } 815 816 if (aux_plane) { 817 aux_dist = plane_state->color_plane[aux_plane].offset - surf_addr; 818 819 if (INTEL_GEN(dev_priv) < 12) 820 aux_dist |= skl_plane_stride(plane_state, aux_plane); 821 } 822 823 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 824 825 intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), stride); 826 intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id), 827 (crtc_y << 16) | crtc_x); 828 intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id), 829 (src_h << 16) | src_w); 830 831 intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist); 832 833 if (icl_is_hdr_plane(dev_priv, plane_id)) 834 intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 835 plane_state->cus_ctl); 836 837 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 838 intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), 839 plane_color_ctl); 840 841 if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) 842 icl_program_input_csc(plane, crtc_state, plane_state); 843 844 if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) 845 intel_uncore_write64_fw(&dev_priv->uncore, 846 PLANE_CC_VAL(pipe, plane_id), plane_state->ccval); 847 848 skl_write_plane_wm(plane, crtc_state); 849 850 intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), 851 key->min_value); 852 intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk); 853 intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), keymax); 854 855 intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id), 856 (y << 16) | x); 857 858 if (INTEL_GEN(dev_priv) < 11) 859 intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id), 860 (plane_state->color_plane[1].y << 16) | plane_state->color_plane[1].x); 861 862 if (!drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) 863 intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane); 864 865 /* 866 * The control register self-arms if the plane was previously 867 * disabled. Try to make the plane enable atomic by writing 868 * the control register just before the surface register. 869 */ 870 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); 871 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 872 intel_plane_ggtt_offset(plane_state) + surf_addr); 873 874 if (plane_state->scaler_id >= 0) 875 skl_program_scaler(plane, crtc_state, plane_state); 876 877 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 878 } 879 880 static void 881 skl_update_plane(struct intel_plane *plane, 882 const struct intel_crtc_state *crtc_state, 883 const struct intel_plane_state *plane_state) 884 { 885 int color_plane = 0; 886 887 if (plane_state->planar_linked_plane && !plane_state->planar_slave) 888 /* Program the UV plane on planar master */ 889 color_plane = 1; 890 891 skl_program_plane(plane, crtc_state, plane_state, color_plane); 892 } 893 static void 894 skl_disable_plane(struct intel_plane *plane, 895 const struct intel_crtc_state *crtc_state) 896 { 897 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 898 enum plane_id plane_id = plane->id; 899 enum pipe pipe = plane->pipe; 900 unsigned long irqflags; 901 902 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 903 904 if (icl_is_hdr_plane(dev_priv, plane_id)) 905 intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0); 906 907 skl_write_plane_wm(plane, crtc_state); 908 909 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); 910 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); 911 912 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 913 } 914 915 static bool 916 skl_plane_get_hw_state(struct intel_plane *plane, 917 enum pipe *pipe) 918 { 919 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 920 enum intel_display_power_domain power_domain; 921 enum plane_id plane_id = plane->id; 922 intel_wakeref_t wakeref; 923 bool ret; 924 925 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 926 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 927 if (!wakeref) 928 return false; 929 930 ret = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; 931 932 *pipe = plane->pipe; 933 934 intel_display_power_put(dev_priv, power_domain, wakeref); 935 936 return ret; 937 } 938 939 static void 940 skl_plane_enable_flip_done(struct intel_plane *plane) 941 { 942 struct drm_i915_private *i915 = to_i915(plane->base.dev); 943 enum pipe pipe = plane->pipe; 944 945 spin_lock_irq(&i915->irq_lock); 946 bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id)); 947 spin_unlock_irq(&i915->irq_lock); 948 } 949 950 static void 951 skl_plane_disable_flip_done(struct intel_plane *plane) 952 { 953 struct drm_i915_private *i915 = to_i915(plane->base.dev); 954 enum pipe pipe = plane->pipe; 955 956 spin_lock_irq(&i915->irq_lock); 957 bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id)); 958 spin_unlock_irq(&i915->irq_lock); 959 } 960 961 static void i9xx_plane_linear_gamma(u16 gamma[8]) 962 { 963 /* The points are not evenly spaced. */ 964 static const u8 in[8] = { 0, 1, 2, 4, 8, 16, 24, 32 }; 965 int i; 966 967 for (i = 0; i < 8; i++) 968 gamma[i] = (in[i] << 8) / 32; 969 } 970 971 static void 972 chv_update_csc(const struct intel_plane_state *plane_state) 973 { 974 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 975 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 976 const struct drm_framebuffer *fb = plane_state->hw.fb; 977 enum plane_id plane_id = plane->id; 978 /* 979 * |r| | c0 c1 c2 | |cr| 980 * |g| = | c3 c4 c5 | x |y | 981 * |b| | c6 c7 c8 | |cb| 982 * 983 * Coefficients are s3.12. 984 * 985 * Cb and Cr apparently come in as signed already, and 986 * we always get full range data in on account of CLRC0/1. 987 */ 988 static const s16 csc_matrix[][9] = { 989 /* BT.601 full range YCbCr -> full range RGB */ 990 [DRM_COLOR_YCBCR_BT601] = { 991 5743, 4096, 0, 992 -2925, 4096, -1410, 993 0, 4096, 7258, 994 }, 995 /* BT.709 full range YCbCr -> full range RGB */ 996 [DRM_COLOR_YCBCR_BT709] = { 997 6450, 4096, 0, 998 -1917, 4096, -767, 999 0, 4096, 7601, 1000 }, 1001 }; 1002 const s16 *csc = csc_matrix[plane_state->hw.color_encoding]; 1003 1004 /* Seems RGB data bypasses the CSC always */ 1005 if (!fb->format->is_yuv) 1006 return; 1007 1008 intel_de_write_fw(dev_priv, SPCSCYGOFF(plane_id), 1009 SPCSC_OOFF(0) | SPCSC_IOFF(0)); 1010 intel_de_write_fw(dev_priv, SPCSCCBOFF(plane_id), 1011 SPCSC_OOFF(0) | SPCSC_IOFF(0)); 1012 intel_de_write_fw(dev_priv, SPCSCCROFF(plane_id), 1013 SPCSC_OOFF(0) | SPCSC_IOFF(0)); 1014 1015 intel_de_write_fw(dev_priv, SPCSCC01(plane_id), 1016 SPCSC_C1(csc[1]) | SPCSC_C0(csc[0])); 1017 intel_de_write_fw(dev_priv, SPCSCC23(plane_id), 1018 SPCSC_C1(csc[3]) | SPCSC_C0(csc[2])); 1019 intel_de_write_fw(dev_priv, SPCSCC45(plane_id), 1020 SPCSC_C1(csc[5]) | SPCSC_C0(csc[4])); 1021 intel_de_write_fw(dev_priv, SPCSCC67(plane_id), 1022 SPCSC_C1(csc[7]) | SPCSC_C0(csc[6])); 1023 intel_de_write_fw(dev_priv, SPCSCC8(plane_id), SPCSC_C0(csc[8])); 1024 1025 intel_de_write_fw(dev_priv, SPCSCYGICLAMP(plane_id), 1026 SPCSC_IMAX(1023) | SPCSC_IMIN(0)); 1027 intel_de_write_fw(dev_priv, SPCSCCBICLAMP(plane_id), 1028 SPCSC_IMAX(512) | SPCSC_IMIN(-512)); 1029 intel_de_write_fw(dev_priv, SPCSCCRICLAMP(plane_id), 1030 SPCSC_IMAX(512) | SPCSC_IMIN(-512)); 1031 1032 intel_de_write_fw(dev_priv, SPCSCYGOCLAMP(plane_id), 1033 SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 1034 intel_de_write_fw(dev_priv, SPCSCCBOCLAMP(plane_id), 1035 SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 1036 intel_de_write_fw(dev_priv, SPCSCCROCLAMP(plane_id), 1037 SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 1038 } 1039 1040 #define SIN_0 0 1041 #define COS_0 1 1042 1043 static void 1044 vlv_update_clrc(const struct intel_plane_state *plane_state) 1045 { 1046 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1047 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1048 const struct drm_framebuffer *fb = plane_state->hw.fb; 1049 enum pipe pipe = plane->pipe; 1050 enum plane_id plane_id = plane->id; 1051 int contrast, brightness, sh_scale, sh_sin, sh_cos; 1052 1053 if (fb->format->is_yuv && 1054 plane_state->hw.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) { 1055 /* 1056 * Expand limited range to full range: 1057 * Contrast is applied first and is used to expand Y range. 1058 * Brightness is applied second and is used to remove the 1059 * offset from Y. Saturation/hue is used to expand CbCr range. 1060 */ 1061 contrast = DIV_ROUND_CLOSEST(255 << 6, 235 - 16); 1062 brightness = -DIV_ROUND_CLOSEST(16 * 255, 235 - 16); 1063 sh_scale = DIV_ROUND_CLOSEST(128 << 7, 240 - 128); 1064 sh_sin = SIN_0 * sh_scale; 1065 sh_cos = COS_0 * sh_scale; 1066 } else { 1067 /* Pass-through everything. */ 1068 contrast = 1 << 6; 1069 brightness = 0; 1070 sh_scale = 1 << 7; 1071 sh_sin = SIN_0 * sh_scale; 1072 sh_cos = COS_0 * sh_scale; 1073 } 1074 1075 /* FIXME these register are single buffered :( */ 1076 intel_de_write_fw(dev_priv, SPCLRC0(pipe, plane_id), 1077 SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness)); 1078 intel_de_write_fw(dev_priv, SPCLRC1(pipe, plane_id), 1079 SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos)); 1080 } 1081 1082 static void 1083 vlv_plane_ratio(const struct intel_crtc_state *crtc_state, 1084 const struct intel_plane_state *plane_state, 1085 unsigned int *num, unsigned int *den) 1086 { 1087 u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR); 1088 const struct drm_framebuffer *fb = plane_state->hw.fb; 1089 unsigned int cpp = fb->format->cpp[0]; 1090 1091 /* 1092 * VLV bspec only considers cases where all three planes are 1093 * enabled, and cases where the primary and one sprite is enabled. 1094 * Let's assume the case with just two sprites enabled also 1095 * maps to the latter case. 1096 */ 1097 if (hweight8(active_planes) == 3) { 1098 switch (cpp) { 1099 case 8: 1100 *num = 11; 1101 *den = 8; 1102 break; 1103 case 4: 1104 *num = 18; 1105 *den = 16; 1106 break; 1107 default: 1108 *num = 1; 1109 *den = 1; 1110 break; 1111 } 1112 } else if (hweight8(active_planes) == 2) { 1113 switch (cpp) { 1114 case 8: 1115 *num = 10; 1116 *den = 8; 1117 break; 1118 case 4: 1119 *num = 17; 1120 *den = 16; 1121 break; 1122 default: 1123 *num = 1; 1124 *den = 1; 1125 break; 1126 } 1127 } else { 1128 switch (cpp) { 1129 case 8: 1130 *num = 10; 1131 *den = 8; 1132 break; 1133 default: 1134 *num = 1; 1135 *den = 1; 1136 break; 1137 } 1138 } 1139 } 1140 1141 int vlv_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 1142 const struct intel_plane_state *plane_state) 1143 { 1144 unsigned int pixel_rate; 1145 unsigned int num, den; 1146 1147 /* 1148 * Note that crtc_state->pixel_rate accounts for both 1149 * horizontal and vertical panel fitter downscaling factors. 1150 * Pre-HSW bspec tells us to only consider the horizontal 1151 * downscaling factor here. We ignore that and just consider 1152 * both for simplicity. 1153 */ 1154 pixel_rate = crtc_state->pixel_rate; 1155 1156 vlv_plane_ratio(crtc_state, plane_state, &num, &den); 1157 1158 return DIV_ROUND_UP(pixel_rate * num, den); 1159 } 1160 1161 static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) 1162 { 1163 u32 sprctl = 0; 1164 1165 if (crtc_state->gamma_enable) 1166 sprctl |= SP_GAMMA_ENABLE; 1167 1168 return sprctl; 1169 } 1170 1171 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state, 1172 const struct intel_plane_state *plane_state) 1173 { 1174 const struct drm_framebuffer *fb = plane_state->hw.fb; 1175 unsigned int rotation = plane_state->hw.rotation; 1176 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1177 u32 sprctl; 1178 1179 sprctl = SP_ENABLE; 1180 1181 switch (fb->format->format) { 1182 case DRM_FORMAT_YUYV: 1183 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; 1184 break; 1185 case DRM_FORMAT_YVYU: 1186 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; 1187 break; 1188 case DRM_FORMAT_UYVY: 1189 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; 1190 break; 1191 case DRM_FORMAT_VYUY: 1192 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; 1193 break; 1194 case DRM_FORMAT_C8: 1195 sprctl |= SP_FORMAT_8BPP; 1196 break; 1197 case DRM_FORMAT_RGB565: 1198 sprctl |= SP_FORMAT_BGR565; 1199 break; 1200 case DRM_FORMAT_XRGB8888: 1201 sprctl |= SP_FORMAT_BGRX8888; 1202 break; 1203 case DRM_FORMAT_ARGB8888: 1204 sprctl |= SP_FORMAT_BGRA8888; 1205 break; 1206 case DRM_FORMAT_XBGR2101010: 1207 sprctl |= SP_FORMAT_RGBX1010102; 1208 break; 1209 case DRM_FORMAT_ABGR2101010: 1210 sprctl |= SP_FORMAT_RGBA1010102; 1211 break; 1212 case DRM_FORMAT_XRGB2101010: 1213 sprctl |= SP_FORMAT_BGRX1010102; 1214 break; 1215 case DRM_FORMAT_ARGB2101010: 1216 sprctl |= SP_FORMAT_BGRA1010102; 1217 break; 1218 case DRM_FORMAT_XBGR8888: 1219 sprctl |= SP_FORMAT_RGBX8888; 1220 break; 1221 case DRM_FORMAT_ABGR8888: 1222 sprctl |= SP_FORMAT_RGBA8888; 1223 break; 1224 default: 1225 MISSING_CASE(fb->format->format); 1226 return 0; 1227 } 1228 1229 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) 1230 sprctl |= SP_YUV_FORMAT_BT709; 1231 1232 if (fb->modifier == I915_FORMAT_MOD_X_TILED) 1233 sprctl |= SP_TILED; 1234 1235 if (rotation & DRM_MODE_ROTATE_180) 1236 sprctl |= SP_ROTATE_180; 1237 1238 if (rotation & DRM_MODE_REFLECT_X) 1239 sprctl |= SP_MIRROR; 1240 1241 if (key->flags & I915_SET_COLORKEY_SOURCE) 1242 sprctl |= SP_SOURCE_KEY; 1243 1244 return sprctl; 1245 } 1246 1247 static void vlv_update_gamma(const struct intel_plane_state *plane_state) 1248 { 1249 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1250 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1251 const struct drm_framebuffer *fb = plane_state->hw.fb; 1252 enum pipe pipe = plane->pipe; 1253 enum plane_id plane_id = plane->id; 1254 u16 gamma[8]; 1255 int i; 1256 1257 /* Seems RGB data bypasses the gamma always */ 1258 if (!fb->format->is_yuv) 1259 return; 1260 1261 i9xx_plane_linear_gamma(gamma); 1262 1263 /* FIXME these register are single buffered :( */ 1264 /* The two end points are implicit (0.0 and 1.0) */ 1265 for (i = 1; i < 8 - 1; i++) 1266 intel_de_write_fw(dev_priv, SPGAMC(pipe, plane_id, i - 1), 1267 gamma[i] << 16 | gamma[i] << 8 | gamma[i]); 1268 } 1269 1270 static void 1271 vlv_update_plane(struct intel_plane *plane, 1272 const struct intel_crtc_state *crtc_state, 1273 const struct intel_plane_state *plane_state) 1274 { 1275 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1276 enum pipe pipe = plane->pipe; 1277 enum plane_id plane_id = plane->id; 1278 u32 sprsurf_offset = plane_state->color_plane[0].offset; 1279 u32 linear_offset; 1280 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1281 int crtc_x = plane_state->uapi.dst.x1; 1282 int crtc_y = plane_state->uapi.dst.y1; 1283 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 1284 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 1285 u32 x = plane_state->color_plane[0].x; 1286 u32 y = plane_state->color_plane[0].y; 1287 unsigned long irqflags; 1288 u32 sprctl; 1289 1290 sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state); 1291 1292 /* Sizes are 0 based */ 1293 crtc_w--; 1294 crtc_h--; 1295 1296 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 1297 1298 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 1299 1300 intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id), 1301 plane_state->color_plane[0].stride); 1302 intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id), 1303 (crtc_y << 16) | crtc_x); 1304 intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id), 1305 (crtc_h << 16) | crtc_w); 1306 intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0); 1307 1308 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) 1309 chv_update_csc(plane_state); 1310 1311 if (key->flags) { 1312 intel_de_write_fw(dev_priv, SPKEYMINVAL(pipe, plane_id), 1313 key->min_value); 1314 intel_de_write_fw(dev_priv, SPKEYMSK(pipe, plane_id), 1315 key->channel_mask); 1316 intel_de_write_fw(dev_priv, SPKEYMAXVAL(pipe, plane_id), 1317 key->max_value); 1318 } 1319 1320 intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset); 1321 intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id), (y << 16) | x); 1322 1323 /* 1324 * The control register self-arms if the plane was previously 1325 * disabled. Try to make the plane enable atomic by writing 1326 * the control register just before the surface register. 1327 */ 1328 intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), sprctl); 1329 intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), 1330 intel_plane_ggtt_offset(plane_state) + sprsurf_offset); 1331 1332 vlv_update_clrc(plane_state); 1333 vlv_update_gamma(plane_state); 1334 1335 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 1336 } 1337 1338 static void 1339 vlv_disable_plane(struct intel_plane *plane, 1340 const struct intel_crtc_state *crtc_state) 1341 { 1342 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1343 enum pipe pipe = plane->pipe; 1344 enum plane_id plane_id = plane->id; 1345 unsigned long irqflags; 1346 1347 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 1348 1349 intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), 0); 1350 intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), 0); 1351 1352 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 1353 } 1354 1355 static bool 1356 vlv_plane_get_hw_state(struct intel_plane *plane, 1357 enum pipe *pipe) 1358 { 1359 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1360 enum intel_display_power_domain power_domain; 1361 enum plane_id plane_id = plane->id; 1362 intel_wakeref_t wakeref; 1363 bool ret; 1364 1365 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 1366 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 1367 if (!wakeref) 1368 return false; 1369 1370 ret = intel_de_read(dev_priv, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE; 1371 1372 *pipe = plane->pipe; 1373 1374 intel_display_power_put(dev_priv, power_domain, wakeref); 1375 1376 return ret; 1377 } 1378 1379 static void ivb_plane_ratio(const struct intel_crtc_state *crtc_state, 1380 const struct intel_plane_state *plane_state, 1381 unsigned int *num, unsigned int *den) 1382 { 1383 u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR); 1384 const struct drm_framebuffer *fb = plane_state->hw.fb; 1385 unsigned int cpp = fb->format->cpp[0]; 1386 1387 if (hweight8(active_planes) == 2) { 1388 switch (cpp) { 1389 case 8: 1390 *num = 10; 1391 *den = 8; 1392 break; 1393 case 4: 1394 *num = 17; 1395 *den = 16; 1396 break; 1397 default: 1398 *num = 1; 1399 *den = 1; 1400 break; 1401 } 1402 } else { 1403 switch (cpp) { 1404 case 8: 1405 *num = 9; 1406 *den = 8; 1407 break; 1408 default: 1409 *num = 1; 1410 *den = 1; 1411 break; 1412 } 1413 } 1414 } 1415 1416 static void ivb_plane_ratio_scaling(const struct intel_crtc_state *crtc_state, 1417 const struct intel_plane_state *plane_state, 1418 unsigned int *num, unsigned int *den) 1419 { 1420 const struct drm_framebuffer *fb = plane_state->hw.fb; 1421 unsigned int cpp = fb->format->cpp[0]; 1422 1423 switch (cpp) { 1424 case 8: 1425 *num = 12; 1426 *den = 8; 1427 break; 1428 case 4: 1429 *num = 19; 1430 *den = 16; 1431 break; 1432 case 2: 1433 *num = 33; 1434 *den = 32; 1435 break; 1436 default: 1437 *num = 1; 1438 *den = 1; 1439 break; 1440 } 1441 } 1442 1443 int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 1444 const struct intel_plane_state *plane_state) 1445 { 1446 unsigned int pixel_rate; 1447 unsigned int num, den; 1448 1449 /* 1450 * Note that crtc_state->pixel_rate accounts for both 1451 * horizontal and vertical panel fitter downscaling factors. 1452 * Pre-HSW bspec tells us to only consider the horizontal 1453 * downscaling factor here. We ignore that and just consider 1454 * both for simplicity. 1455 */ 1456 pixel_rate = crtc_state->pixel_rate; 1457 1458 ivb_plane_ratio(crtc_state, plane_state, &num, &den); 1459 1460 return DIV_ROUND_UP(pixel_rate * num, den); 1461 } 1462 1463 static int ivb_sprite_min_cdclk(const struct intel_crtc_state *crtc_state, 1464 const struct intel_plane_state *plane_state) 1465 { 1466 unsigned int src_w, dst_w, pixel_rate; 1467 unsigned int num, den; 1468 1469 /* 1470 * Note that crtc_state->pixel_rate accounts for both 1471 * horizontal and vertical panel fitter downscaling factors. 1472 * Pre-HSW bspec tells us to only consider the horizontal 1473 * downscaling factor here. We ignore that and just consider 1474 * both for simplicity. 1475 */ 1476 pixel_rate = crtc_state->pixel_rate; 1477 1478 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1479 dst_w = drm_rect_width(&plane_state->uapi.dst); 1480 1481 if (src_w != dst_w) 1482 ivb_plane_ratio_scaling(crtc_state, plane_state, &num, &den); 1483 else 1484 ivb_plane_ratio(crtc_state, plane_state, &num, &den); 1485 1486 /* Horizontal downscaling limits the maximum pixel rate */ 1487 dst_w = min(src_w, dst_w); 1488 1489 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, num * src_w), 1490 den * dst_w); 1491 } 1492 1493 static void hsw_plane_ratio(const struct intel_crtc_state *crtc_state, 1494 const struct intel_plane_state *plane_state, 1495 unsigned int *num, unsigned int *den) 1496 { 1497 u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR); 1498 const struct drm_framebuffer *fb = plane_state->hw.fb; 1499 unsigned int cpp = fb->format->cpp[0]; 1500 1501 if (hweight8(active_planes) == 2) { 1502 switch (cpp) { 1503 case 8: 1504 *num = 10; 1505 *den = 8; 1506 break; 1507 default: 1508 *num = 1; 1509 *den = 1; 1510 break; 1511 } 1512 } else { 1513 switch (cpp) { 1514 case 8: 1515 *num = 9; 1516 *den = 8; 1517 break; 1518 default: 1519 *num = 1; 1520 *den = 1; 1521 break; 1522 } 1523 } 1524 } 1525 1526 int hsw_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 1527 const struct intel_plane_state *plane_state) 1528 { 1529 unsigned int pixel_rate = crtc_state->pixel_rate; 1530 unsigned int num, den; 1531 1532 hsw_plane_ratio(crtc_state, plane_state, &num, &den); 1533 1534 return DIV_ROUND_UP(pixel_rate * num, den); 1535 } 1536 1537 static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) 1538 { 1539 u32 sprctl = 0; 1540 1541 if (crtc_state->gamma_enable) 1542 sprctl |= SPRITE_GAMMA_ENABLE; 1543 1544 if (crtc_state->csc_enable) 1545 sprctl |= SPRITE_PIPE_CSC_ENABLE; 1546 1547 return sprctl; 1548 } 1549 1550 static bool ivb_need_sprite_gamma(const struct intel_plane_state *plane_state) 1551 { 1552 struct drm_i915_private *dev_priv = 1553 to_i915(plane_state->uapi.plane->dev); 1554 const struct drm_framebuffer *fb = plane_state->hw.fb; 1555 1556 return fb->format->cpp[0] == 8 && 1557 (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)); 1558 } 1559 1560 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state, 1561 const struct intel_plane_state *plane_state) 1562 { 1563 struct drm_i915_private *dev_priv = 1564 to_i915(plane_state->uapi.plane->dev); 1565 const struct drm_framebuffer *fb = plane_state->hw.fb; 1566 unsigned int rotation = plane_state->hw.rotation; 1567 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1568 u32 sprctl; 1569 1570 sprctl = SPRITE_ENABLE; 1571 1572 if (IS_IVYBRIDGE(dev_priv)) 1573 sprctl |= SPRITE_TRICKLE_FEED_DISABLE; 1574 1575 switch (fb->format->format) { 1576 case DRM_FORMAT_XBGR8888: 1577 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; 1578 break; 1579 case DRM_FORMAT_XRGB8888: 1580 sprctl |= SPRITE_FORMAT_RGBX888; 1581 break; 1582 case DRM_FORMAT_XBGR2101010: 1583 sprctl |= SPRITE_FORMAT_RGBX101010 | SPRITE_RGB_ORDER_RGBX; 1584 break; 1585 case DRM_FORMAT_XRGB2101010: 1586 sprctl |= SPRITE_FORMAT_RGBX101010; 1587 break; 1588 case DRM_FORMAT_XBGR16161616F: 1589 sprctl |= SPRITE_FORMAT_RGBX161616 | SPRITE_RGB_ORDER_RGBX; 1590 break; 1591 case DRM_FORMAT_XRGB16161616F: 1592 sprctl |= SPRITE_FORMAT_RGBX161616; 1593 break; 1594 case DRM_FORMAT_YUYV: 1595 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; 1596 break; 1597 case DRM_FORMAT_YVYU: 1598 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; 1599 break; 1600 case DRM_FORMAT_UYVY: 1601 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; 1602 break; 1603 case DRM_FORMAT_VYUY: 1604 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; 1605 break; 1606 default: 1607 MISSING_CASE(fb->format->format); 1608 return 0; 1609 } 1610 1611 if (!ivb_need_sprite_gamma(plane_state)) 1612 sprctl |= SPRITE_INT_GAMMA_DISABLE; 1613 1614 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) 1615 sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709; 1616 1617 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 1618 sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE; 1619 1620 if (fb->modifier == I915_FORMAT_MOD_X_TILED) 1621 sprctl |= SPRITE_TILED; 1622 1623 if (rotation & DRM_MODE_ROTATE_180) 1624 sprctl |= SPRITE_ROTATE_180; 1625 1626 if (key->flags & I915_SET_COLORKEY_DESTINATION) 1627 sprctl |= SPRITE_DEST_KEY; 1628 else if (key->flags & I915_SET_COLORKEY_SOURCE) 1629 sprctl |= SPRITE_SOURCE_KEY; 1630 1631 return sprctl; 1632 } 1633 1634 static void ivb_sprite_linear_gamma(const struct intel_plane_state *plane_state, 1635 u16 gamma[18]) 1636 { 1637 int scale, i; 1638 1639 /* 1640 * WaFP16GammaEnabling:ivb,hsw 1641 * "Workaround : When using the 64-bit format, the sprite output 1642 * on each color channel has one quarter amplitude. It can be 1643 * brought up to full amplitude by using sprite internal gamma 1644 * correction, pipe gamma correction, or pipe color space 1645 * conversion to multiply the sprite output by four." 1646 */ 1647 scale = 4; 1648 1649 for (i = 0; i < 16; i++) 1650 gamma[i] = min((scale * i << 10) / 16, (1 << 10) - 1); 1651 1652 gamma[i] = min((scale * i << 10) / 16, 1 << 10); 1653 i++; 1654 1655 gamma[i] = 3 << 10; 1656 i++; 1657 } 1658 1659 static void ivb_update_gamma(const struct intel_plane_state *plane_state) 1660 { 1661 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1662 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1663 enum pipe pipe = plane->pipe; 1664 u16 gamma[18]; 1665 int i; 1666 1667 if (!ivb_need_sprite_gamma(plane_state)) 1668 return; 1669 1670 ivb_sprite_linear_gamma(plane_state, gamma); 1671 1672 /* FIXME these register are single buffered :( */ 1673 for (i = 0; i < 16; i++) 1674 intel_de_write_fw(dev_priv, SPRGAMC(pipe, i), 1675 gamma[i] << 20 | gamma[i] << 10 | gamma[i]); 1676 1677 intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 0), gamma[i]); 1678 intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 1), gamma[i]); 1679 intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 2), gamma[i]); 1680 i++; 1681 1682 intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 0), gamma[i]); 1683 intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 1), gamma[i]); 1684 intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 2), gamma[i]); 1685 i++; 1686 } 1687 1688 static void 1689 ivb_update_plane(struct intel_plane *plane, 1690 const struct intel_crtc_state *crtc_state, 1691 const struct intel_plane_state *plane_state) 1692 { 1693 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1694 enum pipe pipe = plane->pipe; 1695 u32 sprsurf_offset = plane_state->color_plane[0].offset; 1696 u32 linear_offset; 1697 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1698 int crtc_x = plane_state->uapi.dst.x1; 1699 int crtc_y = plane_state->uapi.dst.y1; 1700 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 1701 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 1702 u32 x = plane_state->color_plane[0].x; 1703 u32 y = plane_state->color_plane[0].y; 1704 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1705 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1706 u32 sprctl, sprscale = 0; 1707 unsigned long irqflags; 1708 1709 sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state); 1710 1711 /* Sizes are 0 based */ 1712 src_w--; 1713 src_h--; 1714 crtc_w--; 1715 crtc_h--; 1716 1717 if (crtc_w != src_w || crtc_h != src_h) 1718 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; 1719 1720 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 1721 1722 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 1723 1724 intel_de_write_fw(dev_priv, SPRSTRIDE(pipe), 1725 plane_state->color_plane[0].stride); 1726 intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x); 1727 intel_de_write_fw(dev_priv, SPRSIZE(pipe), (crtc_h << 16) | crtc_w); 1728 if (IS_IVYBRIDGE(dev_priv)) 1729 intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale); 1730 1731 if (key->flags) { 1732 intel_de_write_fw(dev_priv, SPRKEYVAL(pipe), key->min_value); 1733 intel_de_write_fw(dev_priv, SPRKEYMSK(pipe), 1734 key->channel_mask); 1735 intel_de_write_fw(dev_priv, SPRKEYMAX(pipe), key->max_value); 1736 } 1737 1738 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET 1739 * register */ 1740 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 1741 intel_de_write_fw(dev_priv, SPROFFSET(pipe), (y << 16) | x); 1742 } else { 1743 intel_de_write_fw(dev_priv, SPRLINOFF(pipe), linear_offset); 1744 intel_de_write_fw(dev_priv, SPRTILEOFF(pipe), (y << 16) | x); 1745 } 1746 1747 /* 1748 * The control register self-arms if the plane was previously 1749 * disabled. Try to make the plane enable atomic by writing 1750 * the control register just before the surface register. 1751 */ 1752 intel_de_write_fw(dev_priv, SPRCTL(pipe), sprctl); 1753 intel_de_write_fw(dev_priv, SPRSURF(pipe), 1754 intel_plane_ggtt_offset(plane_state) + sprsurf_offset); 1755 1756 ivb_update_gamma(plane_state); 1757 1758 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 1759 } 1760 1761 static void 1762 ivb_disable_plane(struct intel_plane *plane, 1763 const struct intel_crtc_state *crtc_state) 1764 { 1765 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1766 enum pipe pipe = plane->pipe; 1767 unsigned long irqflags; 1768 1769 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 1770 1771 intel_de_write_fw(dev_priv, SPRCTL(pipe), 0); 1772 /* Disable the scaler */ 1773 if (IS_IVYBRIDGE(dev_priv)) 1774 intel_de_write_fw(dev_priv, SPRSCALE(pipe), 0); 1775 intel_de_write_fw(dev_priv, SPRSURF(pipe), 0); 1776 1777 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 1778 } 1779 1780 static bool 1781 ivb_plane_get_hw_state(struct intel_plane *plane, 1782 enum pipe *pipe) 1783 { 1784 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1785 enum intel_display_power_domain power_domain; 1786 intel_wakeref_t wakeref; 1787 bool ret; 1788 1789 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 1790 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 1791 if (!wakeref) 1792 return false; 1793 1794 ret = intel_de_read(dev_priv, SPRCTL(plane->pipe)) & SPRITE_ENABLE; 1795 1796 *pipe = plane->pipe; 1797 1798 intel_display_power_put(dev_priv, power_domain, wakeref); 1799 1800 return ret; 1801 } 1802 1803 static int g4x_sprite_min_cdclk(const struct intel_crtc_state *crtc_state, 1804 const struct intel_plane_state *plane_state) 1805 { 1806 const struct drm_framebuffer *fb = plane_state->hw.fb; 1807 unsigned int hscale, pixel_rate; 1808 unsigned int limit, decimate; 1809 1810 /* 1811 * Note that crtc_state->pixel_rate accounts for both 1812 * horizontal and vertical panel fitter downscaling factors. 1813 * Pre-HSW bspec tells us to only consider the horizontal 1814 * downscaling factor here. We ignore that and just consider 1815 * both for simplicity. 1816 */ 1817 pixel_rate = crtc_state->pixel_rate; 1818 1819 /* Horizontal downscaling limits the maximum pixel rate */ 1820 hscale = drm_rect_calc_hscale(&plane_state->uapi.src, 1821 &plane_state->uapi.dst, 1822 0, INT_MAX); 1823 hscale = max(hscale, 0x10000u); 1824 1825 /* Decimation steps at 2x,4x,8x,16x */ 1826 decimate = ilog2(hscale >> 16); 1827 hscale >>= decimate; 1828 1829 /* Starting limit is 90% of cdclk */ 1830 limit = 9; 1831 1832 /* -10% per decimation step */ 1833 limit -= decimate; 1834 1835 /* -10% for RGB */ 1836 if (!fb->format->is_yuv) 1837 limit--; 1838 1839 /* 1840 * We should also do -10% if sprite scaling is enabled 1841 * on the other pipe, but we can't really check for that, 1842 * so we ignore it. 1843 */ 1844 1845 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, 10 * hscale), 1846 limit << 16); 1847 } 1848 1849 static unsigned int 1850 g4x_sprite_max_stride(struct intel_plane *plane, 1851 u32 pixel_format, u64 modifier, 1852 unsigned int rotation) 1853 { 1854 const struct drm_format_info *info = drm_format_info(pixel_format); 1855 int cpp = info->cpp[0]; 1856 1857 /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */ 1858 if (modifier == I915_FORMAT_MOD_X_TILED) 1859 return min(4096 * cpp, 16 * 1024); 1860 else 1861 return 16 * 1024; 1862 } 1863 1864 static unsigned int 1865 hsw_sprite_max_stride(struct intel_plane *plane, 1866 u32 pixel_format, u64 modifier, 1867 unsigned int rotation) 1868 { 1869 const struct drm_format_info *info = drm_format_info(pixel_format); 1870 int cpp = info->cpp[0]; 1871 1872 /* Limit to 8k pixels to guarantee OFFSET.x doesn't get too big. */ 1873 return min(8192 * cpp, 16 * 1024); 1874 } 1875 1876 static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) 1877 { 1878 u32 dvscntr = 0; 1879 1880 if (crtc_state->gamma_enable) 1881 dvscntr |= DVS_GAMMA_ENABLE; 1882 1883 if (crtc_state->csc_enable) 1884 dvscntr |= DVS_PIPE_CSC_ENABLE; 1885 1886 return dvscntr; 1887 } 1888 1889 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state, 1890 const struct intel_plane_state *plane_state) 1891 { 1892 struct drm_i915_private *dev_priv = 1893 to_i915(plane_state->uapi.plane->dev); 1894 const struct drm_framebuffer *fb = plane_state->hw.fb; 1895 unsigned int rotation = plane_state->hw.rotation; 1896 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1897 u32 dvscntr; 1898 1899 dvscntr = DVS_ENABLE; 1900 1901 if (IS_GEN(dev_priv, 6)) 1902 dvscntr |= DVS_TRICKLE_FEED_DISABLE; 1903 1904 switch (fb->format->format) { 1905 case DRM_FORMAT_XBGR8888: 1906 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; 1907 break; 1908 case DRM_FORMAT_XRGB8888: 1909 dvscntr |= DVS_FORMAT_RGBX888; 1910 break; 1911 case DRM_FORMAT_XBGR2101010: 1912 dvscntr |= DVS_FORMAT_RGBX101010 | DVS_RGB_ORDER_XBGR; 1913 break; 1914 case DRM_FORMAT_XRGB2101010: 1915 dvscntr |= DVS_FORMAT_RGBX101010; 1916 break; 1917 case DRM_FORMAT_XBGR16161616F: 1918 dvscntr |= DVS_FORMAT_RGBX161616 | DVS_RGB_ORDER_XBGR; 1919 break; 1920 case DRM_FORMAT_XRGB16161616F: 1921 dvscntr |= DVS_FORMAT_RGBX161616; 1922 break; 1923 case DRM_FORMAT_YUYV: 1924 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; 1925 break; 1926 case DRM_FORMAT_YVYU: 1927 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; 1928 break; 1929 case DRM_FORMAT_UYVY: 1930 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; 1931 break; 1932 case DRM_FORMAT_VYUY: 1933 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; 1934 break; 1935 default: 1936 MISSING_CASE(fb->format->format); 1937 return 0; 1938 } 1939 1940 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) 1941 dvscntr |= DVS_YUV_FORMAT_BT709; 1942 1943 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 1944 dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE; 1945 1946 if (fb->modifier == I915_FORMAT_MOD_X_TILED) 1947 dvscntr |= DVS_TILED; 1948 1949 if (rotation & DRM_MODE_ROTATE_180) 1950 dvscntr |= DVS_ROTATE_180; 1951 1952 if (key->flags & I915_SET_COLORKEY_DESTINATION) 1953 dvscntr |= DVS_DEST_KEY; 1954 else if (key->flags & I915_SET_COLORKEY_SOURCE) 1955 dvscntr |= DVS_SOURCE_KEY; 1956 1957 return dvscntr; 1958 } 1959 1960 static void g4x_update_gamma(const struct intel_plane_state *plane_state) 1961 { 1962 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1963 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1964 const struct drm_framebuffer *fb = plane_state->hw.fb; 1965 enum pipe pipe = plane->pipe; 1966 u16 gamma[8]; 1967 int i; 1968 1969 /* Seems RGB data bypasses the gamma always */ 1970 if (!fb->format->is_yuv) 1971 return; 1972 1973 i9xx_plane_linear_gamma(gamma); 1974 1975 /* FIXME these register are single buffered :( */ 1976 /* The two end points are implicit (0.0 and 1.0) */ 1977 for (i = 1; i < 8 - 1; i++) 1978 intel_de_write_fw(dev_priv, DVSGAMC_G4X(pipe, i - 1), 1979 gamma[i] << 16 | gamma[i] << 8 | gamma[i]); 1980 } 1981 1982 static void ilk_sprite_linear_gamma(u16 gamma[17]) 1983 { 1984 int i; 1985 1986 for (i = 0; i < 17; i++) 1987 gamma[i] = (i << 10) / 16; 1988 } 1989 1990 static void ilk_update_gamma(const struct intel_plane_state *plane_state) 1991 { 1992 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1993 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1994 const struct drm_framebuffer *fb = plane_state->hw.fb; 1995 enum pipe pipe = plane->pipe; 1996 u16 gamma[17]; 1997 int i; 1998 1999 /* Seems RGB data bypasses the gamma always */ 2000 if (!fb->format->is_yuv) 2001 return; 2002 2003 ilk_sprite_linear_gamma(gamma); 2004 2005 /* FIXME these register are single buffered :( */ 2006 for (i = 0; i < 16; i++) 2007 intel_de_write_fw(dev_priv, DVSGAMC_ILK(pipe, i), 2008 gamma[i] << 20 | gamma[i] << 10 | gamma[i]); 2009 2010 intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 0), gamma[i]); 2011 intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 1), gamma[i]); 2012 intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 2), gamma[i]); 2013 i++; 2014 } 2015 2016 static void 2017 g4x_update_plane(struct intel_plane *plane, 2018 const struct intel_crtc_state *crtc_state, 2019 const struct intel_plane_state *plane_state) 2020 { 2021 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 2022 enum pipe pipe = plane->pipe; 2023 u32 dvssurf_offset = plane_state->color_plane[0].offset; 2024 u32 linear_offset; 2025 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 2026 int crtc_x = plane_state->uapi.dst.x1; 2027 int crtc_y = plane_state->uapi.dst.y1; 2028 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 2029 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 2030 u32 x = plane_state->color_plane[0].x; 2031 u32 y = plane_state->color_plane[0].y; 2032 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 2033 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 2034 u32 dvscntr, dvsscale = 0; 2035 unsigned long irqflags; 2036 2037 dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state); 2038 2039 /* Sizes are 0 based */ 2040 src_w--; 2041 src_h--; 2042 crtc_w--; 2043 crtc_h--; 2044 2045 if (crtc_w != src_w || crtc_h != src_h) 2046 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; 2047 2048 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 2049 2050 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 2051 2052 intel_de_write_fw(dev_priv, DVSSTRIDE(pipe), 2053 plane_state->color_plane[0].stride); 2054 intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x); 2055 intel_de_write_fw(dev_priv, DVSSIZE(pipe), (crtc_h << 16) | crtc_w); 2056 intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale); 2057 2058 if (key->flags) { 2059 intel_de_write_fw(dev_priv, DVSKEYVAL(pipe), key->min_value); 2060 intel_de_write_fw(dev_priv, DVSKEYMSK(pipe), 2061 key->channel_mask); 2062 intel_de_write_fw(dev_priv, DVSKEYMAX(pipe), key->max_value); 2063 } 2064 2065 intel_de_write_fw(dev_priv, DVSLINOFF(pipe), linear_offset); 2066 intel_de_write_fw(dev_priv, DVSTILEOFF(pipe), (y << 16) | x); 2067 2068 /* 2069 * The control register self-arms if the plane was previously 2070 * disabled. Try to make the plane enable atomic by writing 2071 * the control register just before the surface register. 2072 */ 2073 intel_de_write_fw(dev_priv, DVSCNTR(pipe), dvscntr); 2074 intel_de_write_fw(dev_priv, DVSSURF(pipe), 2075 intel_plane_ggtt_offset(plane_state) + dvssurf_offset); 2076 2077 if (IS_G4X(dev_priv)) 2078 g4x_update_gamma(plane_state); 2079 else 2080 ilk_update_gamma(plane_state); 2081 2082 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 2083 } 2084 2085 static void 2086 g4x_disable_plane(struct intel_plane *plane, 2087 const struct intel_crtc_state *crtc_state) 2088 { 2089 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 2090 enum pipe pipe = plane->pipe; 2091 unsigned long irqflags; 2092 2093 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 2094 2095 intel_de_write_fw(dev_priv, DVSCNTR(pipe), 0); 2096 /* Disable the scaler */ 2097 intel_de_write_fw(dev_priv, DVSSCALE(pipe), 0); 2098 intel_de_write_fw(dev_priv, DVSSURF(pipe), 0); 2099 2100 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 2101 } 2102 2103 static bool 2104 g4x_plane_get_hw_state(struct intel_plane *plane, 2105 enum pipe *pipe) 2106 { 2107 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 2108 enum intel_display_power_domain power_domain; 2109 intel_wakeref_t wakeref; 2110 bool ret; 2111 2112 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 2113 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 2114 if (!wakeref) 2115 return false; 2116 2117 ret = intel_de_read(dev_priv, DVSCNTR(plane->pipe)) & DVS_ENABLE; 2118 2119 *pipe = plane->pipe; 2120 2121 intel_display_power_put(dev_priv, power_domain, wakeref); 2122 2123 return ret; 2124 } 2125 2126 static bool intel_fb_scalable(const struct drm_framebuffer *fb) 2127 { 2128 if (!fb) 2129 return false; 2130 2131 switch (fb->format->format) { 2132 case DRM_FORMAT_C8: 2133 return false; 2134 case DRM_FORMAT_XRGB16161616F: 2135 case DRM_FORMAT_ARGB16161616F: 2136 case DRM_FORMAT_XBGR16161616F: 2137 case DRM_FORMAT_ABGR16161616F: 2138 return INTEL_GEN(to_i915(fb->dev)) >= 11; 2139 default: 2140 return true; 2141 } 2142 } 2143 2144 static int 2145 g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state, 2146 struct intel_plane_state *plane_state) 2147 { 2148 const struct drm_framebuffer *fb = plane_state->hw.fb; 2149 const struct drm_rect *src = &plane_state->uapi.src; 2150 const struct drm_rect *dst = &plane_state->uapi.dst; 2151 int src_x, src_w, src_h, crtc_w, crtc_h; 2152 const struct drm_display_mode *adjusted_mode = 2153 &crtc_state->hw.adjusted_mode; 2154 unsigned int stride = plane_state->color_plane[0].stride; 2155 unsigned int cpp = fb->format->cpp[0]; 2156 unsigned int width_bytes; 2157 int min_width, min_height; 2158 2159 crtc_w = drm_rect_width(dst); 2160 crtc_h = drm_rect_height(dst); 2161 2162 src_x = src->x1 >> 16; 2163 src_w = drm_rect_width(src) >> 16; 2164 src_h = drm_rect_height(src) >> 16; 2165 2166 if (src_w == crtc_w && src_h == crtc_h) 2167 return 0; 2168 2169 min_width = 3; 2170 2171 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2172 if (src_h & 1) { 2173 DRM_DEBUG_KMS("Source height must be even with interlaced modes\n"); 2174 return -EINVAL; 2175 } 2176 min_height = 6; 2177 } else { 2178 min_height = 3; 2179 } 2180 2181 width_bytes = ((src_x * cpp) & 63) + src_w * cpp; 2182 2183 if (src_w < min_width || src_h < min_height || 2184 src_w > 2048 || src_h > 2048) { 2185 DRM_DEBUG_KMS("Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n", 2186 src_w, src_h, min_width, min_height, 2048, 2048); 2187 return -EINVAL; 2188 } 2189 2190 if (width_bytes > 4096) { 2191 DRM_DEBUG_KMS("Fetch width (%d) exceeds hardware max with scaling (%u)\n", 2192 width_bytes, 4096); 2193 return -EINVAL; 2194 } 2195 2196 if (stride > 4096) { 2197 DRM_DEBUG_KMS("Stride (%u) exceeds hardware max with scaling (%u)\n", 2198 stride, 4096); 2199 return -EINVAL; 2200 } 2201 2202 return 0; 2203 } 2204 2205 static int 2206 g4x_sprite_check(struct intel_crtc_state *crtc_state, 2207 struct intel_plane_state *plane_state) 2208 { 2209 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2210 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 2211 int min_scale = DRM_PLANE_HELPER_NO_SCALING; 2212 int max_scale = DRM_PLANE_HELPER_NO_SCALING; 2213 int ret; 2214 2215 if (intel_fb_scalable(plane_state->hw.fb)) { 2216 if (INTEL_GEN(dev_priv) < 7) { 2217 min_scale = 1; 2218 max_scale = 16 << 16; 2219 } else if (IS_IVYBRIDGE(dev_priv)) { 2220 min_scale = 1; 2221 max_scale = 2 << 16; 2222 } 2223 } 2224 2225 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 2226 min_scale, max_scale, true); 2227 if (ret) 2228 return ret; 2229 2230 ret = i9xx_check_plane_surface(plane_state); 2231 if (ret) 2232 return ret; 2233 2234 if (!plane_state->uapi.visible) 2235 return 0; 2236 2237 ret = intel_plane_check_src_coordinates(plane_state); 2238 if (ret) 2239 return ret; 2240 2241 ret = g4x_sprite_check_scaling(crtc_state, plane_state); 2242 if (ret) 2243 return ret; 2244 2245 if (INTEL_GEN(dev_priv) >= 7) 2246 plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state); 2247 else 2248 plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state); 2249 2250 return 0; 2251 } 2252 2253 int chv_plane_check_rotation(const struct intel_plane_state *plane_state) 2254 { 2255 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2256 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 2257 unsigned int rotation = plane_state->hw.rotation; 2258 2259 /* CHV ignores the mirror bit when the rotate bit is set :( */ 2260 if (IS_CHERRYVIEW(dev_priv) && 2261 rotation & DRM_MODE_ROTATE_180 && 2262 rotation & DRM_MODE_REFLECT_X) { 2263 drm_dbg_kms(&dev_priv->drm, 2264 "Cannot rotate and reflect at the same time\n"); 2265 return -EINVAL; 2266 } 2267 2268 return 0; 2269 } 2270 2271 static int 2272 vlv_sprite_check(struct intel_crtc_state *crtc_state, 2273 struct intel_plane_state *plane_state) 2274 { 2275 int ret; 2276 2277 ret = chv_plane_check_rotation(plane_state); 2278 if (ret) 2279 return ret; 2280 2281 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 2282 DRM_PLANE_HELPER_NO_SCALING, 2283 DRM_PLANE_HELPER_NO_SCALING, 2284 true); 2285 if (ret) 2286 return ret; 2287 2288 ret = i9xx_check_plane_surface(plane_state); 2289 if (ret) 2290 return ret; 2291 2292 if (!plane_state->uapi.visible) 2293 return 0; 2294 2295 ret = intel_plane_check_src_coordinates(plane_state); 2296 if (ret) 2297 return ret; 2298 2299 plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state); 2300 2301 return 0; 2302 } 2303 2304 static bool intel_format_is_p01x(u32 format) 2305 { 2306 switch (format) { 2307 case DRM_FORMAT_P010: 2308 case DRM_FORMAT_P012: 2309 case DRM_FORMAT_P016: 2310 return true; 2311 default: 2312 return false; 2313 } 2314 } 2315 2316 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, 2317 const struct intel_plane_state *plane_state) 2318 { 2319 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2320 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 2321 const struct drm_framebuffer *fb = plane_state->hw.fb; 2322 unsigned int rotation = plane_state->hw.rotation; 2323 struct drm_format_name_buf format_name; 2324 2325 if (!fb) 2326 return 0; 2327 2328 if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) && 2329 is_ccs_modifier(fb->modifier)) { 2330 drm_dbg_kms(&dev_priv->drm, 2331 "RC support only with 0/180 degree rotation (%x)\n", 2332 rotation); 2333 return -EINVAL; 2334 } 2335 2336 if (rotation & DRM_MODE_REFLECT_X && 2337 fb->modifier == DRM_FORMAT_MOD_LINEAR) { 2338 drm_dbg_kms(&dev_priv->drm, 2339 "horizontal flip is not supported with linear surface formats\n"); 2340 return -EINVAL; 2341 } 2342 2343 if (drm_rotation_90_or_270(rotation)) { 2344 if (fb->modifier != I915_FORMAT_MOD_Y_TILED && 2345 fb->modifier != I915_FORMAT_MOD_Yf_TILED) { 2346 drm_dbg_kms(&dev_priv->drm, 2347 "Y/Yf tiling required for 90/270!\n"); 2348 return -EINVAL; 2349 } 2350 2351 /* 2352 * 90/270 is not allowed with RGB64 16:16:16:16 and 2353 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards. 2354 */ 2355 switch (fb->format->format) { 2356 case DRM_FORMAT_RGB565: 2357 if (INTEL_GEN(dev_priv) >= 11) 2358 break; 2359 fallthrough; 2360 case DRM_FORMAT_C8: 2361 case DRM_FORMAT_XRGB16161616F: 2362 case DRM_FORMAT_XBGR16161616F: 2363 case DRM_FORMAT_ARGB16161616F: 2364 case DRM_FORMAT_ABGR16161616F: 2365 case DRM_FORMAT_Y210: 2366 case DRM_FORMAT_Y212: 2367 case DRM_FORMAT_Y216: 2368 case DRM_FORMAT_XVYU12_16161616: 2369 case DRM_FORMAT_XVYU16161616: 2370 drm_dbg_kms(&dev_priv->drm, 2371 "Unsupported pixel format %s for 90/270!\n", 2372 drm_get_format_name(fb->format->format, 2373 &format_name)); 2374 return -EINVAL; 2375 default: 2376 break; 2377 } 2378 } 2379 2380 /* Y-tiling is not supported in IF-ID Interlace mode */ 2381 if (crtc_state->hw.enable && 2382 crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE && 2383 (fb->modifier == I915_FORMAT_MOD_Y_TILED || 2384 fb->modifier == I915_FORMAT_MOD_Yf_TILED || 2385 fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || 2386 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS || 2387 fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || 2388 fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || 2389 fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) { 2390 drm_dbg_kms(&dev_priv->drm, 2391 "Y/Yf tiling not supported in IF-ID mode\n"); 2392 return -EINVAL; 2393 } 2394 2395 /* Wa_1606054188:tgl */ 2396 if (IS_TIGERLAKE(dev_priv) && 2397 plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE && 2398 intel_format_is_p01x(fb->format->format)) { 2399 drm_dbg_kms(&dev_priv->drm, 2400 "Source color keying not supported with P01x formats\n"); 2401 return -EINVAL; 2402 } 2403 2404 return 0; 2405 } 2406 2407 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state, 2408 const struct intel_plane_state *plane_state) 2409 { 2410 struct drm_i915_private *dev_priv = 2411 to_i915(plane_state->uapi.plane->dev); 2412 int crtc_x = plane_state->uapi.dst.x1; 2413 int crtc_w = drm_rect_width(&plane_state->uapi.dst); 2414 int pipe_src_w = crtc_state->pipe_src_w; 2415 2416 /* 2417 * Display WA #1175: cnl,glk 2418 * Planes other than the cursor may cause FIFO underflow and display 2419 * corruption if starting less than 4 pixels from the right edge of 2420 * the screen. 2421 * Besides the above WA fix the similar problem, where planes other 2422 * than the cursor ending less than 4 pixels from the left edge of the 2423 * screen may cause FIFO underflow and display corruption. 2424 */ 2425 if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) && 2426 (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) { 2427 drm_dbg_kms(&dev_priv->drm, 2428 "requested plane X %s position %d invalid (valid range %d-%d)\n", 2429 crtc_x + crtc_w < 4 ? "end" : "start", 2430 crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x, 2431 4, pipe_src_w - 4); 2432 return -ERANGE; 2433 } 2434 2435 return 0; 2436 } 2437 2438 static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state) 2439 { 2440 const struct drm_framebuffer *fb = plane_state->hw.fb; 2441 unsigned int rotation = plane_state->hw.rotation; 2442 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 2443 2444 /* Display WA #1106 */ 2445 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 2446 src_w & 3 && 2447 (rotation == DRM_MODE_ROTATE_270 || 2448 rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) { 2449 DRM_DEBUG_KMS("src width must be multiple of 4 for rotated planar YUV\n"); 2450 return -EINVAL; 2451 } 2452 2453 return 0; 2454 } 2455 2456 static int skl_plane_max_scale(struct drm_i915_private *dev_priv, 2457 const struct drm_framebuffer *fb) 2458 { 2459 /* 2460 * We don't yet know the final source width nor 2461 * whether we can use the HQ scaler mode. Assume 2462 * the best case. 2463 * FIXME need to properly check this later. 2464 */ 2465 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) || 2466 !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 2467 return 0x30000 - 1; 2468 else 2469 return 0x20000 - 1; 2470 } 2471 2472 static int skl_plane_check(struct intel_crtc_state *crtc_state, 2473 struct intel_plane_state *plane_state) 2474 { 2475 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2476 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 2477 const struct drm_framebuffer *fb = plane_state->hw.fb; 2478 int min_scale = DRM_PLANE_HELPER_NO_SCALING; 2479 int max_scale = DRM_PLANE_HELPER_NO_SCALING; 2480 int ret; 2481 2482 ret = skl_plane_check_fb(crtc_state, plane_state); 2483 if (ret) 2484 return ret; 2485 2486 /* use scaler when colorkey is not required */ 2487 if (!plane_state->ckey.flags && intel_fb_scalable(fb)) { 2488 min_scale = 1; 2489 max_scale = skl_plane_max_scale(dev_priv, fb); 2490 } 2491 2492 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 2493 min_scale, max_scale, true); 2494 if (ret) 2495 return ret; 2496 2497 ret = skl_check_plane_surface(plane_state); 2498 if (ret) 2499 return ret; 2500 2501 if (!plane_state->uapi.visible) 2502 return 0; 2503 2504 ret = skl_plane_check_dst_coordinates(crtc_state, plane_state); 2505 if (ret) 2506 return ret; 2507 2508 ret = intel_plane_check_src_coordinates(plane_state); 2509 if (ret) 2510 return ret; 2511 2512 ret = skl_plane_check_nv12_rotation(plane_state); 2513 if (ret) 2514 return ret; 2515 2516 /* HW only has 8 bits pixel precision, disable plane if invisible */ 2517 if (!(plane_state->hw.alpha >> 8)) 2518 plane_state->uapi.visible = false; 2519 2520 plane_state->ctl = skl_plane_ctl(crtc_state, plane_state); 2521 2522 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2523 plane_state->color_ctl = glk_plane_color_ctl(crtc_state, 2524 plane_state); 2525 2526 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 2527 icl_is_hdr_plane(dev_priv, plane->id)) 2528 /* Enable and use MPEG-2 chroma siting */ 2529 plane_state->cus_ctl = PLANE_CUS_ENABLE | 2530 PLANE_CUS_HPHASE_0 | 2531 PLANE_CUS_VPHASE_SIGN_NEGATIVE | PLANE_CUS_VPHASE_0_25; 2532 else 2533 plane_state->cus_ctl = 0; 2534 2535 return 0; 2536 } 2537 2538 static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv) 2539 { 2540 return INTEL_GEN(dev_priv) >= 9; 2541 } 2542 2543 static void intel_plane_set_ckey(struct intel_plane_state *plane_state, 2544 const struct drm_intel_sprite_colorkey *set) 2545 { 2546 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2547 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 2548 struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 2549 2550 *key = *set; 2551 2552 /* 2553 * We want src key enabled on the 2554 * sprite and not on the primary. 2555 */ 2556 if (plane->id == PLANE_PRIMARY && 2557 set->flags & I915_SET_COLORKEY_SOURCE) 2558 key->flags = 0; 2559 2560 /* 2561 * On SKL+ we want dst key enabled on 2562 * the primary and not on the sprite. 2563 */ 2564 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY && 2565 set->flags & I915_SET_COLORKEY_DESTINATION) 2566 key->flags = 0; 2567 } 2568 2569 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, 2570 struct drm_file *file_priv) 2571 { 2572 struct drm_i915_private *dev_priv = to_i915(dev); 2573 struct drm_intel_sprite_colorkey *set = data; 2574 struct drm_plane *plane; 2575 struct drm_plane_state *plane_state; 2576 struct drm_atomic_state *state; 2577 struct drm_modeset_acquire_ctx ctx; 2578 int ret = 0; 2579 2580 /* ignore the pointless "none" flag */ 2581 set->flags &= ~I915_SET_COLORKEY_NONE; 2582 2583 if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) 2584 return -EINVAL; 2585 2586 /* Make sure we don't try to enable both src & dest simultaneously */ 2587 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) 2588 return -EINVAL; 2589 2590 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2591 set->flags & I915_SET_COLORKEY_DESTINATION) 2592 return -EINVAL; 2593 2594 plane = drm_plane_find(dev, file_priv, set->plane_id); 2595 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) 2596 return -ENOENT; 2597 2598 /* 2599 * SKL+ only plane 2 can do destination keying against plane 1. 2600 * Also multiple planes can't do destination keying on the same 2601 * pipe simultaneously. 2602 */ 2603 if (INTEL_GEN(dev_priv) >= 9 && 2604 to_intel_plane(plane)->id >= PLANE_SPRITE1 && 2605 set->flags & I915_SET_COLORKEY_DESTINATION) 2606 return -EINVAL; 2607 2608 drm_modeset_acquire_init(&ctx, 0); 2609 2610 state = drm_atomic_state_alloc(plane->dev); 2611 if (!state) { 2612 ret = -ENOMEM; 2613 goto out; 2614 } 2615 state->acquire_ctx = &ctx; 2616 2617 while (1) { 2618 plane_state = drm_atomic_get_plane_state(state, plane); 2619 ret = PTR_ERR_OR_ZERO(plane_state); 2620 if (!ret) 2621 intel_plane_set_ckey(to_intel_plane_state(plane_state), set); 2622 2623 /* 2624 * On some platforms we have to configure 2625 * the dst colorkey on the primary plane. 2626 */ 2627 if (!ret && has_dst_key_in_primary_plane(dev_priv)) { 2628 struct intel_crtc *crtc = 2629 intel_get_crtc_for_pipe(dev_priv, 2630 to_intel_plane(plane)->pipe); 2631 2632 plane_state = drm_atomic_get_plane_state(state, 2633 crtc->base.primary); 2634 ret = PTR_ERR_OR_ZERO(plane_state); 2635 if (!ret) 2636 intel_plane_set_ckey(to_intel_plane_state(plane_state), set); 2637 } 2638 2639 if (!ret) 2640 ret = drm_atomic_commit(state); 2641 2642 if (ret != -EDEADLK) 2643 break; 2644 2645 drm_atomic_state_clear(state); 2646 drm_modeset_backoff(&ctx); 2647 } 2648 2649 drm_atomic_state_put(state); 2650 out: 2651 drm_modeset_drop_locks(&ctx); 2652 drm_modeset_acquire_fini(&ctx); 2653 return ret; 2654 } 2655 2656 static const u32 g4x_plane_formats[] = { 2657 DRM_FORMAT_XRGB8888, 2658 DRM_FORMAT_YUYV, 2659 DRM_FORMAT_YVYU, 2660 DRM_FORMAT_UYVY, 2661 DRM_FORMAT_VYUY, 2662 }; 2663 2664 static const u64 i9xx_plane_format_modifiers[] = { 2665 I915_FORMAT_MOD_X_TILED, 2666 DRM_FORMAT_MOD_LINEAR, 2667 DRM_FORMAT_MOD_INVALID 2668 }; 2669 2670 static const u32 snb_plane_formats[] = { 2671 DRM_FORMAT_XRGB8888, 2672 DRM_FORMAT_XBGR8888, 2673 DRM_FORMAT_XRGB2101010, 2674 DRM_FORMAT_XBGR2101010, 2675 DRM_FORMAT_XRGB16161616F, 2676 DRM_FORMAT_XBGR16161616F, 2677 DRM_FORMAT_YUYV, 2678 DRM_FORMAT_YVYU, 2679 DRM_FORMAT_UYVY, 2680 DRM_FORMAT_VYUY, 2681 }; 2682 2683 static const u32 vlv_plane_formats[] = { 2684 DRM_FORMAT_C8, 2685 DRM_FORMAT_RGB565, 2686 DRM_FORMAT_XRGB8888, 2687 DRM_FORMAT_XBGR8888, 2688 DRM_FORMAT_ARGB8888, 2689 DRM_FORMAT_ABGR8888, 2690 DRM_FORMAT_XBGR2101010, 2691 DRM_FORMAT_ABGR2101010, 2692 DRM_FORMAT_YUYV, 2693 DRM_FORMAT_YVYU, 2694 DRM_FORMAT_UYVY, 2695 DRM_FORMAT_VYUY, 2696 }; 2697 2698 static const u32 chv_pipe_b_sprite_formats[] = { 2699 DRM_FORMAT_C8, 2700 DRM_FORMAT_RGB565, 2701 DRM_FORMAT_XRGB8888, 2702 DRM_FORMAT_XBGR8888, 2703 DRM_FORMAT_ARGB8888, 2704 DRM_FORMAT_ABGR8888, 2705 DRM_FORMAT_XRGB2101010, 2706 DRM_FORMAT_XBGR2101010, 2707 DRM_FORMAT_ARGB2101010, 2708 DRM_FORMAT_ABGR2101010, 2709 DRM_FORMAT_YUYV, 2710 DRM_FORMAT_YVYU, 2711 DRM_FORMAT_UYVY, 2712 DRM_FORMAT_VYUY, 2713 }; 2714 2715 static const u32 skl_plane_formats[] = { 2716 DRM_FORMAT_C8, 2717 DRM_FORMAT_RGB565, 2718 DRM_FORMAT_XRGB8888, 2719 DRM_FORMAT_XBGR8888, 2720 DRM_FORMAT_ARGB8888, 2721 DRM_FORMAT_ABGR8888, 2722 DRM_FORMAT_XRGB2101010, 2723 DRM_FORMAT_XBGR2101010, 2724 DRM_FORMAT_XRGB16161616F, 2725 DRM_FORMAT_XBGR16161616F, 2726 DRM_FORMAT_YUYV, 2727 DRM_FORMAT_YVYU, 2728 DRM_FORMAT_UYVY, 2729 DRM_FORMAT_VYUY, 2730 DRM_FORMAT_XYUV8888, 2731 }; 2732 2733 static const u32 skl_planar_formats[] = { 2734 DRM_FORMAT_C8, 2735 DRM_FORMAT_RGB565, 2736 DRM_FORMAT_XRGB8888, 2737 DRM_FORMAT_XBGR8888, 2738 DRM_FORMAT_ARGB8888, 2739 DRM_FORMAT_ABGR8888, 2740 DRM_FORMAT_XRGB2101010, 2741 DRM_FORMAT_XBGR2101010, 2742 DRM_FORMAT_XRGB16161616F, 2743 DRM_FORMAT_XBGR16161616F, 2744 DRM_FORMAT_YUYV, 2745 DRM_FORMAT_YVYU, 2746 DRM_FORMAT_UYVY, 2747 DRM_FORMAT_VYUY, 2748 DRM_FORMAT_NV12, 2749 DRM_FORMAT_XYUV8888, 2750 }; 2751 2752 static const u32 glk_planar_formats[] = { 2753 DRM_FORMAT_C8, 2754 DRM_FORMAT_RGB565, 2755 DRM_FORMAT_XRGB8888, 2756 DRM_FORMAT_XBGR8888, 2757 DRM_FORMAT_ARGB8888, 2758 DRM_FORMAT_ABGR8888, 2759 DRM_FORMAT_XRGB2101010, 2760 DRM_FORMAT_XBGR2101010, 2761 DRM_FORMAT_XRGB16161616F, 2762 DRM_FORMAT_XBGR16161616F, 2763 DRM_FORMAT_YUYV, 2764 DRM_FORMAT_YVYU, 2765 DRM_FORMAT_UYVY, 2766 DRM_FORMAT_VYUY, 2767 DRM_FORMAT_NV12, 2768 DRM_FORMAT_XYUV8888, 2769 DRM_FORMAT_P010, 2770 DRM_FORMAT_P012, 2771 DRM_FORMAT_P016, 2772 }; 2773 2774 static const u32 icl_sdr_y_plane_formats[] = { 2775 DRM_FORMAT_C8, 2776 DRM_FORMAT_RGB565, 2777 DRM_FORMAT_XRGB8888, 2778 DRM_FORMAT_XBGR8888, 2779 DRM_FORMAT_ARGB8888, 2780 DRM_FORMAT_ABGR8888, 2781 DRM_FORMAT_XRGB2101010, 2782 DRM_FORMAT_XBGR2101010, 2783 DRM_FORMAT_ARGB2101010, 2784 DRM_FORMAT_ABGR2101010, 2785 DRM_FORMAT_YUYV, 2786 DRM_FORMAT_YVYU, 2787 DRM_FORMAT_UYVY, 2788 DRM_FORMAT_VYUY, 2789 DRM_FORMAT_Y210, 2790 DRM_FORMAT_Y212, 2791 DRM_FORMAT_Y216, 2792 DRM_FORMAT_XYUV8888, 2793 DRM_FORMAT_XVYU2101010, 2794 DRM_FORMAT_XVYU12_16161616, 2795 DRM_FORMAT_XVYU16161616, 2796 }; 2797 2798 static const u32 icl_sdr_uv_plane_formats[] = { 2799 DRM_FORMAT_C8, 2800 DRM_FORMAT_RGB565, 2801 DRM_FORMAT_XRGB8888, 2802 DRM_FORMAT_XBGR8888, 2803 DRM_FORMAT_ARGB8888, 2804 DRM_FORMAT_ABGR8888, 2805 DRM_FORMAT_XRGB2101010, 2806 DRM_FORMAT_XBGR2101010, 2807 DRM_FORMAT_ARGB2101010, 2808 DRM_FORMAT_ABGR2101010, 2809 DRM_FORMAT_YUYV, 2810 DRM_FORMAT_YVYU, 2811 DRM_FORMAT_UYVY, 2812 DRM_FORMAT_VYUY, 2813 DRM_FORMAT_NV12, 2814 DRM_FORMAT_P010, 2815 DRM_FORMAT_P012, 2816 DRM_FORMAT_P016, 2817 DRM_FORMAT_Y210, 2818 DRM_FORMAT_Y212, 2819 DRM_FORMAT_Y216, 2820 DRM_FORMAT_XYUV8888, 2821 DRM_FORMAT_XVYU2101010, 2822 DRM_FORMAT_XVYU12_16161616, 2823 DRM_FORMAT_XVYU16161616, 2824 }; 2825 2826 static const u32 icl_hdr_plane_formats[] = { 2827 DRM_FORMAT_C8, 2828 DRM_FORMAT_RGB565, 2829 DRM_FORMAT_XRGB8888, 2830 DRM_FORMAT_XBGR8888, 2831 DRM_FORMAT_ARGB8888, 2832 DRM_FORMAT_ABGR8888, 2833 DRM_FORMAT_XRGB2101010, 2834 DRM_FORMAT_XBGR2101010, 2835 DRM_FORMAT_ARGB2101010, 2836 DRM_FORMAT_ABGR2101010, 2837 DRM_FORMAT_XRGB16161616F, 2838 DRM_FORMAT_XBGR16161616F, 2839 DRM_FORMAT_ARGB16161616F, 2840 DRM_FORMAT_ABGR16161616F, 2841 DRM_FORMAT_YUYV, 2842 DRM_FORMAT_YVYU, 2843 DRM_FORMAT_UYVY, 2844 DRM_FORMAT_VYUY, 2845 DRM_FORMAT_NV12, 2846 DRM_FORMAT_P010, 2847 DRM_FORMAT_P012, 2848 DRM_FORMAT_P016, 2849 DRM_FORMAT_Y210, 2850 DRM_FORMAT_Y212, 2851 DRM_FORMAT_Y216, 2852 DRM_FORMAT_XYUV8888, 2853 DRM_FORMAT_XVYU2101010, 2854 DRM_FORMAT_XVYU12_16161616, 2855 DRM_FORMAT_XVYU16161616, 2856 }; 2857 2858 static const u64 skl_plane_format_modifiers_noccs[] = { 2859 I915_FORMAT_MOD_Yf_TILED, 2860 I915_FORMAT_MOD_Y_TILED, 2861 I915_FORMAT_MOD_X_TILED, 2862 DRM_FORMAT_MOD_LINEAR, 2863 DRM_FORMAT_MOD_INVALID 2864 }; 2865 2866 static const u64 skl_plane_format_modifiers_ccs[] = { 2867 I915_FORMAT_MOD_Yf_TILED_CCS, 2868 I915_FORMAT_MOD_Y_TILED_CCS, 2869 I915_FORMAT_MOD_Yf_TILED, 2870 I915_FORMAT_MOD_Y_TILED, 2871 I915_FORMAT_MOD_X_TILED, 2872 DRM_FORMAT_MOD_LINEAR, 2873 DRM_FORMAT_MOD_INVALID 2874 }; 2875 2876 static const u64 gen12_plane_format_modifiers_mc_ccs[] = { 2877 I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, 2878 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, 2879 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, 2880 I915_FORMAT_MOD_Y_TILED, 2881 I915_FORMAT_MOD_X_TILED, 2882 DRM_FORMAT_MOD_LINEAR, 2883 DRM_FORMAT_MOD_INVALID 2884 }; 2885 2886 static const u64 gen12_plane_format_modifiers_rc_ccs[] = { 2887 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, 2888 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, 2889 I915_FORMAT_MOD_Y_TILED, 2890 I915_FORMAT_MOD_X_TILED, 2891 DRM_FORMAT_MOD_LINEAR, 2892 DRM_FORMAT_MOD_INVALID 2893 }; 2894 2895 static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane, 2896 u32 format, u64 modifier) 2897 { 2898 switch (modifier) { 2899 case DRM_FORMAT_MOD_LINEAR: 2900 case I915_FORMAT_MOD_X_TILED: 2901 break; 2902 default: 2903 return false; 2904 } 2905 2906 switch (format) { 2907 case DRM_FORMAT_XRGB8888: 2908 case DRM_FORMAT_YUYV: 2909 case DRM_FORMAT_YVYU: 2910 case DRM_FORMAT_UYVY: 2911 case DRM_FORMAT_VYUY: 2912 if (modifier == DRM_FORMAT_MOD_LINEAR || 2913 modifier == I915_FORMAT_MOD_X_TILED) 2914 return true; 2915 fallthrough; 2916 default: 2917 return false; 2918 } 2919 } 2920 2921 static bool snb_sprite_format_mod_supported(struct drm_plane *_plane, 2922 u32 format, u64 modifier) 2923 { 2924 switch (modifier) { 2925 case DRM_FORMAT_MOD_LINEAR: 2926 case I915_FORMAT_MOD_X_TILED: 2927 break; 2928 default: 2929 return false; 2930 } 2931 2932 switch (format) { 2933 case DRM_FORMAT_XRGB8888: 2934 case DRM_FORMAT_XBGR8888: 2935 case DRM_FORMAT_XRGB2101010: 2936 case DRM_FORMAT_XBGR2101010: 2937 case DRM_FORMAT_XRGB16161616F: 2938 case DRM_FORMAT_XBGR16161616F: 2939 case DRM_FORMAT_YUYV: 2940 case DRM_FORMAT_YVYU: 2941 case DRM_FORMAT_UYVY: 2942 case DRM_FORMAT_VYUY: 2943 if (modifier == DRM_FORMAT_MOD_LINEAR || 2944 modifier == I915_FORMAT_MOD_X_TILED) 2945 return true; 2946 fallthrough; 2947 default: 2948 return false; 2949 } 2950 } 2951 2952 static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane, 2953 u32 format, u64 modifier) 2954 { 2955 switch (modifier) { 2956 case DRM_FORMAT_MOD_LINEAR: 2957 case I915_FORMAT_MOD_X_TILED: 2958 break; 2959 default: 2960 return false; 2961 } 2962 2963 switch (format) { 2964 case DRM_FORMAT_C8: 2965 case DRM_FORMAT_RGB565: 2966 case DRM_FORMAT_ABGR8888: 2967 case DRM_FORMAT_ARGB8888: 2968 case DRM_FORMAT_XBGR8888: 2969 case DRM_FORMAT_XRGB8888: 2970 case DRM_FORMAT_XBGR2101010: 2971 case DRM_FORMAT_ABGR2101010: 2972 case DRM_FORMAT_XRGB2101010: 2973 case DRM_FORMAT_ARGB2101010: 2974 case DRM_FORMAT_YUYV: 2975 case DRM_FORMAT_YVYU: 2976 case DRM_FORMAT_UYVY: 2977 case DRM_FORMAT_VYUY: 2978 if (modifier == DRM_FORMAT_MOD_LINEAR || 2979 modifier == I915_FORMAT_MOD_X_TILED) 2980 return true; 2981 fallthrough; 2982 default: 2983 return false; 2984 } 2985 } 2986 2987 static bool skl_plane_format_mod_supported(struct drm_plane *_plane, 2988 u32 format, u64 modifier) 2989 { 2990 struct intel_plane *plane = to_intel_plane(_plane); 2991 2992 switch (modifier) { 2993 case DRM_FORMAT_MOD_LINEAR: 2994 case I915_FORMAT_MOD_X_TILED: 2995 case I915_FORMAT_MOD_Y_TILED: 2996 case I915_FORMAT_MOD_Yf_TILED: 2997 break; 2998 case I915_FORMAT_MOD_Y_TILED_CCS: 2999 case I915_FORMAT_MOD_Yf_TILED_CCS: 3000 if (!plane->has_ccs) 3001 return false; 3002 break; 3003 default: 3004 return false; 3005 } 3006 3007 switch (format) { 3008 case DRM_FORMAT_XRGB8888: 3009 case DRM_FORMAT_XBGR8888: 3010 case DRM_FORMAT_ARGB8888: 3011 case DRM_FORMAT_ABGR8888: 3012 if (is_ccs_modifier(modifier)) 3013 return true; 3014 fallthrough; 3015 case DRM_FORMAT_RGB565: 3016 case DRM_FORMAT_XRGB2101010: 3017 case DRM_FORMAT_XBGR2101010: 3018 case DRM_FORMAT_ARGB2101010: 3019 case DRM_FORMAT_ABGR2101010: 3020 case DRM_FORMAT_YUYV: 3021 case DRM_FORMAT_YVYU: 3022 case DRM_FORMAT_UYVY: 3023 case DRM_FORMAT_VYUY: 3024 case DRM_FORMAT_NV12: 3025 case DRM_FORMAT_XYUV8888: 3026 case DRM_FORMAT_P010: 3027 case DRM_FORMAT_P012: 3028 case DRM_FORMAT_P016: 3029 case DRM_FORMAT_XVYU2101010: 3030 if (modifier == I915_FORMAT_MOD_Yf_TILED) 3031 return true; 3032 fallthrough; 3033 case DRM_FORMAT_C8: 3034 case DRM_FORMAT_XBGR16161616F: 3035 case DRM_FORMAT_ABGR16161616F: 3036 case DRM_FORMAT_XRGB16161616F: 3037 case DRM_FORMAT_ARGB16161616F: 3038 case DRM_FORMAT_Y210: 3039 case DRM_FORMAT_Y212: 3040 case DRM_FORMAT_Y216: 3041 case DRM_FORMAT_XVYU12_16161616: 3042 case DRM_FORMAT_XVYU16161616: 3043 if (modifier == DRM_FORMAT_MOD_LINEAR || 3044 modifier == I915_FORMAT_MOD_X_TILED || 3045 modifier == I915_FORMAT_MOD_Y_TILED) 3046 return true; 3047 fallthrough; 3048 default: 3049 return false; 3050 } 3051 } 3052 3053 static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv, 3054 enum plane_id plane_id) 3055 { 3056 /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */ 3057 if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) || 3058 IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0)) 3059 return false; 3060 3061 return plane_id < PLANE_SPRITE4; 3062 } 3063 3064 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, 3065 u32 format, u64 modifier) 3066 { 3067 struct drm_i915_private *dev_priv = to_i915(_plane->dev); 3068 struct intel_plane *plane = to_intel_plane(_plane); 3069 3070 switch (modifier) { 3071 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 3072 if (!gen12_plane_supports_mc_ccs(dev_priv, plane->id)) 3073 return false; 3074 fallthrough; 3075 case DRM_FORMAT_MOD_LINEAR: 3076 case I915_FORMAT_MOD_X_TILED: 3077 case I915_FORMAT_MOD_Y_TILED: 3078 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: 3079 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: 3080 break; 3081 default: 3082 return false; 3083 } 3084 3085 switch (format) { 3086 case DRM_FORMAT_XRGB8888: 3087 case DRM_FORMAT_XBGR8888: 3088 case DRM_FORMAT_ARGB8888: 3089 case DRM_FORMAT_ABGR8888: 3090 if (is_ccs_modifier(modifier)) 3091 return true; 3092 fallthrough; 3093 case DRM_FORMAT_YUYV: 3094 case DRM_FORMAT_YVYU: 3095 case DRM_FORMAT_UYVY: 3096 case DRM_FORMAT_VYUY: 3097 case DRM_FORMAT_NV12: 3098 case DRM_FORMAT_XYUV8888: 3099 case DRM_FORMAT_P010: 3100 case DRM_FORMAT_P012: 3101 case DRM_FORMAT_P016: 3102 if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) 3103 return true; 3104 fallthrough; 3105 case DRM_FORMAT_RGB565: 3106 case DRM_FORMAT_XRGB2101010: 3107 case DRM_FORMAT_XBGR2101010: 3108 case DRM_FORMAT_ARGB2101010: 3109 case DRM_FORMAT_ABGR2101010: 3110 case DRM_FORMAT_XVYU2101010: 3111 case DRM_FORMAT_C8: 3112 case DRM_FORMAT_XBGR16161616F: 3113 case DRM_FORMAT_ABGR16161616F: 3114 case DRM_FORMAT_XRGB16161616F: 3115 case DRM_FORMAT_ARGB16161616F: 3116 case DRM_FORMAT_Y210: 3117 case DRM_FORMAT_Y212: 3118 case DRM_FORMAT_Y216: 3119 case DRM_FORMAT_XVYU12_16161616: 3120 case DRM_FORMAT_XVYU16161616: 3121 if (modifier == DRM_FORMAT_MOD_LINEAR || 3122 modifier == I915_FORMAT_MOD_X_TILED || 3123 modifier == I915_FORMAT_MOD_Y_TILED) 3124 return true; 3125 fallthrough; 3126 default: 3127 return false; 3128 } 3129 } 3130 3131 static const struct drm_plane_funcs g4x_sprite_funcs = { 3132 .update_plane = drm_atomic_helper_update_plane, 3133 .disable_plane = drm_atomic_helper_disable_plane, 3134 .destroy = intel_plane_destroy, 3135 .atomic_duplicate_state = intel_plane_duplicate_state, 3136 .atomic_destroy_state = intel_plane_destroy_state, 3137 .format_mod_supported = g4x_sprite_format_mod_supported, 3138 }; 3139 3140 static const struct drm_plane_funcs snb_sprite_funcs = { 3141 .update_plane = drm_atomic_helper_update_plane, 3142 .disable_plane = drm_atomic_helper_disable_plane, 3143 .destroy = intel_plane_destroy, 3144 .atomic_duplicate_state = intel_plane_duplicate_state, 3145 .atomic_destroy_state = intel_plane_destroy_state, 3146 .format_mod_supported = snb_sprite_format_mod_supported, 3147 }; 3148 3149 static const struct drm_plane_funcs vlv_sprite_funcs = { 3150 .update_plane = drm_atomic_helper_update_plane, 3151 .disable_plane = drm_atomic_helper_disable_plane, 3152 .destroy = intel_plane_destroy, 3153 .atomic_duplicate_state = intel_plane_duplicate_state, 3154 .atomic_destroy_state = intel_plane_destroy_state, 3155 .format_mod_supported = vlv_sprite_format_mod_supported, 3156 }; 3157 3158 static const struct drm_plane_funcs skl_plane_funcs = { 3159 .update_plane = drm_atomic_helper_update_plane, 3160 .disable_plane = drm_atomic_helper_disable_plane, 3161 .destroy = intel_plane_destroy, 3162 .atomic_duplicate_state = intel_plane_duplicate_state, 3163 .atomic_destroy_state = intel_plane_destroy_state, 3164 .format_mod_supported = skl_plane_format_mod_supported, 3165 }; 3166 3167 static const struct drm_plane_funcs gen12_plane_funcs = { 3168 .update_plane = drm_atomic_helper_update_plane, 3169 .disable_plane = drm_atomic_helper_disable_plane, 3170 .destroy = intel_plane_destroy, 3171 .atomic_duplicate_state = intel_plane_duplicate_state, 3172 .atomic_destroy_state = intel_plane_destroy_state, 3173 .format_mod_supported = gen12_plane_format_mod_supported, 3174 }; 3175 3176 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv, 3177 enum pipe pipe, enum plane_id plane_id) 3178 { 3179 if (!HAS_FBC(dev_priv)) 3180 return false; 3181 3182 return pipe == PIPE_A && plane_id == PLANE_PRIMARY; 3183 } 3184 3185 static bool skl_plane_has_planar(struct drm_i915_private *dev_priv, 3186 enum pipe pipe, enum plane_id plane_id) 3187 { 3188 /* Display WA #0870: skl, bxt */ 3189 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) 3190 return false; 3191 3192 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C) 3193 return false; 3194 3195 if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0) 3196 return false; 3197 3198 return true; 3199 } 3200 3201 static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv, 3202 enum pipe pipe, enum plane_id plane_id, 3203 int *num_formats) 3204 { 3205 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { 3206 *num_formats = ARRAY_SIZE(skl_planar_formats); 3207 return skl_planar_formats; 3208 } else { 3209 *num_formats = ARRAY_SIZE(skl_plane_formats); 3210 return skl_plane_formats; 3211 } 3212 } 3213 3214 static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv, 3215 enum pipe pipe, enum plane_id plane_id, 3216 int *num_formats) 3217 { 3218 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { 3219 *num_formats = ARRAY_SIZE(glk_planar_formats); 3220 return glk_planar_formats; 3221 } else { 3222 *num_formats = ARRAY_SIZE(skl_plane_formats); 3223 return skl_plane_formats; 3224 } 3225 } 3226 3227 static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv, 3228 enum pipe pipe, enum plane_id plane_id, 3229 int *num_formats) 3230 { 3231 if (icl_is_hdr_plane(dev_priv, plane_id)) { 3232 *num_formats = ARRAY_SIZE(icl_hdr_plane_formats); 3233 return icl_hdr_plane_formats; 3234 } else if (icl_is_nv12_y_plane(dev_priv, plane_id)) { 3235 *num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats); 3236 return icl_sdr_y_plane_formats; 3237 } else { 3238 *num_formats = ARRAY_SIZE(icl_sdr_uv_plane_formats); 3239 return icl_sdr_uv_plane_formats; 3240 } 3241 } 3242 3243 static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv, 3244 enum plane_id plane_id) 3245 { 3246 if (gen12_plane_supports_mc_ccs(dev_priv, plane_id)) 3247 return gen12_plane_format_modifiers_mc_ccs; 3248 else 3249 return gen12_plane_format_modifiers_rc_ccs; 3250 } 3251 3252 static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv, 3253 enum pipe pipe, enum plane_id plane_id) 3254 { 3255 if (plane_id == PLANE_CURSOR) 3256 return false; 3257 3258 if (INTEL_GEN(dev_priv) >= 10) 3259 return true; 3260 3261 if (IS_GEMINILAKE(dev_priv)) 3262 return pipe != PIPE_C; 3263 3264 return pipe != PIPE_C && 3265 (plane_id == PLANE_PRIMARY || 3266 plane_id == PLANE_SPRITE0); 3267 } 3268 3269 struct intel_plane * 3270 skl_universal_plane_create(struct drm_i915_private *dev_priv, 3271 enum pipe pipe, enum plane_id plane_id) 3272 { 3273 const struct drm_plane_funcs *plane_funcs; 3274 struct intel_plane *plane; 3275 enum drm_plane_type plane_type; 3276 unsigned int supported_rotations; 3277 unsigned int supported_csc; 3278 const u64 *modifiers; 3279 const u32 *formats; 3280 int num_formats; 3281 int ret; 3282 3283 plane = intel_plane_alloc(); 3284 if (IS_ERR(plane)) 3285 return plane; 3286 3287 plane->pipe = pipe; 3288 plane->id = plane_id; 3289 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id); 3290 3291 plane->has_fbc = skl_plane_has_fbc(dev_priv, pipe, plane_id); 3292 if (plane->has_fbc) { 3293 struct intel_fbc *fbc = &dev_priv->fbc; 3294 3295 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit; 3296 } 3297 3298 if (INTEL_GEN(dev_priv) >= 11) { 3299 plane->min_width = icl_plane_min_width; 3300 plane->max_width = icl_plane_max_width; 3301 plane->max_height = icl_plane_max_height; 3302 } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { 3303 plane->max_width = glk_plane_max_width; 3304 plane->max_height = skl_plane_max_height; 3305 } else { 3306 plane->max_width = skl_plane_max_width; 3307 plane->max_height = skl_plane_max_height; 3308 } 3309 3310 plane->max_stride = skl_plane_max_stride; 3311 plane->update_plane = skl_update_plane; 3312 plane->disable_plane = skl_disable_plane; 3313 plane->get_hw_state = skl_plane_get_hw_state; 3314 plane->check_plane = skl_plane_check; 3315 plane->min_cdclk = skl_plane_min_cdclk; 3316 3317 if (plane_id == PLANE_PRIMARY) { 3318 plane->need_async_flip_disable_wa = IS_GEN_RANGE(dev_priv, 9, 10); 3319 plane->async_flip = skl_plane_async_flip; 3320 plane->enable_flip_done = skl_plane_enable_flip_done; 3321 plane->disable_flip_done = skl_plane_disable_flip_done; 3322 } 3323 3324 if (INTEL_GEN(dev_priv) >= 11) 3325 formats = icl_get_plane_formats(dev_priv, pipe, 3326 plane_id, &num_formats); 3327 else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 3328 formats = glk_get_plane_formats(dev_priv, pipe, 3329 plane_id, &num_formats); 3330 else 3331 formats = skl_get_plane_formats(dev_priv, pipe, 3332 plane_id, &num_formats); 3333 3334 plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id); 3335 if (INTEL_GEN(dev_priv) >= 12) { 3336 modifiers = gen12_get_plane_modifiers(dev_priv, plane_id); 3337 plane_funcs = &gen12_plane_funcs; 3338 } else { 3339 if (plane->has_ccs) 3340 modifiers = skl_plane_format_modifiers_ccs; 3341 else 3342 modifiers = skl_plane_format_modifiers_noccs; 3343 plane_funcs = &skl_plane_funcs; 3344 } 3345 3346 if (plane_id == PLANE_PRIMARY) 3347 plane_type = DRM_PLANE_TYPE_PRIMARY; 3348 else 3349 plane_type = DRM_PLANE_TYPE_OVERLAY; 3350 3351 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 3352 0, plane_funcs, 3353 formats, num_formats, modifiers, 3354 plane_type, 3355 "plane %d%c", plane_id + 1, 3356 pipe_name(pipe)); 3357 if (ret) 3358 goto fail; 3359 3360 supported_rotations = 3361 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | 3362 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; 3363 3364 if (INTEL_GEN(dev_priv) >= 10) 3365 supported_rotations |= DRM_MODE_REFLECT_X; 3366 3367 drm_plane_create_rotation_property(&plane->base, 3368 DRM_MODE_ROTATE_0, 3369 supported_rotations); 3370 3371 supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709); 3372 3373 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 3374 supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020); 3375 3376 drm_plane_create_color_properties(&plane->base, 3377 supported_csc, 3378 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 3379 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 3380 DRM_COLOR_YCBCR_BT709, 3381 DRM_COLOR_YCBCR_LIMITED_RANGE); 3382 3383 drm_plane_create_alpha_property(&plane->base); 3384 drm_plane_create_blend_mode_property(&plane->base, 3385 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 3386 BIT(DRM_MODE_BLEND_PREMULTI) | 3387 BIT(DRM_MODE_BLEND_COVERAGE)); 3388 3389 drm_plane_create_zpos_immutable_property(&plane->base, plane_id); 3390 3391 if (INTEL_GEN(dev_priv) >= 12) 3392 drm_plane_enable_fb_damage_clips(&plane->base); 3393 3394 if (INTEL_GEN(dev_priv) >= 10) 3395 drm_plane_create_scaling_filter_property(&plane->base, 3396 BIT(DRM_SCALING_FILTER_DEFAULT) | 3397 BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR)); 3398 3399 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); 3400 3401 return plane; 3402 3403 fail: 3404 intel_plane_free(plane); 3405 3406 return ERR_PTR(ret); 3407 } 3408 3409 struct intel_plane * 3410 intel_sprite_plane_create(struct drm_i915_private *dev_priv, 3411 enum pipe pipe, int sprite) 3412 { 3413 struct intel_plane *plane; 3414 const struct drm_plane_funcs *plane_funcs; 3415 unsigned int supported_rotations; 3416 const u64 *modifiers; 3417 const u32 *formats; 3418 int num_formats; 3419 int ret, zpos; 3420 3421 if (INTEL_GEN(dev_priv) >= 9) 3422 return skl_universal_plane_create(dev_priv, pipe, 3423 PLANE_SPRITE0 + sprite); 3424 3425 plane = intel_plane_alloc(); 3426 if (IS_ERR(plane)) 3427 return plane; 3428 3429 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 3430 plane->update_plane = vlv_update_plane; 3431 plane->disable_plane = vlv_disable_plane; 3432 plane->get_hw_state = vlv_plane_get_hw_state; 3433 plane->check_plane = vlv_sprite_check; 3434 plane->max_stride = i965_plane_max_stride; 3435 plane->min_cdclk = vlv_plane_min_cdclk; 3436 3437 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 3438 formats = chv_pipe_b_sprite_formats; 3439 num_formats = ARRAY_SIZE(chv_pipe_b_sprite_formats); 3440 } else { 3441 formats = vlv_plane_formats; 3442 num_formats = ARRAY_SIZE(vlv_plane_formats); 3443 } 3444 modifiers = i9xx_plane_format_modifiers; 3445 3446 plane_funcs = &vlv_sprite_funcs; 3447 } else if (INTEL_GEN(dev_priv) >= 7) { 3448 plane->update_plane = ivb_update_plane; 3449 plane->disable_plane = ivb_disable_plane; 3450 plane->get_hw_state = ivb_plane_get_hw_state; 3451 plane->check_plane = g4x_sprite_check; 3452 3453 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 3454 plane->max_stride = hsw_sprite_max_stride; 3455 plane->min_cdclk = hsw_plane_min_cdclk; 3456 } else { 3457 plane->max_stride = g4x_sprite_max_stride; 3458 plane->min_cdclk = ivb_sprite_min_cdclk; 3459 } 3460 3461 formats = snb_plane_formats; 3462 num_formats = ARRAY_SIZE(snb_plane_formats); 3463 modifiers = i9xx_plane_format_modifiers; 3464 3465 plane_funcs = &snb_sprite_funcs; 3466 } else { 3467 plane->update_plane = g4x_update_plane; 3468 plane->disable_plane = g4x_disable_plane; 3469 plane->get_hw_state = g4x_plane_get_hw_state; 3470 plane->check_plane = g4x_sprite_check; 3471 plane->max_stride = g4x_sprite_max_stride; 3472 plane->min_cdclk = g4x_sprite_min_cdclk; 3473 3474 modifiers = i9xx_plane_format_modifiers; 3475 if (IS_GEN(dev_priv, 6)) { 3476 formats = snb_plane_formats; 3477 num_formats = ARRAY_SIZE(snb_plane_formats); 3478 3479 plane_funcs = &snb_sprite_funcs; 3480 } else { 3481 formats = g4x_plane_formats; 3482 num_formats = ARRAY_SIZE(g4x_plane_formats); 3483 3484 plane_funcs = &g4x_sprite_funcs; 3485 } 3486 } 3487 3488 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 3489 supported_rotations = 3490 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | 3491 DRM_MODE_REFLECT_X; 3492 } else { 3493 supported_rotations = 3494 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 3495 } 3496 3497 plane->pipe = pipe; 3498 plane->id = PLANE_SPRITE0 + sprite; 3499 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); 3500 3501 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 3502 0, plane_funcs, 3503 formats, num_formats, modifiers, 3504 DRM_PLANE_TYPE_OVERLAY, 3505 "sprite %c", sprite_name(pipe, sprite)); 3506 if (ret) 3507 goto fail; 3508 3509 drm_plane_create_rotation_property(&plane->base, 3510 DRM_MODE_ROTATE_0, 3511 supported_rotations); 3512 3513 drm_plane_create_color_properties(&plane->base, 3514 BIT(DRM_COLOR_YCBCR_BT601) | 3515 BIT(DRM_COLOR_YCBCR_BT709), 3516 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 3517 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 3518 DRM_COLOR_YCBCR_BT709, 3519 DRM_COLOR_YCBCR_LIMITED_RANGE); 3520 3521 zpos = sprite + 1; 3522 drm_plane_create_zpos_immutable_property(&plane->base, zpos); 3523 3524 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); 3525 3526 return plane; 3527 3528 fail: 3529 intel_plane_free(plane); 3530 3531 return ERR_PTR(ret); 3532 } 3533