1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/export.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 34 #include <drm/display/drm_hdmi_helper.h> 35 #include <drm/drm_atomic_helper.h> 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_edid.h> 38 39 #include "i915_drv.h" 40 #include "intel_atomic.h" 41 #include "intel_connector.h" 42 #include "intel_crtc.h" 43 #include "intel_de.h" 44 #include "intel_display_types.h" 45 #include "intel_fifo_underrun.h" 46 #include "intel_gmbus.h" 47 #include "intel_hdmi.h" 48 #include "intel_hotplug.h" 49 #include "intel_panel.h" 50 #include "intel_sdvo.h" 51 #include "intel_sdvo_regs.h" 52 53 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 54 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 55 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 56 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) 57 58 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ 59 SDVO_TV_MASK) 60 61 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 62 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) 63 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 64 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 65 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) 66 67 68 static const char * const tv_format_names[] = { 69 "NTSC_M" , "NTSC_J" , "NTSC_443", 70 "PAL_B" , "PAL_D" , "PAL_G" , 71 "PAL_H" , "PAL_I" , "PAL_M" , 72 "PAL_N" , "PAL_NC" , "PAL_60" , 73 "SECAM_B" , "SECAM_D" , "SECAM_G" , 74 "SECAM_K" , "SECAM_K1", "SECAM_L" , 75 "SECAM_60" 76 }; 77 78 #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names) 79 80 struct intel_sdvo { 81 struct intel_encoder base; 82 83 struct i2c_adapter *i2c; 84 u8 slave_addr; 85 86 struct i2c_adapter ddc; 87 88 /* Register for the SDVO device: SDVOB or SDVOC */ 89 i915_reg_t sdvo_reg; 90 91 /* Active outputs controlled by this SDVO output */ 92 u16 controlled_output; 93 94 /* 95 * Capabilities of the SDVO device returned by 96 * intel_sdvo_get_capabilities() 97 */ 98 struct intel_sdvo_caps caps; 99 100 u8 colorimetry_cap; 101 102 /* Pixel clock limitations reported by the SDVO device, in kHz */ 103 int pixel_clock_min, pixel_clock_max; 104 105 /* 106 * For multiple function SDVO device, 107 * this is for current attached outputs. 108 */ 109 u16 attached_output; 110 111 /* 112 * Hotplug activation bits for this device 113 */ 114 u16 hotplug_active; 115 116 enum port port; 117 118 bool has_hdmi_monitor; 119 bool has_hdmi_audio; 120 121 /* DDC bus used by this SDVO encoder */ 122 u8 ddc_bus; 123 124 /* 125 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd 126 */ 127 u8 dtd_sdvo_flags; 128 }; 129 130 struct intel_sdvo_connector { 131 struct intel_connector base; 132 133 /* Mark the type of connector */ 134 u16 output_flag; 135 136 /* This contains all current supported TV format */ 137 u8 tv_format_supported[TV_FORMAT_NUM]; 138 int format_supported_num; 139 struct drm_property *tv_format; 140 141 /* add the property for the SDVO-TV */ 142 struct drm_property *left; 143 struct drm_property *right; 144 struct drm_property *top; 145 struct drm_property *bottom; 146 struct drm_property *hpos; 147 struct drm_property *vpos; 148 struct drm_property *contrast; 149 struct drm_property *saturation; 150 struct drm_property *hue; 151 struct drm_property *sharpness; 152 struct drm_property *flicker_filter; 153 struct drm_property *flicker_filter_adaptive; 154 struct drm_property *flicker_filter_2d; 155 struct drm_property *tv_chroma_filter; 156 struct drm_property *tv_luma_filter; 157 struct drm_property *dot_crawl; 158 159 /* add the property for the SDVO-TV/LVDS */ 160 struct drm_property *brightness; 161 162 /* this is to get the range of margin.*/ 163 u32 max_hscan, max_vscan; 164 165 /** 166 * This is set if we treat the device as HDMI, instead of DVI. 167 */ 168 bool is_hdmi; 169 }; 170 171 struct intel_sdvo_connector_state { 172 /* base.base: tv.saturation/contrast/hue/brightness */ 173 struct intel_digital_connector_state base; 174 175 struct { 176 unsigned overscan_h, overscan_v, hpos, vpos, sharpness; 177 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive; 178 unsigned chroma_filter, luma_filter, dot_crawl; 179 } tv; 180 }; 181 182 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) 183 { 184 return container_of(encoder, struct intel_sdvo, base); 185 } 186 187 static struct intel_sdvo *intel_attached_sdvo(struct intel_connector *connector) 188 { 189 return to_sdvo(intel_attached_encoder(connector)); 190 } 191 192 static struct intel_sdvo_connector * 193 to_intel_sdvo_connector(struct drm_connector *connector) 194 { 195 return container_of(connector, struct intel_sdvo_connector, base.base); 196 } 197 198 #define to_intel_sdvo_connector_state(conn_state) \ 199 container_of((conn_state), struct intel_sdvo_connector_state, base.base) 200 201 static bool 202 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo); 203 static bool 204 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 205 struct intel_sdvo_connector *intel_sdvo_connector, 206 int type); 207 static bool 208 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 209 struct intel_sdvo_connector *intel_sdvo_connector); 210 211 /* 212 * Writes the SDVOB or SDVOC with the given value, but always writes both 213 * SDVOB and SDVOC to work around apparent hardware issues (according to 214 * comments in the BIOS). 215 */ 216 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 217 { 218 struct drm_device *dev = intel_sdvo->base.base.dev; 219 struct drm_i915_private *dev_priv = to_i915(dev); 220 u32 bval = val, cval = val; 221 int i; 222 223 if (HAS_PCH_SPLIT(dev_priv)) { 224 intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val); 225 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); 226 /* 227 * HW workaround, need to write this twice for issue 228 * that may result in first write getting masked. 229 */ 230 if (HAS_PCH_IBX(dev_priv)) { 231 intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val); 232 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); 233 } 234 return; 235 } 236 237 if (intel_sdvo->port == PORT_B) 238 cval = intel_de_read(dev_priv, GEN3_SDVOC); 239 else 240 bval = intel_de_read(dev_priv, GEN3_SDVOB); 241 242 /* 243 * Write the registers twice for luck. Sometimes, 244 * writing them only once doesn't appear to 'stick'. 245 * The BIOS does this too. Yay, magic 246 */ 247 for (i = 0; i < 2; i++) { 248 intel_de_write(dev_priv, GEN3_SDVOB, bval); 249 intel_de_posting_read(dev_priv, GEN3_SDVOB); 250 251 intel_de_write(dev_priv, GEN3_SDVOC, cval); 252 intel_de_posting_read(dev_priv, GEN3_SDVOC); 253 } 254 } 255 256 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 257 { 258 struct i2c_msg msgs[] = { 259 { 260 .addr = intel_sdvo->slave_addr, 261 .flags = 0, 262 .len = 1, 263 .buf = &addr, 264 }, 265 { 266 .addr = intel_sdvo->slave_addr, 267 .flags = I2C_M_RD, 268 .len = 1, 269 .buf = ch, 270 } 271 }; 272 int ret; 273 274 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) 275 return true; 276 277 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); 278 return false; 279 } 280 281 #define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ } 282 283 /** Mapping of command numbers to names, for debug output */ 284 static const struct { 285 u8 cmd; 286 const char *name; 287 } __packed sdvo_cmd_names[] = { 288 SDVO_CMD_NAME_ENTRY(RESET), 289 SDVO_CMD_NAME_ENTRY(GET_DEVICE_CAPS), 290 SDVO_CMD_NAME_ENTRY(GET_FIRMWARE_REV), 291 SDVO_CMD_NAME_ENTRY(GET_TRAINED_INPUTS), 292 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_OUTPUTS), 293 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_OUTPUTS), 294 SDVO_CMD_NAME_ENTRY(GET_IN_OUT_MAP), 295 SDVO_CMD_NAME_ENTRY(SET_IN_OUT_MAP), 296 SDVO_CMD_NAME_ENTRY(GET_ATTACHED_DISPLAYS), 297 SDVO_CMD_NAME_ENTRY(GET_HOT_PLUG_SUPPORT), 298 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_HOT_PLUG), 299 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_HOT_PLUG), 300 SDVO_CMD_NAME_ENTRY(GET_INTERRUPT_EVENT_SOURCE), 301 SDVO_CMD_NAME_ENTRY(SET_TARGET_INPUT), 302 SDVO_CMD_NAME_ENTRY(SET_TARGET_OUTPUT), 303 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART1), 304 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART2), 305 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART1), 306 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART2), 307 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART1), 308 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART2), 309 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART1), 310 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART2), 311 SDVO_CMD_NAME_ENTRY(CREATE_PREFERRED_INPUT_TIMING), 312 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART1), 313 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART2), 314 SDVO_CMD_NAME_ENTRY(GET_INPUT_PIXEL_CLOCK_RANGE), 315 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_PIXEL_CLOCK_RANGE), 316 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_CLOCK_RATE_MULTS), 317 SDVO_CMD_NAME_ENTRY(GET_CLOCK_RATE_MULT), 318 SDVO_CMD_NAME_ENTRY(SET_CLOCK_RATE_MULT), 319 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_TV_FORMATS), 320 SDVO_CMD_NAME_ENTRY(GET_TV_FORMAT), 321 SDVO_CMD_NAME_ENTRY(SET_TV_FORMAT), 322 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_POWER_STATES), 323 SDVO_CMD_NAME_ENTRY(GET_POWER_STATE), 324 SDVO_CMD_NAME_ENTRY(SET_ENCODER_POWER_STATE), 325 SDVO_CMD_NAME_ENTRY(SET_DISPLAY_POWER_STATE), 326 SDVO_CMD_NAME_ENTRY(SET_CONTROL_BUS_SWITCH), 327 SDVO_CMD_NAME_ENTRY(GET_SDTV_RESOLUTION_SUPPORT), 328 SDVO_CMD_NAME_ENTRY(GET_SCALED_HDTV_RESOLUTION_SUPPORT), 329 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_ENHANCEMENTS), 330 331 /* Add the op code for SDVO enhancements */ 332 SDVO_CMD_NAME_ENTRY(GET_MAX_HPOS), 333 SDVO_CMD_NAME_ENTRY(GET_HPOS), 334 SDVO_CMD_NAME_ENTRY(SET_HPOS), 335 SDVO_CMD_NAME_ENTRY(GET_MAX_VPOS), 336 SDVO_CMD_NAME_ENTRY(GET_VPOS), 337 SDVO_CMD_NAME_ENTRY(SET_VPOS), 338 SDVO_CMD_NAME_ENTRY(GET_MAX_SATURATION), 339 SDVO_CMD_NAME_ENTRY(GET_SATURATION), 340 SDVO_CMD_NAME_ENTRY(SET_SATURATION), 341 SDVO_CMD_NAME_ENTRY(GET_MAX_HUE), 342 SDVO_CMD_NAME_ENTRY(GET_HUE), 343 SDVO_CMD_NAME_ENTRY(SET_HUE), 344 SDVO_CMD_NAME_ENTRY(GET_MAX_CONTRAST), 345 SDVO_CMD_NAME_ENTRY(GET_CONTRAST), 346 SDVO_CMD_NAME_ENTRY(SET_CONTRAST), 347 SDVO_CMD_NAME_ENTRY(GET_MAX_BRIGHTNESS), 348 SDVO_CMD_NAME_ENTRY(GET_BRIGHTNESS), 349 SDVO_CMD_NAME_ENTRY(SET_BRIGHTNESS), 350 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_H), 351 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_H), 352 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_H), 353 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_V), 354 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_V), 355 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_V), 356 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER), 357 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER), 358 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER), 359 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_ADAPTIVE), 360 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_ADAPTIVE), 361 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_ADAPTIVE), 362 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_2D), 363 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_2D), 364 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_2D), 365 SDVO_CMD_NAME_ENTRY(GET_MAX_SHARPNESS), 366 SDVO_CMD_NAME_ENTRY(GET_SHARPNESS), 367 SDVO_CMD_NAME_ENTRY(SET_SHARPNESS), 368 SDVO_CMD_NAME_ENTRY(GET_DOT_CRAWL), 369 SDVO_CMD_NAME_ENTRY(SET_DOT_CRAWL), 370 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_CHROMA_FILTER), 371 SDVO_CMD_NAME_ENTRY(GET_TV_CHROMA_FILTER), 372 SDVO_CMD_NAME_ENTRY(SET_TV_CHROMA_FILTER), 373 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_LUMA_FILTER), 374 SDVO_CMD_NAME_ENTRY(GET_TV_LUMA_FILTER), 375 SDVO_CMD_NAME_ENTRY(SET_TV_LUMA_FILTER), 376 377 /* HDMI op code */ 378 SDVO_CMD_NAME_ENTRY(GET_SUPP_ENCODE), 379 SDVO_CMD_NAME_ENTRY(GET_ENCODE), 380 SDVO_CMD_NAME_ENTRY(SET_ENCODE), 381 SDVO_CMD_NAME_ENTRY(SET_PIXEL_REPLI), 382 SDVO_CMD_NAME_ENTRY(GET_PIXEL_REPLI), 383 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY_CAP), 384 SDVO_CMD_NAME_ENTRY(SET_COLORIMETRY), 385 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY), 386 SDVO_CMD_NAME_ENTRY(GET_AUDIO_ENCRYPT_PREFER), 387 SDVO_CMD_NAME_ENTRY(SET_AUDIO_STAT), 388 SDVO_CMD_NAME_ENTRY(GET_AUDIO_STAT), 389 SDVO_CMD_NAME_ENTRY(GET_HBUF_INDEX), 390 SDVO_CMD_NAME_ENTRY(SET_HBUF_INDEX), 391 SDVO_CMD_NAME_ENTRY(GET_HBUF_INFO), 392 SDVO_CMD_NAME_ENTRY(GET_HBUF_AV_SPLIT), 393 SDVO_CMD_NAME_ENTRY(SET_HBUF_AV_SPLIT), 394 SDVO_CMD_NAME_ENTRY(GET_HBUF_TXRATE), 395 SDVO_CMD_NAME_ENTRY(SET_HBUF_TXRATE), 396 SDVO_CMD_NAME_ENTRY(SET_HBUF_DATA), 397 SDVO_CMD_NAME_ENTRY(GET_HBUF_DATA), 398 }; 399 400 #undef SDVO_CMD_NAME_ENTRY 401 402 static const char *sdvo_cmd_name(u8 cmd) 403 { 404 int i; 405 406 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 407 if (cmd == sdvo_cmd_names[i].cmd) 408 return sdvo_cmd_names[i].name; 409 } 410 411 return NULL; 412 } 413 414 #define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC") 415 416 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 417 const void *args, int args_len) 418 { 419 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 420 const char *cmd_name; 421 int i, pos = 0; 422 char buffer[64]; 423 424 #define BUF_PRINT(args...) \ 425 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) 426 427 for (i = 0; i < args_len; i++) { 428 BUF_PRINT("%02X ", ((u8 *)args)[i]); 429 } 430 for (; i < 8; i++) { 431 BUF_PRINT(" "); 432 } 433 434 cmd_name = sdvo_cmd_name(cmd); 435 if (cmd_name) 436 BUF_PRINT("(%s)", cmd_name); 437 else 438 BUF_PRINT("(%02X)", cmd); 439 440 drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1); 441 #undef BUF_PRINT 442 443 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); 444 } 445 446 static const char * const cmd_status_names[] = { 447 [SDVO_CMD_STATUS_POWER_ON] = "Power on", 448 [SDVO_CMD_STATUS_SUCCESS] = "Success", 449 [SDVO_CMD_STATUS_NOTSUPP] = "Not supported", 450 [SDVO_CMD_STATUS_INVALID_ARG] = "Invalid arg", 451 [SDVO_CMD_STATUS_PENDING] = "Pending", 452 [SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED] = "Target not specified", 453 [SDVO_CMD_STATUS_SCALING_NOT_SUPP] = "Scaling not supported", 454 }; 455 456 static const char *sdvo_cmd_status(u8 status) 457 { 458 if (status < ARRAY_SIZE(cmd_status_names)) 459 return cmd_status_names[status]; 460 else 461 return NULL; 462 } 463 464 static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 465 const void *args, int args_len, 466 bool unlocked) 467 { 468 u8 *buf, status; 469 struct i2c_msg *msgs; 470 int i, ret = true; 471 472 /* Would be simpler to allocate both in one go ? */ 473 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); 474 if (!buf) 475 return false; 476 477 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); 478 if (!msgs) { 479 kfree(buf); 480 return false; 481 } 482 483 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 484 485 for (i = 0; i < args_len; i++) { 486 msgs[i].addr = intel_sdvo->slave_addr; 487 msgs[i].flags = 0; 488 msgs[i].len = 2; 489 msgs[i].buf = buf + 2 *i; 490 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 491 buf[2*i + 1] = ((u8*)args)[i]; 492 } 493 msgs[i].addr = intel_sdvo->slave_addr; 494 msgs[i].flags = 0; 495 msgs[i].len = 2; 496 msgs[i].buf = buf + 2*i; 497 buf[2*i + 0] = SDVO_I2C_OPCODE; 498 buf[2*i + 1] = cmd; 499 500 /* the following two are to read the response */ 501 status = SDVO_I2C_CMD_STATUS; 502 msgs[i+1].addr = intel_sdvo->slave_addr; 503 msgs[i+1].flags = 0; 504 msgs[i+1].len = 1; 505 msgs[i+1].buf = &status; 506 507 msgs[i+2].addr = intel_sdvo->slave_addr; 508 msgs[i+2].flags = I2C_M_RD; 509 msgs[i+2].len = 1; 510 msgs[i+2].buf = &status; 511 512 if (unlocked) 513 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); 514 else 515 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3); 516 if (ret < 0) { 517 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 518 ret = false; 519 goto out; 520 } 521 if (ret != i+3) { 522 /* failure in I2C transfer */ 523 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); 524 ret = false; 525 } 526 527 out: 528 kfree(msgs); 529 kfree(buf); 530 return ret; 531 } 532 533 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 534 const void *args, int args_len) 535 { 536 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true); 537 } 538 539 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 540 void *response, int response_len) 541 { 542 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 543 const char *cmd_status; 544 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ 545 u8 status; 546 int i, pos = 0; 547 char buffer[64]; 548 549 buffer[0] = '\0'; 550 551 /* 552 * The documentation states that all commands will be 553 * processed within 15µs, and that we need only poll 554 * the status byte a maximum of 3 times in order for the 555 * command to be complete. 556 * 557 * Check 5 times in case the hardware failed to read the docs. 558 * 559 * Also beware that the first response by many devices is to 560 * reply PENDING and stall for time. TVs are notorious for 561 * requiring longer than specified to complete their replies. 562 * Originally (in the DDX long ago), the delay was only ever 15ms 563 * with an additional delay of 30ms applied for TVs added later after 564 * many experiments. To accommodate both sets of delays, we do a 565 * sequence of slow checks if the device is falling behind and fails 566 * to reply within 5*15µs. 567 */ 568 if (!intel_sdvo_read_byte(intel_sdvo, 569 SDVO_I2C_CMD_STATUS, 570 &status)) 571 goto log_fail; 572 573 while ((status == SDVO_CMD_STATUS_PENDING || 574 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { 575 if (retry < 10) 576 msleep(15); 577 else 578 udelay(15); 579 580 if (!intel_sdvo_read_byte(intel_sdvo, 581 SDVO_I2C_CMD_STATUS, 582 &status)) 583 goto log_fail; 584 } 585 586 #define BUF_PRINT(args...) \ 587 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) 588 589 cmd_status = sdvo_cmd_status(status); 590 if (cmd_status) 591 BUF_PRINT("(%s)", cmd_status); 592 else 593 BUF_PRINT("(??? %d)", status); 594 595 if (status != SDVO_CMD_STATUS_SUCCESS) 596 goto log_fail; 597 598 /* Read the command response */ 599 for (i = 0; i < response_len; i++) { 600 if (!intel_sdvo_read_byte(intel_sdvo, 601 SDVO_I2C_RETURN_0 + i, 602 &((u8 *)response)[i])) 603 goto log_fail; 604 BUF_PRINT(" %02X", ((u8 *)response)[i]); 605 } 606 607 drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1); 608 #undef BUF_PRINT 609 610 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); 611 return true; 612 613 log_fail: 614 DRM_DEBUG_KMS("%s: R: ... failed %s\n", 615 SDVO_NAME(intel_sdvo), buffer); 616 return false; 617 } 618 619 static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode) 620 { 621 if (adjusted_mode->crtc_clock >= 100000) 622 return 1; 623 else if (adjusted_mode->crtc_clock >= 50000) 624 return 2; 625 else 626 return 4; 627 } 628 629 static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 630 u8 ddc_bus) 631 { 632 /* This must be the immediately preceding write before the i2c xfer */ 633 return __intel_sdvo_write_cmd(intel_sdvo, 634 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 635 &ddc_bus, 1, false); 636 } 637 638 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 639 { 640 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 641 return false; 642 643 return intel_sdvo_read_response(intel_sdvo, NULL, 0); 644 } 645 646 static bool 647 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 648 { 649 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 650 return false; 651 652 return intel_sdvo_read_response(intel_sdvo, value, len); 653 } 654 655 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 656 { 657 struct intel_sdvo_set_target_input_args targets = {0}; 658 return intel_sdvo_set_value(intel_sdvo, 659 SDVO_CMD_SET_TARGET_INPUT, 660 &targets, sizeof(targets)); 661 } 662 663 /* 664 * Return whether each input is trained. 665 * 666 * This function is making an assumption about the layout of the response, 667 * which should be checked against the docs. 668 */ 669 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 670 { 671 struct intel_sdvo_get_trained_inputs_response response; 672 673 BUILD_BUG_ON(sizeof(response) != 1); 674 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 675 &response, sizeof(response))) 676 return false; 677 678 *input_1 = response.input0_trained; 679 *input_2 = response.input1_trained; 680 return true; 681 } 682 683 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 684 u16 outputs) 685 { 686 return intel_sdvo_set_value(intel_sdvo, 687 SDVO_CMD_SET_ACTIVE_OUTPUTS, 688 &outputs, sizeof(outputs)); 689 } 690 691 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, 692 u16 *outputs) 693 { 694 return intel_sdvo_get_value(intel_sdvo, 695 SDVO_CMD_GET_ACTIVE_OUTPUTS, 696 outputs, sizeof(*outputs)); 697 } 698 699 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 700 int mode) 701 { 702 u8 state = SDVO_ENCODER_STATE_ON; 703 704 switch (mode) { 705 case DRM_MODE_DPMS_ON: 706 state = SDVO_ENCODER_STATE_ON; 707 break; 708 case DRM_MODE_DPMS_STANDBY: 709 state = SDVO_ENCODER_STATE_STANDBY; 710 break; 711 case DRM_MODE_DPMS_SUSPEND: 712 state = SDVO_ENCODER_STATE_SUSPEND; 713 break; 714 case DRM_MODE_DPMS_OFF: 715 state = SDVO_ENCODER_STATE_OFF; 716 break; 717 } 718 719 return intel_sdvo_set_value(intel_sdvo, 720 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 721 } 722 723 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 724 int *clock_min, 725 int *clock_max) 726 { 727 struct intel_sdvo_pixel_clock_range clocks; 728 729 BUILD_BUG_ON(sizeof(clocks) != 4); 730 if (!intel_sdvo_get_value(intel_sdvo, 731 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 732 &clocks, sizeof(clocks))) 733 return false; 734 735 /* Convert the values from units of 10 kHz to kHz. */ 736 *clock_min = clocks.min * 10; 737 *clock_max = clocks.max * 10; 738 return true; 739 } 740 741 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 742 u16 outputs) 743 { 744 return intel_sdvo_set_value(intel_sdvo, 745 SDVO_CMD_SET_TARGET_OUTPUT, 746 &outputs, sizeof(outputs)); 747 } 748 749 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 750 struct intel_sdvo_dtd *dtd) 751 { 752 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 753 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 754 } 755 756 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 757 struct intel_sdvo_dtd *dtd) 758 { 759 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 760 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 761 } 762 763 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 764 struct intel_sdvo_dtd *dtd) 765 { 766 return intel_sdvo_set_timing(intel_sdvo, 767 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 768 } 769 770 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 771 struct intel_sdvo_dtd *dtd) 772 { 773 return intel_sdvo_set_timing(intel_sdvo, 774 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 775 } 776 777 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, 778 struct intel_sdvo_dtd *dtd) 779 { 780 return intel_sdvo_get_timing(intel_sdvo, 781 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); 782 } 783 784 static bool 785 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 786 struct intel_sdvo_connector *intel_sdvo_connector, 787 const struct drm_display_mode *mode) 788 { 789 struct intel_sdvo_preferred_input_timing_args args; 790 791 memset(&args, 0, sizeof(args)); 792 args.clock = mode->clock / 10; 793 args.width = mode->hdisplay; 794 args.height = mode->vdisplay; 795 args.interlace = 0; 796 797 if (IS_LVDS(intel_sdvo_connector)) { 798 const struct drm_display_mode *fixed_mode = 799 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); 800 801 if (fixed_mode->hdisplay != args.width || 802 fixed_mode->vdisplay != args.height) 803 args.scaled = 1; 804 } 805 806 return intel_sdvo_set_value(intel_sdvo, 807 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 808 &args, sizeof(args)); 809 } 810 811 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 812 struct intel_sdvo_dtd *dtd) 813 { 814 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 815 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 816 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 817 &dtd->part1, sizeof(dtd->part1)) && 818 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 819 &dtd->part2, sizeof(dtd->part2)); 820 } 821 822 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 823 { 824 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 825 } 826 827 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 828 const struct drm_display_mode *mode) 829 { 830 u16 width, height; 831 u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len; 832 u16 h_sync_offset, v_sync_offset; 833 int mode_clock; 834 835 memset(dtd, 0, sizeof(*dtd)); 836 837 width = mode->hdisplay; 838 height = mode->vdisplay; 839 840 /* do some mode translations */ 841 h_blank_len = mode->htotal - mode->hdisplay; 842 h_sync_len = mode->hsync_end - mode->hsync_start; 843 844 v_blank_len = mode->vtotal - mode->vdisplay; 845 v_sync_len = mode->vsync_end - mode->vsync_start; 846 847 h_sync_offset = mode->hsync_start - mode->hdisplay; 848 v_sync_offset = mode->vsync_start - mode->vdisplay; 849 850 mode_clock = mode->clock; 851 mode_clock /= 10; 852 dtd->part1.clock = mode_clock; 853 854 dtd->part1.h_active = width & 0xff; 855 dtd->part1.h_blank = h_blank_len & 0xff; 856 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 857 ((h_blank_len >> 8) & 0xf); 858 dtd->part1.v_active = height & 0xff; 859 dtd->part1.v_blank = v_blank_len & 0xff; 860 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 861 ((v_blank_len >> 8) & 0xf); 862 863 dtd->part2.h_sync_off = h_sync_offset & 0xff; 864 dtd->part2.h_sync_width = h_sync_len & 0xff; 865 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 866 (v_sync_len & 0xf); 867 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 868 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 869 ((v_sync_len & 0x30) >> 4); 870 871 dtd->part2.dtd_flags = 0x18; 872 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 873 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; 874 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 875 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; 876 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 877 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; 878 879 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 880 } 881 882 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, 883 const struct intel_sdvo_dtd *dtd) 884 { 885 struct drm_display_mode mode = {}; 886 887 mode.hdisplay = dtd->part1.h_active; 888 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 889 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; 890 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 891 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; 892 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 893 mode.htotal = mode.hdisplay + dtd->part1.h_blank; 894 mode.htotal += (dtd->part1.h_high & 0xf) << 8; 895 896 mode.vdisplay = dtd->part1.v_active; 897 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 898 mode.vsync_start = mode.vdisplay; 899 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 900 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 901 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; 902 mode.vsync_end = mode.vsync_start + 903 (dtd->part2.v_sync_off_width & 0xf); 904 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 905 mode.vtotal = mode.vdisplay + dtd->part1.v_blank; 906 mode.vtotal += (dtd->part1.v_high & 0xf) << 8; 907 908 mode.clock = dtd->part1.clock * 10; 909 910 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) 911 mode.flags |= DRM_MODE_FLAG_INTERLACE; 912 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 913 mode.flags |= DRM_MODE_FLAG_PHSYNC; 914 else 915 mode.flags |= DRM_MODE_FLAG_NHSYNC; 916 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 917 mode.flags |= DRM_MODE_FLAG_PVSYNC; 918 else 919 mode.flags |= DRM_MODE_FLAG_NVSYNC; 920 921 drm_mode_set_crtcinfo(&mode, 0); 922 923 drm_mode_copy(pmode, &mode); 924 } 925 926 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) 927 { 928 struct intel_sdvo_encode encode; 929 930 BUILD_BUG_ON(sizeof(encode) != 2); 931 return intel_sdvo_get_value(intel_sdvo, 932 SDVO_CMD_GET_SUPP_ENCODE, 933 &encode, sizeof(encode)); 934 } 935 936 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 937 u8 mode) 938 { 939 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 940 } 941 942 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 943 u8 mode) 944 { 945 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 946 } 947 948 static bool intel_sdvo_set_pixel_replication(struct intel_sdvo *intel_sdvo, 949 u8 pixel_repeat) 950 { 951 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_PIXEL_REPLI, 952 &pixel_repeat, 1); 953 } 954 955 static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo, 956 u8 audio_state) 957 { 958 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT, 959 &audio_state, 1); 960 } 961 962 static bool intel_sdvo_get_hbuf_size(struct intel_sdvo *intel_sdvo, 963 u8 *hbuf_size) 964 { 965 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, 966 hbuf_size, 1)) 967 return false; 968 969 /* Buffer size is 0 based, hooray! However zero means zero. */ 970 if (*hbuf_size) 971 (*hbuf_size)++; 972 973 return true; 974 } 975 976 #if 0 977 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) 978 { 979 int i, j; 980 u8 set_buf_index[2]; 981 u8 av_split; 982 u8 buf_size; 983 u8 buf[48]; 984 u8 *pos; 985 986 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 987 988 for (i = 0; i <= av_split; i++) { 989 set_buf_index[0] = i; set_buf_index[1] = 0; 990 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 991 set_buf_index, 2); 992 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 993 intel_sdvo_read_response(encoder, &buf_size, 1); 994 995 pos = buf; 996 for (j = 0; j <= buf_size; j += 8) { 997 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 998 NULL, 0); 999 intel_sdvo_read_response(encoder, pos, 8); 1000 pos += 8; 1001 } 1002 } 1003 } 1004 #endif 1005 1006 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, 1007 unsigned int if_index, u8 tx_rate, 1008 const u8 *data, unsigned int length) 1009 { 1010 u8 set_buf_index[2] = { if_index, 0 }; 1011 u8 hbuf_size, tmp[8]; 1012 int i; 1013 1014 if (!intel_sdvo_set_value(intel_sdvo, 1015 SDVO_CMD_SET_HBUF_INDEX, 1016 set_buf_index, 2)) 1017 return false; 1018 1019 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) 1020 return false; 1021 1022 DRM_DEBUG_KMS("writing sdvo hbuf: %i, length %u, hbuf_size: %i\n", 1023 if_index, length, hbuf_size); 1024 1025 if (hbuf_size < length) 1026 return false; 1027 1028 for (i = 0; i < hbuf_size; i += 8) { 1029 memset(tmp, 0, 8); 1030 if (i < length) 1031 memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); 1032 1033 if (!intel_sdvo_set_value(intel_sdvo, 1034 SDVO_CMD_SET_HBUF_DATA, 1035 tmp, 8)) 1036 return false; 1037 } 1038 1039 return intel_sdvo_set_value(intel_sdvo, 1040 SDVO_CMD_SET_HBUF_TXRATE, 1041 &tx_rate, 1); 1042 } 1043 1044 static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo, 1045 unsigned int if_index, 1046 u8 *data, unsigned int length) 1047 { 1048 u8 set_buf_index[2] = { if_index, 0 }; 1049 u8 hbuf_size, tx_rate, av_split; 1050 int i; 1051 1052 if (!intel_sdvo_get_value(intel_sdvo, 1053 SDVO_CMD_GET_HBUF_AV_SPLIT, 1054 &av_split, 1)) 1055 return -ENXIO; 1056 1057 if (av_split < if_index) 1058 return 0; 1059 1060 if (!intel_sdvo_set_value(intel_sdvo, 1061 SDVO_CMD_SET_HBUF_INDEX, 1062 set_buf_index, 2)) 1063 return -ENXIO; 1064 1065 if (!intel_sdvo_get_value(intel_sdvo, 1066 SDVO_CMD_GET_HBUF_TXRATE, 1067 &tx_rate, 1)) 1068 return -ENXIO; 1069 1070 if (tx_rate == SDVO_HBUF_TX_DISABLED) 1071 return 0; 1072 1073 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) 1074 return false; 1075 1076 DRM_DEBUG_KMS("reading sdvo hbuf: %i, length %u, hbuf_size: %i\n", 1077 if_index, length, hbuf_size); 1078 1079 hbuf_size = min_t(unsigned int, length, hbuf_size); 1080 1081 for (i = 0; i < hbuf_size; i += 8) { 1082 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA, NULL, 0)) 1083 return -ENXIO; 1084 if (!intel_sdvo_read_response(intel_sdvo, &data[i], 1085 min_t(unsigned int, 8, hbuf_size - i))) 1086 return -ENXIO; 1087 } 1088 1089 return hbuf_size; 1090 } 1091 1092 static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo, 1093 struct intel_crtc_state *crtc_state, 1094 struct drm_connector_state *conn_state) 1095 { 1096 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 1097 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 1098 const struct drm_display_mode *adjusted_mode = 1099 &crtc_state->hw.adjusted_mode; 1100 int ret; 1101 1102 if (!crtc_state->has_hdmi_sink) 1103 return true; 1104 1105 crtc_state->infoframes.enable |= 1106 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 1107 1108 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, 1109 conn_state->connector, 1110 adjusted_mode); 1111 if (ret) 1112 return false; 1113 1114 drm_hdmi_avi_infoframe_quant_range(frame, 1115 conn_state->connector, 1116 adjusted_mode, 1117 crtc_state->limited_color_range ? 1118 HDMI_QUANTIZATION_RANGE_LIMITED : 1119 HDMI_QUANTIZATION_RANGE_FULL); 1120 1121 ret = hdmi_avi_infoframe_check(frame); 1122 if (drm_WARN_ON(&dev_priv->drm, ret)) 1123 return false; 1124 1125 return true; 1126 } 1127 1128 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 1129 const struct intel_crtc_state *crtc_state) 1130 { 1131 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 1132 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1133 const union hdmi_infoframe *frame = &crtc_state->infoframes.avi; 1134 ssize_t len; 1135 1136 if ((crtc_state->infoframes.enable & 1137 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0) 1138 return true; 1139 1140 if (drm_WARN_ON(&dev_priv->drm, 1141 frame->any.type != HDMI_INFOFRAME_TYPE_AVI)) 1142 return false; 1143 1144 len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data)); 1145 if (drm_WARN_ON(&dev_priv->drm, len < 0)) 1146 return false; 1147 1148 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1149 SDVO_HBUF_TX_VSYNC, 1150 sdvo_data, len); 1151 } 1152 1153 static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo, 1154 struct intel_crtc_state *crtc_state) 1155 { 1156 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1157 union hdmi_infoframe *frame = &crtc_state->infoframes.avi; 1158 ssize_t len; 1159 int ret; 1160 1161 if (!crtc_state->has_hdmi_sink) 1162 return; 1163 1164 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1165 sdvo_data, sizeof(sdvo_data)); 1166 if (len < 0) { 1167 DRM_DEBUG_KMS("failed to read AVI infoframe\n"); 1168 return; 1169 } else if (len == 0) { 1170 return; 1171 } 1172 1173 crtc_state->infoframes.enable |= 1174 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 1175 1176 ret = hdmi_infoframe_unpack(frame, sdvo_data, len); 1177 if (ret) { 1178 DRM_DEBUG_KMS("Failed to unpack AVI infoframe\n"); 1179 return; 1180 } 1181 1182 if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI) 1183 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 1184 frame->any.type, HDMI_INFOFRAME_TYPE_AVI); 1185 } 1186 1187 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo, 1188 const struct drm_connector_state *conn_state) 1189 { 1190 struct intel_sdvo_tv_format format; 1191 u32 format_map; 1192 1193 format_map = 1 << conn_state->tv.mode; 1194 memset(&format, 0, sizeof(format)); 1195 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 1196 1197 BUILD_BUG_ON(sizeof(format) != 6); 1198 return intel_sdvo_set_value(intel_sdvo, 1199 SDVO_CMD_SET_TV_FORMAT, 1200 &format, sizeof(format)); 1201 } 1202 1203 static bool 1204 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 1205 const struct drm_display_mode *mode) 1206 { 1207 struct intel_sdvo_dtd output_dtd; 1208 1209 if (!intel_sdvo_set_target_output(intel_sdvo, 1210 intel_sdvo->attached_output)) 1211 return false; 1212 1213 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1214 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1215 return false; 1216 1217 return true; 1218 } 1219 1220 /* 1221 * Asks the sdvo controller for the preferred input mode given the output mode. 1222 * Unfortunately we have to set up the full output mode to do that. 1223 */ 1224 static bool 1225 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, 1226 struct intel_sdvo_connector *intel_sdvo_connector, 1227 const struct drm_display_mode *mode, 1228 struct drm_display_mode *adjusted_mode) 1229 { 1230 struct intel_sdvo_dtd input_dtd; 1231 1232 /* Reset the input timing to the screen. Assume always input 0. */ 1233 if (!intel_sdvo_set_target_input(intel_sdvo)) 1234 return false; 1235 1236 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 1237 intel_sdvo_connector, 1238 mode)) 1239 return false; 1240 1241 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1242 &input_dtd)) 1243 return false; 1244 1245 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1246 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; 1247 1248 return true; 1249 } 1250 1251 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) 1252 { 1253 struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc->dev); 1254 unsigned dotclock = pipe_config->port_clock; 1255 struct dpll *clock = &pipe_config->dpll; 1256 1257 /* 1258 * SDVO TV has fixed PLL values depend on its clock range, 1259 * this mirrors vbios setting. 1260 */ 1261 if (dotclock >= 100000 && dotclock < 140500) { 1262 clock->p1 = 2; 1263 clock->p2 = 10; 1264 clock->n = 3; 1265 clock->m1 = 16; 1266 clock->m2 = 8; 1267 } else if (dotclock >= 140500 && dotclock <= 200000) { 1268 clock->p1 = 1; 1269 clock->p2 = 10; 1270 clock->n = 6; 1271 clock->m1 = 12; 1272 clock->m2 = 8; 1273 } else { 1274 drm_WARN(&dev_priv->drm, 1, 1275 "SDVO TV clock out of range: %i\n", dotclock); 1276 } 1277 1278 pipe_config->clock_set = true; 1279 } 1280 1281 static bool intel_has_hdmi_sink(struct intel_sdvo *sdvo, 1282 const struct drm_connector_state *conn_state) 1283 { 1284 return sdvo->has_hdmi_monitor && 1285 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1286 } 1287 1288 static bool intel_sdvo_limited_color_range(struct intel_encoder *encoder, 1289 const struct intel_crtc_state *crtc_state, 1290 const struct drm_connector_state *conn_state) 1291 { 1292 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1293 1294 if ((intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220) == 0) 1295 return false; 1296 1297 return intel_hdmi_limited_color_range(crtc_state, conn_state); 1298 } 1299 1300 static bool intel_sdvo_has_audio(struct intel_encoder *encoder, 1301 const struct intel_crtc_state *crtc_state, 1302 const struct drm_connector_state *conn_state) 1303 { 1304 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1305 const struct intel_digital_connector_state *intel_conn_state = 1306 to_intel_digital_connector_state(conn_state); 1307 1308 if (!crtc_state->has_hdmi_sink) 1309 return false; 1310 1311 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 1312 return intel_sdvo->has_hdmi_audio; 1313 else 1314 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 1315 } 1316 1317 static int intel_sdvo_compute_config(struct intel_encoder *encoder, 1318 struct intel_crtc_state *pipe_config, 1319 struct drm_connector_state *conn_state) 1320 { 1321 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1322 struct intel_sdvo_connector *intel_sdvo_connector = 1323 to_intel_sdvo_connector(conn_state->connector); 1324 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1325 struct drm_display_mode *mode = &pipe_config->hw.mode; 1326 1327 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); 1328 pipe_config->pipe_bpp = 8*3; 1329 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1330 1331 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) 1332 pipe_config->has_pch_encoder = true; 1333 1334 /* 1335 * We need to construct preferred input timings based on our 1336 * output timings. To do that, we have to set the output 1337 * timings, even though this isn't really the right place in 1338 * the sequence to do it. Oh well. 1339 */ 1340 if (IS_TV(intel_sdvo_connector)) { 1341 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) 1342 return -EINVAL; 1343 1344 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1345 intel_sdvo_connector, 1346 mode, 1347 adjusted_mode); 1348 pipe_config->sdvo_tv_clock = true; 1349 } else if (IS_LVDS(intel_sdvo_connector)) { 1350 const struct drm_display_mode *fixed_mode = 1351 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); 1352 int ret; 1353 1354 ret = intel_panel_compute_config(&intel_sdvo_connector->base, 1355 adjusted_mode); 1356 if (ret) 1357 return ret; 1358 1359 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, fixed_mode)) 1360 return -EINVAL; 1361 1362 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1363 intel_sdvo_connector, 1364 mode, 1365 adjusted_mode); 1366 } 1367 1368 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 1369 return -EINVAL; 1370 1371 /* 1372 * Make the CRTC code factor in the SDVO pixel multiplier. The 1373 * SDVO device will factor out the multiplier during mode_set. 1374 */ 1375 pipe_config->pixel_multiplier = 1376 intel_sdvo_get_pixel_multiplier(adjusted_mode); 1377 1378 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo, conn_state); 1379 1380 pipe_config->has_audio = intel_sdvo_has_audio(encoder, pipe_config, conn_state); 1381 1382 pipe_config->limited_color_range = 1383 intel_sdvo_limited_color_range(encoder, pipe_config, 1384 conn_state); 1385 1386 /* Clock computation needs to happen after pixel multiplier. */ 1387 if (IS_TV(intel_sdvo_connector)) 1388 i9xx_adjust_sdvo_tv_clock(pipe_config); 1389 1390 if (conn_state->picture_aspect_ratio) 1391 adjusted_mode->picture_aspect_ratio = 1392 conn_state->picture_aspect_ratio; 1393 1394 if (!intel_sdvo_compute_avi_infoframe(intel_sdvo, 1395 pipe_config, conn_state)) { 1396 DRM_DEBUG_KMS("bad AVI infoframe\n"); 1397 return -EINVAL; 1398 } 1399 1400 return 0; 1401 } 1402 1403 #define UPDATE_PROPERTY(input, NAME) \ 1404 do { \ 1405 val = input; \ 1406 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \ 1407 } while (0) 1408 1409 static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo, 1410 const struct intel_sdvo_connector_state *sdvo_state) 1411 { 1412 const struct drm_connector_state *conn_state = &sdvo_state->base.base; 1413 struct intel_sdvo_connector *intel_sdvo_conn = 1414 to_intel_sdvo_connector(conn_state->connector); 1415 u16 val; 1416 1417 if (intel_sdvo_conn->left) 1418 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H); 1419 1420 if (intel_sdvo_conn->top) 1421 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V); 1422 1423 if (intel_sdvo_conn->hpos) 1424 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS); 1425 1426 if (intel_sdvo_conn->vpos) 1427 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS); 1428 1429 if (intel_sdvo_conn->saturation) 1430 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION); 1431 1432 if (intel_sdvo_conn->contrast) 1433 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST); 1434 1435 if (intel_sdvo_conn->hue) 1436 UPDATE_PROPERTY(conn_state->tv.hue, HUE); 1437 1438 if (intel_sdvo_conn->brightness) 1439 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS); 1440 1441 if (intel_sdvo_conn->sharpness) 1442 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS); 1443 1444 if (intel_sdvo_conn->flicker_filter) 1445 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER); 1446 1447 if (intel_sdvo_conn->flicker_filter_2d) 1448 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D); 1449 1450 if (intel_sdvo_conn->flicker_filter_adaptive) 1451 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 1452 1453 if (intel_sdvo_conn->tv_chroma_filter) 1454 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER); 1455 1456 if (intel_sdvo_conn->tv_luma_filter) 1457 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER); 1458 1459 if (intel_sdvo_conn->dot_crawl) 1460 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL); 1461 1462 #undef UPDATE_PROPERTY 1463 } 1464 1465 static void intel_sdvo_pre_enable(struct intel_atomic_state *state, 1466 struct intel_encoder *intel_encoder, 1467 const struct intel_crtc_state *crtc_state, 1468 const struct drm_connector_state *conn_state) 1469 { 1470 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 1471 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1472 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1473 const struct intel_sdvo_connector_state *sdvo_state = 1474 to_intel_sdvo_connector_state(conn_state); 1475 struct intel_sdvo_connector *intel_sdvo_connector = 1476 to_intel_sdvo_connector(conn_state->connector); 1477 const struct drm_display_mode *mode = &crtc_state->hw.mode; 1478 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); 1479 u32 sdvox; 1480 struct intel_sdvo_in_out_map in_out; 1481 struct intel_sdvo_dtd input_dtd, output_dtd; 1482 int rate; 1483 1484 intel_sdvo_update_props(intel_sdvo, sdvo_state); 1485 1486 /* 1487 * First, set the input mapping for the first input to our controlled 1488 * output. This is only correct if we're a single-input device, in 1489 * which case the first input is the output from the appropriate SDVO 1490 * channel on the motherboard. In a two-input device, the first input 1491 * will be SDVOB and the second SDVOC. 1492 */ 1493 in_out.in0 = intel_sdvo->attached_output; 1494 in_out.in1 = 0; 1495 1496 intel_sdvo_set_value(intel_sdvo, 1497 SDVO_CMD_SET_IN_OUT_MAP, 1498 &in_out, sizeof(in_out)); 1499 1500 /* Set the output timings to the screen */ 1501 if (!intel_sdvo_set_target_output(intel_sdvo, 1502 intel_sdvo->attached_output)) 1503 return; 1504 1505 /* lvds has a special fixed output timing. */ 1506 if (IS_LVDS(intel_sdvo_connector)) { 1507 const struct drm_display_mode *fixed_mode = 1508 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); 1509 1510 intel_sdvo_get_dtd_from_mode(&output_dtd, fixed_mode); 1511 } else { 1512 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1513 } 1514 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1515 drm_info(&dev_priv->drm, 1516 "Setting output timings on %s failed\n", 1517 SDVO_NAME(intel_sdvo)); 1518 1519 /* Set the input timing to the screen. Assume always input 0. */ 1520 if (!intel_sdvo_set_target_input(intel_sdvo)) 1521 return; 1522 1523 if (crtc_state->has_hdmi_sink) { 1524 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 1525 intel_sdvo_set_colorimetry(intel_sdvo, 1526 crtc_state->limited_color_range ? 1527 SDVO_COLORIMETRY_RGB220 : 1528 SDVO_COLORIMETRY_RGB256); 1529 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state); 1530 intel_sdvo_set_pixel_replication(intel_sdvo, 1531 !!(adjusted_mode->flags & 1532 DRM_MODE_FLAG_DBLCLK)); 1533 } else 1534 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); 1535 1536 if (IS_TV(intel_sdvo_connector) && 1537 !intel_sdvo_set_tv_format(intel_sdvo, conn_state)) 1538 return; 1539 1540 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1541 1542 if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector)) 1543 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; 1544 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1545 drm_info(&dev_priv->drm, 1546 "Setting input timings on %s failed\n", 1547 SDVO_NAME(intel_sdvo)); 1548 1549 switch (crtc_state->pixel_multiplier) { 1550 default: 1551 drm_WARN(&dev_priv->drm, 1, 1552 "unknown pixel multiplier specified\n"); 1553 fallthrough; 1554 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1555 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1556 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1557 } 1558 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1559 return; 1560 1561 /* Set the SDVO control regs. */ 1562 if (DISPLAY_VER(dev_priv) >= 4) { 1563 /* The real mode polarity is set by the SDVO commands, using 1564 * struct intel_sdvo_dtd. */ 1565 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; 1566 if (DISPLAY_VER(dev_priv) < 5) 1567 sdvox |= SDVO_BORDER_ENABLE; 1568 } else { 1569 sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1570 if (intel_sdvo->port == PORT_B) 1571 sdvox &= SDVOB_PRESERVE_MASK; 1572 else 1573 sdvox &= SDVOC_PRESERVE_MASK; 1574 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1575 } 1576 1577 if (HAS_PCH_CPT(dev_priv)) 1578 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1579 else 1580 sdvox |= SDVO_PIPE_SEL(crtc->pipe); 1581 1582 if (DISPLAY_VER(dev_priv) >= 4) { 1583 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1584 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 1585 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 1586 /* done in crtc_mode_set as it lives inside the dpll register */ 1587 } else { 1588 sdvox |= (crtc_state->pixel_multiplier - 1) 1589 << SDVO_PORT_MULTIPLY_SHIFT; 1590 } 1591 1592 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && 1593 DISPLAY_VER(dev_priv) < 5) 1594 sdvox |= SDVO_STALL_SELECT; 1595 intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1596 } 1597 1598 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) 1599 { 1600 struct intel_sdvo_connector *intel_sdvo_connector = 1601 to_intel_sdvo_connector(&connector->base); 1602 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1603 u16 active_outputs = 0; 1604 1605 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1606 1607 return active_outputs & intel_sdvo_connector->output_flag; 1608 } 1609 1610 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, 1611 i915_reg_t sdvo_reg, enum pipe *pipe) 1612 { 1613 u32 val; 1614 1615 val = intel_de_read(dev_priv, sdvo_reg); 1616 1617 /* asserts want to know the pipe even if the port is disabled */ 1618 if (HAS_PCH_CPT(dev_priv)) 1619 *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT; 1620 else if (IS_CHERRYVIEW(dev_priv)) 1621 *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV; 1622 else 1623 *pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT; 1624 1625 return val & SDVO_ENABLE; 1626 } 1627 1628 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, 1629 enum pipe *pipe) 1630 { 1631 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1632 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1633 u16 active_outputs = 0; 1634 bool ret; 1635 1636 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1637 1638 ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe); 1639 1640 return ret || active_outputs; 1641 } 1642 1643 static void intel_sdvo_get_config(struct intel_encoder *encoder, 1644 struct intel_crtc_state *pipe_config) 1645 { 1646 struct drm_device *dev = encoder->base.dev; 1647 struct drm_i915_private *dev_priv = to_i915(dev); 1648 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1649 struct intel_sdvo_dtd dtd; 1650 int encoder_pixel_multiplier = 0; 1651 int dotclock; 1652 u32 flags = 0, sdvox; 1653 u8 val; 1654 bool ret; 1655 1656 pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO); 1657 1658 sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1659 1660 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1661 if (!ret) { 1662 /* 1663 * Some sdvo encoders are not spec compliant and don't 1664 * implement the mandatory get_timings function. 1665 */ 1666 drm_dbg(&dev_priv->drm, "failed to retrieve SDVO DTD\n"); 1667 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; 1668 } else { 1669 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1670 flags |= DRM_MODE_FLAG_PHSYNC; 1671 else 1672 flags |= DRM_MODE_FLAG_NHSYNC; 1673 1674 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1675 flags |= DRM_MODE_FLAG_PVSYNC; 1676 else 1677 flags |= DRM_MODE_FLAG_NVSYNC; 1678 } 1679 1680 pipe_config->hw.adjusted_mode.flags |= flags; 1681 1682 /* 1683 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in 1684 * the sdvo port register, on all other platforms it is part of the dpll 1685 * state. Since the general pipe state readout happens before the 1686 * encoder->get_config we so already have a valid pixel multplier on all 1687 * other platfroms. 1688 */ 1689 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 1690 pipe_config->pixel_multiplier = 1691 ((sdvox & SDVO_PORT_MULTIPLY_MASK) 1692 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1693 } 1694 1695 dotclock = pipe_config->port_clock; 1696 1697 if (pipe_config->pixel_multiplier) 1698 dotclock /= pipe_config->pixel_multiplier; 1699 1700 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1701 1702 /* Cross check the port pixel multiplier with the sdvo encoder state. */ 1703 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, 1704 &val, 1)) { 1705 switch (val) { 1706 case SDVO_CLOCK_RATE_MULT_1X: 1707 encoder_pixel_multiplier = 1; 1708 break; 1709 case SDVO_CLOCK_RATE_MULT_2X: 1710 encoder_pixel_multiplier = 2; 1711 break; 1712 case SDVO_CLOCK_RATE_MULT_4X: 1713 encoder_pixel_multiplier = 4; 1714 break; 1715 } 1716 } 1717 1718 drm_WARN(dev, 1719 encoder_pixel_multiplier != pipe_config->pixel_multiplier, 1720 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", 1721 pipe_config->pixel_multiplier, encoder_pixel_multiplier); 1722 1723 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY, 1724 &val, 1)) { 1725 if (val == SDVO_COLORIMETRY_RGB220) 1726 pipe_config->limited_color_range = true; 1727 } 1728 1729 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, 1730 &val, 1)) { 1731 u8 mask = SDVO_AUDIO_ELD_VALID | SDVO_AUDIO_PRESENCE_DETECT; 1732 1733 if ((val & mask) == mask) 1734 pipe_config->has_audio = true; 1735 } 1736 1737 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, 1738 &val, 1)) { 1739 if (val == SDVO_ENCODE_HDMI) 1740 pipe_config->has_hdmi_sink = true; 1741 } 1742 1743 intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config); 1744 } 1745 1746 static void intel_sdvo_disable_audio(struct intel_sdvo *intel_sdvo) 1747 { 1748 intel_sdvo_set_audio_state(intel_sdvo, 0); 1749 } 1750 1751 static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo, 1752 const struct intel_crtc_state *crtc_state, 1753 const struct drm_connector_state *conn_state) 1754 { 1755 const struct drm_display_mode *adjusted_mode = 1756 &crtc_state->hw.adjusted_mode; 1757 struct drm_connector *connector = conn_state->connector; 1758 u8 *eld = connector->eld; 1759 1760 eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 1761 1762 intel_sdvo_set_audio_state(intel_sdvo, 0); 1763 1764 intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD, 1765 SDVO_HBUF_TX_DISABLED, 1766 eld, drm_eld_size(eld)); 1767 1768 intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID | 1769 SDVO_AUDIO_PRESENCE_DETECT); 1770 } 1771 1772 static void intel_disable_sdvo(struct intel_atomic_state *state, 1773 struct intel_encoder *encoder, 1774 const struct intel_crtc_state *old_crtc_state, 1775 const struct drm_connector_state *conn_state) 1776 { 1777 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1778 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1779 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1780 u32 temp; 1781 1782 if (old_crtc_state->has_audio) 1783 intel_sdvo_disable_audio(intel_sdvo); 1784 1785 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1786 if (0) 1787 intel_sdvo_set_encoder_power_state(intel_sdvo, 1788 DRM_MODE_DPMS_OFF); 1789 1790 temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1791 1792 temp &= ~SDVO_ENABLE; 1793 intel_sdvo_write_sdvox(intel_sdvo, temp); 1794 1795 /* 1796 * HW workaround for IBX, we need to move the port 1797 * to transcoder A after disabling it to allow the 1798 * matching DP port to be enabled on transcoder A. 1799 */ 1800 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 1801 /* 1802 * We get CPU/PCH FIFO underruns on the other pipe when 1803 * doing the workaround. Sweep them under the rug. 1804 */ 1805 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1806 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1807 1808 temp &= ~SDVO_PIPE_SEL_MASK; 1809 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 1810 intel_sdvo_write_sdvox(intel_sdvo, temp); 1811 1812 temp &= ~SDVO_ENABLE; 1813 intel_sdvo_write_sdvox(intel_sdvo, temp); 1814 1815 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 1816 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1817 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1818 } 1819 } 1820 1821 static void pch_disable_sdvo(struct intel_atomic_state *state, 1822 struct intel_encoder *encoder, 1823 const struct intel_crtc_state *old_crtc_state, 1824 const struct drm_connector_state *old_conn_state) 1825 { 1826 } 1827 1828 static void pch_post_disable_sdvo(struct intel_atomic_state *state, 1829 struct intel_encoder *encoder, 1830 const struct intel_crtc_state *old_crtc_state, 1831 const struct drm_connector_state *old_conn_state) 1832 { 1833 intel_disable_sdvo(state, encoder, old_crtc_state, old_conn_state); 1834 } 1835 1836 static void intel_enable_sdvo(struct intel_atomic_state *state, 1837 struct intel_encoder *encoder, 1838 const struct intel_crtc_state *pipe_config, 1839 const struct drm_connector_state *conn_state) 1840 { 1841 struct drm_device *dev = encoder->base.dev; 1842 struct drm_i915_private *dev_priv = to_i915(dev); 1843 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1844 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1845 u32 temp; 1846 bool input1, input2; 1847 int i; 1848 bool success; 1849 1850 temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1851 temp |= SDVO_ENABLE; 1852 intel_sdvo_write_sdvox(intel_sdvo, temp); 1853 1854 for (i = 0; i < 2; i++) 1855 intel_crtc_wait_for_next_vblank(crtc); 1856 1857 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1858 /* 1859 * Warn if the device reported failure to sync. 1860 * 1861 * A lot of SDVO devices fail to notify of sync, but it's 1862 * a given it the status is a success, we succeeded. 1863 */ 1864 if (success && !input1) { 1865 drm_dbg_kms(&dev_priv->drm, 1866 "First %s output reported failure to " 1867 "sync\n", SDVO_NAME(intel_sdvo)); 1868 } 1869 1870 if (0) 1871 intel_sdvo_set_encoder_power_state(intel_sdvo, 1872 DRM_MODE_DPMS_ON); 1873 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1874 1875 if (pipe_config->has_audio) 1876 intel_sdvo_enable_audio(intel_sdvo, pipe_config, conn_state); 1877 } 1878 1879 static enum drm_mode_status 1880 intel_sdvo_mode_valid(struct drm_connector *connector, 1881 struct drm_display_mode *mode) 1882 { 1883 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 1884 struct intel_sdvo_connector *intel_sdvo_connector = 1885 to_intel_sdvo_connector(connector); 1886 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 1887 bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo, connector->state); 1888 int clock = mode->clock; 1889 1890 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1891 return MODE_NO_DBLESCAN; 1892 1893 if (clock > max_dotclk) 1894 return MODE_CLOCK_HIGH; 1895 1896 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1897 if (!has_hdmi_sink) 1898 return MODE_CLOCK_LOW; 1899 clock *= 2; 1900 } 1901 1902 if (intel_sdvo->pixel_clock_min > clock) 1903 return MODE_CLOCK_LOW; 1904 1905 if (intel_sdvo->pixel_clock_max < clock) 1906 return MODE_CLOCK_HIGH; 1907 1908 if (IS_LVDS(intel_sdvo_connector)) { 1909 enum drm_mode_status status; 1910 1911 status = intel_panel_mode_valid(&intel_sdvo_connector->base, mode); 1912 if (status != MODE_OK) 1913 return status; 1914 } 1915 1916 return MODE_OK; 1917 } 1918 1919 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1920 { 1921 BUILD_BUG_ON(sizeof(*caps) != 8); 1922 if (!intel_sdvo_get_value(intel_sdvo, 1923 SDVO_CMD_GET_DEVICE_CAPS, 1924 caps, sizeof(*caps))) 1925 return false; 1926 1927 DRM_DEBUG_KMS("SDVO capabilities:\n" 1928 " vendor_id: %d\n" 1929 " device_id: %d\n" 1930 " device_rev_id: %d\n" 1931 " sdvo_version_major: %d\n" 1932 " sdvo_version_minor: %d\n" 1933 " sdvo_inputs_mask: %d\n" 1934 " smooth_scaling: %d\n" 1935 " sharp_scaling: %d\n" 1936 " up_scaling: %d\n" 1937 " down_scaling: %d\n" 1938 " stall_support: %d\n" 1939 " output_flags: %d\n", 1940 caps->vendor_id, 1941 caps->device_id, 1942 caps->device_rev_id, 1943 caps->sdvo_version_major, 1944 caps->sdvo_version_minor, 1945 caps->sdvo_inputs_mask, 1946 caps->smooth_scaling, 1947 caps->sharp_scaling, 1948 caps->up_scaling, 1949 caps->down_scaling, 1950 caps->stall_support, 1951 caps->output_flags); 1952 1953 return true; 1954 } 1955 1956 static u8 intel_sdvo_get_colorimetry_cap(struct intel_sdvo *intel_sdvo) 1957 { 1958 u8 cap; 1959 1960 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY_CAP, 1961 &cap, sizeof(cap))) 1962 return SDVO_COLORIMETRY_RGB256; 1963 1964 return cap; 1965 } 1966 1967 static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) 1968 { 1969 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 1970 u16 hotplug; 1971 1972 if (!I915_HAS_HOTPLUG(dev_priv)) 1973 return 0; 1974 1975 /* 1976 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise 1977 * on the line. 1978 */ 1979 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) 1980 return 0; 1981 1982 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, 1983 &hotplug, sizeof(hotplug))) 1984 return 0; 1985 1986 return hotplug; 1987 } 1988 1989 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) 1990 { 1991 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1992 1993 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, 1994 &intel_sdvo->hotplug_active, 2); 1995 } 1996 1997 static enum intel_hotplug_state 1998 intel_sdvo_hotplug(struct intel_encoder *encoder, 1999 struct intel_connector *connector) 2000 { 2001 intel_sdvo_enable_hotplug(encoder); 2002 2003 return intel_encoder_hotplug(encoder, connector); 2004 } 2005 2006 static bool 2007 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) 2008 { 2009 /* Is there more than one type of output? */ 2010 return hweight16(intel_sdvo->caps.output_flags) > 1; 2011 } 2012 2013 static struct edid * 2014 intel_sdvo_get_edid(struct drm_connector *connector) 2015 { 2016 struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2017 return drm_get_edid(connector, &sdvo->ddc); 2018 } 2019 2020 /* Mac mini hack -- use the same DDC as the analog connector */ 2021 static struct edid * 2022 intel_sdvo_get_analog_edid(struct drm_connector *connector) 2023 { 2024 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2025 2026 return drm_get_edid(connector, 2027 intel_gmbus_get_adapter(dev_priv, 2028 dev_priv->display.vbt.crt_ddc_pin)); 2029 } 2030 2031 static enum drm_connector_status 2032 intel_sdvo_tmds_sink_detect(struct drm_connector *connector) 2033 { 2034 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2035 struct intel_sdvo_connector *intel_sdvo_connector = 2036 to_intel_sdvo_connector(connector); 2037 enum drm_connector_status status; 2038 struct edid *edid; 2039 2040 edid = intel_sdvo_get_edid(connector); 2041 2042 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { 2043 u8 ddc, saved_ddc = intel_sdvo->ddc_bus; 2044 2045 /* 2046 * Don't use the 1 as the argument of DDC bus switch to get 2047 * the EDID. It is used for SDVO SPD ROM. 2048 */ 2049 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { 2050 intel_sdvo->ddc_bus = ddc; 2051 edid = intel_sdvo_get_edid(connector); 2052 if (edid) 2053 break; 2054 } 2055 /* 2056 * If we found the EDID on the other bus, 2057 * assume that is the correct DDC bus. 2058 */ 2059 if (edid == NULL) 2060 intel_sdvo->ddc_bus = saved_ddc; 2061 } 2062 2063 /* 2064 * When there is no edid and no monitor is connected with VGA 2065 * port, try to use the CRT ddc to read the EDID for DVI-connector. 2066 */ 2067 if (edid == NULL) 2068 edid = intel_sdvo_get_analog_edid(connector); 2069 2070 status = connector_status_unknown; 2071 if (edid != NULL) { 2072 /* DDC bus is shared, match EDID to connector type */ 2073 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 2074 status = connector_status_connected; 2075 if (intel_sdvo_connector->is_hdmi) { 2076 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); 2077 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); 2078 } 2079 } else 2080 status = connector_status_disconnected; 2081 kfree(edid); 2082 } 2083 2084 return status; 2085 } 2086 2087 static bool 2088 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, 2089 struct edid *edid) 2090 { 2091 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 2092 bool connector_is_digital = !!IS_DIGITAL(sdvo); 2093 2094 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", 2095 connector_is_digital, monitor_is_digital); 2096 return connector_is_digital == monitor_is_digital; 2097 } 2098 2099 static enum drm_connector_status 2100 intel_sdvo_detect(struct drm_connector *connector, bool force) 2101 { 2102 struct drm_i915_private *i915 = to_i915(connector->dev); 2103 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2104 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2105 enum drm_connector_status ret; 2106 u16 response; 2107 2108 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2109 connector->base.id, connector->name); 2110 2111 if (!INTEL_DISPLAY_ENABLED(i915)) 2112 return connector_status_disconnected; 2113 2114 if (!intel_sdvo_get_value(intel_sdvo, 2115 SDVO_CMD_GET_ATTACHED_DISPLAYS, 2116 &response, 2)) 2117 return connector_status_unknown; 2118 2119 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", 2120 response & 0xff, response >> 8, 2121 intel_sdvo_connector->output_flag); 2122 2123 if (response == 0) 2124 return connector_status_disconnected; 2125 2126 intel_sdvo->attached_output = response; 2127 2128 intel_sdvo->has_hdmi_monitor = false; 2129 intel_sdvo->has_hdmi_audio = false; 2130 2131 if ((intel_sdvo_connector->output_flag & response) == 0) 2132 ret = connector_status_disconnected; 2133 else if (IS_TMDS(intel_sdvo_connector)) 2134 ret = intel_sdvo_tmds_sink_detect(connector); 2135 else { 2136 struct edid *edid; 2137 2138 /* if we have an edid check it matches the connection */ 2139 edid = intel_sdvo_get_edid(connector); 2140 if (edid == NULL) 2141 edid = intel_sdvo_get_analog_edid(connector); 2142 if (edid != NULL) { 2143 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, 2144 edid)) 2145 ret = connector_status_connected; 2146 else 2147 ret = connector_status_disconnected; 2148 2149 kfree(edid); 2150 } else 2151 ret = connector_status_connected; 2152 } 2153 2154 return ret; 2155 } 2156 2157 static int intel_sdvo_get_ddc_modes(struct drm_connector *connector) 2158 { 2159 int num_modes = 0; 2160 struct edid *edid; 2161 2162 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2163 connector->base.id, connector->name); 2164 2165 /* set the bus switch and get the modes */ 2166 edid = intel_sdvo_get_edid(connector); 2167 2168 /* 2169 * Mac mini hack. On this device, the DVI-I connector shares one DDC 2170 * link between analog and digital outputs. So, if the regular SDVO 2171 * DDC fails, check to see if the analog output is disconnected, in 2172 * which case we'll look there for the digital DDC data. 2173 */ 2174 if (!edid) 2175 edid = intel_sdvo_get_analog_edid(connector); 2176 2177 if (!edid) 2178 return 0; 2179 2180 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), 2181 edid)) 2182 num_modes += intel_connector_update_modes(connector, edid); 2183 2184 kfree(edid); 2185 2186 return num_modes; 2187 } 2188 2189 /* 2190 * Set of SDVO TV modes. 2191 * Note! This is in reply order (see loop in get_tv_modes). 2192 * XXX: all 60Hz refresh? 2193 */ 2194 static const struct drm_display_mode sdvo_tv_modes[] = { 2195 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 2196 416, 0, 200, 201, 232, 233, 0, 2197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2198 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 2199 416, 0, 240, 241, 272, 273, 0, 2200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2201 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 2202 496, 0, 300, 301, 332, 333, 0, 2203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2204 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 2205 736, 0, 350, 351, 382, 383, 0, 2206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2207 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 2208 736, 0, 400, 401, 432, 433, 0, 2209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2210 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 2211 736, 0, 480, 481, 512, 513, 0, 2212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2213 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 2214 800, 0, 480, 481, 512, 513, 0, 2215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2216 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 2217 800, 0, 576, 577, 608, 609, 0, 2218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2219 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 2220 816, 0, 350, 351, 382, 383, 0, 2221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2222 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 2223 816, 0, 400, 401, 432, 433, 0, 2224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2225 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 2226 816, 0, 480, 481, 512, 513, 0, 2227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2228 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 2229 816, 0, 540, 541, 572, 573, 0, 2230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2231 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 2232 816, 0, 576, 577, 608, 609, 0, 2233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2234 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 2235 864, 0, 576, 577, 608, 609, 0, 2236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2237 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 2238 896, 0, 600, 601, 632, 633, 0, 2239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2240 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 2241 928, 0, 624, 625, 656, 657, 0, 2242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2243 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 2244 1016, 0, 766, 767, 798, 799, 0, 2245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2246 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 2247 1120, 0, 768, 769, 800, 801, 0, 2248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2249 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 2250 1376, 0, 1024, 1025, 1056, 1057, 0, 2251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2252 }; 2253 2254 static int intel_sdvo_get_tv_modes(struct drm_connector *connector) 2255 { 2256 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2257 const struct drm_connector_state *conn_state = connector->state; 2258 struct intel_sdvo_sdtv_resolution_request tv_res; 2259 u32 reply = 0, format_map = 0; 2260 int num_modes = 0; 2261 int i; 2262 2263 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2264 connector->base.id, connector->name); 2265 2266 /* 2267 * Read the list of supported input resolutions for the selected TV 2268 * format. 2269 */ 2270 format_map = 1 << conn_state->tv.mode; 2271 memcpy(&tv_res, &format_map, 2272 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 2273 2274 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) 2275 return 0; 2276 2277 BUILD_BUG_ON(sizeof(tv_res) != 3); 2278 if (!intel_sdvo_write_cmd(intel_sdvo, 2279 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 2280 &tv_res, sizeof(tv_res))) 2281 return 0; 2282 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 2283 return 0; 2284 2285 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) { 2286 if (reply & (1 << i)) { 2287 struct drm_display_mode *nmode; 2288 nmode = drm_mode_duplicate(connector->dev, 2289 &sdvo_tv_modes[i]); 2290 if (nmode) { 2291 drm_mode_probed_add(connector, nmode); 2292 num_modes++; 2293 } 2294 } 2295 } 2296 2297 return num_modes; 2298 } 2299 2300 static int intel_sdvo_get_lvds_modes(struct drm_connector *connector) 2301 { 2302 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2303 2304 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 2305 connector->base.id, connector->name); 2306 2307 return intel_panel_get_modes(to_intel_connector(connector)); 2308 } 2309 2310 static int intel_sdvo_get_modes(struct drm_connector *connector) 2311 { 2312 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2313 2314 if (IS_TV(intel_sdvo_connector)) 2315 return intel_sdvo_get_tv_modes(connector); 2316 else if (IS_LVDS(intel_sdvo_connector)) 2317 return intel_sdvo_get_lvds_modes(connector); 2318 else 2319 return intel_sdvo_get_ddc_modes(connector); 2320 } 2321 2322 static int 2323 intel_sdvo_connector_atomic_get_property(struct drm_connector *connector, 2324 const struct drm_connector_state *state, 2325 struct drm_property *property, 2326 u64 *val) 2327 { 2328 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2329 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state); 2330 2331 if (property == intel_sdvo_connector->tv_format) { 2332 int i; 2333 2334 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2335 if (state->tv.mode == intel_sdvo_connector->tv_format_supported[i]) { 2336 *val = i; 2337 2338 return 0; 2339 } 2340 2341 drm_WARN_ON(connector->dev, 1); 2342 *val = 0; 2343 } else if (property == intel_sdvo_connector->top || 2344 property == intel_sdvo_connector->bottom) 2345 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v; 2346 else if (property == intel_sdvo_connector->left || 2347 property == intel_sdvo_connector->right) 2348 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h; 2349 else if (property == intel_sdvo_connector->hpos) 2350 *val = sdvo_state->tv.hpos; 2351 else if (property == intel_sdvo_connector->vpos) 2352 *val = sdvo_state->tv.vpos; 2353 else if (property == intel_sdvo_connector->saturation) 2354 *val = state->tv.saturation; 2355 else if (property == intel_sdvo_connector->contrast) 2356 *val = state->tv.contrast; 2357 else if (property == intel_sdvo_connector->hue) 2358 *val = state->tv.hue; 2359 else if (property == intel_sdvo_connector->brightness) 2360 *val = state->tv.brightness; 2361 else if (property == intel_sdvo_connector->sharpness) 2362 *val = sdvo_state->tv.sharpness; 2363 else if (property == intel_sdvo_connector->flicker_filter) 2364 *val = sdvo_state->tv.flicker_filter; 2365 else if (property == intel_sdvo_connector->flicker_filter_2d) 2366 *val = sdvo_state->tv.flicker_filter_2d; 2367 else if (property == intel_sdvo_connector->flicker_filter_adaptive) 2368 *val = sdvo_state->tv.flicker_filter_adaptive; 2369 else if (property == intel_sdvo_connector->tv_chroma_filter) 2370 *val = sdvo_state->tv.chroma_filter; 2371 else if (property == intel_sdvo_connector->tv_luma_filter) 2372 *val = sdvo_state->tv.luma_filter; 2373 else if (property == intel_sdvo_connector->dot_crawl) 2374 *val = sdvo_state->tv.dot_crawl; 2375 else 2376 return intel_digital_connector_atomic_get_property(connector, state, property, val); 2377 2378 return 0; 2379 } 2380 2381 static int 2382 intel_sdvo_connector_atomic_set_property(struct drm_connector *connector, 2383 struct drm_connector_state *state, 2384 struct drm_property *property, 2385 u64 val) 2386 { 2387 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2388 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state); 2389 2390 if (property == intel_sdvo_connector->tv_format) { 2391 state->tv.mode = intel_sdvo_connector->tv_format_supported[val]; 2392 2393 if (state->crtc) { 2394 struct drm_crtc_state *crtc_state = 2395 drm_atomic_get_new_crtc_state(state->state, state->crtc); 2396 2397 crtc_state->connectors_changed = true; 2398 } 2399 } else if (property == intel_sdvo_connector->top || 2400 property == intel_sdvo_connector->bottom) 2401 /* Cannot set these independent from each other */ 2402 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val; 2403 else if (property == intel_sdvo_connector->left || 2404 property == intel_sdvo_connector->right) 2405 /* Cannot set these independent from each other */ 2406 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val; 2407 else if (property == intel_sdvo_connector->hpos) 2408 sdvo_state->tv.hpos = val; 2409 else if (property == intel_sdvo_connector->vpos) 2410 sdvo_state->tv.vpos = val; 2411 else if (property == intel_sdvo_connector->saturation) 2412 state->tv.saturation = val; 2413 else if (property == intel_sdvo_connector->contrast) 2414 state->tv.contrast = val; 2415 else if (property == intel_sdvo_connector->hue) 2416 state->tv.hue = val; 2417 else if (property == intel_sdvo_connector->brightness) 2418 state->tv.brightness = val; 2419 else if (property == intel_sdvo_connector->sharpness) 2420 sdvo_state->tv.sharpness = val; 2421 else if (property == intel_sdvo_connector->flicker_filter) 2422 sdvo_state->tv.flicker_filter = val; 2423 else if (property == intel_sdvo_connector->flicker_filter_2d) 2424 sdvo_state->tv.flicker_filter_2d = val; 2425 else if (property == intel_sdvo_connector->flicker_filter_adaptive) 2426 sdvo_state->tv.flicker_filter_adaptive = val; 2427 else if (property == intel_sdvo_connector->tv_chroma_filter) 2428 sdvo_state->tv.chroma_filter = val; 2429 else if (property == intel_sdvo_connector->tv_luma_filter) 2430 sdvo_state->tv.luma_filter = val; 2431 else if (property == intel_sdvo_connector->dot_crawl) 2432 sdvo_state->tv.dot_crawl = val; 2433 else 2434 return intel_digital_connector_atomic_set_property(connector, state, property, val); 2435 2436 return 0; 2437 } 2438 2439 static int 2440 intel_sdvo_connector_register(struct drm_connector *connector) 2441 { 2442 struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2443 int ret; 2444 2445 ret = intel_connector_register(connector); 2446 if (ret) 2447 return ret; 2448 2449 return sysfs_create_link(&connector->kdev->kobj, 2450 &sdvo->ddc.dev.kobj, 2451 sdvo->ddc.dev.kobj.name); 2452 } 2453 2454 static void 2455 intel_sdvo_connector_unregister(struct drm_connector *connector) 2456 { 2457 struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2458 2459 sysfs_remove_link(&connector->kdev->kobj, 2460 sdvo->ddc.dev.kobj.name); 2461 intel_connector_unregister(connector); 2462 } 2463 2464 static struct drm_connector_state * 2465 intel_sdvo_connector_duplicate_state(struct drm_connector *connector) 2466 { 2467 struct intel_sdvo_connector_state *state; 2468 2469 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL); 2470 if (!state) 2471 return NULL; 2472 2473 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base); 2474 return &state->base.base; 2475 } 2476 2477 static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 2478 .detect = intel_sdvo_detect, 2479 .fill_modes = drm_helper_probe_single_connector_modes, 2480 .atomic_get_property = intel_sdvo_connector_atomic_get_property, 2481 .atomic_set_property = intel_sdvo_connector_atomic_set_property, 2482 .late_register = intel_sdvo_connector_register, 2483 .early_unregister = intel_sdvo_connector_unregister, 2484 .destroy = intel_connector_destroy, 2485 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2486 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state, 2487 }; 2488 2489 static int intel_sdvo_atomic_check(struct drm_connector *conn, 2490 struct drm_atomic_state *state) 2491 { 2492 struct drm_connector_state *new_conn_state = 2493 drm_atomic_get_new_connector_state(state, conn); 2494 struct drm_connector_state *old_conn_state = 2495 drm_atomic_get_old_connector_state(state, conn); 2496 struct intel_sdvo_connector_state *old_state = 2497 to_intel_sdvo_connector_state(old_conn_state); 2498 struct intel_sdvo_connector_state *new_state = 2499 to_intel_sdvo_connector_state(new_conn_state); 2500 2501 if (new_conn_state->crtc && 2502 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) || 2503 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) { 2504 struct drm_crtc_state *crtc_state = 2505 drm_atomic_get_new_crtc_state(state, 2506 new_conn_state->crtc); 2507 2508 crtc_state->connectors_changed = true; 2509 } 2510 2511 return intel_digital_connector_atomic_check(conn, state); 2512 } 2513 2514 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 2515 .get_modes = intel_sdvo_get_modes, 2516 .mode_valid = intel_sdvo_mode_valid, 2517 .atomic_check = intel_sdvo_atomic_check, 2518 }; 2519 2520 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) 2521 { 2522 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)); 2523 2524 i2c_del_adapter(&intel_sdvo->ddc); 2525 intel_encoder_destroy(encoder); 2526 } 2527 2528 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 2529 .destroy = intel_sdvo_enc_destroy, 2530 }; 2531 2532 static void 2533 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) 2534 { 2535 u16 mask = 0; 2536 unsigned int num_bits; 2537 2538 /* 2539 * Make a mask of outputs less than or equal to our own priority in the 2540 * list. 2541 */ 2542 switch (sdvo->controlled_output) { 2543 case SDVO_OUTPUT_LVDS1: 2544 mask |= SDVO_OUTPUT_LVDS1; 2545 fallthrough; 2546 case SDVO_OUTPUT_LVDS0: 2547 mask |= SDVO_OUTPUT_LVDS0; 2548 fallthrough; 2549 case SDVO_OUTPUT_TMDS1: 2550 mask |= SDVO_OUTPUT_TMDS1; 2551 fallthrough; 2552 case SDVO_OUTPUT_TMDS0: 2553 mask |= SDVO_OUTPUT_TMDS0; 2554 fallthrough; 2555 case SDVO_OUTPUT_RGB1: 2556 mask |= SDVO_OUTPUT_RGB1; 2557 fallthrough; 2558 case SDVO_OUTPUT_RGB0: 2559 mask |= SDVO_OUTPUT_RGB0; 2560 break; 2561 } 2562 2563 /* Count bits to find what number we are in the priority list. */ 2564 mask &= sdvo->caps.output_flags; 2565 num_bits = hweight16(mask); 2566 /* If more than 3 outputs, default to DDC bus 3 for now. */ 2567 if (num_bits > 3) 2568 num_bits = 3; 2569 2570 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 2571 sdvo->ddc_bus = 1 << num_bits; 2572 } 2573 2574 /* 2575 * Choose the appropriate DDC bus for control bus switch command for this 2576 * SDVO output based on the controlled output. 2577 * 2578 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 2579 * outputs, then LVDS outputs. 2580 */ 2581 static void 2582 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, 2583 struct intel_sdvo *sdvo) 2584 { 2585 struct sdvo_device_mapping *mapping; 2586 2587 if (sdvo->port == PORT_B) 2588 mapping = &dev_priv->display.vbt.sdvo_mappings[0]; 2589 else 2590 mapping = &dev_priv->display.vbt.sdvo_mappings[1]; 2591 2592 if (mapping->initialized) 2593 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); 2594 else 2595 intel_sdvo_guess_ddc_bus(sdvo); 2596 } 2597 2598 static void 2599 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, 2600 struct intel_sdvo *sdvo) 2601 { 2602 struct sdvo_device_mapping *mapping; 2603 u8 pin; 2604 2605 if (sdvo->port == PORT_B) 2606 mapping = &dev_priv->display.vbt.sdvo_mappings[0]; 2607 else 2608 mapping = &dev_priv->display.vbt.sdvo_mappings[1]; 2609 2610 if (mapping->initialized && 2611 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin)) 2612 pin = mapping->i2c_pin; 2613 else 2614 pin = GMBUS_PIN_DPB; 2615 2616 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); 2617 2618 /* 2619 * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow 2620 * our code totally fails once we start using gmbus. Hence fall back to 2621 * bit banging for now. 2622 */ 2623 intel_gmbus_force_bit(sdvo->i2c, true); 2624 } 2625 2626 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ 2627 static void 2628 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) 2629 { 2630 intel_gmbus_force_bit(sdvo->i2c, false); 2631 } 2632 2633 static bool 2634 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo) 2635 { 2636 return intel_sdvo_check_supp_encode(intel_sdvo); 2637 } 2638 2639 static u8 2640 intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv, 2641 struct intel_sdvo *sdvo) 2642 { 2643 struct sdvo_device_mapping *my_mapping, *other_mapping; 2644 2645 if (sdvo->port == PORT_B) { 2646 my_mapping = &dev_priv->display.vbt.sdvo_mappings[0]; 2647 other_mapping = &dev_priv->display.vbt.sdvo_mappings[1]; 2648 } else { 2649 my_mapping = &dev_priv->display.vbt.sdvo_mappings[1]; 2650 other_mapping = &dev_priv->display.vbt.sdvo_mappings[0]; 2651 } 2652 2653 /* If the BIOS described our SDVO device, take advantage of it. */ 2654 if (my_mapping->slave_addr) 2655 return my_mapping->slave_addr; 2656 2657 /* 2658 * If the BIOS only described a different SDVO device, use the 2659 * address that it isn't using. 2660 */ 2661 if (other_mapping->slave_addr) { 2662 if (other_mapping->slave_addr == 0x70) 2663 return 0x72; 2664 else 2665 return 0x70; 2666 } 2667 2668 /* 2669 * No SDVO device info is found for another DVO port, 2670 * so use mapping assumption we had before BIOS parsing. 2671 */ 2672 if (sdvo->port == PORT_B) 2673 return 0x70; 2674 else 2675 return 0x72; 2676 } 2677 2678 static int 2679 intel_sdvo_connector_init(struct intel_sdvo_connector *connector, 2680 struct intel_sdvo *encoder) 2681 { 2682 struct drm_connector *drm_connector; 2683 int ret; 2684 2685 drm_connector = &connector->base.base; 2686 ret = drm_connector_init(encoder->base.base.dev, 2687 drm_connector, 2688 &intel_sdvo_connector_funcs, 2689 connector->base.base.connector_type); 2690 if (ret < 0) 2691 return ret; 2692 2693 drm_connector_helper_add(drm_connector, 2694 &intel_sdvo_connector_helper_funcs); 2695 2696 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 2697 connector->base.base.interlace_allowed = true; 2698 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; 2699 2700 intel_connector_attach_encoder(&connector->base, &encoder->base); 2701 2702 return 0; 2703 } 2704 2705 static void 2706 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, 2707 struct intel_sdvo_connector *connector) 2708 { 2709 intel_attach_force_audio_property(&connector->base.base); 2710 if (intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220) 2711 intel_attach_broadcast_rgb_property(&connector->base.base); 2712 intel_attach_aspect_ratio_property(&connector->base.base); 2713 } 2714 2715 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) 2716 { 2717 struct intel_sdvo_connector *sdvo_connector; 2718 struct intel_sdvo_connector_state *conn_state; 2719 2720 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL); 2721 if (!sdvo_connector) 2722 return NULL; 2723 2724 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL); 2725 if (!conn_state) { 2726 kfree(sdvo_connector); 2727 return NULL; 2728 } 2729 2730 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base, 2731 &conn_state->base.base); 2732 2733 INIT_LIST_HEAD(&sdvo_connector->base.panel.fixed_modes); 2734 2735 return sdvo_connector; 2736 } 2737 2738 static bool 2739 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, u16 type) 2740 { 2741 struct drm_encoder *encoder = &intel_sdvo->base.base; 2742 struct drm_connector *connector; 2743 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2744 struct intel_connector *intel_connector; 2745 struct intel_sdvo_connector *intel_sdvo_connector; 2746 2747 DRM_DEBUG_KMS("initialising DVI type 0x%x\n", type); 2748 2749 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2750 if (!intel_sdvo_connector) 2751 return false; 2752 2753 intel_sdvo_connector->output_flag = type; 2754 2755 intel_connector = &intel_sdvo_connector->base; 2756 connector = &intel_connector->base; 2757 if (intel_sdvo_get_hotplug_support(intel_sdvo) & 2758 intel_sdvo_connector->output_flag) { 2759 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; 2760 /* 2761 * Some SDVO devices have one-shot hotplug interrupts. 2762 * Ensure that they get re-enabled when an interrupt happens. 2763 */ 2764 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 2765 intel_encoder->hotplug = intel_sdvo_hotplug; 2766 intel_sdvo_enable_hotplug(intel_encoder); 2767 } else { 2768 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2769 } 2770 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2771 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2772 2773 if (intel_sdvo_is_hdmi_connector(intel_sdvo)) { 2774 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2775 intel_sdvo_connector->is_hdmi = true; 2776 } 2777 2778 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2779 kfree(intel_sdvo_connector); 2780 return false; 2781 } 2782 2783 if (intel_sdvo_connector->is_hdmi) 2784 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); 2785 2786 return true; 2787 } 2788 2789 static bool 2790 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, u16 type) 2791 { 2792 struct drm_encoder *encoder = &intel_sdvo->base.base; 2793 struct drm_connector *connector; 2794 struct intel_connector *intel_connector; 2795 struct intel_sdvo_connector *intel_sdvo_connector; 2796 2797 DRM_DEBUG_KMS("initialising TV type 0x%x\n", type); 2798 2799 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2800 if (!intel_sdvo_connector) 2801 return false; 2802 2803 intel_connector = &intel_sdvo_connector->base; 2804 connector = &intel_connector->base; 2805 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2806 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2807 2808 intel_sdvo_connector->output_flag = type; 2809 2810 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2811 kfree(intel_sdvo_connector); 2812 return false; 2813 } 2814 2815 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2816 goto err; 2817 2818 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2819 goto err; 2820 2821 return true; 2822 2823 err: 2824 intel_connector_destroy(connector); 2825 return false; 2826 } 2827 2828 static bool 2829 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, u16 type) 2830 { 2831 struct drm_encoder *encoder = &intel_sdvo->base.base; 2832 struct drm_connector *connector; 2833 struct intel_connector *intel_connector; 2834 struct intel_sdvo_connector *intel_sdvo_connector; 2835 2836 DRM_DEBUG_KMS("initialising analog type 0x%x\n", type); 2837 2838 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2839 if (!intel_sdvo_connector) 2840 return false; 2841 2842 intel_connector = &intel_sdvo_connector->base; 2843 connector = &intel_connector->base; 2844 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2845 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2846 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2847 2848 intel_sdvo_connector->output_flag = type; 2849 2850 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2851 kfree(intel_sdvo_connector); 2852 return false; 2853 } 2854 2855 return true; 2856 } 2857 2858 static bool 2859 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, u16 type) 2860 { 2861 struct drm_encoder *encoder = &intel_sdvo->base.base; 2862 struct drm_i915_private *i915 = to_i915(encoder->dev); 2863 struct drm_connector *connector; 2864 struct intel_connector *intel_connector; 2865 struct intel_sdvo_connector *intel_sdvo_connector; 2866 2867 DRM_DEBUG_KMS("initialising LVDS type 0x%x\n", type); 2868 2869 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2870 if (!intel_sdvo_connector) 2871 return false; 2872 2873 intel_connector = &intel_sdvo_connector->base; 2874 connector = &intel_connector->base; 2875 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2876 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2877 2878 intel_sdvo_connector->output_flag = type; 2879 2880 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2881 kfree(intel_sdvo_connector); 2882 return false; 2883 } 2884 2885 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2886 goto err; 2887 2888 intel_bios_init_panel(i915, &intel_connector->panel, NULL, NULL); 2889 2890 /* 2891 * Fetch modes from VBT. For SDVO prefer the VBT mode since some 2892 * SDVO->LVDS transcoders can't cope with the EDID mode. 2893 */ 2894 intel_panel_add_vbt_sdvo_fixed_mode(intel_connector); 2895 2896 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 2897 mutex_lock(&i915->drm.mode_config.mutex); 2898 2899 intel_ddc_get_modes(connector, &intel_sdvo->ddc); 2900 intel_panel_add_edid_fixed_modes(intel_connector, false); 2901 2902 mutex_unlock(&i915->drm.mode_config.mutex); 2903 } 2904 2905 intel_panel_init(intel_connector); 2906 2907 if (!intel_panel_preferred_fixed_mode(intel_connector)) 2908 goto err; 2909 2910 return true; 2911 2912 err: 2913 intel_connector_destroy(connector); 2914 return false; 2915 } 2916 2917 static u16 intel_sdvo_filter_output_flags(u16 flags) 2918 { 2919 flags &= SDVO_OUTPUT_MASK; 2920 2921 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2922 if (!(flags & SDVO_OUTPUT_TMDS0)) 2923 flags &= ~SDVO_OUTPUT_TMDS1; 2924 2925 if (!(flags & SDVO_OUTPUT_RGB0)) 2926 flags &= ~SDVO_OUTPUT_RGB1; 2927 2928 if (!(flags & SDVO_OUTPUT_LVDS0)) 2929 flags &= ~SDVO_OUTPUT_LVDS1; 2930 2931 return flags; 2932 } 2933 2934 static bool intel_sdvo_output_init(struct intel_sdvo *sdvo, u16 type) 2935 { 2936 if (type & SDVO_TMDS_MASK) 2937 return intel_sdvo_dvi_init(sdvo, type); 2938 else if (type & SDVO_TV_MASK) 2939 return intel_sdvo_tv_init(sdvo, type); 2940 else if (type & SDVO_RGB_MASK) 2941 return intel_sdvo_analog_init(sdvo, type); 2942 else if (type & SDVO_LVDS_MASK) 2943 return intel_sdvo_lvds_init(sdvo, type); 2944 else 2945 return false; 2946 } 2947 2948 static bool 2949 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo) 2950 { 2951 static const u16 probe_order[] = { 2952 SDVO_OUTPUT_TMDS0, 2953 SDVO_OUTPUT_TMDS1, 2954 /* TV has no XXX1 function block */ 2955 SDVO_OUTPUT_SVID0, 2956 SDVO_OUTPUT_CVBS0, 2957 SDVO_OUTPUT_YPRPB0, 2958 SDVO_OUTPUT_RGB0, 2959 SDVO_OUTPUT_RGB1, 2960 SDVO_OUTPUT_LVDS0, 2961 SDVO_OUTPUT_LVDS1, 2962 }; 2963 struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); 2964 u16 flags; 2965 int i; 2966 2967 flags = intel_sdvo_filter_output_flags(intel_sdvo->caps.output_flags); 2968 2969 if (flags == 0) { 2970 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%04x)\n", 2971 SDVO_NAME(intel_sdvo), intel_sdvo->caps.output_flags); 2972 return false; 2973 } 2974 2975 intel_sdvo->controlled_output = flags; 2976 2977 intel_sdvo_select_ddc_bus(i915, intel_sdvo); 2978 2979 for (i = 0; i < ARRAY_SIZE(probe_order); i++) { 2980 u16 type = flags & probe_order[i]; 2981 2982 if (!type) 2983 continue; 2984 2985 if (!intel_sdvo_output_init(intel_sdvo, type)) 2986 return false; 2987 } 2988 2989 intel_sdvo->base.pipe_mask = ~0; 2990 2991 return true; 2992 } 2993 2994 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) 2995 { 2996 struct drm_device *dev = intel_sdvo->base.base.dev; 2997 struct drm_connector *connector, *tmp; 2998 2999 list_for_each_entry_safe(connector, tmp, 3000 &dev->mode_config.connector_list, head) { 3001 if (intel_attached_encoder(to_intel_connector(connector)) == &intel_sdvo->base) { 3002 drm_connector_unregister(connector); 3003 intel_connector_destroy(connector); 3004 } 3005 } 3006 } 3007 3008 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 3009 struct intel_sdvo_connector *intel_sdvo_connector, 3010 int type) 3011 { 3012 struct drm_device *dev = intel_sdvo->base.base.dev; 3013 struct intel_sdvo_tv_format format; 3014 u32 format_map, i; 3015 3016 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 3017 return false; 3018 3019 BUILD_BUG_ON(sizeof(format) != 6); 3020 if (!intel_sdvo_get_value(intel_sdvo, 3021 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 3022 &format, sizeof(format))) 3023 return false; 3024 3025 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 3026 3027 if (format_map == 0) 3028 return false; 3029 3030 intel_sdvo_connector->format_supported_num = 0; 3031 for (i = 0 ; i < TV_FORMAT_NUM; i++) 3032 if (format_map & (1 << i)) 3033 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 3034 3035 3036 intel_sdvo_connector->tv_format = 3037 drm_property_create(dev, DRM_MODE_PROP_ENUM, 3038 "mode", intel_sdvo_connector->format_supported_num); 3039 if (!intel_sdvo_connector->tv_format) 3040 return false; 3041 3042 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 3043 drm_property_add_enum(intel_sdvo_connector->tv_format, i, 3044 tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 3045 3046 intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0]; 3047 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 3048 intel_sdvo_connector->tv_format, 0); 3049 return true; 3050 3051 } 3052 3053 #define _ENHANCEMENT(state_assignment, name, NAME) do { \ 3054 if (enhancements.name) { \ 3055 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 3056 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 3057 return false; \ 3058 intel_sdvo_connector->name = \ 3059 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ 3060 if (!intel_sdvo_connector->name) return false; \ 3061 state_assignment = response; \ 3062 drm_object_attach_property(&connector->base, \ 3063 intel_sdvo_connector->name, 0); \ 3064 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 3065 data_value[0], data_value[1], response); \ 3066 } \ 3067 } while (0) 3068 3069 #define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME) 3070 3071 static bool 3072 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 3073 struct intel_sdvo_connector *intel_sdvo_connector, 3074 struct intel_sdvo_enhancements_reply enhancements) 3075 { 3076 struct drm_device *dev = intel_sdvo->base.base.dev; 3077 struct drm_connector *connector = &intel_sdvo_connector->base.base; 3078 struct drm_connector_state *conn_state = connector->state; 3079 struct intel_sdvo_connector_state *sdvo_state = 3080 to_intel_sdvo_connector_state(conn_state); 3081 u16 response, data_value[2]; 3082 3083 /* when horizontal overscan is supported, Add the left/right property */ 3084 if (enhancements.overscan_h) { 3085 if (!intel_sdvo_get_value(intel_sdvo, 3086 SDVO_CMD_GET_MAX_OVERSCAN_H, 3087 &data_value, 4)) 3088 return false; 3089 3090 if (!intel_sdvo_get_value(intel_sdvo, 3091 SDVO_CMD_GET_OVERSCAN_H, 3092 &response, 2)) 3093 return false; 3094 3095 sdvo_state->tv.overscan_h = response; 3096 3097 intel_sdvo_connector->max_hscan = data_value[0]; 3098 intel_sdvo_connector->left = 3099 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); 3100 if (!intel_sdvo_connector->left) 3101 return false; 3102 3103 drm_object_attach_property(&connector->base, 3104 intel_sdvo_connector->left, 0); 3105 3106 intel_sdvo_connector->right = 3107 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); 3108 if (!intel_sdvo_connector->right) 3109 return false; 3110 3111 drm_object_attach_property(&connector->base, 3112 intel_sdvo_connector->right, 0); 3113 DRM_DEBUG_KMS("h_overscan: max %d, " 3114 "default %d, current %d\n", 3115 data_value[0], data_value[1], response); 3116 } 3117 3118 if (enhancements.overscan_v) { 3119 if (!intel_sdvo_get_value(intel_sdvo, 3120 SDVO_CMD_GET_MAX_OVERSCAN_V, 3121 &data_value, 4)) 3122 return false; 3123 3124 if (!intel_sdvo_get_value(intel_sdvo, 3125 SDVO_CMD_GET_OVERSCAN_V, 3126 &response, 2)) 3127 return false; 3128 3129 sdvo_state->tv.overscan_v = response; 3130 3131 intel_sdvo_connector->max_vscan = data_value[0]; 3132 intel_sdvo_connector->top = 3133 drm_property_create_range(dev, 0, 3134 "top_margin", 0, data_value[0]); 3135 if (!intel_sdvo_connector->top) 3136 return false; 3137 3138 drm_object_attach_property(&connector->base, 3139 intel_sdvo_connector->top, 0); 3140 3141 intel_sdvo_connector->bottom = 3142 drm_property_create_range(dev, 0, 3143 "bottom_margin", 0, data_value[0]); 3144 if (!intel_sdvo_connector->bottom) 3145 return false; 3146 3147 drm_object_attach_property(&connector->base, 3148 intel_sdvo_connector->bottom, 0); 3149 DRM_DEBUG_KMS("v_overscan: max %d, " 3150 "default %d, current %d\n", 3151 data_value[0], data_value[1], response); 3152 } 3153 3154 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS); 3155 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS); 3156 ENHANCEMENT(&conn_state->tv, saturation, SATURATION); 3157 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST); 3158 ENHANCEMENT(&conn_state->tv, hue, HUE); 3159 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS); 3160 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS); 3161 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER); 3162 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 3163 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D); 3164 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER); 3165 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER); 3166 3167 if (enhancements.dot_crawl) { 3168 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 3169 return false; 3170 3171 sdvo_state->tv.dot_crawl = response & 0x1; 3172 intel_sdvo_connector->dot_crawl = 3173 drm_property_create_range(dev, 0, "dot_crawl", 0, 1); 3174 if (!intel_sdvo_connector->dot_crawl) 3175 return false; 3176 3177 drm_object_attach_property(&connector->base, 3178 intel_sdvo_connector->dot_crawl, 0); 3179 DRM_DEBUG_KMS("dot crawl: current %d\n", response); 3180 } 3181 3182 return true; 3183 } 3184 3185 static bool 3186 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 3187 struct intel_sdvo_connector *intel_sdvo_connector, 3188 struct intel_sdvo_enhancements_reply enhancements) 3189 { 3190 struct drm_device *dev = intel_sdvo->base.base.dev; 3191 struct drm_connector *connector = &intel_sdvo_connector->base.base; 3192 u16 response, data_value[2]; 3193 3194 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS); 3195 3196 return true; 3197 } 3198 #undef ENHANCEMENT 3199 #undef _ENHANCEMENT 3200 3201 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 3202 struct intel_sdvo_connector *intel_sdvo_connector) 3203 { 3204 union { 3205 struct intel_sdvo_enhancements_reply reply; 3206 u16 response; 3207 } enhancements; 3208 3209 BUILD_BUG_ON(sizeof(enhancements) != 2); 3210 3211 if (!intel_sdvo_get_value(intel_sdvo, 3212 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 3213 &enhancements, sizeof(enhancements)) || 3214 enhancements.response == 0) { 3215 DRM_DEBUG_KMS("No enhancement is supported\n"); 3216 return true; 3217 } 3218 3219 if (IS_TV(intel_sdvo_connector)) 3220 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 3221 else if (IS_LVDS(intel_sdvo_connector)) 3222 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 3223 else 3224 return true; 3225 } 3226 3227 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, 3228 struct i2c_msg *msgs, 3229 int num) 3230 { 3231 struct intel_sdvo *sdvo = adapter->algo_data; 3232 3233 if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) 3234 return -EIO; 3235 3236 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); 3237 } 3238 3239 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) 3240 { 3241 struct intel_sdvo *sdvo = adapter->algo_data; 3242 return sdvo->i2c->algo->functionality(sdvo->i2c); 3243 } 3244 3245 static const struct i2c_algorithm intel_sdvo_ddc_proxy = { 3246 .master_xfer = intel_sdvo_ddc_proxy_xfer, 3247 .functionality = intel_sdvo_ddc_proxy_func 3248 }; 3249 3250 static void proxy_lock_bus(struct i2c_adapter *adapter, 3251 unsigned int flags) 3252 { 3253 struct intel_sdvo *sdvo = adapter->algo_data; 3254 sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags); 3255 } 3256 3257 static int proxy_trylock_bus(struct i2c_adapter *adapter, 3258 unsigned int flags) 3259 { 3260 struct intel_sdvo *sdvo = adapter->algo_data; 3261 return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags); 3262 } 3263 3264 static void proxy_unlock_bus(struct i2c_adapter *adapter, 3265 unsigned int flags) 3266 { 3267 struct intel_sdvo *sdvo = adapter->algo_data; 3268 sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags); 3269 } 3270 3271 static const struct i2c_lock_operations proxy_lock_ops = { 3272 .lock_bus = proxy_lock_bus, 3273 .trylock_bus = proxy_trylock_bus, 3274 .unlock_bus = proxy_unlock_bus, 3275 }; 3276 3277 static bool 3278 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, 3279 struct drm_i915_private *dev_priv) 3280 { 3281 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 3282 3283 sdvo->ddc.owner = THIS_MODULE; 3284 sdvo->ddc.class = I2C_CLASS_DDC; 3285 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); 3286 sdvo->ddc.dev.parent = &pdev->dev; 3287 sdvo->ddc.algo_data = sdvo; 3288 sdvo->ddc.algo = &intel_sdvo_ddc_proxy; 3289 sdvo->ddc.lock_ops = &proxy_lock_ops; 3290 3291 return i2c_add_adapter(&sdvo->ddc) == 0; 3292 } 3293 3294 static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv, 3295 enum port port) 3296 { 3297 if (HAS_PCH_SPLIT(dev_priv)) 3298 drm_WARN_ON(&dev_priv->drm, port != PORT_B); 3299 else 3300 drm_WARN_ON(&dev_priv->drm, port != PORT_B && port != PORT_C); 3301 } 3302 3303 bool intel_sdvo_init(struct drm_i915_private *dev_priv, 3304 i915_reg_t sdvo_reg, enum port port) 3305 { 3306 struct intel_encoder *intel_encoder; 3307 struct intel_sdvo *intel_sdvo; 3308 int i; 3309 3310 assert_sdvo_port_valid(dev_priv, port); 3311 3312 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); 3313 if (!intel_sdvo) 3314 return false; 3315 3316 intel_sdvo->sdvo_reg = sdvo_reg; 3317 intel_sdvo->port = port; 3318 intel_sdvo->slave_addr = 3319 intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1; 3320 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo); 3321 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv)) 3322 goto err_i2c_bus; 3323 3324 /* encoder type will be decided later */ 3325 intel_encoder = &intel_sdvo->base; 3326 intel_encoder->type = INTEL_OUTPUT_SDVO; 3327 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 3328 intel_encoder->port = port; 3329 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 3330 &intel_sdvo_enc_funcs, 0, 3331 "SDVO %c", port_name(port)); 3332 3333 /* Read the regs to test if we can talk to the device */ 3334 for (i = 0; i < 0x40; i++) { 3335 u8 byte; 3336 3337 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { 3338 drm_dbg_kms(&dev_priv->drm, 3339 "No SDVO device found on %s\n", 3340 SDVO_NAME(intel_sdvo)); 3341 goto err; 3342 } 3343 } 3344 3345 intel_encoder->compute_config = intel_sdvo_compute_config; 3346 if (HAS_PCH_SPLIT(dev_priv)) { 3347 intel_encoder->disable = pch_disable_sdvo; 3348 intel_encoder->post_disable = pch_post_disable_sdvo; 3349 } else { 3350 intel_encoder->disable = intel_disable_sdvo; 3351 } 3352 intel_encoder->pre_enable = intel_sdvo_pre_enable; 3353 intel_encoder->enable = intel_enable_sdvo; 3354 intel_encoder->get_hw_state = intel_sdvo_get_hw_state; 3355 intel_encoder->get_config = intel_sdvo_get_config; 3356 3357 /* In default case sdvo lvds is false */ 3358 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 3359 goto err; 3360 3361 intel_sdvo->colorimetry_cap = 3362 intel_sdvo_get_colorimetry_cap(intel_sdvo); 3363 3364 if (!intel_sdvo_output_setup(intel_sdvo)) { 3365 drm_dbg_kms(&dev_priv->drm, 3366 "SDVO output failed to setup on %s\n", 3367 SDVO_NAME(intel_sdvo)); 3368 /* Output_setup can leave behind connectors! */ 3369 goto err_output; 3370 } 3371 3372 /* 3373 * Only enable the hotplug irq if we need it, to work around noisy 3374 * hotplug lines. 3375 */ 3376 if (intel_sdvo->hotplug_active) { 3377 if (intel_sdvo->port == PORT_B) 3378 intel_encoder->hpd_pin = HPD_SDVO_B; 3379 else 3380 intel_encoder->hpd_pin = HPD_SDVO_C; 3381 } 3382 3383 /* 3384 * Cloning SDVO with anything is often impossible, since the SDVO 3385 * encoder can request a special input timing mode. And even if that's 3386 * not the case we have evidence that cloning a plain unscaled mode with 3387 * VGA doesn't really work. Furthermore the cloning flags are way too 3388 * simplistic anyway to express such constraints, so just give up on 3389 * cloning for SDVO encoders. 3390 */ 3391 intel_sdvo->base.cloneable = 0; 3392 3393 /* Set the input timing to the screen. Assume always input 0. */ 3394 if (!intel_sdvo_set_target_input(intel_sdvo)) 3395 goto err_output; 3396 3397 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 3398 &intel_sdvo->pixel_clock_min, 3399 &intel_sdvo->pixel_clock_max)) 3400 goto err_output; 3401 3402 drm_dbg_kms(&dev_priv->drm, "%s device VID/DID: %02X:%02X.%02X, " 3403 "clock range %dMHz - %dMHz, " 3404 "input 1: %c, input 2: %c, " 3405 "output 1: %c, output 2: %c\n", 3406 SDVO_NAME(intel_sdvo), 3407 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 3408 intel_sdvo->caps.device_rev_id, 3409 intel_sdvo->pixel_clock_min / 1000, 3410 intel_sdvo->pixel_clock_max / 1000, 3411 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 3412 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 3413 /* check currently supported outputs */ 3414 intel_sdvo->caps.output_flags & 3415 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0 | 3416 SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_SVID0 | 3417 SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_YPRPB0) ? 'Y' : 'N', 3418 intel_sdvo->caps.output_flags & 3419 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1 | 3420 SDVO_OUTPUT_LVDS1) ? 'Y' : 'N'); 3421 return true; 3422 3423 err_output: 3424 intel_sdvo_output_cleanup(intel_sdvo); 3425 3426 err: 3427 drm_encoder_cleanup(&intel_encoder->base); 3428 i2c_del_adapter(&intel_sdvo->ddc); 3429 err_i2c_bus: 3430 intel_sdvo_unselect_i2c_bus(intel_sdvo); 3431 kfree(intel_sdvo); 3432 3433 return false; 3434 } 3435