1 /*
2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
3  * Copyright © 2006-2007 Intel Corporation
4  *   Jesse Barnes <jesse.barnes@intel.com>
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23  * DEALINGS IN THE SOFTWARE.
24  *
25  * Authors:
26  *	Eric Anholt <eric@anholt.net>
27  */
28 
29 #include <linux/delay.h>
30 #include <linux/export.h>
31 #include <linux/i2c.h>
32 #include <linux/slab.h>
33 
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 
38 #include "i915_drv.h"
39 #include "intel_atomic.h"
40 #include "intel_connector.h"
41 #include "intel_crtc.h"
42 #include "intel_de.h"
43 #include "intel_display_types.h"
44 #include "intel_fifo_underrun.h"
45 #include "intel_gmbus.h"
46 #include "intel_hdmi.h"
47 #include "intel_hotplug.h"
48 #include "intel_panel.h"
49 #include "intel_sdvo.h"
50 #include "intel_sdvo_regs.h"
51 
52 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
53 #define SDVO_RGB_MASK  (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
54 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
55 #define SDVO_TV_MASK   (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
56 
57 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
58 			SDVO_TV_MASK)
59 
60 #define IS_TV(c)	(c->output_flag & SDVO_TV_MASK)
61 #define IS_TMDS(c)	(c->output_flag & SDVO_TMDS_MASK)
62 #define IS_LVDS(c)	(c->output_flag & SDVO_LVDS_MASK)
63 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
64 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
65 
66 
67 static const char * const tv_format_names[] = {
68 	"NTSC_M"   , "NTSC_J"  , "NTSC_443",
69 	"PAL_B"    , "PAL_D"   , "PAL_G"   ,
70 	"PAL_H"    , "PAL_I"   , "PAL_M"   ,
71 	"PAL_N"    , "PAL_NC"  , "PAL_60"  ,
72 	"SECAM_B"  , "SECAM_D" , "SECAM_G" ,
73 	"SECAM_K"  , "SECAM_K1", "SECAM_L" ,
74 	"SECAM_60"
75 };
76 
77 #define TV_FORMAT_NUM  ARRAY_SIZE(tv_format_names)
78 
79 struct intel_sdvo {
80 	struct intel_encoder base;
81 
82 	struct i2c_adapter *i2c;
83 	u8 slave_addr;
84 
85 	struct i2c_adapter ddc;
86 
87 	/* Register for the SDVO device: SDVOB or SDVOC */
88 	i915_reg_t sdvo_reg;
89 
90 	/* Active outputs controlled by this SDVO output */
91 	u16 controlled_output;
92 
93 	/*
94 	 * Capabilities of the SDVO device returned by
95 	 * intel_sdvo_get_capabilities()
96 	 */
97 	struct intel_sdvo_caps caps;
98 
99 	u8 colorimetry_cap;
100 
101 	/* Pixel clock limitations reported by the SDVO device, in kHz */
102 	int pixel_clock_min, pixel_clock_max;
103 
104 	/*
105 	* For multiple function SDVO device,
106 	* this is for current attached outputs.
107 	*/
108 	u16 attached_output;
109 
110 	/*
111 	 * Hotplug activation bits for this device
112 	 */
113 	u16 hotplug_active;
114 
115 	enum port port;
116 
117 	bool has_hdmi_monitor;
118 	bool has_hdmi_audio;
119 
120 	/* DDC bus used by this SDVO encoder */
121 	u8 ddc_bus;
122 
123 	/*
124 	 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
125 	 */
126 	u8 dtd_sdvo_flags;
127 };
128 
129 struct intel_sdvo_connector {
130 	struct intel_connector base;
131 
132 	/* Mark the type of connector */
133 	u16 output_flag;
134 
135 	/* This contains all current supported TV format */
136 	u8 tv_format_supported[TV_FORMAT_NUM];
137 	int   format_supported_num;
138 	struct drm_property *tv_format;
139 
140 	/* add the property for the SDVO-TV */
141 	struct drm_property *left;
142 	struct drm_property *right;
143 	struct drm_property *top;
144 	struct drm_property *bottom;
145 	struct drm_property *hpos;
146 	struct drm_property *vpos;
147 	struct drm_property *contrast;
148 	struct drm_property *saturation;
149 	struct drm_property *hue;
150 	struct drm_property *sharpness;
151 	struct drm_property *flicker_filter;
152 	struct drm_property *flicker_filter_adaptive;
153 	struct drm_property *flicker_filter_2d;
154 	struct drm_property *tv_chroma_filter;
155 	struct drm_property *tv_luma_filter;
156 	struct drm_property *dot_crawl;
157 
158 	/* add the property for the SDVO-TV/LVDS */
159 	struct drm_property *brightness;
160 
161 	/* this is to get the range of margin.*/
162 	u32 max_hscan, max_vscan;
163 
164 	/**
165 	 * This is set if we treat the device as HDMI, instead of DVI.
166 	 */
167 	bool is_hdmi;
168 };
169 
170 struct intel_sdvo_connector_state {
171 	/* base.base: tv.saturation/contrast/hue/brightness */
172 	struct intel_digital_connector_state base;
173 
174 	struct {
175 		unsigned overscan_h, overscan_v, hpos, vpos, sharpness;
176 		unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive;
177 		unsigned chroma_filter, luma_filter, dot_crawl;
178 	} tv;
179 };
180 
181 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
182 {
183 	return container_of(encoder, struct intel_sdvo, base);
184 }
185 
186 static struct intel_sdvo *intel_attached_sdvo(struct intel_connector *connector)
187 {
188 	return to_sdvo(intel_attached_encoder(connector));
189 }
190 
191 static struct intel_sdvo_connector *
192 to_intel_sdvo_connector(struct drm_connector *connector)
193 {
194 	return container_of(connector, struct intel_sdvo_connector, base.base);
195 }
196 
197 #define to_intel_sdvo_connector_state(conn_state) \
198 	container_of((conn_state), struct intel_sdvo_connector_state, base.base)
199 
200 static bool
201 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, u16 flags);
202 static bool
203 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
204 			      struct intel_sdvo_connector *intel_sdvo_connector,
205 			      int type);
206 static bool
207 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
208 				   struct intel_sdvo_connector *intel_sdvo_connector);
209 
210 /*
211  * Writes the SDVOB or SDVOC with the given value, but always writes both
212  * SDVOB and SDVOC to work around apparent hardware issues (according to
213  * comments in the BIOS).
214  */
215 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
216 {
217 	struct drm_device *dev = intel_sdvo->base.base.dev;
218 	struct drm_i915_private *dev_priv = to_i915(dev);
219 	u32 bval = val, cval = val;
220 	int i;
221 
222 	if (HAS_PCH_SPLIT(dev_priv)) {
223 		intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val);
224 		intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg);
225 		/*
226 		 * HW workaround, need to write this twice for issue
227 		 * that may result in first write getting masked.
228 		 */
229 		if (HAS_PCH_IBX(dev_priv)) {
230 			intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val);
231 			intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg);
232 		}
233 		return;
234 	}
235 
236 	if (intel_sdvo->port == PORT_B)
237 		cval = intel_de_read(dev_priv, GEN3_SDVOC);
238 	else
239 		bval = intel_de_read(dev_priv, GEN3_SDVOB);
240 
241 	/*
242 	 * Write the registers twice for luck. Sometimes,
243 	 * writing them only once doesn't appear to 'stick'.
244 	 * The BIOS does this too. Yay, magic
245 	 */
246 	for (i = 0; i < 2; i++) {
247 		intel_de_write(dev_priv, GEN3_SDVOB, bval);
248 		intel_de_posting_read(dev_priv, GEN3_SDVOB);
249 
250 		intel_de_write(dev_priv, GEN3_SDVOC, cval);
251 		intel_de_posting_read(dev_priv, GEN3_SDVOC);
252 	}
253 }
254 
255 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
256 {
257 	struct i2c_msg msgs[] = {
258 		{
259 			.addr = intel_sdvo->slave_addr,
260 			.flags = 0,
261 			.len = 1,
262 			.buf = &addr,
263 		},
264 		{
265 			.addr = intel_sdvo->slave_addr,
266 			.flags = I2C_M_RD,
267 			.len = 1,
268 			.buf = ch,
269 		}
270 	};
271 	int ret;
272 
273 	if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
274 		return true;
275 
276 	DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
277 	return false;
278 }
279 
280 #define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ }
281 
282 /** Mapping of command numbers to names, for debug output */
283 static const struct {
284 	u8 cmd;
285 	const char *name;
286 } __attribute__ ((packed)) sdvo_cmd_names[] = {
287 	SDVO_CMD_NAME_ENTRY(RESET),
288 	SDVO_CMD_NAME_ENTRY(GET_DEVICE_CAPS),
289 	SDVO_CMD_NAME_ENTRY(GET_FIRMWARE_REV),
290 	SDVO_CMD_NAME_ENTRY(GET_TRAINED_INPUTS),
291 	SDVO_CMD_NAME_ENTRY(GET_ACTIVE_OUTPUTS),
292 	SDVO_CMD_NAME_ENTRY(SET_ACTIVE_OUTPUTS),
293 	SDVO_CMD_NAME_ENTRY(GET_IN_OUT_MAP),
294 	SDVO_CMD_NAME_ENTRY(SET_IN_OUT_MAP),
295 	SDVO_CMD_NAME_ENTRY(GET_ATTACHED_DISPLAYS),
296 	SDVO_CMD_NAME_ENTRY(GET_HOT_PLUG_SUPPORT),
297 	SDVO_CMD_NAME_ENTRY(SET_ACTIVE_HOT_PLUG),
298 	SDVO_CMD_NAME_ENTRY(GET_ACTIVE_HOT_PLUG),
299 	SDVO_CMD_NAME_ENTRY(GET_INTERRUPT_EVENT_SOURCE),
300 	SDVO_CMD_NAME_ENTRY(SET_TARGET_INPUT),
301 	SDVO_CMD_NAME_ENTRY(SET_TARGET_OUTPUT),
302 	SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART1),
303 	SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART2),
304 	SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART1),
305 	SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART2),
306 	SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART1),
307 	SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART2),
308 	SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART1),
309 	SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART2),
310 	SDVO_CMD_NAME_ENTRY(CREATE_PREFERRED_INPUT_TIMING),
311 	SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART1),
312 	SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART2),
313 	SDVO_CMD_NAME_ENTRY(GET_INPUT_PIXEL_CLOCK_RANGE),
314 	SDVO_CMD_NAME_ENTRY(GET_OUTPUT_PIXEL_CLOCK_RANGE),
315 	SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_CLOCK_RATE_MULTS),
316 	SDVO_CMD_NAME_ENTRY(GET_CLOCK_RATE_MULT),
317 	SDVO_CMD_NAME_ENTRY(SET_CLOCK_RATE_MULT),
318 	SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_TV_FORMATS),
319 	SDVO_CMD_NAME_ENTRY(GET_TV_FORMAT),
320 	SDVO_CMD_NAME_ENTRY(SET_TV_FORMAT),
321 	SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_POWER_STATES),
322 	SDVO_CMD_NAME_ENTRY(GET_POWER_STATE),
323 	SDVO_CMD_NAME_ENTRY(SET_ENCODER_POWER_STATE),
324 	SDVO_CMD_NAME_ENTRY(SET_DISPLAY_POWER_STATE),
325 	SDVO_CMD_NAME_ENTRY(SET_CONTROL_BUS_SWITCH),
326 	SDVO_CMD_NAME_ENTRY(GET_SDTV_RESOLUTION_SUPPORT),
327 	SDVO_CMD_NAME_ENTRY(GET_SCALED_HDTV_RESOLUTION_SUPPORT),
328 	SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_ENHANCEMENTS),
329 
330 	/* Add the op code for SDVO enhancements */
331 	SDVO_CMD_NAME_ENTRY(GET_MAX_HPOS),
332 	SDVO_CMD_NAME_ENTRY(GET_HPOS),
333 	SDVO_CMD_NAME_ENTRY(SET_HPOS),
334 	SDVO_CMD_NAME_ENTRY(GET_MAX_VPOS),
335 	SDVO_CMD_NAME_ENTRY(GET_VPOS),
336 	SDVO_CMD_NAME_ENTRY(SET_VPOS),
337 	SDVO_CMD_NAME_ENTRY(GET_MAX_SATURATION),
338 	SDVO_CMD_NAME_ENTRY(GET_SATURATION),
339 	SDVO_CMD_NAME_ENTRY(SET_SATURATION),
340 	SDVO_CMD_NAME_ENTRY(GET_MAX_HUE),
341 	SDVO_CMD_NAME_ENTRY(GET_HUE),
342 	SDVO_CMD_NAME_ENTRY(SET_HUE),
343 	SDVO_CMD_NAME_ENTRY(GET_MAX_CONTRAST),
344 	SDVO_CMD_NAME_ENTRY(GET_CONTRAST),
345 	SDVO_CMD_NAME_ENTRY(SET_CONTRAST),
346 	SDVO_CMD_NAME_ENTRY(GET_MAX_BRIGHTNESS),
347 	SDVO_CMD_NAME_ENTRY(GET_BRIGHTNESS),
348 	SDVO_CMD_NAME_ENTRY(SET_BRIGHTNESS),
349 	SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_H),
350 	SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_H),
351 	SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_H),
352 	SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_V),
353 	SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_V),
354 	SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_V),
355 	SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER),
356 	SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER),
357 	SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER),
358 	SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_ADAPTIVE),
359 	SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_ADAPTIVE),
360 	SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_ADAPTIVE),
361 	SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_2D),
362 	SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_2D),
363 	SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_2D),
364 	SDVO_CMD_NAME_ENTRY(GET_MAX_SHARPNESS),
365 	SDVO_CMD_NAME_ENTRY(GET_SHARPNESS),
366 	SDVO_CMD_NAME_ENTRY(SET_SHARPNESS),
367 	SDVO_CMD_NAME_ENTRY(GET_DOT_CRAWL),
368 	SDVO_CMD_NAME_ENTRY(SET_DOT_CRAWL),
369 	SDVO_CMD_NAME_ENTRY(GET_MAX_TV_CHROMA_FILTER),
370 	SDVO_CMD_NAME_ENTRY(GET_TV_CHROMA_FILTER),
371 	SDVO_CMD_NAME_ENTRY(SET_TV_CHROMA_FILTER),
372 	SDVO_CMD_NAME_ENTRY(GET_MAX_TV_LUMA_FILTER),
373 	SDVO_CMD_NAME_ENTRY(GET_TV_LUMA_FILTER),
374 	SDVO_CMD_NAME_ENTRY(SET_TV_LUMA_FILTER),
375 
376 	/* HDMI op code */
377 	SDVO_CMD_NAME_ENTRY(GET_SUPP_ENCODE),
378 	SDVO_CMD_NAME_ENTRY(GET_ENCODE),
379 	SDVO_CMD_NAME_ENTRY(SET_ENCODE),
380 	SDVO_CMD_NAME_ENTRY(SET_PIXEL_REPLI),
381 	SDVO_CMD_NAME_ENTRY(GET_PIXEL_REPLI),
382 	SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY_CAP),
383 	SDVO_CMD_NAME_ENTRY(SET_COLORIMETRY),
384 	SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY),
385 	SDVO_CMD_NAME_ENTRY(GET_AUDIO_ENCRYPT_PREFER),
386 	SDVO_CMD_NAME_ENTRY(SET_AUDIO_STAT),
387 	SDVO_CMD_NAME_ENTRY(GET_AUDIO_STAT),
388 	SDVO_CMD_NAME_ENTRY(GET_HBUF_INDEX),
389 	SDVO_CMD_NAME_ENTRY(SET_HBUF_INDEX),
390 	SDVO_CMD_NAME_ENTRY(GET_HBUF_INFO),
391 	SDVO_CMD_NAME_ENTRY(GET_HBUF_AV_SPLIT),
392 	SDVO_CMD_NAME_ENTRY(SET_HBUF_AV_SPLIT),
393 	SDVO_CMD_NAME_ENTRY(GET_HBUF_TXRATE),
394 	SDVO_CMD_NAME_ENTRY(SET_HBUF_TXRATE),
395 	SDVO_CMD_NAME_ENTRY(SET_HBUF_DATA),
396 	SDVO_CMD_NAME_ENTRY(GET_HBUF_DATA),
397 };
398 
399 #undef SDVO_CMD_NAME_ENTRY
400 
401 static const char *sdvo_cmd_name(u8 cmd)
402 {
403 	int i;
404 
405 	for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
406 		if (cmd == sdvo_cmd_names[i].cmd)
407 			return sdvo_cmd_names[i].name;
408 	}
409 
410 	return NULL;
411 }
412 
413 #define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC")
414 
415 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
416 				   const void *args, int args_len)
417 {
418 	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
419 	const char *cmd_name;
420 	int i, pos = 0;
421 	char buffer[64];
422 
423 #define BUF_PRINT(args...) \
424 	pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args)
425 
426 	for (i = 0; i < args_len; i++) {
427 		BUF_PRINT("%02X ", ((u8 *)args)[i]);
428 	}
429 	for (; i < 8; i++) {
430 		BUF_PRINT("   ");
431 	}
432 
433 	cmd_name = sdvo_cmd_name(cmd);
434 	if (cmd_name)
435 		BUF_PRINT("(%s)", cmd_name);
436 	else
437 		BUF_PRINT("(%02X)", cmd);
438 
439 	drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
440 #undef BUF_PRINT
441 
442 	DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
443 }
444 
445 static const char * const cmd_status_names[] = {
446 	[SDVO_CMD_STATUS_POWER_ON] = "Power on",
447 	[SDVO_CMD_STATUS_SUCCESS] = "Success",
448 	[SDVO_CMD_STATUS_NOTSUPP] = "Not supported",
449 	[SDVO_CMD_STATUS_INVALID_ARG] = "Invalid arg",
450 	[SDVO_CMD_STATUS_PENDING] = "Pending",
451 	[SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED] = "Target not specified",
452 	[SDVO_CMD_STATUS_SCALING_NOT_SUPP] = "Scaling not supported",
453 };
454 
455 static const char *sdvo_cmd_status(u8 status)
456 {
457 	if (status < ARRAY_SIZE(cmd_status_names))
458 		return cmd_status_names[status];
459 	else
460 		return NULL;
461 }
462 
463 static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
464 				   const void *args, int args_len,
465 				   bool unlocked)
466 {
467 	u8 *buf, status;
468 	struct i2c_msg *msgs;
469 	int i, ret = true;
470 
471 	/* Would be simpler to allocate both in one go ? */
472 	buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
473 	if (!buf)
474 		return false;
475 
476 	msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
477 	if (!msgs) {
478 		kfree(buf);
479 		return false;
480 	}
481 
482 	intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
483 
484 	for (i = 0; i < args_len; i++) {
485 		msgs[i].addr = intel_sdvo->slave_addr;
486 		msgs[i].flags = 0;
487 		msgs[i].len = 2;
488 		msgs[i].buf = buf + 2 *i;
489 		buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
490 		buf[2*i + 1] = ((u8*)args)[i];
491 	}
492 	msgs[i].addr = intel_sdvo->slave_addr;
493 	msgs[i].flags = 0;
494 	msgs[i].len = 2;
495 	msgs[i].buf = buf + 2*i;
496 	buf[2*i + 0] = SDVO_I2C_OPCODE;
497 	buf[2*i + 1] = cmd;
498 
499 	/* the following two are to read the response */
500 	status = SDVO_I2C_CMD_STATUS;
501 	msgs[i+1].addr = intel_sdvo->slave_addr;
502 	msgs[i+1].flags = 0;
503 	msgs[i+1].len = 1;
504 	msgs[i+1].buf = &status;
505 
506 	msgs[i+2].addr = intel_sdvo->slave_addr;
507 	msgs[i+2].flags = I2C_M_RD;
508 	msgs[i+2].len = 1;
509 	msgs[i+2].buf = &status;
510 
511 	if (unlocked)
512 		ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
513 	else
514 		ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3);
515 	if (ret < 0) {
516 		DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
517 		ret = false;
518 		goto out;
519 	}
520 	if (ret != i+3) {
521 		/* failure in I2C transfer */
522 		DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
523 		ret = false;
524 	}
525 
526 out:
527 	kfree(msgs);
528 	kfree(buf);
529 	return ret;
530 }
531 
532 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
533 				 const void *args, int args_len)
534 {
535 	return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true);
536 }
537 
538 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
539 				     void *response, int response_len)
540 {
541 	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
542 	const char *cmd_status;
543 	u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
544 	u8 status;
545 	int i, pos = 0;
546 	char buffer[64];
547 
548 	buffer[0] = '\0';
549 
550 	/*
551 	 * The documentation states that all commands will be
552 	 * processed within 15µs, and that we need only poll
553 	 * the status byte a maximum of 3 times in order for the
554 	 * command to be complete.
555 	 *
556 	 * Check 5 times in case the hardware failed to read the docs.
557 	 *
558 	 * Also beware that the first response by many devices is to
559 	 * reply PENDING and stall for time. TVs are notorious for
560 	 * requiring longer than specified to complete their replies.
561 	 * Originally (in the DDX long ago), the delay was only ever 15ms
562 	 * with an additional delay of 30ms applied for TVs added later after
563 	 * many experiments. To accommodate both sets of delays, we do a
564 	 * sequence of slow checks if the device is falling behind and fails
565 	 * to reply within 5*15µs.
566 	 */
567 	if (!intel_sdvo_read_byte(intel_sdvo,
568 				  SDVO_I2C_CMD_STATUS,
569 				  &status))
570 		goto log_fail;
571 
572 	while ((status == SDVO_CMD_STATUS_PENDING ||
573 		status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
574 		if (retry < 10)
575 			msleep(15);
576 		else
577 			udelay(15);
578 
579 		if (!intel_sdvo_read_byte(intel_sdvo,
580 					  SDVO_I2C_CMD_STATUS,
581 					  &status))
582 			goto log_fail;
583 	}
584 
585 #define BUF_PRINT(args...) \
586 	pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args)
587 
588 	cmd_status = sdvo_cmd_status(status);
589 	if (cmd_status)
590 		BUF_PRINT("(%s)", cmd_status);
591 	else
592 		BUF_PRINT("(??? %d)", status);
593 
594 	if (status != SDVO_CMD_STATUS_SUCCESS)
595 		goto log_fail;
596 
597 	/* Read the command response */
598 	for (i = 0; i < response_len; i++) {
599 		if (!intel_sdvo_read_byte(intel_sdvo,
600 					  SDVO_I2C_RETURN_0 + i,
601 					  &((u8 *)response)[i]))
602 			goto log_fail;
603 		BUF_PRINT(" %02X", ((u8 *)response)[i]);
604 	}
605 
606 	drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
607 #undef BUF_PRINT
608 
609 	DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
610 	return true;
611 
612 log_fail:
613 	DRM_DEBUG_KMS("%s: R: ... failed %s\n",
614 		      SDVO_NAME(intel_sdvo), buffer);
615 	return false;
616 }
617 
618 static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode)
619 {
620 	if (adjusted_mode->crtc_clock >= 100000)
621 		return 1;
622 	else if (adjusted_mode->crtc_clock >= 50000)
623 		return 2;
624 	else
625 		return 4;
626 }
627 
628 static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
629 						u8 ddc_bus)
630 {
631 	/* This must be the immediately preceding write before the i2c xfer */
632 	return __intel_sdvo_write_cmd(intel_sdvo,
633 				      SDVO_CMD_SET_CONTROL_BUS_SWITCH,
634 				      &ddc_bus, 1, false);
635 }
636 
637 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
638 {
639 	if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
640 		return false;
641 
642 	return intel_sdvo_read_response(intel_sdvo, NULL, 0);
643 }
644 
645 static bool
646 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
647 {
648 	if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
649 		return false;
650 
651 	return intel_sdvo_read_response(intel_sdvo, value, len);
652 }
653 
654 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
655 {
656 	struct intel_sdvo_set_target_input_args targets = {0};
657 	return intel_sdvo_set_value(intel_sdvo,
658 				    SDVO_CMD_SET_TARGET_INPUT,
659 				    &targets, sizeof(targets));
660 }
661 
662 /*
663  * Return whether each input is trained.
664  *
665  * This function is making an assumption about the layout of the response,
666  * which should be checked against the docs.
667  */
668 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
669 {
670 	struct intel_sdvo_get_trained_inputs_response response;
671 
672 	BUILD_BUG_ON(sizeof(response) != 1);
673 	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
674 				  &response, sizeof(response)))
675 		return false;
676 
677 	*input_1 = response.input0_trained;
678 	*input_2 = response.input1_trained;
679 	return true;
680 }
681 
682 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
683 					  u16 outputs)
684 {
685 	return intel_sdvo_set_value(intel_sdvo,
686 				    SDVO_CMD_SET_ACTIVE_OUTPUTS,
687 				    &outputs, sizeof(outputs));
688 }
689 
690 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
691 					  u16 *outputs)
692 {
693 	return intel_sdvo_get_value(intel_sdvo,
694 				    SDVO_CMD_GET_ACTIVE_OUTPUTS,
695 				    outputs, sizeof(*outputs));
696 }
697 
698 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
699 					       int mode)
700 {
701 	u8 state = SDVO_ENCODER_STATE_ON;
702 
703 	switch (mode) {
704 	case DRM_MODE_DPMS_ON:
705 		state = SDVO_ENCODER_STATE_ON;
706 		break;
707 	case DRM_MODE_DPMS_STANDBY:
708 		state = SDVO_ENCODER_STATE_STANDBY;
709 		break;
710 	case DRM_MODE_DPMS_SUSPEND:
711 		state = SDVO_ENCODER_STATE_SUSPEND;
712 		break;
713 	case DRM_MODE_DPMS_OFF:
714 		state = SDVO_ENCODER_STATE_OFF;
715 		break;
716 	}
717 
718 	return intel_sdvo_set_value(intel_sdvo,
719 				    SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
720 }
721 
722 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
723 						   int *clock_min,
724 						   int *clock_max)
725 {
726 	struct intel_sdvo_pixel_clock_range clocks;
727 
728 	BUILD_BUG_ON(sizeof(clocks) != 4);
729 	if (!intel_sdvo_get_value(intel_sdvo,
730 				  SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
731 				  &clocks, sizeof(clocks)))
732 		return false;
733 
734 	/* Convert the values from units of 10 kHz to kHz. */
735 	*clock_min = clocks.min * 10;
736 	*clock_max = clocks.max * 10;
737 	return true;
738 }
739 
740 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
741 					 u16 outputs)
742 {
743 	return intel_sdvo_set_value(intel_sdvo,
744 				    SDVO_CMD_SET_TARGET_OUTPUT,
745 				    &outputs, sizeof(outputs));
746 }
747 
748 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
749 				  struct intel_sdvo_dtd *dtd)
750 {
751 	return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
752 		intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
753 }
754 
755 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
756 				  struct intel_sdvo_dtd *dtd)
757 {
758 	return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
759 		intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
760 }
761 
762 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
763 					 struct intel_sdvo_dtd *dtd)
764 {
765 	return intel_sdvo_set_timing(intel_sdvo,
766 				     SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
767 }
768 
769 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
770 					 struct intel_sdvo_dtd *dtd)
771 {
772 	return intel_sdvo_set_timing(intel_sdvo,
773 				     SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
774 }
775 
776 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
777 					struct intel_sdvo_dtd *dtd)
778 {
779 	return intel_sdvo_get_timing(intel_sdvo,
780 				     SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
781 }
782 
783 static bool
784 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
785 					 struct intel_sdvo_connector *intel_sdvo_connector,
786 					 u16 clock,
787 					 u16 width,
788 					 u16 height)
789 {
790 	struct intel_sdvo_preferred_input_timing_args args;
791 
792 	memset(&args, 0, sizeof(args));
793 	args.clock = clock;
794 	args.width = width;
795 	args.height = height;
796 	args.interlace = 0;
797 
798 	if (IS_LVDS(intel_sdvo_connector)) {
799 		const struct drm_display_mode *fixed_mode =
800 			intel_sdvo_connector->base.panel.fixed_mode;
801 
802 		if (fixed_mode->hdisplay != width ||
803 		    fixed_mode->vdisplay != height)
804 			args.scaled = 1;
805 	}
806 
807 	return intel_sdvo_set_value(intel_sdvo,
808 				    SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
809 				    &args, sizeof(args));
810 }
811 
812 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
813 						  struct intel_sdvo_dtd *dtd)
814 {
815 	BUILD_BUG_ON(sizeof(dtd->part1) != 8);
816 	BUILD_BUG_ON(sizeof(dtd->part2) != 8);
817 	return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
818 				    &dtd->part1, sizeof(dtd->part1)) &&
819 		intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
820 				     &dtd->part2, sizeof(dtd->part2));
821 }
822 
823 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
824 {
825 	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
826 }
827 
828 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
829 					 const struct drm_display_mode *mode)
830 {
831 	u16 width, height;
832 	u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len;
833 	u16 h_sync_offset, v_sync_offset;
834 	int mode_clock;
835 
836 	memset(dtd, 0, sizeof(*dtd));
837 
838 	width = mode->hdisplay;
839 	height = mode->vdisplay;
840 
841 	/* do some mode translations */
842 	h_blank_len = mode->htotal - mode->hdisplay;
843 	h_sync_len = mode->hsync_end - mode->hsync_start;
844 
845 	v_blank_len = mode->vtotal - mode->vdisplay;
846 	v_sync_len = mode->vsync_end - mode->vsync_start;
847 
848 	h_sync_offset = mode->hsync_start - mode->hdisplay;
849 	v_sync_offset = mode->vsync_start - mode->vdisplay;
850 
851 	mode_clock = mode->clock;
852 	mode_clock /= 10;
853 	dtd->part1.clock = mode_clock;
854 
855 	dtd->part1.h_active = width & 0xff;
856 	dtd->part1.h_blank = h_blank_len & 0xff;
857 	dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
858 		((h_blank_len >> 8) & 0xf);
859 	dtd->part1.v_active = height & 0xff;
860 	dtd->part1.v_blank = v_blank_len & 0xff;
861 	dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
862 		((v_blank_len >> 8) & 0xf);
863 
864 	dtd->part2.h_sync_off = h_sync_offset & 0xff;
865 	dtd->part2.h_sync_width = h_sync_len & 0xff;
866 	dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
867 		(v_sync_len & 0xf);
868 	dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
869 		((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
870 		((v_sync_len & 0x30) >> 4);
871 
872 	dtd->part2.dtd_flags = 0x18;
873 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
874 		dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
875 	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
876 		dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
877 	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
878 		dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
879 
880 	dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
881 }
882 
883 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
884 					 const struct intel_sdvo_dtd *dtd)
885 {
886 	struct drm_display_mode mode = {};
887 
888 	mode.hdisplay = dtd->part1.h_active;
889 	mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
890 	mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
891 	mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
892 	mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
893 	mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
894 	mode.htotal = mode.hdisplay + dtd->part1.h_blank;
895 	mode.htotal += (dtd->part1.h_high & 0xf) << 8;
896 
897 	mode.vdisplay = dtd->part1.v_active;
898 	mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
899 	mode.vsync_start = mode.vdisplay;
900 	mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
901 	mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
902 	mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
903 	mode.vsync_end = mode.vsync_start +
904 		(dtd->part2.v_sync_off_width & 0xf);
905 	mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
906 	mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
907 	mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
908 
909 	mode.clock = dtd->part1.clock * 10;
910 
911 	if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
912 		mode.flags |= DRM_MODE_FLAG_INTERLACE;
913 	if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
914 		mode.flags |= DRM_MODE_FLAG_PHSYNC;
915 	else
916 		mode.flags |= DRM_MODE_FLAG_NHSYNC;
917 	if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
918 		mode.flags |= DRM_MODE_FLAG_PVSYNC;
919 	else
920 		mode.flags |= DRM_MODE_FLAG_NVSYNC;
921 
922 	drm_mode_set_crtcinfo(&mode, 0);
923 
924 	drm_mode_copy(pmode, &mode);
925 }
926 
927 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
928 {
929 	struct intel_sdvo_encode encode;
930 
931 	BUILD_BUG_ON(sizeof(encode) != 2);
932 	return intel_sdvo_get_value(intel_sdvo,
933 				  SDVO_CMD_GET_SUPP_ENCODE,
934 				  &encode, sizeof(encode));
935 }
936 
937 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
938 				  u8 mode)
939 {
940 	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
941 }
942 
943 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
944 				       u8 mode)
945 {
946 	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
947 }
948 
949 static bool intel_sdvo_set_pixel_replication(struct intel_sdvo *intel_sdvo,
950 					     u8 pixel_repeat)
951 {
952 	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_PIXEL_REPLI,
953 				    &pixel_repeat, 1);
954 }
955 
956 static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo,
957 				       u8 audio_state)
958 {
959 	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT,
960 				    &audio_state, 1);
961 }
962 
963 static bool intel_sdvo_get_hbuf_size(struct intel_sdvo *intel_sdvo,
964 				     u8 *hbuf_size)
965 {
966 	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
967 				  hbuf_size, 1))
968 		return false;
969 
970 	/* Buffer size is 0 based, hooray! However zero means zero. */
971 	if (*hbuf_size)
972 		(*hbuf_size)++;
973 
974 	return true;
975 }
976 
977 #if 0
978 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
979 {
980 	int i, j;
981 	u8 set_buf_index[2];
982 	u8 av_split;
983 	u8 buf_size;
984 	u8 buf[48];
985 	u8 *pos;
986 
987 	intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
988 
989 	for (i = 0; i <= av_split; i++) {
990 		set_buf_index[0] = i; set_buf_index[1] = 0;
991 		intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
992 				     set_buf_index, 2);
993 		intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
994 		intel_sdvo_read_response(encoder, &buf_size, 1);
995 
996 		pos = buf;
997 		for (j = 0; j <= buf_size; j += 8) {
998 			intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
999 					     NULL, 0);
1000 			intel_sdvo_read_response(encoder, pos, 8);
1001 			pos += 8;
1002 		}
1003 	}
1004 }
1005 #endif
1006 
1007 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
1008 				       unsigned int if_index, u8 tx_rate,
1009 				       const u8 *data, unsigned int length)
1010 {
1011 	u8 set_buf_index[2] = { if_index, 0 };
1012 	u8 hbuf_size, tmp[8];
1013 	int i;
1014 
1015 	if (!intel_sdvo_set_value(intel_sdvo,
1016 				  SDVO_CMD_SET_HBUF_INDEX,
1017 				  set_buf_index, 2))
1018 		return false;
1019 
1020 	if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
1021 		return false;
1022 
1023 	DRM_DEBUG_KMS("writing sdvo hbuf: %i, length %u, hbuf_size: %i\n",
1024 		      if_index, length, hbuf_size);
1025 
1026 	if (hbuf_size < length)
1027 		return false;
1028 
1029 	for (i = 0; i < hbuf_size; i += 8) {
1030 		memset(tmp, 0, 8);
1031 		if (i < length)
1032 			memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
1033 
1034 		if (!intel_sdvo_set_value(intel_sdvo,
1035 					  SDVO_CMD_SET_HBUF_DATA,
1036 					  tmp, 8))
1037 			return false;
1038 	}
1039 
1040 	return intel_sdvo_set_value(intel_sdvo,
1041 				    SDVO_CMD_SET_HBUF_TXRATE,
1042 				    &tx_rate, 1);
1043 }
1044 
1045 static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo,
1046 					 unsigned int if_index,
1047 					 u8 *data, unsigned int length)
1048 {
1049 	u8 set_buf_index[2] = { if_index, 0 };
1050 	u8 hbuf_size, tx_rate, av_split;
1051 	int i;
1052 
1053 	if (!intel_sdvo_get_value(intel_sdvo,
1054 				  SDVO_CMD_GET_HBUF_AV_SPLIT,
1055 				  &av_split, 1))
1056 		return -ENXIO;
1057 
1058 	if (av_split < if_index)
1059 		return 0;
1060 
1061 	if (!intel_sdvo_set_value(intel_sdvo,
1062 				  SDVO_CMD_SET_HBUF_INDEX,
1063 				  set_buf_index, 2))
1064 		return -ENXIO;
1065 
1066 	if (!intel_sdvo_get_value(intel_sdvo,
1067 				  SDVO_CMD_GET_HBUF_TXRATE,
1068 				  &tx_rate, 1))
1069 		return -ENXIO;
1070 
1071 	if (tx_rate == SDVO_HBUF_TX_DISABLED)
1072 		return 0;
1073 
1074 	if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
1075 		return false;
1076 
1077 	DRM_DEBUG_KMS("reading sdvo hbuf: %i, length %u, hbuf_size: %i\n",
1078 		      if_index, length, hbuf_size);
1079 
1080 	hbuf_size = min_t(unsigned int, length, hbuf_size);
1081 
1082 	for (i = 0; i < hbuf_size; i += 8) {
1083 		if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA, NULL, 0))
1084 			return -ENXIO;
1085 		if (!intel_sdvo_read_response(intel_sdvo, &data[i],
1086 					      min_t(unsigned int, 8, hbuf_size - i)))
1087 			return -ENXIO;
1088 	}
1089 
1090 	return hbuf_size;
1091 }
1092 
1093 static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
1094 					     struct intel_crtc_state *crtc_state,
1095 					     struct drm_connector_state *conn_state)
1096 {
1097 	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
1098 	struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
1099 	const struct drm_display_mode *adjusted_mode =
1100 		&crtc_state->hw.adjusted_mode;
1101 	int ret;
1102 
1103 	if (!crtc_state->has_hdmi_sink)
1104 		return true;
1105 
1106 	crtc_state->infoframes.enable |=
1107 		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
1108 
1109 	ret = drm_hdmi_avi_infoframe_from_display_mode(frame,
1110 						       conn_state->connector,
1111 						       adjusted_mode);
1112 	if (ret)
1113 		return false;
1114 
1115 	drm_hdmi_avi_infoframe_quant_range(frame,
1116 					   conn_state->connector,
1117 					   adjusted_mode,
1118 					   crtc_state->limited_color_range ?
1119 					   HDMI_QUANTIZATION_RANGE_LIMITED :
1120 					   HDMI_QUANTIZATION_RANGE_FULL);
1121 
1122 	ret = hdmi_avi_infoframe_check(frame);
1123 	if (drm_WARN_ON(&dev_priv->drm, ret))
1124 		return false;
1125 
1126 	return true;
1127 }
1128 
1129 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
1130 					 const struct intel_crtc_state *crtc_state)
1131 {
1132 	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
1133 	u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
1134 	const union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
1135 	ssize_t len;
1136 
1137 	if ((crtc_state->infoframes.enable &
1138 	     intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0)
1139 		return true;
1140 
1141 	if (drm_WARN_ON(&dev_priv->drm,
1142 			frame->any.type != HDMI_INFOFRAME_TYPE_AVI))
1143 		return false;
1144 
1145 	len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data));
1146 	if (drm_WARN_ON(&dev_priv->drm, len < 0))
1147 		return false;
1148 
1149 	return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1150 					  SDVO_HBUF_TX_VSYNC,
1151 					  sdvo_data, len);
1152 }
1153 
1154 static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo,
1155 					 struct intel_crtc_state *crtc_state)
1156 {
1157 	u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
1158 	union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
1159 	ssize_t len;
1160 	int ret;
1161 
1162 	if (!crtc_state->has_hdmi_sink)
1163 		return;
1164 
1165 	len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1166 					sdvo_data, sizeof(sdvo_data));
1167 	if (len < 0) {
1168 		DRM_DEBUG_KMS("failed to read AVI infoframe\n");
1169 		return;
1170 	} else if (len == 0) {
1171 		return;
1172 	}
1173 
1174 	crtc_state->infoframes.enable |=
1175 		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
1176 
1177 	ret = hdmi_infoframe_unpack(frame, sdvo_data, len);
1178 	if (ret) {
1179 		DRM_DEBUG_KMS("Failed to unpack AVI infoframe\n");
1180 		return;
1181 	}
1182 
1183 	if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI)
1184 		DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
1185 			      frame->any.type, HDMI_INFOFRAME_TYPE_AVI);
1186 }
1187 
1188 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
1189 				     const struct drm_connector_state *conn_state)
1190 {
1191 	struct intel_sdvo_tv_format format;
1192 	u32 format_map;
1193 
1194 	format_map = 1 << conn_state->tv.mode;
1195 	memset(&format, 0, sizeof(format));
1196 	memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
1197 
1198 	BUILD_BUG_ON(sizeof(format) != 6);
1199 	return intel_sdvo_set_value(intel_sdvo,
1200 				    SDVO_CMD_SET_TV_FORMAT,
1201 				    &format, sizeof(format));
1202 }
1203 
1204 static bool
1205 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1206 					const struct drm_display_mode *mode)
1207 {
1208 	struct intel_sdvo_dtd output_dtd;
1209 
1210 	if (!intel_sdvo_set_target_output(intel_sdvo,
1211 					  intel_sdvo->attached_output))
1212 		return false;
1213 
1214 	intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1215 	if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1216 		return false;
1217 
1218 	return true;
1219 }
1220 
1221 /*
1222  * Asks the sdvo controller for the preferred input mode given the output mode.
1223  * Unfortunately we have to set up the full output mode to do that.
1224  */
1225 static bool
1226 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
1227 				    struct intel_sdvo_connector *intel_sdvo_connector,
1228 				    const struct drm_display_mode *mode,
1229 				    struct drm_display_mode *adjusted_mode)
1230 {
1231 	struct intel_sdvo_dtd input_dtd;
1232 
1233 	/* Reset the input timing to the screen. Assume always input 0. */
1234 	if (!intel_sdvo_set_target_input(intel_sdvo))
1235 		return false;
1236 
1237 	if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1238 						      intel_sdvo_connector,
1239 						      mode->clock / 10,
1240 						      mode->hdisplay,
1241 						      mode->vdisplay))
1242 		return false;
1243 
1244 	if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
1245 						   &input_dtd))
1246 		return false;
1247 
1248 	intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1249 	intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
1250 
1251 	return true;
1252 }
1253 
1254 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
1255 {
1256 	struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc->dev);
1257 	unsigned dotclock = pipe_config->port_clock;
1258 	struct dpll *clock = &pipe_config->dpll;
1259 
1260 	/*
1261 	 * SDVO TV has fixed PLL values depend on its clock range,
1262 	 * this mirrors vbios setting.
1263 	 */
1264 	if (dotclock >= 100000 && dotclock < 140500) {
1265 		clock->p1 = 2;
1266 		clock->p2 = 10;
1267 		clock->n = 3;
1268 		clock->m1 = 16;
1269 		clock->m2 = 8;
1270 	} else if (dotclock >= 140500 && dotclock <= 200000) {
1271 		clock->p1 = 1;
1272 		clock->p2 = 10;
1273 		clock->n = 6;
1274 		clock->m1 = 12;
1275 		clock->m2 = 8;
1276 	} else {
1277 		drm_WARN(&dev_priv->drm, 1,
1278 			 "SDVO TV clock out of range: %i\n", dotclock);
1279 	}
1280 
1281 	pipe_config->clock_set = true;
1282 }
1283 
1284 static bool intel_has_hdmi_sink(struct intel_sdvo *sdvo,
1285 				const struct drm_connector_state *conn_state)
1286 {
1287 	return sdvo->has_hdmi_monitor &&
1288 		READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1289 }
1290 
1291 static bool intel_sdvo_limited_color_range(struct intel_encoder *encoder,
1292 					   const struct intel_crtc_state *crtc_state,
1293 					   const struct drm_connector_state *conn_state)
1294 {
1295 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1296 
1297 	if ((intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220) == 0)
1298 		return false;
1299 
1300 	return intel_hdmi_limited_color_range(crtc_state, conn_state);
1301 }
1302 
1303 static int intel_sdvo_compute_config(struct intel_encoder *encoder,
1304 				     struct intel_crtc_state *pipe_config,
1305 				     struct drm_connector_state *conn_state)
1306 {
1307 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1308 	struct intel_sdvo_connector_state *intel_sdvo_state =
1309 		to_intel_sdvo_connector_state(conn_state);
1310 	struct intel_sdvo_connector *intel_sdvo_connector =
1311 		to_intel_sdvo_connector(conn_state->connector);
1312 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1313 	struct drm_display_mode *mode = &pipe_config->hw.mode;
1314 
1315 	DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1316 	pipe_config->pipe_bpp = 8*3;
1317 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1318 
1319 	if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
1320 		pipe_config->has_pch_encoder = true;
1321 
1322 	/*
1323 	 * We need to construct preferred input timings based on our
1324 	 * output timings.  To do that, we have to set the output
1325 	 * timings, even though this isn't really the right place in
1326 	 * the sequence to do it. Oh well.
1327 	 */
1328 	if (IS_TV(intel_sdvo_connector)) {
1329 		if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1330 			return -EINVAL;
1331 
1332 		(void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1333 							   intel_sdvo_connector,
1334 							   mode,
1335 							   adjusted_mode);
1336 		pipe_config->sdvo_tv_clock = true;
1337 	} else if (IS_LVDS(intel_sdvo_connector)) {
1338 		int ret;
1339 
1340 		ret = intel_panel_compute_config(&intel_sdvo_connector->base,
1341 						 adjusted_mode);
1342 		if (ret)
1343 			return ret;
1344 
1345 		if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1346 							     intel_sdvo_connector->base.panel.fixed_mode))
1347 			return -EINVAL;
1348 
1349 		(void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1350 							   intel_sdvo_connector,
1351 							   mode,
1352 							   adjusted_mode);
1353 	}
1354 
1355 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1356 		return -EINVAL;
1357 
1358 	/*
1359 	 * Make the CRTC code factor in the SDVO pixel multiplier.  The
1360 	 * SDVO device will factor out the multiplier during mode_set.
1361 	 */
1362 	pipe_config->pixel_multiplier =
1363 		intel_sdvo_get_pixel_multiplier(adjusted_mode);
1364 
1365 	pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo, conn_state);
1366 
1367 	if (pipe_config->has_hdmi_sink) {
1368 		if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO)
1369 			pipe_config->has_audio = intel_sdvo->has_hdmi_audio;
1370 		else
1371 			pipe_config->has_audio =
1372 				intel_sdvo_state->base.force_audio == HDMI_AUDIO_ON;
1373 	}
1374 
1375 	pipe_config->limited_color_range =
1376 		intel_sdvo_limited_color_range(encoder, pipe_config,
1377 					       conn_state);
1378 
1379 	/* Clock computation needs to happen after pixel multiplier. */
1380 	if (IS_TV(intel_sdvo_connector))
1381 		i9xx_adjust_sdvo_tv_clock(pipe_config);
1382 
1383 	if (conn_state->picture_aspect_ratio)
1384 		adjusted_mode->picture_aspect_ratio =
1385 			conn_state->picture_aspect_ratio;
1386 
1387 	if (!intel_sdvo_compute_avi_infoframe(intel_sdvo,
1388 					      pipe_config, conn_state)) {
1389 		DRM_DEBUG_KMS("bad AVI infoframe\n");
1390 		return -EINVAL;
1391 	}
1392 
1393 	return 0;
1394 }
1395 
1396 #define UPDATE_PROPERTY(input, NAME) \
1397 	do { \
1398 		val = input; \
1399 		intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \
1400 	} while (0)
1401 
1402 static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo,
1403 				    const struct intel_sdvo_connector_state *sdvo_state)
1404 {
1405 	const struct drm_connector_state *conn_state = &sdvo_state->base.base;
1406 	struct intel_sdvo_connector *intel_sdvo_conn =
1407 		to_intel_sdvo_connector(conn_state->connector);
1408 	u16 val;
1409 
1410 	if (intel_sdvo_conn->left)
1411 		UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H);
1412 
1413 	if (intel_sdvo_conn->top)
1414 		UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V);
1415 
1416 	if (intel_sdvo_conn->hpos)
1417 		UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS);
1418 
1419 	if (intel_sdvo_conn->vpos)
1420 		UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS);
1421 
1422 	if (intel_sdvo_conn->saturation)
1423 		UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION);
1424 
1425 	if (intel_sdvo_conn->contrast)
1426 		UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST);
1427 
1428 	if (intel_sdvo_conn->hue)
1429 		UPDATE_PROPERTY(conn_state->tv.hue, HUE);
1430 
1431 	if (intel_sdvo_conn->brightness)
1432 		UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS);
1433 
1434 	if (intel_sdvo_conn->sharpness)
1435 		UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS);
1436 
1437 	if (intel_sdvo_conn->flicker_filter)
1438 		UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER);
1439 
1440 	if (intel_sdvo_conn->flicker_filter_2d)
1441 		UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D);
1442 
1443 	if (intel_sdvo_conn->flicker_filter_adaptive)
1444 		UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
1445 
1446 	if (intel_sdvo_conn->tv_chroma_filter)
1447 		UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER);
1448 
1449 	if (intel_sdvo_conn->tv_luma_filter)
1450 		UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER);
1451 
1452 	if (intel_sdvo_conn->dot_crawl)
1453 		UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL);
1454 
1455 #undef UPDATE_PROPERTY
1456 }
1457 
1458 static void intel_sdvo_pre_enable(struct intel_atomic_state *state,
1459 				  struct intel_encoder *intel_encoder,
1460 				  const struct intel_crtc_state *crtc_state,
1461 				  const struct drm_connector_state *conn_state)
1462 {
1463 	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
1464 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1465 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1466 	const struct intel_sdvo_connector_state *sdvo_state =
1467 		to_intel_sdvo_connector_state(conn_state);
1468 	const struct intel_sdvo_connector *intel_sdvo_connector =
1469 		to_intel_sdvo_connector(conn_state->connector);
1470 	const struct drm_display_mode *mode = &crtc_state->hw.mode;
1471 	struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
1472 	u32 sdvox;
1473 	struct intel_sdvo_in_out_map in_out;
1474 	struct intel_sdvo_dtd input_dtd, output_dtd;
1475 	int rate;
1476 
1477 	intel_sdvo_update_props(intel_sdvo, sdvo_state);
1478 
1479 	/*
1480 	 * First, set the input mapping for the first input to our controlled
1481 	 * output. This is only correct if we're a single-input device, in
1482 	 * which case the first input is the output from the appropriate SDVO
1483 	 * channel on the motherboard.  In a two-input device, the first input
1484 	 * will be SDVOB and the second SDVOC.
1485 	 */
1486 	in_out.in0 = intel_sdvo->attached_output;
1487 	in_out.in1 = 0;
1488 
1489 	intel_sdvo_set_value(intel_sdvo,
1490 			     SDVO_CMD_SET_IN_OUT_MAP,
1491 			     &in_out, sizeof(in_out));
1492 
1493 	/* Set the output timings to the screen */
1494 	if (!intel_sdvo_set_target_output(intel_sdvo,
1495 					  intel_sdvo->attached_output))
1496 		return;
1497 
1498 	/* lvds has a special fixed output timing. */
1499 	if (IS_LVDS(intel_sdvo_connector))
1500 		intel_sdvo_get_dtd_from_mode(&output_dtd,
1501 					     intel_sdvo_connector->base.panel.fixed_mode);
1502 	else
1503 		intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1504 	if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1505 		drm_info(&dev_priv->drm,
1506 			 "Setting output timings on %s failed\n",
1507 			 SDVO_NAME(intel_sdvo));
1508 
1509 	/* Set the input timing to the screen. Assume always input 0. */
1510 	if (!intel_sdvo_set_target_input(intel_sdvo))
1511 		return;
1512 
1513 	if (crtc_state->has_hdmi_sink) {
1514 		intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1515 		intel_sdvo_set_colorimetry(intel_sdvo,
1516 					   crtc_state->limited_color_range ?
1517 					   SDVO_COLORIMETRY_RGB220 :
1518 					   SDVO_COLORIMETRY_RGB256);
1519 		intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state);
1520 		intel_sdvo_set_pixel_replication(intel_sdvo,
1521 						 !!(adjusted_mode->flags &
1522 						    DRM_MODE_FLAG_DBLCLK));
1523 	} else
1524 		intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
1525 
1526 	if (IS_TV(intel_sdvo_connector) &&
1527 	    !intel_sdvo_set_tv_format(intel_sdvo, conn_state))
1528 		return;
1529 
1530 	intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1531 
1532 	if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector))
1533 		input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
1534 	if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1535 		drm_info(&dev_priv->drm,
1536 			 "Setting input timings on %s failed\n",
1537 			 SDVO_NAME(intel_sdvo));
1538 
1539 	switch (crtc_state->pixel_multiplier) {
1540 	default:
1541 		drm_WARN(&dev_priv->drm, 1,
1542 			 "unknown pixel multiplier specified\n");
1543 		fallthrough;
1544 	case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1545 	case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1546 	case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
1547 	}
1548 	if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1549 		return;
1550 
1551 	/* Set the SDVO control regs. */
1552 	if (DISPLAY_VER(dev_priv) >= 4) {
1553 		/* The real mode polarity is set by the SDVO commands, using
1554 		 * struct intel_sdvo_dtd. */
1555 		sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
1556 		if (DISPLAY_VER(dev_priv) < 5)
1557 			sdvox |= SDVO_BORDER_ENABLE;
1558 	} else {
1559 		sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1560 		if (intel_sdvo->port == PORT_B)
1561 			sdvox &= SDVOB_PRESERVE_MASK;
1562 		else
1563 			sdvox &= SDVOC_PRESERVE_MASK;
1564 		sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1565 	}
1566 
1567 	if (HAS_PCH_CPT(dev_priv))
1568 		sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1569 	else
1570 		sdvox |= SDVO_PIPE_SEL(crtc->pipe);
1571 
1572 	if (DISPLAY_VER(dev_priv) >= 4) {
1573 		/* done in crtc_mode_set as the dpll_md reg must be written early */
1574 	} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
1575 		   IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
1576 		/* done in crtc_mode_set as it lives inside the dpll register */
1577 	} else {
1578 		sdvox |= (crtc_state->pixel_multiplier - 1)
1579 			<< SDVO_PORT_MULTIPLY_SHIFT;
1580 	}
1581 
1582 	if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1583 	    DISPLAY_VER(dev_priv) < 5)
1584 		sdvox |= SDVO_STALL_SELECT;
1585 	intel_sdvo_write_sdvox(intel_sdvo, sdvox);
1586 }
1587 
1588 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
1589 {
1590 	struct intel_sdvo_connector *intel_sdvo_connector =
1591 		to_intel_sdvo_connector(&connector->base);
1592 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1593 	u16 active_outputs = 0;
1594 
1595 	intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1596 
1597 	return active_outputs & intel_sdvo_connector->output_flag;
1598 }
1599 
1600 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
1601 			     i915_reg_t sdvo_reg, enum pipe *pipe)
1602 {
1603 	u32 val;
1604 
1605 	val = intel_de_read(dev_priv, sdvo_reg);
1606 
1607 	/* asserts want to know the pipe even if the port is disabled */
1608 	if (HAS_PCH_CPT(dev_priv))
1609 		*pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT;
1610 	else if (IS_CHERRYVIEW(dev_priv))
1611 		*pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV;
1612 	else
1613 		*pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT;
1614 
1615 	return val & SDVO_ENABLE;
1616 }
1617 
1618 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1619 				    enum pipe *pipe)
1620 {
1621 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1622 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1623 	u16 active_outputs = 0;
1624 	bool ret;
1625 
1626 	intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1627 
1628 	ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe);
1629 
1630 	return ret || active_outputs;
1631 }
1632 
1633 static void intel_sdvo_get_config(struct intel_encoder *encoder,
1634 				  struct intel_crtc_state *pipe_config)
1635 {
1636 	struct drm_device *dev = encoder->base.dev;
1637 	struct drm_i915_private *dev_priv = to_i915(dev);
1638 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1639 	struct intel_sdvo_dtd dtd;
1640 	int encoder_pixel_multiplier = 0;
1641 	int dotclock;
1642 	u32 flags = 0, sdvox;
1643 	u8 val;
1644 	bool ret;
1645 
1646 	pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO);
1647 
1648 	sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1649 
1650 	ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1651 	if (!ret) {
1652 		/*
1653 		 * Some sdvo encoders are not spec compliant and don't
1654 		 * implement the mandatory get_timings function.
1655 		 */
1656 		drm_dbg(&dev_priv->drm, "failed to retrieve SDVO DTD\n");
1657 		pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1658 	} else {
1659 		if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1660 			flags |= DRM_MODE_FLAG_PHSYNC;
1661 		else
1662 			flags |= DRM_MODE_FLAG_NHSYNC;
1663 
1664 		if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1665 			flags |= DRM_MODE_FLAG_PVSYNC;
1666 		else
1667 			flags |= DRM_MODE_FLAG_NVSYNC;
1668 	}
1669 
1670 	pipe_config->hw.adjusted_mode.flags |= flags;
1671 
1672 	/*
1673 	 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1674 	 * the sdvo port register, on all other platforms it is part of the dpll
1675 	 * state. Since the general pipe state readout happens before the
1676 	 * encoder->get_config we so already have a valid pixel multplier on all
1677 	 * other platfroms.
1678 	 */
1679 	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
1680 		pipe_config->pixel_multiplier =
1681 			((sdvox & SDVO_PORT_MULTIPLY_MASK)
1682 			 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1683 	}
1684 
1685 	dotclock = pipe_config->port_clock;
1686 
1687 	if (pipe_config->pixel_multiplier)
1688 		dotclock /= pipe_config->pixel_multiplier;
1689 
1690 	pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
1691 
1692 	/* Cross check the port pixel multiplier with the sdvo encoder state. */
1693 	if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1694 				 &val, 1)) {
1695 		switch (val) {
1696 		case SDVO_CLOCK_RATE_MULT_1X:
1697 			encoder_pixel_multiplier = 1;
1698 			break;
1699 		case SDVO_CLOCK_RATE_MULT_2X:
1700 			encoder_pixel_multiplier = 2;
1701 			break;
1702 		case SDVO_CLOCK_RATE_MULT_4X:
1703 			encoder_pixel_multiplier = 4;
1704 			break;
1705 		}
1706 	}
1707 
1708 	drm_WARN(dev,
1709 		 encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1710 		 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1711 		 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
1712 
1713 	if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY,
1714 				 &val, 1)) {
1715 		if (val == SDVO_COLORIMETRY_RGB220)
1716 			pipe_config->limited_color_range = true;
1717 	}
1718 
1719 	if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT,
1720 				 &val, 1)) {
1721 		u8 mask = SDVO_AUDIO_ELD_VALID | SDVO_AUDIO_PRESENCE_DETECT;
1722 
1723 		if ((val & mask) == mask)
1724 			pipe_config->has_audio = true;
1725 	}
1726 
1727 	if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1728 				 &val, 1)) {
1729 		if (val == SDVO_ENCODE_HDMI)
1730 			pipe_config->has_hdmi_sink = true;
1731 	}
1732 
1733 	intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config);
1734 }
1735 
1736 static void intel_sdvo_disable_audio(struct intel_sdvo *intel_sdvo)
1737 {
1738 	intel_sdvo_set_audio_state(intel_sdvo, 0);
1739 }
1740 
1741 static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo,
1742 				    const struct intel_crtc_state *crtc_state,
1743 				    const struct drm_connector_state *conn_state)
1744 {
1745 	const struct drm_display_mode *adjusted_mode =
1746 		&crtc_state->hw.adjusted_mode;
1747 	struct drm_connector *connector = conn_state->connector;
1748 	u8 *eld = connector->eld;
1749 
1750 	eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
1751 
1752 	intel_sdvo_set_audio_state(intel_sdvo, 0);
1753 
1754 	intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD,
1755 				   SDVO_HBUF_TX_DISABLED,
1756 				   eld, drm_eld_size(eld));
1757 
1758 	intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID |
1759 				   SDVO_AUDIO_PRESENCE_DETECT);
1760 }
1761 
1762 static void intel_disable_sdvo(struct intel_atomic_state *state,
1763 			       struct intel_encoder *encoder,
1764 			       const struct intel_crtc_state *old_crtc_state,
1765 			       const struct drm_connector_state *conn_state)
1766 {
1767 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1768 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1769 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1770 	u32 temp;
1771 
1772 	if (old_crtc_state->has_audio)
1773 		intel_sdvo_disable_audio(intel_sdvo);
1774 
1775 	intel_sdvo_set_active_outputs(intel_sdvo, 0);
1776 	if (0)
1777 		intel_sdvo_set_encoder_power_state(intel_sdvo,
1778 						   DRM_MODE_DPMS_OFF);
1779 
1780 	temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1781 
1782 	temp &= ~SDVO_ENABLE;
1783 	intel_sdvo_write_sdvox(intel_sdvo, temp);
1784 
1785 	/*
1786 	 * HW workaround for IBX, we need to move the port
1787 	 * to transcoder A after disabling it to allow the
1788 	 * matching DP port to be enabled on transcoder A.
1789 	 */
1790 	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1791 		/*
1792 		 * We get CPU/PCH FIFO underruns on the other pipe when
1793 		 * doing the workaround. Sweep them under the rug.
1794 		 */
1795 		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1796 		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1797 
1798 		temp &= ~SDVO_PIPE_SEL_MASK;
1799 		temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1800 		intel_sdvo_write_sdvox(intel_sdvo, temp);
1801 
1802 		temp &= ~SDVO_ENABLE;
1803 		intel_sdvo_write_sdvox(intel_sdvo, temp);
1804 
1805 		intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1806 		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1807 		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1808 	}
1809 }
1810 
1811 static void pch_disable_sdvo(struct intel_atomic_state *state,
1812 			     struct intel_encoder *encoder,
1813 			     const struct intel_crtc_state *old_crtc_state,
1814 			     const struct drm_connector_state *old_conn_state)
1815 {
1816 }
1817 
1818 static void pch_post_disable_sdvo(struct intel_atomic_state *state,
1819 				  struct intel_encoder *encoder,
1820 				  const struct intel_crtc_state *old_crtc_state,
1821 				  const struct drm_connector_state *old_conn_state)
1822 {
1823 	intel_disable_sdvo(state, encoder, old_crtc_state, old_conn_state);
1824 }
1825 
1826 static void intel_enable_sdvo(struct intel_atomic_state *state,
1827 			      struct intel_encoder *encoder,
1828 			      const struct intel_crtc_state *pipe_config,
1829 			      const struct drm_connector_state *conn_state)
1830 {
1831 	struct drm_device *dev = encoder->base.dev;
1832 	struct drm_i915_private *dev_priv = to_i915(dev);
1833 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1834 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1835 	u32 temp;
1836 	bool input1, input2;
1837 	int i;
1838 	bool success;
1839 
1840 	temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1841 	temp |= SDVO_ENABLE;
1842 	intel_sdvo_write_sdvox(intel_sdvo, temp);
1843 
1844 	for (i = 0; i < 2; i++)
1845 		intel_crtc_wait_for_next_vblank(crtc);
1846 
1847 	success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1848 	/*
1849 	 * Warn if the device reported failure to sync.
1850 	 *
1851 	 * A lot of SDVO devices fail to notify of sync, but it's
1852 	 * a given it the status is a success, we succeeded.
1853 	 */
1854 	if (success && !input1) {
1855 		drm_dbg_kms(&dev_priv->drm,
1856 			    "First %s output reported failure to "
1857 			    "sync\n", SDVO_NAME(intel_sdvo));
1858 	}
1859 
1860 	if (0)
1861 		intel_sdvo_set_encoder_power_state(intel_sdvo,
1862 						   DRM_MODE_DPMS_ON);
1863 	intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1864 
1865 	if (pipe_config->has_audio)
1866 		intel_sdvo_enable_audio(intel_sdvo, pipe_config, conn_state);
1867 }
1868 
1869 static enum drm_mode_status
1870 intel_sdvo_mode_valid(struct drm_connector *connector,
1871 		      struct drm_display_mode *mode)
1872 {
1873 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
1874 	struct intel_sdvo_connector *intel_sdvo_connector =
1875 		to_intel_sdvo_connector(connector);
1876 	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1877 	bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo, connector->state);
1878 	int clock = mode->clock;
1879 
1880 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1881 		return MODE_NO_DBLESCAN;
1882 
1883 	if (clock > max_dotclk)
1884 		return MODE_CLOCK_HIGH;
1885 
1886 	if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1887 		if (!has_hdmi_sink)
1888 			return MODE_CLOCK_LOW;
1889 		clock *= 2;
1890 	}
1891 
1892 	if (intel_sdvo->pixel_clock_min > clock)
1893 		return MODE_CLOCK_LOW;
1894 
1895 	if (intel_sdvo->pixel_clock_max < clock)
1896 		return MODE_CLOCK_HIGH;
1897 
1898 	if (IS_LVDS(intel_sdvo_connector)) {
1899 		enum drm_mode_status status;
1900 
1901 		status = intel_panel_mode_valid(&intel_sdvo_connector->base, mode);
1902 		if (status != MODE_OK)
1903 			return status;
1904 	}
1905 
1906 	return MODE_OK;
1907 }
1908 
1909 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
1910 {
1911 	BUILD_BUG_ON(sizeof(*caps) != 8);
1912 	if (!intel_sdvo_get_value(intel_sdvo,
1913 				  SDVO_CMD_GET_DEVICE_CAPS,
1914 				  caps, sizeof(*caps)))
1915 		return false;
1916 
1917 	DRM_DEBUG_KMS("SDVO capabilities:\n"
1918 		      "  vendor_id: %d\n"
1919 		      "  device_id: %d\n"
1920 		      "  device_rev_id: %d\n"
1921 		      "  sdvo_version_major: %d\n"
1922 		      "  sdvo_version_minor: %d\n"
1923 		      "  sdvo_inputs_mask: %d\n"
1924 		      "  smooth_scaling: %d\n"
1925 		      "  sharp_scaling: %d\n"
1926 		      "  up_scaling: %d\n"
1927 		      "  down_scaling: %d\n"
1928 		      "  stall_support: %d\n"
1929 		      "  output_flags: %d\n",
1930 		      caps->vendor_id,
1931 		      caps->device_id,
1932 		      caps->device_rev_id,
1933 		      caps->sdvo_version_major,
1934 		      caps->sdvo_version_minor,
1935 		      caps->sdvo_inputs_mask,
1936 		      caps->smooth_scaling,
1937 		      caps->sharp_scaling,
1938 		      caps->up_scaling,
1939 		      caps->down_scaling,
1940 		      caps->stall_support,
1941 		      caps->output_flags);
1942 
1943 	return true;
1944 }
1945 
1946 static u8 intel_sdvo_get_colorimetry_cap(struct intel_sdvo *intel_sdvo)
1947 {
1948 	u8 cap;
1949 
1950 	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY_CAP,
1951 				  &cap, sizeof(cap)))
1952 		return SDVO_COLORIMETRY_RGB256;
1953 
1954 	return cap;
1955 }
1956 
1957 static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
1958 {
1959 	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
1960 	u16 hotplug;
1961 
1962 	if (!I915_HAS_HOTPLUG(dev_priv))
1963 		return 0;
1964 
1965 	/*
1966 	 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1967 	 * on the line.
1968 	 */
1969 	if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1970 		return 0;
1971 
1972 	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1973 					&hotplug, sizeof(hotplug)))
1974 		return 0;
1975 
1976 	return hotplug;
1977 }
1978 
1979 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
1980 {
1981 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1982 
1983 	intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1984 			     &intel_sdvo->hotplug_active, 2);
1985 }
1986 
1987 static enum intel_hotplug_state
1988 intel_sdvo_hotplug(struct intel_encoder *encoder,
1989 		   struct intel_connector *connector)
1990 {
1991 	intel_sdvo_enable_hotplug(encoder);
1992 
1993 	return intel_encoder_hotplug(encoder, connector);
1994 }
1995 
1996 static bool
1997 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
1998 {
1999 	/* Is there more than one type of output? */
2000 	return hweight16(intel_sdvo->caps.output_flags) > 1;
2001 }
2002 
2003 static struct edid *
2004 intel_sdvo_get_edid(struct drm_connector *connector)
2005 {
2006 	struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector));
2007 	return drm_get_edid(connector, &sdvo->ddc);
2008 }
2009 
2010 /* Mac mini hack -- use the same DDC as the analog connector */
2011 static struct edid *
2012 intel_sdvo_get_analog_edid(struct drm_connector *connector)
2013 {
2014 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2015 
2016 	return drm_get_edid(connector,
2017 			    intel_gmbus_get_adapter(dev_priv,
2018 						    dev_priv->vbt.crt_ddc_pin));
2019 }
2020 
2021 static enum drm_connector_status
2022 intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
2023 {
2024 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
2025 	struct intel_sdvo_connector *intel_sdvo_connector =
2026 		to_intel_sdvo_connector(connector);
2027 	enum drm_connector_status status;
2028 	struct edid *edid;
2029 
2030 	edid = intel_sdvo_get_edid(connector);
2031 
2032 	if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
2033 		u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
2034 
2035 		/*
2036 		 * Don't use the 1 as the argument of DDC bus switch to get
2037 		 * the EDID. It is used for SDVO SPD ROM.
2038 		 */
2039 		for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
2040 			intel_sdvo->ddc_bus = ddc;
2041 			edid = intel_sdvo_get_edid(connector);
2042 			if (edid)
2043 				break;
2044 		}
2045 		/*
2046 		 * If we found the EDID on the other bus,
2047 		 * assume that is the correct DDC bus.
2048 		 */
2049 		if (edid == NULL)
2050 			intel_sdvo->ddc_bus = saved_ddc;
2051 	}
2052 
2053 	/*
2054 	 * When there is no edid and no monitor is connected with VGA
2055 	 * port, try to use the CRT ddc to read the EDID for DVI-connector.
2056 	 */
2057 	if (edid == NULL)
2058 		edid = intel_sdvo_get_analog_edid(connector);
2059 
2060 	status = connector_status_unknown;
2061 	if (edid != NULL) {
2062 		/* DDC bus is shared, match EDID to connector type */
2063 		if (edid->input & DRM_EDID_INPUT_DIGITAL) {
2064 			status = connector_status_connected;
2065 			if (intel_sdvo_connector->is_hdmi) {
2066 				intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
2067 				intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
2068 			}
2069 		} else
2070 			status = connector_status_disconnected;
2071 		kfree(edid);
2072 	}
2073 
2074 	return status;
2075 }
2076 
2077 static bool
2078 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
2079 				  struct edid *edid)
2080 {
2081 	bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
2082 	bool connector_is_digital = !!IS_DIGITAL(sdvo);
2083 
2084 	DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
2085 		      connector_is_digital, monitor_is_digital);
2086 	return connector_is_digital == monitor_is_digital;
2087 }
2088 
2089 static enum drm_connector_status
2090 intel_sdvo_detect(struct drm_connector *connector, bool force)
2091 {
2092 	struct drm_i915_private *i915 = to_i915(connector->dev);
2093 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
2094 	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2095 	enum drm_connector_status ret;
2096 	u16 response;
2097 
2098 	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2099 		      connector->base.id, connector->name);
2100 
2101 	if (!INTEL_DISPLAY_ENABLED(i915))
2102 		return connector_status_disconnected;
2103 
2104 	if (!intel_sdvo_get_value(intel_sdvo,
2105 				  SDVO_CMD_GET_ATTACHED_DISPLAYS,
2106 				  &response, 2))
2107 		return connector_status_unknown;
2108 
2109 	DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
2110 		      response & 0xff, response >> 8,
2111 		      intel_sdvo_connector->output_flag);
2112 
2113 	if (response == 0)
2114 		return connector_status_disconnected;
2115 
2116 	intel_sdvo->attached_output = response;
2117 
2118 	intel_sdvo->has_hdmi_monitor = false;
2119 	intel_sdvo->has_hdmi_audio = false;
2120 
2121 	if ((intel_sdvo_connector->output_flag & response) == 0)
2122 		ret = connector_status_disconnected;
2123 	else if (IS_TMDS(intel_sdvo_connector))
2124 		ret = intel_sdvo_tmds_sink_detect(connector);
2125 	else {
2126 		struct edid *edid;
2127 
2128 		/* if we have an edid check it matches the connection */
2129 		edid = intel_sdvo_get_edid(connector);
2130 		if (edid == NULL)
2131 			edid = intel_sdvo_get_analog_edid(connector);
2132 		if (edid != NULL) {
2133 			if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
2134 							      edid))
2135 				ret = connector_status_connected;
2136 			else
2137 				ret = connector_status_disconnected;
2138 
2139 			kfree(edid);
2140 		} else
2141 			ret = connector_status_connected;
2142 	}
2143 
2144 	return ret;
2145 }
2146 
2147 static int intel_sdvo_get_ddc_modes(struct drm_connector *connector)
2148 {
2149 	int num_modes = 0;
2150 	struct edid *edid;
2151 
2152 	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2153 		      connector->base.id, connector->name);
2154 
2155 	/* set the bus switch and get the modes */
2156 	edid = intel_sdvo_get_edid(connector);
2157 
2158 	/*
2159 	 * Mac mini hack.  On this device, the DVI-I connector shares one DDC
2160 	 * link between analog and digital outputs. So, if the regular SDVO
2161 	 * DDC fails, check to see if the analog output is disconnected, in
2162 	 * which case we'll look there for the digital DDC data.
2163 	 */
2164 	if (!edid)
2165 		edid = intel_sdvo_get_analog_edid(connector);
2166 
2167 	if (!edid)
2168 		return 0;
2169 
2170 	if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
2171 					      edid))
2172 		num_modes += intel_connector_update_modes(connector, edid);
2173 
2174 	kfree(edid);
2175 
2176 	return num_modes;
2177 }
2178 
2179 /*
2180  * Set of SDVO TV modes.
2181  * Note!  This is in reply order (see loop in get_tv_modes).
2182  * XXX: all 60Hz refresh?
2183  */
2184 static const struct drm_display_mode sdvo_tv_modes[] = {
2185 	{ DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
2186 		   416, 0, 200, 201, 232, 233, 0,
2187 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2188 	{ DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
2189 		   416, 0, 240, 241, 272, 273, 0,
2190 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2191 	{ DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
2192 		   496, 0, 300, 301, 332, 333, 0,
2193 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2194 	{ DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
2195 		   736, 0, 350, 351, 382, 383, 0,
2196 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2197 	{ DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
2198 		   736, 0, 400, 401, 432, 433, 0,
2199 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2200 	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
2201 		   736, 0, 480, 481, 512, 513, 0,
2202 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2203 	{ DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
2204 		   800, 0, 480, 481, 512, 513, 0,
2205 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2206 	{ DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
2207 		   800, 0, 576, 577, 608, 609, 0,
2208 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2209 	{ DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
2210 		   816, 0, 350, 351, 382, 383, 0,
2211 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2212 	{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
2213 		   816, 0, 400, 401, 432, 433, 0,
2214 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2215 	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
2216 		   816, 0, 480, 481, 512, 513, 0,
2217 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2218 	{ DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
2219 		   816, 0, 540, 541, 572, 573, 0,
2220 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2221 	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
2222 		   816, 0, 576, 577, 608, 609, 0,
2223 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2224 	{ DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
2225 		   864, 0, 576, 577, 608, 609, 0,
2226 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2227 	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
2228 		   896, 0, 600, 601, 632, 633, 0,
2229 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2230 	{ DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
2231 		   928, 0, 624, 625, 656, 657, 0,
2232 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2233 	{ DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
2234 		   1016, 0, 766, 767, 798, 799, 0,
2235 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2236 	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
2237 		   1120, 0, 768, 769, 800, 801, 0,
2238 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2239 	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
2240 		   1376, 0, 1024, 1025, 1056, 1057, 0,
2241 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2242 };
2243 
2244 static int intel_sdvo_get_tv_modes(struct drm_connector *connector)
2245 {
2246 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
2247 	const struct drm_connector_state *conn_state = connector->state;
2248 	struct intel_sdvo_sdtv_resolution_request tv_res;
2249 	u32 reply = 0, format_map = 0;
2250 	int num_modes = 0;
2251 	int i;
2252 
2253 	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2254 		      connector->base.id, connector->name);
2255 
2256 	/*
2257 	 * Read the list of supported input resolutions for the selected TV
2258 	 * format.
2259 	 */
2260 	format_map = 1 << conn_state->tv.mode;
2261 	memcpy(&tv_res, &format_map,
2262 	       min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
2263 
2264 	if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
2265 		return 0;
2266 
2267 	BUILD_BUG_ON(sizeof(tv_res) != 3);
2268 	if (!intel_sdvo_write_cmd(intel_sdvo,
2269 				  SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
2270 				  &tv_res, sizeof(tv_res)))
2271 		return 0;
2272 	if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
2273 		return 0;
2274 
2275 	for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) {
2276 		if (reply & (1 << i)) {
2277 			struct drm_display_mode *nmode;
2278 			nmode = drm_mode_duplicate(connector->dev,
2279 						   &sdvo_tv_modes[i]);
2280 			if (nmode) {
2281 				drm_mode_probed_add(connector, nmode);
2282 				num_modes++;
2283 			}
2284 		}
2285 	}
2286 
2287 	return num_modes;
2288 }
2289 
2290 static int intel_sdvo_get_lvds_modes(struct drm_connector *connector)
2291 {
2292 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
2293 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2294 	struct drm_display_mode *newmode;
2295 	int num_modes = 0;
2296 
2297 	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2298 		    connector->base.id, connector->name);
2299 
2300 	/*
2301 	 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
2302 	 * SDVO->LVDS transcoders can't cope with the EDID mode.
2303 	 */
2304 	if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
2305 		newmode = drm_mode_duplicate(connector->dev,
2306 					     dev_priv->vbt.sdvo_lvds_vbt_mode);
2307 		if (newmode != NULL) {
2308 			/* Guarantee the mode is preferred */
2309 			newmode->type = (DRM_MODE_TYPE_PREFERRED |
2310 					 DRM_MODE_TYPE_DRIVER);
2311 			drm_mode_probed_add(connector, newmode);
2312 			num_modes++;
2313 		}
2314 	}
2315 
2316 	/*
2317 	 * Attempt to get the mode list from DDC.
2318 	 * Assume that the preferred modes are
2319 	 * arranged in priority order.
2320 	 */
2321 	num_modes += intel_ddc_get_modes(connector, &intel_sdvo->ddc);
2322 
2323 	return num_modes;
2324 }
2325 
2326 static int intel_sdvo_get_modes(struct drm_connector *connector)
2327 {
2328 	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2329 
2330 	if (IS_TV(intel_sdvo_connector))
2331 		return intel_sdvo_get_tv_modes(connector);
2332 	else if (IS_LVDS(intel_sdvo_connector))
2333 		return intel_sdvo_get_lvds_modes(connector);
2334 	else
2335 		return intel_sdvo_get_ddc_modes(connector);
2336 }
2337 
2338 static int
2339 intel_sdvo_connector_atomic_get_property(struct drm_connector *connector,
2340 					 const struct drm_connector_state *state,
2341 					 struct drm_property *property,
2342 					 u64 *val)
2343 {
2344 	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2345 	const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state);
2346 
2347 	if (property == intel_sdvo_connector->tv_format) {
2348 		int i;
2349 
2350 		for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2351 			if (state->tv.mode == intel_sdvo_connector->tv_format_supported[i]) {
2352 				*val = i;
2353 
2354 				return 0;
2355 			}
2356 
2357 		drm_WARN_ON(connector->dev, 1);
2358 		*val = 0;
2359 	} else if (property == intel_sdvo_connector->top ||
2360 		   property == intel_sdvo_connector->bottom)
2361 		*val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v;
2362 	else if (property == intel_sdvo_connector->left ||
2363 		 property == intel_sdvo_connector->right)
2364 		*val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h;
2365 	else if (property == intel_sdvo_connector->hpos)
2366 		*val = sdvo_state->tv.hpos;
2367 	else if (property == intel_sdvo_connector->vpos)
2368 		*val = sdvo_state->tv.vpos;
2369 	else if (property == intel_sdvo_connector->saturation)
2370 		*val = state->tv.saturation;
2371 	else if (property == intel_sdvo_connector->contrast)
2372 		*val = state->tv.contrast;
2373 	else if (property == intel_sdvo_connector->hue)
2374 		*val = state->tv.hue;
2375 	else if (property == intel_sdvo_connector->brightness)
2376 		*val = state->tv.brightness;
2377 	else if (property == intel_sdvo_connector->sharpness)
2378 		*val = sdvo_state->tv.sharpness;
2379 	else if (property == intel_sdvo_connector->flicker_filter)
2380 		*val = sdvo_state->tv.flicker_filter;
2381 	else if (property == intel_sdvo_connector->flicker_filter_2d)
2382 		*val = sdvo_state->tv.flicker_filter_2d;
2383 	else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2384 		*val = sdvo_state->tv.flicker_filter_adaptive;
2385 	else if (property == intel_sdvo_connector->tv_chroma_filter)
2386 		*val = sdvo_state->tv.chroma_filter;
2387 	else if (property == intel_sdvo_connector->tv_luma_filter)
2388 		*val = sdvo_state->tv.luma_filter;
2389 	else if (property == intel_sdvo_connector->dot_crawl)
2390 		*val = sdvo_state->tv.dot_crawl;
2391 	else
2392 		return intel_digital_connector_atomic_get_property(connector, state, property, val);
2393 
2394 	return 0;
2395 }
2396 
2397 static int
2398 intel_sdvo_connector_atomic_set_property(struct drm_connector *connector,
2399 					 struct drm_connector_state *state,
2400 					 struct drm_property *property,
2401 					 u64 val)
2402 {
2403 	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2404 	struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state);
2405 
2406 	if (property == intel_sdvo_connector->tv_format) {
2407 		state->tv.mode = intel_sdvo_connector->tv_format_supported[val];
2408 
2409 		if (state->crtc) {
2410 			struct drm_crtc_state *crtc_state =
2411 				drm_atomic_get_new_crtc_state(state->state, state->crtc);
2412 
2413 			crtc_state->connectors_changed = true;
2414 		}
2415 	} else if (property == intel_sdvo_connector->top ||
2416 		   property == intel_sdvo_connector->bottom)
2417 		/* Cannot set these independent from each other */
2418 		sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val;
2419 	else if (property == intel_sdvo_connector->left ||
2420 		 property == intel_sdvo_connector->right)
2421 		/* Cannot set these independent from each other */
2422 		sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val;
2423 	else if (property == intel_sdvo_connector->hpos)
2424 		sdvo_state->tv.hpos = val;
2425 	else if (property == intel_sdvo_connector->vpos)
2426 		sdvo_state->tv.vpos = val;
2427 	else if (property == intel_sdvo_connector->saturation)
2428 		state->tv.saturation = val;
2429 	else if (property == intel_sdvo_connector->contrast)
2430 		state->tv.contrast = val;
2431 	else if (property == intel_sdvo_connector->hue)
2432 		state->tv.hue = val;
2433 	else if (property == intel_sdvo_connector->brightness)
2434 		state->tv.brightness = val;
2435 	else if (property == intel_sdvo_connector->sharpness)
2436 		sdvo_state->tv.sharpness = val;
2437 	else if (property == intel_sdvo_connector->flicker_filter)
2438 		sdvo_state->tv.flicker_filter = val;
2439 	else if (property == intel_sdvo_connector->flicker_filter_2d)
2440 		sdvo_state->tv.flicker_filter_2d = val;
2441 	else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2442 		sdvo_state->tv.flicker_filter_adaptive = val;
2443 	else if (property == intel_sdvo_connector->tv_chroma_filter)
2444 		sdvo_state->tv.chroma_filter = val;
2445 	else if (property == intel_sdvo_connector->tv_luma_filter)
2446 		sdvo_state->tv.luma_filter = val;
2447 	else if (property == intel_sdvo_connector->dot_crawl)
2448 		sdvo_state->tv.dot_crawl = val;
2449 	else
2450 		return intel_digital_connector_atomic_set_property(connector, state, property, val);
2451 
2452 	return 0;
2453 }
2454 
2455 static int
2456 intel_sdvo_connector_register(struct drm_connector *connector)
2457 {
2458 	struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector));
2459 	int ret;
2460 
2461 	ret = intel_connector_register(connector);
2462 	if (ret)
2463 		return ret;
2464 
2465 	return sysfs_create_link(&connector->kdev->kobj,
2466 				 &sdvo->ddc.dev.kobj,
2467 				 sdvo->ddc.dev.kobj.name);
2468 }
2469 
2470 static void
2471 intel_sdvo_connector_unregister(struct drm_connector *connector)
2472 {
2473 	struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector));
2474 
2475 	sysfs_remove_link(&connector->kdev->kobj,
2476 			  sdvo->ddc.dev.kobj.name);
2477 	intel_connector_unregister(connector);
2478 }
2479 
2480 static struct drm_connector_state *
2481 intel_sdvo_connector_duplicate_state(struct drm_connector *connector)
2482 {
2483 	struct intel_sdvo_connector_state *state;
2484 
2485 	state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
2486 	if (!state)
2487 		return NULL;
2488 
2489 	__drm_atomic_helper_connector_duplicate_state(connector, &state->base.base);
2490 	return &state->base.base;
2491 }
2492 
2493 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2494 	.detect = intel_sdvo_detect,
2495 	.fill_modes = drm_helper_probe_single_connector_modes,
2496 	.atomic_get_property = intel_sdvo_connector_atomic_get_property,
2497 	.atomic_set_property = intel_sdvo_connector_atomic_set_property,
2498 	.late_register = intel_sdvo_connector_register,
2499 	.early_unregister = intel_sdvo_connector_unregister,
2500 	.destroy = intel_connector_destroy,
2501 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2502 	.atomic_duplicate_state = intel_sdvo_connector_duplicate_state,
2503 };
2504 
2505 static int intel_sdvo_atomic_check(struct drm_connector *conn,
2506 				   struct drm_atomic_state *state)
2507 {
2508 	struct drm_connector_state *new_conn_state =
2509 		drm_atomic_get_new_connector_state(state, conn);
2510 	struct drm_connector_state *old_conn_state =
2511 		drm_atomic_get_old_connector_state(state, conn);
2512 	struct intel_sdvo_connector_state *old_state =
2513 		to_intel_sdvo_connector_state(old_conn_state);
2514 	struct intel_sdvo_connector_state *new_state =
2515 		to_intel_sdvo_connector_state(new_conn_state);
2516 
2517 	if (new_conn_state->crtc &&
2518 	    (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) ||
2519 	     memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) {
2520 		struct drm_crtc_state *crtc_state =
2521 			drm_atomic_get_new_crtc_state(state,
2522 						      new_conn_state->crtc);
2523 
2524 		crtc_state->connectors_changed = true;
2525 	}
2526 
2527 	return intel_digital_connector_atomic_check(conn, state);
2528 }
2529 
2530 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2531 	.get_modes = intel_sdvo_get_modes,
2532 	.mode_valid = intel_sdvo_mode_valid,
2533 	.atomic_check = intel_sdvo_atomic_check,
2534 };
2535 
2536 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
2537 {
2538 	struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
2539 
2540 	i2c_del_adapter(&intel_sdvo->ddc);
2541 	intel_encoder_destroy(encoder);
2542 }
2543 
2544 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2545 	.destroy = intel_sdvo_enc_destroy,
2546 };
2547 
2548 static void
2549 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2550 {
2551 	u16 mask = 0;
2552 	unsigned int num_bits;
2553 
2554 	/*
2555 	 * Make a mask of outputs less than or equal to our own priority in the
2556 	 * list.
2557 	 */
2558 	switch (sdvo->controlled_output) {
2559 	case SDVO_OUTPUT_LVDS1:
2560 		mask |= SDVO_OUTPUT_LVDS1;
2561 		fallthrough;
2562 	case SDVO_OUTPUT_LVDS0:
2563 		mask |= SDVO_OUTPUT_LVDS0;
2564 		fallthrough;
2565 	case SDVO_OUTPUT_TMDS1:
2566 		mask |= SDVO_OUTPUT_TMDS1;
2567 		fallthrough;
2568 	case SDVO_OUTPUT_TMDS0:
2569 		mask |= SDVO_OUTPUT_TMDS0;
2570 		fallthrough;
2571 	case SDVO_OUTPUT_RGB1:
2572 		mask |= SDVO_OUTPUT_RGB1;
2573 		fallthrough;
2574 	case SDVO_OUTPUT_RGB0:
2575 		mask |= SDVO_OUTPUT_RGB0;
2576 		break;
2577 	}
2578 
2579 	/* Count bits to find what number we are in the priority list. */
2580 	mask &= sdvo->caps.output_flags;
2581 	num_bits = hweight16(mask);
2582 	/* If more than 3 outputs, default to DDC bus 3 for now. */
2583 	if (num_bits > 3)
2584 		num_bits = 3;
2585 
2586 	/* Corresponds to SDVO_CONTROL_BUS_DDCx */
2587 	sdvo->ddc_bus = 1 << num_bits;
2588 }
2589 
2590 /*
2591  * Choose the appropriate DDC bus for control bus switch command for this
2592  * SDVO output based on the controlled output.
2593  *
2594  * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2595  * outputs, then LVDS outputs.
2596  */
2597 static void
2598 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
2599 			  struct intel_sdvo *sdvo)
2600 {
2601 	struct sdvo_device_mapping *mapping;
2602 
2603 	if (sdvo->port == PORT_B)
2604 		mapping = &dev_priv->vbt.sdvo_mappings[0];
2605 	else
2606 		mapping = &dev_priv->vbt.sdvo_mappings[1];
2607 
2608 	if (mapping->initialized)
2609 		sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2610 	else
2611 		intel_sdvo_guess_ddc_bus(sdvo);
2612 }
2613 
2614 static void
2615 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2616 			  struct intel_sdvo *sdvo)
2617 {
2618 	struct sdvo_device_mapping *mapping;
2619 	u8 pin;
2620 
2621 	if (sdvo->port == PORT_B)
2622 		mapping = &dev_priv->vbt.sdvo_mappings[0];
2623 	else
2624 		mapping = &dev_priv->vbt.sdvo_mappings[1];
2625 
2626 	if (mapping->initialized &&
2627 	    intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
2628 		pin = mapping->i2c_pin;
2629 	else
2630 		pin = GMBUS_PIN_DPB;
2631 
2632 	sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2633 
2634 	/*
2635 	 * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2636 	 * our code totally fails once we start using gmbus. Hence fall back to
2637 	 * bit banging for now.
2638 	 */
2639 	intel_gmbus_force_bit(sdvo->i2c, true);
2640 }
2641 
2642 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2643 static void
2644 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2645 {
2646 	intel_gmbus_force_bit(sdvo->i2c, false);
2647 }
2648 
2649 static bool
2650 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
2651 {
2652 	return intel_sdvo_check_supp_encode(intel_sdvo);
2653 }
2654 
2655 static u8
2656 intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv,
2657 			  struct intel_sdvo *sdvo)
2658 {
2659 	struct sdvo_device_mapping *my_mapping, *other_mapping;
2660 
2661 	if (sdvo->port == PORT_B) {
2662 		my_mapping = &dev_priv->vbt.sdvo_mappings[0];
2663 		other_mapping = &dev_priv->vbt.sdvo_mappings[1];
2664 	} else {
2665 		my_mapping = &dev_priv->vbt.sdvo_mappings[1];
2666 		other_mapping = &dev_priv->vbt.sdvo_mappings[0];
2667 	}
2668 
2669 	/* If the BIOS described our SDVO device, take advantage of it. */
2670 	if (my_mapping->slave_addr)
2671 		return my_mapping->slave_addr;
2672 
2673 	/*
2674 	 * If the BIOS only described a different SDVO device, use the
2675 	 * address that it isn't using.
2676 	 */
2677 	if (other_mapping->slave_addr) {
2678 		if (other_mapping->slave_addr == 0x70)
2679 			return 0x72;
2680 		else
2681 			return 0x70;
2682 	}
2683 
2684 	/*
2685 	 * No SDVO device info is found for another DVO port,
2686 	 * so use mapping assumption we had before BIOS parsing.
2687 	 */
2688 	if (sdvo->port == PORT_B)
2689 		return 0x70;
2690 	else
2691 		return 0x72;
2692 }
2693 
2694 static int
2695 intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2696 			  struct intel_sdvo *encoder)
2697 {
2698 	struct drm_connector *drm_connector;
2699 	int ret;
2700 
2701 	drm_connector = &connector->base.base;
2702 	ret = drm_connector_init(encoder->base.base.dev,
2703 			   drm_connector,
2704 			   &intel_sdvo_connector_funcs,
2705 			   connector->base.base.connector_type);
2706 	if (ret < 0)
2707 		return ret;
2708 
2709 	drm_connector_helper_add(drm_connector,
2710 				 &intel_sdvo_connector_helper_funcs);
2711 
2712 	connector->base.base.interlace_allowed = 1;
2713 	connector->base.base.doublescan_allowed = 0;
2714 	connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
2715 	connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
2716 
2717 	intel_connector_attach_encoder(&connector->base, &encoder->base);
2718 
2719 	return 0;
2720 }
2721 
2722 static void
2723 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2724 			       struct intel_sdvo_connector *connector)
2725 {
2726 	intel_attach_force_audio_property(&connector->base.base);
2727 	if (intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220)
2728 		intel_attach_broadcast_rgb_property(&connector->base.base);
2729 	intel_attach_aspect_ratio_property(&connector->base.base);
2730 }
2731 
2732 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
2733 {
2734 	struct intel_sdvo_connector *sdvo_connector;
2735 	struct intel_sdvo_connector_state *conn_state;
2736 
2737 	sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL);
2738 	if (!sdvo_connector)
2739 		return NULL;
2740 
2741 	conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
2742 	if (!conn_state) {
2743 		kfree(sdvo_connector);
2744 		return NULL;
2745 	}
2746 
2747 	__drm_atomic_helper_connector_reset(&sdvo_connector->base.base,
2748 					    &conn_state->base.base);
2749 
2750 	return sdvo_connector;
2751 }
2752 
2753 static bool
2754 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
2755 {
2756 	struct drm_encoder *encoder = &intel_sdvo->base.base;
2757 	struct drm_connector *connector;
2758 	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2759 	struct intel_connector *intel_connector;
2760 	struct intel_sdvo_connector *intel_sdvo_connector;
2761 
2762 	DRM_DEBUG_KMS("initialising DVI device %d\n", device);
2763 
2764 	intel_sdvo_connector = intel_sdvo_connector_alloc();
2765 	if (!intel_sdvo_connector)
2766 		return false;
2767 
2768 	if (device == 0) {
2769 		intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
2770 		intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
2771 	} else if (device == 1) {
2772 		intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
2773 		intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
2774 	}
2775 
2776 	intel_connector = &intel_sdvo_connector->base;
2777 	connector = &intel_connector->base;
2778 	if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2779 		intel_sdvo_connector->output_flag) {
2780 		intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
2781 		/*
2782 		 * Some SDVO devices have one-shot hotplug interrupts.
2783 		 * Ensure that they get re-enabled when an interrupt happens.
2784 		 */
2785 		intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
2786 		intel_encoder->hotplug = intel_sdvo_hotplug;
2787 		intel_sdvo_enable_hotplug(intel_encoder);
2788 	} else {
2789 		intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
2790 	}
2791 	encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2792 	connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2793 
2794 	if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
2795 		connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2796 		intel_sdvo_connector->is_hdmi = true;
2797 	}
2798 
2799 	if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2800 		kfree(intel_sdvo_connector);
2801 		return false;
2802 	}
2803 
2804 	if (intel_sdvo_connector->is_hdmi)
2805 		intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
2806 
2807 	return true;
2808 }
2809 
2810 static bool
2811 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
2812 {
2813 	struct drm_encoder *encoder = &intel_sdvo->base.base;
2814 	struct drm_connector *connector;
2815 	struct intel_connector *intel_connector;
2816 	struct intel_sdvo_connector *intel_sdvo_connector;
2817 
2818 	DRM_DEBUG_KMS("initialising TV type %d\n", type);
2819 
2820 	intel_sdvo_connector = intel_sdvo_connector_alloc();
2821 	if (!intel_sdvo_connector)
2822 		return false;
2823 
2824 	intel_connector = &intel_sdvo_connector->base;
2825 	connector = &intel_connector->base;
2826 	encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2827 	connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2828 
2829 	intel_sdvo->controlled_output |= type;
2830 	intel_sdvo_connector->output_flag = type;
2831 
2832 	if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2833 		kfree(intel_sdvo_connector);
2834 		return false;
2835 	}
2836 
2837 	if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2838 		goto err;
2839 
2840 	if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2841 		goto err;
2842 
2843 	return true;
2844 
2845 err:
2846 	intel_connector_destroy(connector);
2847 	return false;
2848 }
2849 
2850 static bool
2851 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
2852 {
2853 	struct drm_encoder *encoder = &intel_sdvo->base.base;
2854 	struct drm_connector *connector;
2855 	struct intel_connector *intel_connector;
2856 	struct intel_sdvo_connector *intel_sdvo_connector;
2857 
2858 	DRM_DEBUG_KMS("initialising analog device %d\n", device);
2859 
2860 	intel_sdvo_connector = intel_sdvo_connector_alloc();
2861 	if (!intel_sdvo_connector)
2862 		return false;
2863 
2864 	intel_connector = &intel_sdvo_connector->base;
2865 	connector = &intel_connector->base;
2866 	intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2867 	encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2868 	connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2869 
2870 	if (device == 0) {
2871 		intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2872 		intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2873 	} else if (device == 1) {
2874 		intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2875 		intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2876 	}
2877 
2878 	if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2879 		kfree(intel_sdvo_connector);
2880 		return false;
2881 	}
2882 
2883 	return true;
2884 }
2885 
2886 static bool
2887 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
2888 {
2889 	struct drm_encoder *encoder = &intel_sdvo->base.base;
2890 	struct drm_connector *connector;
2891 	struct intel_connector *intel_connector;
2892 	struct intel_sdvo_connector *intel_sdvo_connector;
2893 	struct drm_display_mode *mode;
2894 
2895 	DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
2896 
2897 	intel_sdvo_connector = intel_sdvo_connector_alloc();
2898 	if (!intel_sdvo_connector)
2899 		return false;
2900 
2901 	intel_connector = &intel_sdvo_connector->base;
2902 	connector = &intel_connector->base;
2903 	encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2904 	connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2905 
2906 	if (device == 0) {
2907 		intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2908 		intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2909 	} else if (device == 1) {
2910 		intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2911 		intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2912 	}
2913 
2914 	if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2915 		kfree(intel_sdvo_connector);
2916 		return false;
2917 	}
2918 
2919 	if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2920 		goto err;
2921 
2922 	intel_sdvo_get_lvds_modes(connector);
2923 
2924 	list_for_each_entry(mode, &connector->probed_modes, head) {
2925 		if (mode->type & DRM_MODE_TYPE_PREFERRED) {
2926 			struct drm_display_mode *fixed_mode =
2927 				drm_mode_duplicate(connector->dev, mode);
2928 
2929 			intel_panel_init(&intel_connector->panel,
2930 					 fixed_mode, NULL);
2931 			break;
2932 		}
2933 	}
2934 
2935 	if (!intel_connector->panel.fixed_mode)
2936 		goto err;
2937 
2938 	return true;
2939 
2940 err:
2941 	intel_connector_destroy(connector);
2942 	return false;
2943 }
2944 
2945 static bool
2946 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, u16 flags)
2947 {
2948 	/* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
2949 
2950 	if (flags & SDVO_OUTPUT_TMDS0)
2951 		if (!intel_sdvo_dvi_init(intel_sdvo, 0))
2952 			return false;
2953 
2954 	if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
2955 		if (!intel_sdvo_dvi_init(intel_sdvo, 1))
2956 			return false;
2957 
2958 	/* TV has no XXX1 function block */
2959 	if (flags & SDVO_OUTPUT_SVID0)
2960 		if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
2961 			return false;
2962 
2963 	if (flags & SDVO_OUTPUT_CVBS0)
2964 		if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
2965 			return false;
2966 
2967 	if (flags & SDVO_OUTPUT_YPRPB0)
2968 		if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2969 			return false;
2970 
2971 	if (flags & SDVO_OUTPUT_RGB0)
2972 		if (!intel_sdvo_analog_init(intel_sdvo, 0))
2973 			return false;
2974 
2975 	if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
2976 		if (!intel_sdvo_analog_init(intel_sdvo, 1))
2977 			return false;
2978 
2979 	if (flags & SDVO_OUTPUT_LVDS0)
2980 		if (!intel_sdvo_lvds_init(intel_sdvo, 0))
2981 			return false;
2982 
2983 	if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
2984 		if (!intel_sdvo_lvds_init(intel_sdvo, 1))
2985 			return false;
2986 
2987 	if ((flags & SDVO_OUTPUT_MASK) == 0) {
2988 		unsigned char bytes[2];
2989 
2990 		intel_sdvo->controlled_output = 0;
2991 		memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
2992 		DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2993 			      SDVO_NAME(intel_sdvo),
2994 			      bytes[0], bytes[1]);
2995 		return false;
2996 	}
2997 	intel_sdvo->base.pipe_mask = ~0;
2998 
2999 	return true;
3000 }
3001 
3002 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
3003 {
3004 	struct drm_device *dev = intel_sdvo->base.base.dev;
3005 	struct drm_connector *connector, *tmp;
3006 
3007 	list_for_each_entry_safe(connector, tmp,
3008 				 &dev->mode_config.connector_list, head) {
3009 		if (intel_attached_encoder(to_intel_connector(connector)) == &intel_sdvo->base) {
3010 			drm_connector_unregister(connector);
3011 			intel_connector_destroy(connector);
3012 		}
3013 	}
3014 }
3015 
3016 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
3017 					  struct intel_sdvo_connector *intel_sdvo_connector,
3018 					  int type)
3019 {
3020 	struct drm_device *dev = intel_sdvo->base.base.dev;
3021 	struct intel_sdvo_tv_format format;
3022 	u32 format_map, i;
3023 
3024 	if (!intel_sdvo_set_target_output(intel_sdvo, type))
3025 		return false;
3026 
3027 	BUILD_BUG_ON(sizeof(format) != 6);
3028 	if (!intel_sdvo_get_value(intel_sdvo,
3029 				  SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
3030 				  &format, sizeof(format)))
3031 		return false;
3032 
3033 	memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
3034 
3035 	if (format_map == 0)
3036 		return false;
3037 
3038 	intel_sdvo_connector->format_supported_num = 0;
3039 	for (i = 0 ; i < TV_FORMAT_NUM; i++)
3040 		if (format_map & (1 << i))
3041 			intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
3042 
3043 
3044 	intel_sdvo_connector->tv_format =
3045 			drm_property_create(dev, DRM_MODE_PROP_ENUM,
3046 					    "mode", intel_sdvo_connector->format_supported_num);
3047 	if (!intel_sdvo_connector->tv_format)
3048 		return false;
3049 
3050 	for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
3051 		drm_property_add_enum(intel_sdvo_connector->tv_format, i,
3052 				      tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
3053 
3054 	intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0];
3055 	drm_object_attach_property(&intel_sdvo_connector->base.base.base,
3056 				   intel_sdvo_connector->tv_format, 0);
3057 	return true;
3058 
3059 }
3060 
3061 #define _ENHANCEMENT(state_assignment, name, NAME) do { \
3062 	if (enhancements.name) { \
3063 		if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
3064 		    !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
3065 			return false; \
3066 		intel_sdvo_connector->name = \
3067 			drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
3068 		if (!intel_sdvo_connector->name) return false; \
3069 		state_assignment = response; \
3070 		drm_object_attach_property(&connector->base, \
3071 					   intel_sdvo_connector->name, 0); \
3072 		DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
3073 			      data_value[0], data_value[1], response); \
3074 	} \
3075 } while (0)
3076 
3077 #define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME)
3078 
3079 static bool
3080 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
3081 				      struct intel_sdvo_connector *intel_sdvo_connector,
3082 				      struct intel_sdvo_enhancements_reply enhancements)
3083 {
3084 	struct drm_device *dev = intel_sdvo->base.base.dev;
3085 	struct drm_connector *connector = &intel_sdvo_connector->base.base;
3086 	struct drm_connector_state *conn_state = connector->state;
3087 	struct intel_sdvo_connector_state *sdvo_state =
3088 		to_intel_sdvo_connector_state(conn_state);
3089 	u16 response, data_value[2];
3090 
3091 	/* when horizontal overscan is supported, Add the left/right property */
3092 	if (enhancements.overscan_h) {
3093 		if (!intel_sdvo_get_value(intel_sdvo,
3094 					  SDVO_CMD_GET_MAX_OVERSCAN_H,
3095 					  &data_value, 4))
3096 			return false;
3097 
3098 		if (!intel_sdvo_get_value(intel_sdvo,
3099 					  SDVO_CMD_GET_OVERSCAN_H,
3100 					  &response, 2))
3101 			return false;
3102 
3103 		sdvo_state->tv.overscan_h = response;
3104 
3105 		intel_sdvo_connector->max_hscan = data_value[0];
3106 		intel_sdvo_connector->left =
3107 			drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
3108 		if (!intel_sdvo_connector->left)
3109 			return false;
3110 
3111 		drm_object_attach_property(&connector->base,
3112 					   intel_sdvo_connector->left, 0);
3113 
3114 		intel_sdvo_connector->right =
3115 			drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
3116 		if (!intel_sdvo_connector->right)
3117 			return false;
3118 
3119 		drm_object_attach_property(&connector->base,
3120 					      intel_sdvo_connector->right, 0);
3121 		DRM_DEBUG_KMS("h_overscan: max %d, "
3122 			      "default %d, current %d\n",
3123 			      data_value[0], data_value[1], response);
3124 	}
3125 
3126 	if (enhancements.overscan_v) {
3127 		if (!intel_sdvo_get_value(intel_sdvo,
3128 					  SDVO_CMD_GET_MAX_OVERSCAN_V,
3129 					  &data_value, 4))
3130 			return false;
3131 
3132 		if (!intel_sdvo_get_value(intel_sdvo,
3133 					  SDVO_CMD_GET_OVERSCAN_V,
3134 					  &response, 2))
3135 			return false;
3136 
3137 		sdvo_state->tv.overscan_v = response;
3138 
3139 		intel_sdvo_connector->max_vscan = data_value[0];
3140 		intel_sdvo_connector->top =
3141 			drm_property_create_range(dev, 0,
3142 					    "top_margin", 0, data_value[0]);
3143 		if (!intel_sdvo_connector->top)
3144 			return false;
3145 
3146 		drm_object_attach_property(&connector->base,
3147 					   intel_sdvo_connector->top, 0);
3148 
3149 		intel_sdvo_connector->bottom =
3150 			drm_property_create_range(dev, 0,
3151 					    "bottom_margin", 0, data_value[0]);
3152 		if (!intel_sdvo_connector->bottom)
3153 			return false;
3154 
3155 		drm_object_attach_property(&connector->base,
3156 					      intel_sdvo_connector->bottom, 0);
3157 		DRM_DEBUG_KMS("v_overscan: max %d, "
3158 			      "default %d, current %d\n",
3159 			      data_value[0], data_value[1], response);
3160 	}
3161 
3162 	ENHANCEMENT(&sdvo_state->tv, hpos, HPOS);
3163 	ENHANCEMENT(&sdvo_state->tv, vpos, VPOS);
3164 	ENHANCEMENT(&conn_state->tv, saturation, SATURATION);
3165 	ENHANCEMENT(&conn_state->tv, contrast, CONTRAST);
3166 	ENHANCEMENT(&conn_state->tv, hue, HUE);
3167 	ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS);
3168 	ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS);
3169 	ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER);
3170 	ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
3171 	ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D);
3172 	_ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER);
3173 	_ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER);
3174 
3175 	if (enhancements.dot_crawl) {
3176 		if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
3177 			return false;
3178 
3179 		sdvo_state->tv.dot_crawl = response & 0x1;
3180 		intel_sdvo_connector->dot_crawl =
3181 			drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
3182 		if (!intel_sdvo_connector->dot_crawl)
3183 			return false;
3184 
3185 		drm_object_attach_property(&connector->base,
3186 					   intel_sdvo_connector->dot_crawl, 0);
3187 		DRM_DEBUG_KMS("dot crawl: current %d\n", response);
3188 	}
3189 
3190 	return true;
3191 }
3192 
3193 static bool
3194 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
3195 					struct intel_sdvo_connector *intel_sdvo_connector,
3196 					struct intel_sdvo_enhancements_reply enhancements)
3197 {
3198 	struct drm_device *dev = intel_sdvo->base.base.dev;
3199 	struct drm_connector *connector = &intel_sdvo_connector->base.base;
3200 	u16 response, data_value[2];
3201 
3202 	ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS);
3203 
3204 	return true;
3205 }
3206 #undef ENHANCEMENT
3207 #undef _ENHANCEMENT
3208 
3209 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
3210 					       struct intel_sdvo_connector *intel_sdvo_connector)
3211 {
3212 	union {
3213 		struct intel_sdvo_enhancements_reply reply;
3214 		u16 response;
3215 	} enhancements;
3216 
3217 	BUILD_BUG_ON(sizeof(enhancements) != 2);
3218 
3219 	if (!intel_sdvo_get_value(intel_sdvo,
3220 				  SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
3221 				  &enhancements, sizeof(enhancements)) ||
3222 	    enhancements.response == 0) {
3223 		DRM_DEBUG_KMS("No enhancement is supported\n");
3224 		return true;
3225 	}
3226 
3227 	if (IS_TV(intel_sdvo_connector))
3228 		return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
3229 	else if (IS_LVDS(intel_sdvo_connector))
3230 		return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
3231 	else
3232 		return true;
3233 }
3234 
3235 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
3236 				     struct i2c_msg *msgs,
3237 				     int num)
3238 {
3239 	struct intel_sdvo *sdvo = adapter->algo_data;
3240 
3241 	if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
3242 		return -EIO;
3243 
3244 	return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
3245 }
3246 
3247 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
3248 {
3249 	struct intel_sdvo *sdvo = adapter->algo_data;
3250 	return sdvo->i2c->algo->functionality(sdvo->i2c);
3251 }
3252 
3253 static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
3254 	.master_xfer	= intel_sdvo_ddc_proxy_xfer,
3255 	.functionality	= intel_sdvo_ddc_proxy_func
3256 };
3257 
3258 static void proxy_lock_bus(struct i2c_adapter *adapter,
3259 			   unsigned int flags)
3260 {
3261 	struct intel_sdvo *sdvo = adapter->algo_data;
3262 	sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags);
3263 }
3264 
3265 static int proxy_trylock_bus(struct i2c_adapter *adapter,
3266 			     unsigned int flags)
3267 {
3268 	struct intel_sdvo *sdvo = adapter->algo_data;
3269 	return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags);
3270 }
3271 
3272 static void proxy_unlock_bus(struct i2c_adapter *adapter,
3273 			     unsigned int flags)
3274 {
3275 	struct intel_sdvo *sdvo = adapter->algo_data;
3276 	sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags);
3277 }
3278 
3279 static const struct i2c_lock_operations proxy_lock_ops = {
3280 	.lock_bus =    proxy_lock_bus,
3281 	.trylock_bus = proxy_trylock_bus,
3282 	.unlock_bus =  proxy_unlock_bus,
3283 };
3284 
3285 static bool
3286 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
3287 			  struct drm_i915_private *dev_priv)
3288 {
3289 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
3290 
3291 	sdvo->ddc.owner = THIS_MODULE;
3292 	sdvo->ddc.class = I2C_CLASS_DDC;
3293 	snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
3294 	sdvo->ddc.dev.parent = &pdev->dev;
3295 	sdvo->ddc.algo_data = sdvo;
3296 	sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
3297 	sdvo->ddc.lock_ops = &proxy_lock_ops;
3298 
3299 	return i2c_add_adapter(&sdvo->ddc) == 0;
3300 }
3301 
3302 static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv,
3303 				   enum port port)
3304 {
3305 	if (HAS_PCH_SPLIT(dev_priv))
3306 		drm_WARN_ON(&dev_priv->drm, port != PORT_B);
3307 	else
3308 		drm_WARN_ON(&dev_priv->drm, port != PORT_B && port != PORT_C);
3309 }
3310 
3311 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
3312 		     i915_reg_t sdvo_reg, enum port port)
3313 {
3314 	struct intel_encoder *intel_encoder;
3315 	struct intel_sdvo *intel_sdvo;
3316 	int i;
3317 
3318 	assert_sdvo_port_valid(dev_priv, port);
3319 
3320 	intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
3321 	if (!intel_sdvo)
3322 		return false;
3323 
3324 	intel_sdvo->sdvo_reg = sdvo_reg;
3325 	intel_sdvo->port = port;
3326 	intel_sdvo->slave_addr =
3327 		intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1;
3328 	intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
3329 	if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv))
3330 		goto err_i2c_bus;
3331 
3332 	/* encoder type will be decided later */
3333 	intel_encoder = &intel_sdvo->base;
3334 	intel_encoder->type = INTEL_OUTPUT_SDVO;
3335 	intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
3336 	intel_encoder->port = port;
3337 	drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3338 			 &intel_sdvo_enc_funcs, 0,
3339 			 "SDVO %c", port_name(port));
3340 
3341 	/* Read the regs to test if we can talk to the device */
3342 	for (i = 0; i < 0x40; i++) {
3343 		u8 byte;
3344 
3345 		if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
3346 			drm_dbg_kms(&dev_priv->drm,
3347 				    "No SDVO device found on %s\n",
3348 				    SDVO_NAME(intel_sdvo));
3349 			goto err;
3350 		}
3351 	}
3352 
3353 	intel_encoder->compute_config = intel_sdvo_compute_config;
3354 	if (HAS_PCH_SPLIT(dev_priv)) {
3355 		intel_encoder->disable = pch_disable_sdvo;
3356 		intel_encoder->post_disable = pch_post_disable_sdvo;
3357 	} else {
3358 		intel_encoder->disable = intel_disable_sdvo;
3359 	}
3360 	intel_encoder->pre_enable = intel_sdvo_pre_enable;
3361 	intel_encoder->enable = intel_enable_sdvo;
3362 	intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
3363 	intel_encoder->get_config = intel_sdvo_get_config;
3364 
3365 	/* In default case sdvo lvds is false */
3366 	if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
3367 		goto err;
3368 
3369 	intel_sdvo->colorimetry_cap =
3370 		intel_sdvo_get_colorimetry_cap(intel_sdvo);
3371 
3372 	if (intel_sdvo_output_setup(intel_sdvo,
3373 				    intel_sdvo->caps.output_flags) != true) {
3374 		drm_dbg_kms(&dev_priv->drm,
3375 			    "SDVO output failed to setup on %s\n",
3376 			    SDVO_NAME(intel_sdvo));
3377 		/* Output_setup can leave behind connectors! */
3378 		goto err_output;
3379 	}
3380 
3381 	/*
3382 	 * Only enable the hotplug irq if we need it, to work around noisy
3383 	 * hotplug lines.
3384 	 */
3385 	if (intel_sdvo->hotplug_active) {
3386 		if (intel_sdvo->port == PORT_B)
3387 			intel_encoder->hpd_pin = HPD_SDVO_B;
3388 		else
3389 			intel_encoder->hpd_pin = HPD_SDVO_C;
3390 	}
3391 
3392 	/*
3393 	 * Cloning SDVO with anything is often impossible, since the SDVO
3394 	 * encoder can request a special input timing mode. And even if that's
3395 	 * not the case we have evidence that cloning a plain unscaled mode with
3396 	 * VGA doesn't really work. Furthermore the cloning flags are way too
3397 	 * simplistic anyway to express such constraints, so just give up on
3398 	 * cloning for SDVO encoders.
3399 	 */
3400 	intel_sdvo->base.cloneable = 0;
3401 
3402 	intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo);
3403 
3404 	/* Set the input timing to the screen. Assume always input 0. */
3405 	if (!intel_sdvo_set_target_input(intel_sdvo))
3406 		goto err_output;
3407 
3408 	if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3409 						    &intel_sdvo->pixel_clock_min,
3410 						    &intel_sdvo->pixel_clock_max))
3411 		goto err_output;
3412 
3413 	drm_dbg_kms(&dev_priv->drm, "%s device VID/DID: %02X:%02X.%02X, "
3414 			"clock range %dMHz - %dMHz, "
3415 			"input 1: %c, input 2: %c, "
3416 			"output 1: %c, output 2: %c\n",
3417 			SDVO_NAME(intel_sdvo),
3418 			intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3419 			intel_sdvo->caps.device_rev_id,
3420 			intel_sdvo->pixel_clock_min / 1000,
3421 			intel_sdvo->pixel_clock_max / 1000,
3422 			(intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
3423 			(intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
3424 			/* check currently supported outputs */
3425 			intel_sdvo->caps.output_flags &
3426 			(SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
3427 			intel_sdvo->caps.output_flags &
3428 			(SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
3429 	return true;
3430 
3431 err_output:
3432 	intel_sdvo_output_cleanup(intel_sdvo);
3433 
3434 err:
3435 	drm_encoder_cleanup(&intel_encoder->base);
3436 	i2c_del_adapter(&intel_sdvo->ddc);
3437 err_i2c_bus:
3438 	intel_sdvo_unselect_i2c_bus(intel_sdvo);
3439 	kfree(intel_sdvo);
3440 
3441 	return false;
3442 }
3443