1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/export.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 #include <drm/i915_drm.h> 38 39 #include "i915_drv.h" 40 #include "intel_atomic.h" 41 #include "intel_connector.h" 42 #include "intel_display_types.h" 43 #include "intel_fifo_underrun.h" 44 #include "intel_gmbus.h" 45 #include "intel_hdmi.h" 46 #include "intel_hotplug.h" 47 #include "intel_panel.h" 48 #include "intel_sdvo.h" 49 #include "intel_sdvo_regs.h" 50 51 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 52 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 53 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 54 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) 55 56 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ 57 SDVO_TV_MASK) 58 59 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 60 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) 61 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 62 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 63 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) 64 65 66 static const char * const tv_format_names[] = { 67 "NTSC_M" , "NTSC_J" , "NTSC_443", 68 "PAL_B" , "PAL_D" , "PAL_G" , 69 "PAL_H" , "PAL_I" , "PAL_M" , 70 "PAL_N" , "PAL_NC" , "PAL_60" , 71 "SECAM_B" , "SECAM_D" , "SECAM_G" , 72 "SECAM_K" , "SECAM_K1", "SECAM_L" , 73 "SECAM_60" 74 }; 75 76 #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names) 77 78 struct intel_sdvo { 79 struct intel_encoder base; 80 81 struct i2c_adapter *i2c; 82 u8 slave_addr; 83 84 struct i2c_adapter ddc; 85 86 /* Register for the SDVO device: SDVOB or SDVOC */ 87 i915_reg_t sdvo_reg; 88 89 /* Active outputs controlled by this SDVO output */ 90 u16 controlled_output; 91 92 /* 93 * Capabilities of the SDVO device returned by 94 * intel_sdvo_get_capabilities() 95 */ 96 struct intel_sdvo_caps caps; 97 98 /* Pixel clock limitations reported by the SDVO device, in kHz */ 99 int pixel_clock_min, pixel_clock_max; 100 101 /* 102 * For multiple function SDVO device, 103 * this is for current attached outputs. 104 */ 105 u16 attached_output; 106 107 /* 108 * Hotplug activation bits for this device 109 */ 110 u16 hotplug_active; 111 112 enum port port; 113 114 bool has_hdmi_monitor; 115 bool has_hdmi_audio; 116 117 /* DDC bus used by this SDVO encoder */ 118 u8 ddc_bus; 119 120 /* 121 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd 122 */ 123 u8 dtd_sdvo_flags; 124 }; 125 126 struct intel_sdvo_connector { 127 struct intel_connector base; 128 129 /* Mark the type of connector */ 130 u16 output_flag; 131 132 /* This contains all current supported TV format */ 133 u8 tv_format_supported[TV_FORMAT_NUM]; 134 int format_supported_num; 135 struct drm_property *tv_format; 136 137 /* add the property for the SDVO-TV */ 138 struct drm_property *left; 139 struct drm_property *right; 140 struct drm_property *top; 141 struct drm_property *bottom; 142 struct drm_property *hpos; 143 struct drm_property *vpos; 144 struct drm_property *contrast; 145 struct drm_property *saturation; 146 struct drm_property *hue; 147 struct drm_property *sharpness; 148 struct drm_property *flicker_filter; 149 struct drm_property *flicker_filter_adaptive; 150 struct drm_property *flicker_filter_2d; 151 struct drm_property *tv_chroma_filter; 152 struct drm_property *tv_luma_filter; 153 struct drm_property *dot_crawl; 154 155 /* add the property for the SDVO-TV/LVDS */ 156 struct drm_property *brightness; 157 158 /* this is to get the range of margin.*/ 159 u32 max_hscan, max_vscan; 160 161 /** 162 * This is set if we treat the device as HDMI, instead of DVI. 163 */ 164 bool is_hdmi; 165 }; 166 167 struct intel_sdvo_connector_state { 168 /* base.base: tv.saturation/contrast/hue/brightness */ 169 struct intel_digital_connector_state base; 170 171 struct { 172 unsigned overscan_h, overscan_v, hpos, vpos, sharpness; 173 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive; 174 unsigned chroma_filter, luma_filter, dot_crawl; 175 } tv; 176 }; 177 178 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) 179 { 180 return container_of(encoder, struct intel_sdvo, base); 181 } 182 183 static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) 184 { 185 return to_sdvo(intel_attached_encoder(connector)); 186 } 187 188 static struct intel_sdvo_connector * 189 to_intel_sdvo_connector(struct drm_connector *connector) 190 { 191 return container_of(connector, struct intel_sdvo_connector, base.base); 192 } 193 194 #define to_intel_sdvo_connector_state(conn_state) \ 195 container_of((conn_state), struct intel_sdvo_connector_state, base.base) 196 197 static bool 198 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, u16 flags); 199 static bool 200 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 201 struct intel_sdvo_connector *intel_sdvo_connector, 202 int type); 203 static bool 204 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 205 struct intel_sdvo_connector *intel_sdvo_connector); 206 207 /* 208 * Writes the SDVOB or SDVOC with the given value, but always writes both 209 * SDVOB and SDVOC to work around apparent hardware issues (according to 210 * comments in the BIOS). 211 */ 212 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 213 { 214 struct drm_device *dev = intel_sdvo->base.base.dev; 215 struct drm_i915_private *dev_priv = to_i915(dev); 216 u32 bval = val, cval = val; 217 int i; 218 219 if (HAS_PCH_SPLIT(dev_priv)) { 220 I915_WRITE(intel_sdvo->sdvo_reg, val); 221 POSTING_READ(intel_sdvo->sdvo_reg); 222 /* 223 * HW workaround, need to write this twice for issue 224 * that may result in first write getting masked. 225 */ 226 if (HAS_PCH_IBX(dev_priv)) { 227 I915_WRITE(intel_sdvo->sdvo_reg, val); 228 POSTING_READ(intel_sdvo->sdvo_reg); 229 } 230 return; 231 } 232 233 if (intel_sdvo->port == PORT_B) 234 cval = I915_READ(GEN3_SDVOC); 235 else 236 bval = I915_READ(GEN3_SDVOB); 237 238 /* 239 * Write the registers twice for luck. Sometimes, 240 * writing them only once doesn't appear to 'stick'. 241 * The BIOS does this too. Yay, magic 242 */ 243 for (i = 0; i < 2; i++) { 244 I915_WRITE(GEN3_SDVOB, bval); 245 POSTING_READ(GEN3_SDVOB); 246 247 I915_WRITE(GEN3_SDVOC, cval); 248 POSTING_READ(GEN3_SDVOC); 249 } 250 } 251 252 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 253 { 254 struct i2c_msg msgs[] = { 255 { 256 .addr = intel_sdvo->slave_addr, 257 .flags = 0, 258 .len = 1, 259 .buf = &addr, 260 }, 261 { 262 .addr = intel_sdvo->slave_addr, 263 .flags = I2C_M_RD, 264 .len = 1, 265 .buf = ch, 266 } 267 }; 268 int ret; 269 270 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) 271 return true; 272 273 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); 274 return false; 275 } 276 277 #define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ } 278 279 /** Mapping of command numbers to names, for debug output */ 280 static const struct { 281 u8 cmd; 282 const char *name; 283 } __attribute__ ((packed)) sdvo_cmd_names[] = { 284 SDVO_CMD_NAME_ENTRY(RESET), 285 SDVO_CMD_NAME_ENTRY(GET_DEVICE_CAPS), 286 SDVO_CMD_NAME_ENTRY(GET_FIRMWARE_REV), 287 SDVO_CMD_NAME_ENTRY(GET_TRAINED_INPUTS), 288 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_OUTPUTS), 289 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_OUTPUTS), 290 SDVO_CMD_NAME_ENTRY(GET_IN_OUT_MAP), 291 SDVO_CMD_NAME_ENTRY(SET_IN_OUT_MAP), 292 SDVO_CMD_NAME_ENTRY(GET_ATTACHED_DISPLAYS), 293 SDVO_CMD_NAME_ENTRY(GET_HOT_PLUG_SUPPORT), 294 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_HOT_PLUG), 295 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_HOT_PLUG), 296 SDVO_CMD_NAME_ENTRY(GET_INTERRUPT_EVENT_SOURCE), 297 SDVO_CMD_NAME_ENTRY(SET_TARGET_INPUT), 298 SDVO_CMD_NAME_ENTRY(SET_TARGET_OUTPUT), 299 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART1), 300 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART2), 301 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART1), 302 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART2), 303 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART1), 304 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART2), 305 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART1), 306 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART2), 307 SDVO_CMD_NAME_ENTRY(CREATE_PREFERRED_INPUT_TIMING), 308 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART1), 309 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART2), 310 SDVO_CMD_NAME_ENTRY(GET_INPUT_PIXEL_CLOCK_RANGE), 311 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_PIXEL_CLOCK_RANGE), 312 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_CLOCK_RATE_MULTS), 313 SDVO_CMD_NAME_ENTRY(GET_CLOCK_RATE_MULT), 314 SDVO_CMD_NAME_ENTRY(SET_CLOCK_RATE_MULT), 315 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_TV_FORMATS), 316 SDVO_CMD_NAME_ENTRY(GET_TV_FORMAT), 317 SDVO_CMD_NAME_ENTRY(SET_TV_FORMAT), 318 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_POWER_STATES), 319 SDVO_CMD_NAME_ENTRY(GET_POWER_STATE), 320 SDVO_CMD_NAME_ENTRY(SET_ENCODER_POWER_STATE), 321 SDVO_CMD_NAME_ENTRY(SET_DISPLAY_POWER_STATE), 322 SDVO_CMD_NAME_ENTRY(SET_CONTROL_BUS_SWITCH), 323 SDVO_CMD_NAME_ENTRY(GET_SDTV_RESOLUTION_SUPPORT), 324 SDVO_CMD_NAME_ENTRY(GET_SCALED_HDTV_RESOLUTION_SUPPORT), 325 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_ENHANCEMENTS), 326 327 /* Add the op code for SDVO enhancements */ 328 SDVO_CMD_NAME_ENTRY(GET_MAX_HPOS), 329 SDVO_CMD_NAME_ENTRY(GET_HPOS), 330 SDVO_CMD_NAME_ENTRY(SET_HPOS), 331 SDVO_CMD_NAME_ENTRY(GET_MAX_VPOS), 332 SDVO_CMD_NAME_ENTRY(GET_VPOS), 333 SDVO_CMD_NAME_ENTRY(SET_VPOS), 334 SDVO_CMD_NAME_ENTRY(GET_MAX_SATURATION), 335 SDVO_CMD_NAME_ENTRY(GET_SATURATION), 336 SDVO_CMD_NAME_ENTRY(SET_SATURATION), 337 SDVO_CMD_NAME_ENTRY(GET_MAX_HUE), 338 SDVO_CMD_NAME_ENTRY(GET_HUE), 339 SDVO_CMD_NAME_ENTRY(SET_HUE), 340 SDVO_CMD_NAME_ENTRY(GET_MAX_CONTRAST), 341 SDVO_CMD_NAME_ENTRY(GET_CONTRAST), 342 SDVO_CMD_NAME_ENTRY(SET_CONTRAST), 343 SDVO_CMD_NAME_ENTRY(GET_MAX_BRIGHTNESS), 344 SDVO_CMD_NAME_ENTRY(GET_BRIGHTNESS), 345 SDVO_CMD_NAME_ENTRY(SET_BRIGHTNESS), 346 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_H), 347 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_H), 348 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_H), 349 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_V), 350 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_V), 351 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_V), 352 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER), 353 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER), 354 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER), 355 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_ADAPTIVE), 356 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_ADAPTIVE), 357 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_ADAPTIVE), 358 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_2D), 359 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_2D), 360 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_2D), 361 SDVO_CMD_NAME_ENTRY(GET_MAX_SHARPNESS), 362 SDVO_CMD_NAME_ENTRY(GET_SHARPNESS), 363 SDVO_CMD_NAME_ENTRY(SET_SHARPNESS), 364 SDVO_CMD_NAME_ENTRY(GET_DOT_CRAWL), 365 SDVO_CMD_NAME_ENTRY(SET_DOT_CRAWL), 366 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_CHROMA_FILTER), 367 SDVO_CMD_NAME_ENTRY(GET_TV_CHROMA_FILTER), 368 SDVO_CMD_NAME_ENTRY(SET_TV_CHROMA_FILTER), 369 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_LUMA_FILTER), 370 SDVO_CMD_NAME_ENTRY(GET_TV_LUMA_FILTER), 371 SDVO_CMD_NAME_ENTRY(SET_TV_LUMA_FILTER), 372 373 /* HDMI op code */ 374 SDVO_CMD_NAME_ENTRY(GET_SUPP_ENCODE), 375 SDVO_CMD_NAME_ENTRY(GET_ENCODE), 376 SDVO_CMD_NAME_ENTRY(SET_ENCODE), 377 SDVO_CMD_NAME_ENTRY(SET_PIXEL_REPLI), 378 SDVO_CMD_NAME_ENTRY(GET_PIXEL_REPLI), 379 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY_CAP), 380 SDVO_CMD_NAME_ENTRY(SET_COLORIMETRY), 381 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY), 382 SDVO_CMD_NAME_ENTRY(GET_AUDIO_ENCRYPT_PREFER), 383 SDVO_CMD_NAME_ENTRY(SET_AUDIO_STAT), 384 SDVO_CMD_NAME_ENTRY(GET_AUDIO_STAT), 385 SDVO_CMD_NAME_ENTRY(GET_HBUF_INDEX), 386 SDVO_CMD_NAME_ENTRY(SET_HBUF_INDEX), 387 SDVO_CMD_NAME_ENTRY(GET_HBUF_INFO), 388 SDVO_CMD_NAME_ENTRY(GET_HBUF_AV_SPLIT), 389 SDVO_CMD_NAME_ENTRY(SET_HBUF_AV_SPLIT), 390 SDVO_CMD_NAME_ENTRY(GET_HBUF_TXRATE), 391 SDVO_CMD_NAME_ENTRY(SET_HBUF_TXRATE), 392 SDVO_CMD_NAME_ENTRY(SET_HBUF_DATA), 393 SDVO_CMD_NAME_ENTRY(GET_HBUF_DATA), 394 }; 395 396 #undef SDVO_CMD_NAME_ENTRY 397 398 static const char *sdvo_cmd_name(u8 cmd) 399 { 400 int i; 401 402 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 403 if (cmd == sdvo_cmd_names[i].cmd) 404 return sdvo_cmd_names[i].name; 405 } 406 407 return NULL; 408 } 409 410 #define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC") 411 412 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 413 const void *args, int args_len) 414 { 415 const char *cmd_name; 416 int i, pos = 0; 417 #define BUF_LEN 256 418 char buffer[BUF_LEN]; 419 420 #define BUF_PRINT(args...) \ 421 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) 422 423 424 for (i = 0; i < args_len; i++) { 425 BUF_PRINT("%02X ", ((u8 *)args)[i]); 426 } 427 for (; i < 8; i++) { 428 BUF_PRINT(" "); 429 } 430 431 cmd_name = sdvo_cmd_name(cmd); 432 if (cmd_name) 433 BUF_PRINT("(%s)", cmd_name); 434 else 435 BUF_PRINT("(%02X)", cmd); 436 BUG_ON(pos >= BUF_LEN - 1); 437 #undef BUF_PRINT 438 #undef BUF_LEN 439 440 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); 441 } 442 443 static const char * const cmd_status_names[] = { 444 [SDVO_CMD_STATUS_POWER_ON] = "Power on", 445 [SDVO_CMD_STATUS_SUCCESS] = "Success", 446 [SDVO_CMD_STATUS_NOTSUPP] = "Not supported", 447 [SDVO_CMD_STATUS_INVALID_ARG] = "Invalid arg", 448 [SDVO_CMD_STATUS_PENDING] = "Pending", 449 [SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED] = "Target not specified", 450 [SDVO_CMD_STATUS_SCALING_NOT_SUPP] = "Scaling not supported", 451 }; 452 453 static const char *sdvo_cmd_status(u8 status) 454 { 455 if (status < ARRAY_SIZE(cmd_status_names)) 456 return cmd_status_names[status]; 457 else 458 return NULL; 459 } 460 461 static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 462 const void *args, int args_len, 463 bool unlocked) 464 { 465 u8 *buf, status; 466 struct i2c_msg *msgs; 467 int i, ret = true; 468 469 /* Would be simpler to allocate both in one go ? */ 470 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); 471 if (!buf) 472 return false; 473 474 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); 475 if (!msgs) { 476 kfree(buf); 477 return false; 478 } 479 480 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 481 482 for (i = 0; i < args_len; i++) { 483 msgs[i].addr = intel_sdvo->slave_addr; 484 msgs[i].flags = 0; 485 msgs[i].len = 2; 486 msgs[i].buf = buf + 2 *i; 487 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 488 buf[2*i + 1] = ((u8*)args)[i]; 489 } 490 msgs[i].addr = intel_sdvo->slave_addr; 491 msgs[i].flags = 0; 492 msgs[i].len = 2; 493 msgs[i].buf = buf + 2*i; 494 buf[2*i + 0] = SDVO_I2C_OPCODE; 495 buf[2*i + 1] = cmd; 496 497 /* the following two are to read the response */ 498 status = SDVO_I2C_CMD_STATUS; 499 msgs[i+1].addr = intel_sdvo->slave_addr; 500 msgs[i+1].flags = 0; 501 msgs[i+1].len = 1; 502 msgs[i+1].buf = &status; 503 504 msgs[i+2].addr = intel_sdvo->slave_addr; 505 msgs[i+2].flags = I2C_M_RD; 506 msgs[i+2].len = 1; 507 msgs[i+2].buf = &status; 508 509 if (unlocked) 510 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); 511 else 512 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3); 513 if (ret < 0) { 514 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 515 ret = false; 516 goto out; 517 } 518 if (ret != i+3) { 519 /* failure in I2C transfer */ 520 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); 521 ret = false; 522 } 523 524 out: 525 kfree(msgs); 526 kfree(buf); 527 return ret; 528 } 529 530 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 531 const void *args, int args_len) 532 { 533 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true); 534 } 535 536 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 537 void *response, int response_len) 538 { 539 const char *cmd_status; 540 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ 541 u8 status; 542 int i, pos = 0; 543 #define BUF_LEN 256 544 char buffer[BUF_LEN]; 545 546 buffer[0] = '\0'; 547 548 /* 549 * The documentation states that all commands will be 550 * processed within 15µs, and that we need only poll 551 * the status byte a maximum of 3 times in order for the 552 * command to be complete. 553 * 554 * Check 5 times in case the hardware failed to read the docs. 555 * 556 * Also beware that the first response by many devices is to 557 * reply PENDING and stall for time. TVs are notorious for 558 * requiring longer than specified to complete their replies. 559 * Originally (in the DDX long ago), the delay was only ever 15ms 560 * with an additional delay of 30ms applied for TVs added later after 561 * many experiments. To accommodate both sets of delays, we do a 562 * sequence of slow checks if the device is falling behind and fails 563 * to reply within 5*15µs. 564 */ 565 if (!intel_sdvo_read_byte(intel_sdvo, 566 SDVO_I2C_CMD_STATUS, 567 &status)) 568 goto log_fail; 569 570 while ((status == SDVO_CMD_STATUS_PENDING || 571 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { 572 if (retry < 10) 573 msleep(15); 574 else 575 udelay(15); 576 577 if (!intel_sdvo_read_byte(intel_sdvo, 578 SDVO_I2C_CMD_STATUS, 579 &status)) 580 goto log_fail; 581 } 582 583 #define BUF_PRINT(args...) \ 584 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) 585 586 cmd_status = sdvo_cmd_status(status); 587 if (cmd_status) 588 BUF_PRINT("(%s)", cmd_status); 589 else 590 BUF_PRINT("(??? %d)", status); 591 592 if (status != SDVO_CMD_STATUS_SUCCESS) 593 goto log_fail; 594 595 /* Read the command response */ 596 for (i = 0; i < response_len; i++) { 597 if (!intel_sdvo_read_byte(intel_sdvo, 598 SDVO_I2C_RETURN_0 + i, 599 &((u8 *)response)[i])) 600 goto log_fail; 601 BUF_PRINT(" %02X", ((u8 *)response)[i]); 602 } 603 BUG_ON(pos >= BUF_LEN - 1); 604 #undef BUF_PRINT 605 #undef BUF_LEN 606 607 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); 608 return true; 609 610 log_fail: 611 DRM_DEBUG_KMS("%s: R: ... failed %s\n", 612 SDVO_NAME(intel_sdvo), buffer); 613 return false; 614 } 615 616 static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode) 617 { 618 if (adjusted_mode->crtc_clock >= 100000) 619 return 1; 620 else if (adjusted_mode->crtc_clock >= 50000) 621 return 2; 622 else 623 return 4; 624 } 625 626 static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 627 u8 ddc_bus) 628 { 629 /* This must be the immediately preceding write before the i2c xfer */ 630 return __intel_sdvo_write_cmd(intel_sdvo, 631 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 632 &ddc_bus, 1, false); 633 } 634 635 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 636 { 637 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 638 return false; 639 640 return intel_sdvo_read_response(intel_sdvo, NULL, 0); 641 } 642 643 static bool 644 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 645 { 646 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 647 return false; 648 649 return intel_sdvo_read_response(intel_sdvo, value, len); 650 } 651 652 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 653 { 654 struct intel_sdvo_set_target_input_args targets = {0}; 655 return intel_sdvo_set_value(intel_sdvo, 656 SDVO_CMD_SET_TARGET_INPUT, 657 &targets, sizeof(targets)); 658 } 659 660 /* 661 * Return whether each input is trained. 662 * 663 * This function is making an assumption about the layout of the response, 664 * which should be checked against the docs. 665 */ 666 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 667 { 668 struct intel_sdvo_get_trained_inputs_response response; 669 670 BUILD_BUG_ON(sizeof(response) != 1); 671 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 672 &response, sizeof(response))) 673 return false; 674 675 *input_1 = response.input0_trained; 676 *input_2 = response.input1_trained; 677 return true; 678 } 679 680 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 681 u16 outputs) 682 { 683 return intel_sdvo_set_value(intel_sdvo, 684 SDVO_CMD_SET_ACTIVE_OUTPUTS, 685 &outputs, sizeof(outputs)); 686 } 687 688 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, 689 u16 *outputs) 690 { 691 return intel_sdvo_get_value(intel_sdvo, 692 SDVO_CMD_GET_ACTIVE_OUTPUTS, 693 outputs, sizeof(*outputs)); 694 } 695 696 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 697 int mode) 698 { 699 u8 state = SDVO_ENCODER_STATE_ON; 700 701 switch (mode) { 702 case DRM_MODE_DPMS_ON: 703 state = SDVO_ENCODER_STATE_ON; 704 break; 705 case DRM_MODE_DPMS_STANDBY: 706 state = SDVO_ENCODER_STATE_STANDBY; 707 break; 708 case DRM_MODE_DPMS_SUSPEND: 709 state = SDVO_ENCODER_STATE_SUSPEND; 710 break; 711 case DRM_MODE_DPMS_OFF: 712 state = SDVO_ENCODER_STATE_OFF; 713 break; 714 } 715 716 return intel_sdvo_set_value(intel_sdvo, 717 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 718 } 719 720 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 721 int *clock_min, 722 int *clock_max) 723 { 724 struct intel_sdvo_pixel_clock_range clocks; 725 726 BUILD_BUG_ON(sizeof(clocks) != 4); 727 if (!intel_sdvo_get_value(intel_sdvo, 728 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 729 &clocks, sizeof(clocks))) 730 return false; 731 732 /* Convert the values from units of 10 kHz to kHz. */ 733 *clock_min = clocks.min * 10; 734 *clock_max = clocks.max * 10; 735 return true; 736 } 737 738 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 739 u16 outputs) 740 { 741 return intel_sdvo_set_value(intel_sdvo, 742 SDVO_CMD_SET_TARGET_OUTPUT, 743 &outputs, sizeof(outputs)); 744 } 745 746 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 747 struct intel_sdvo_dtd *dtd) 748 { 749 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 750 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 751 } 752 753 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 754 struct intel_sdvo_dtd *dtd) 755 { 756 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 757 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 758 } 759 760 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 761 struct intel_sdvo_dtd *dtd) 762 { 763 return intel_sdvo_set_timing(intel_sdvo, 764 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 765 } 766 767 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 768 struct intel_sdvo_dtd *dtd) 769 { 770 return intel_sdvo_set_timing(intel_sdvo, 771 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 772 } 773 774 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, 775 struct intel_sdvo_dtd *dtd) 776 { 777 return intel_sdvo_get_timing(intel_sdvo, 778 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); 779 } 780 781 static bool 782 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 783 struct intel_sdvo_connector *intel_sdvo_connector, 784 u16 clock, 785 u16 width, 786 u16 height) 787 { 788 struct intel_sdvo_preferred_input_timing_args args; 789 790 memset(&args, 0, sizeof(args)); 791 args.clock = clock; 792 args.width = width; 793 args.height = height; 794 args.interlace = 0; 795 796 if (IS_LVDS(intel_sdvo_connector)) { 797 const struct drm_display_mode *fixed_mode = 798 intel_sdvo_connector->base.panel.fixed_mode; 799 800 if (fixed_mode->hdisplay != width || 801 fixed_mode->vdisplay != height) 802 args.scaled = 1; 803 } 804 805 return intel_sdvo_set_value(intel_sdvo, 806 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 807 &args, sizeof(args)); 808 } 809 810 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 811 struct intel_sdvo_dtd *dtd) 812 { 813 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 814 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 815 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 816 &dtd->part1, sizeof(dtd->part1)) && 817 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 818 &dtd->part2, sizeof(dtd->part2)); 819 } 820 821 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 822 { 823 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 824 } 825 826 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 827 const struct drm_display_mode *mode) 828 { 829 u16 width, height; 830 u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len; 831 u16 h_sync_offset, v_sync_offset; 832 int mode_clock; 833 834 memset(dtd, 0, sizeof(*dtd)); 835 836 width = mode->hdisplay; 837 height = mode->vdisplay; 838 839 /* do some mode translations */ 840 h_blank_len = mode->htotal - mode->hdisplay; 841 h_sync_len = mode->hsync_end - mode->hsync_start; 842 843 v_blank_len = mode->vtotal - mode->vdisplay; 844 v_sync_len = mode->vsync_end - mode->vsync_start; 845 846 h_sync_offset = mode->hsync_start - mode->hdisplay; 847 v_sync_offset = mode->vsync_start - mode->vdisplay; 848 849 mode_clock = mode->clock; 850 mode_clock /= 10; 851 dtd->part1.clock = mode_clock; 852 853 dtd->part1.h_active = width & 0xff; 854 dtd->part1.h_blank = h_blank_len & 0xff; 855 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 856 ((h_blank_len >> 8) & 0xf); 857 dtd->part1.v_active = height & 0xff; 858 dtd->part1.v_blank = v_blank_len & 0xff; 859 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 860 ((v_blank_len >> 8) & 0xf); 861 862 dtd->part2.h_sync_off = h_sync_offset & 0xff; 863 dtd->part2.h_sync_width = h_sync_len & 0xff; 864 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 865 (v_sync_len & 0xf); 866 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 867 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 868 ((v_sync_len & 0x30) >> 4); 869 870 dtd->part2.dtd_flags = 0x18; 871 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 872 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; 873 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 874 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; 875 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 876 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; 877 878 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 879 } 880 881 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, 882 const struct intel_sdvo_dtd *dtd) 883 { 884 struct drm_display_mode mode = {}; 885 886 mode.hdisplay = dtd->part1.h_active; 887 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 888 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; 889 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 890 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; 891 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 892 mode.htotal = mode.hdisplay + dtd->part1.h_blank; 893 mode.htotal += (dtd->part1.h_high & 0xf) << 8; 894 895 mode.vdisplay = dtd->part1.v_active; 896 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 897 mode.vsync_start = mode.vdisplay; 898 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 899 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 900 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; 901 mode.vsync_end = mode.vsync_start + 902 (dtd->part2.v_sync_off_width & 0xf); 903 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 904 mode.vtotal = mode.vdisplay + dtd->part1.v_blank; 905 mode.vtotal += (dtd->part1.v_high & 0xf) << 8; 906 907 mode.clock = dtd->part1.clock * 10; 908 909 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) 910 mode.flags |= DRM_MODE_FLAG_INTERLACE; 911 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 912 mode.flags |= DRM_MODE_FLAG_PHSYNC; 913 else 914 mode.flags |= DRM_MODE_FLAG_NHSYNC; 915 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 916 mode.flags |= DRM_MODE_FLAG_PVSYNC; 917 else 918 mode.flags |= DRM_MODE_FLAG_NVSYNC; 919 920 drm_mode_set_crtcinfo(&mode, 0); 921 922 drm_mode_copy(pmode, &mode); 923 } 924 925 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) 926 { 927 struct intel_sdvo_encode encode; 928 929 BUILD_BUG_ON(sizeof(encode) != 2); 930 return intel_sdvo_get_value(intel_sdvo, 931 SDVO_CMD_GET_SUPP_ENCODE, 932 &encode, sizeof(encode)); 933 } 934 935 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 936 u8 mode) 937 { 938 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 939 } 940 941 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 942 u8 mode) 943 { 944 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 945 } 946 947 static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo, 948 u8 audio_state) 949 { 950 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT, 951 &audio_state, 1); 952 } 953 954 static bool intel_sdvo_get_hbuf_size(struct intel_sdvo *intel_sdvo, 955 u8 *hbuf_size) 956 { 957 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, 958 hbuf_size, 1)) 959 return false; 960 961 /* Buffer size is 0 based, hooray! However zero means zero. */ 962 if (*hbuf_size) 963 (*hbuf_size)++; 964 965 return true; 966 } 967 968 #if 0 969 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) 970 { 971 int i, j; 972 u8 set_buf_index[2]; 973 u8 av_split; 974 u8 buf_size; 975 u8 buf[48]; 976 u8 *pos; 977 978 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 979 980 for (i = 0; i <= av_split; i++) { 981 set_buf_index[0] = i; set_buf_index[1] = 0; 982 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 983 set_buf_index, 2); 984 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 985 intel_sdvo_read_response(encoder, &buf_size, 1); 986 987 pos = buf; 988 for (j = 0; j <= buf_size; j += 8) { 989 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 990 NULL, 0); 991 intel_sdvo_read_response(encoder, pos, 8); 992 pos += 8; 993 } 994 } 995 } 996 #endif 997 998 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, 999 unsigned int if_index, u8 tx_rate, 1000 const u8 *data, unsigned int length) 1001 { 1002 u8 set_buf_index[2] = { if_index, 0 }; 1003 u8 hbuf_size, tmp[8]; 1004 int i; 1005 1006 if (!intel_sdvo_set_value(intel_sdvo, 1007 SDVO_CMD_SET_HBUF_INDEX, 1008 set_buf_index, 2)) 1009 return false; 1010 1011 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) 1012 return false; 1013 1014 DRM_DEBUG_KMS("writing sdvo hbuf: %i, length %u, hbuf_size: %i\n", 1015 if_index, length, hbuf_size); 1016 1017 if (hbuf_size < length) 1018 return false; 1019 1020 for (i = 0; i < hbuf_size; i += 8) { 1021 memset(tmp, 0, 8); 1022 if (i < length) 1023 memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); 1024 1025 if (!intel_sdvo_set_value(intel_sdvo, 1026 SDVO_CMD_SET_HBUF_DATA, 1027 tmp, 8)) 1028 return false; 1029 } 1030 1031 return intel_sdvo_set_value(intel_sdvo, 1032 SDVO_CMD_SET_HBUF_TXRATE, 1033 &tx_rate, 1); 1034 } 1035 1036 static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo, 1037 unsigned int if_index, 1038 u8 *data, unsigned int length) 1039 { 1040 u8 set_buf_index[2] = { if_index, 0 }; 1041 u8 hbuf_size, tx_rate, av_split; 1042 int i; 1043 1044 if (!intel_sdvo_get_value(intel_sdvo, 1045 SDVO_CMD_GET_HBUF_AV_SPLIT, 1046 &av_split, 1)) 1047 return -ENXIO; 1048 1049 if (av_split < if_index) 1050 return 0; 1051 1052 if (!intel_sdvo_set_value(intel_sdvo, 1053 SDVO_CMD_SET_HBUF_INDEX, 1054 set_buf_index, 2)) 1055 return -ENXIO; 1056 1057 if (!intel_sdvo_get_value(intel_sdvo, 1058 SDVO_CMD_GET_HBUF_TXRATE, 1059 &tx_rate, 1)) 1060 return -ENXIO; 1061 1062 if (tx_rate == SDVO_HBUF_TX_DISABLED) 1063 return 0; 1064 1065 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) 1066 return false; 1067 1068 DRM_DEBUG_KMS("reading sdvo hbuf: %i, length %u, hbuf_size: %i\n", 1069 if_index, length, hbuf_size); 1070 1071 hbuf_size = min_t(unsigned int, length, hbuf_size); 1072 1073 for (i = 0; i < hbuf_size; i += 8) { 1074 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA, NULL, 0)) 1075 return -ENXIO; 1076 if (!intel_sdvo_read_response(intel_sdvo, &data[i], 1077 min_t(unsigned int, 8, hbuf_size - i))) 1078 return -ENXIO; 1079 } 1080 1081 return hbuf_size; 1082 } 1083 1084 static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo, 1085 struct intel_crtc_state *crtc_state, 1086 struct drm_connector_state *conn_state) 1087 { 1088 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 1089 const struct drm_display_mode *adjusted_mode = 1090 &crtc_state->base.adjusted_mode; 1091 int ret; 1092 1093 if (!crtc_state->has_hdmi_sink) 1094 return true; 1095 1096 crtc_state->infoframes.enable |= 1097 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 1098 1099 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, 1100 conn_state->connector, 1101 adjusted_mode); 1102 if (ret) 1103 return false; 1104 1105 drm_hdmi_avi_infoframe_quant_range(frame, 1106 conn_state->connector, 1107 adjusted_mode, 1108 crtc_state->limited_color_range ? 1109 HDMI_QUANTIZATION_RANGE_LIMITED : 1110 HDMI_QUANTIZATION_RANGE_FULL); 1111 1112 ret = hdmi_avi_infoframe_check(frame); 1113 if (WARN_ON(ret)) 1114 return false; 1115 1116 return true; 1117 } 1118 1119 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 1120 const struct intel_crtc_state *crtc_state) 1121 { 1122 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1123 const union hdmi_infoframe *frame = &crtc_state->infoframes.avi; 1124 ssize_t len; 1125 1126 if ((crtc_state->infoframes.enable & 1127 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0) 1128 return true; 1129 1130 if (WARN_ON(frame->any.type != HDMI_INFOFRAME_TYPE_AVI)) 1131 return false; 1132 1133 len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data)); 1134 if (WARN_ON(len < 0)) 1135 return false; 1136 1137 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1138 SDVO_HBUF_TX_VSYNC, 1139 sdvo_data, len); 1140 } 1141 1142 static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo, 1143 struct intel_crtc_state *crtc_state) 1144 { 1145 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1146 union hdmi_infoframe *frame = &crtc_state->infoframes.avi; 1147 ssize_t len; 1148 int ret; 1149 1150 if (!crtc_state->has_hdmi_sink) 1151 return; 1152 1153 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1154 sdvo_data, sizeof(sdvo_data)); 1155 if (len < 0) { 1156 DRM_DEBUG_KMS("failed to read AVI infoframe\n"); 1157 return; 1158 } else if (len == 0) { 1159 return; 1160 } 1161 1162 crtc_state->infoframes.enable |= 1163 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 1164 1165 ret = hdmi_infoframe_unpack(frame, sdvo_data, len); 1166 if (ret) { 1167 DRM_DEBUG_KMS("Failed to unpack AVI infoframe\n"); 1168 return; 1169 } 1170 1171 if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI) 1172 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 1173 frame->any.type, HDMI_INFOFRAME_TYPE_AVI); 1174 } 1175 1176 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo, 1177 const struct drm_connector_state *conn_state) 1178 { 1179 struct intel_sdvo_tv_format format; 1180 u32 format_map; 1181 1182 format_map = 1 << conn_state->tv.mode; 1183 memset(&format, 0, sizeof(format)); 1184 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 1185 1186 BUILD_BUG_ON(sizeof(format) != 6); 1187 return intel_sdvo_set_value(intel_sdvo, 1188 SDVO_CMD_SET_TV_FORMAT, 1189 &format, sizeof(format)); 1190 } 1191 1192 static bool 1193 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 1194 const struct drm_display_mode *mode) 1195 { 1196 struct intel_sdvo_dtd output_dtd; 1197 1198 if (!intel_sdvo_set_target_output(intel_sdvo, 1199 intel_sdvo->attached_output)) 1200 return false; 1201 1202 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1203 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1204 return false; 1205 1206 return true; 1207 } 1208 1209 /* 1210 * Asks the sdvo controller for the preferred input mode given the output mode. 1211 * Unfortunately we have to set up the full output mode to do that. 1212 */ 1213 static bool 1214 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, 1215 struct intel_sdvo_connector *intel_sdvo_connector, 1216 const struct drm_display_mode *mode, 1217 struct drm_display_mode *adjusted_mode) 1218 { 1219 struct intel_sdvo_dtd input_dtd; 1220 1221 /* Reset the input timing to the screen. Assume always input 0. */ 1222 if (!intel_sdvo_set_target_input(intel_sdvo)) 1223 return false; 1224 1225 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 1226 intel_sdvo_connector, 1227 mode->clock / 10, 1228 mode->hdisplay, 1229 mode->vdisplay)) 1230 return false; 1231 1232 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1233 &input_dtd)) 1234 return false; 1235 1236 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1237 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; 1238 1239 return true; 1240 } 1241 1242 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) 1243 { 1244 unsigned dotclock = pipe_config->port_clock; 1245 struct dpll *clock = &pipe_config->dpll; 1246 1247 /* 1248 * SDVO TV has fixed PLL values depend on its clock range, 1249 * this mirrors vbios setting. 1250 */ 1251 if (dotclock >= 100000 && dotclock < 140500) { 1252 clock->p1 = 2; 1253 clock->p2 = 10; 1254 clock->n = 3; 1255 clock->m1 = 16; 1256 clock->m2 = 8; 1257 } else if (dotclock >= 140500 && dotclock <= 200000) { 1258 clock->p1 = 1; 1259 clock->p2 = 10; 1260 clock->n = 6; 1261 clock->m1 = 12; 1262 clock->m2 = 8; 1263 } else { 1264 WARN(1, "SDVO TV clock out of range: %i\n", dotclock); 1265 } 1266 1267 pipe_config->clock_set = true; 1268 } 1269 1270 static int intel_sdvo_compute_config(struct intel_encoder *encoder, 1271 struct intel_crtc_state *pipe_config, 1272 struct drm_connector_state *conn_state) 1273 { 1274 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1275 struct intel_sdvo_connector_state *intel_sdvo_state = 1276 to_intel_sdvo_connector_state(conn_state); 1277 struct intel_sdvo_connector *intel_sdvo_connector = 1278 to_intel_sdvo_connector(conn_state->connector); 1279 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1280 struct drm_display_mode *mode = &pipe_config->base.mode; 1281 1282 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); 1283 pipe_config->pipe_bpp = 8*3; 1284 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1285 1286 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) 1287 pipe_config->has_pch_encoder = true; 1288 1289 /* 1290 * We need to construct preferred input timings based on our 1291 * output timings. To do that, we have to set the output 1292 * timings, even though this isn't really the right place in 1293 * the sequence to do it. Oh well. 1294 */ 1295 if (IS_TV(intel_sdvo_connector)) { 1296 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) 1297 return -EINVAL; 1298 1299 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1300 intel_sdvo_connector, 1301 mode, 1302 adjusted_mode); 1303 pipe_config->sdvo_tv_clock = true; 1304 } else if (IS_LVDS(intel_sdvo_connector)) { 1305 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1306 intel_sdvo_connector->base.panel.fixed_mode)) 1307 return -EINVAL; 1308 1309 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1310 intel_sdvo_connector, 1311 mode, 1312 adjusted_mode); 1313 } 1314 1315 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 1316 return -EINVAL; 1317 1318 /* 1319 * Make the CRTC code factor in the SDVO pixel multiplier. The 1320 * SDVO device will factor out the multiplier during mode_set. 1321 */ 1322 pipe_config->pixel_multiplier = 1323 intel_sdvo_get_pixel_multiplier(adjusted_mode); 1324 1325 if (intel_sdvo_state->base.force_audio != HDMI_AUDIO_OFF_DVI) 1326 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor; 1327 1328 if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_ON || 1329 (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO && intel_sdvo->has_hdmi_audio)) 1330 pipe_config->has_audio = true; 1331 1332 if (intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 1333 /* 1334 * See CEA-861-E - 5.1 Default Encoding Parameters 1335 * 1336 * FIXME: This bit is only valid when using TMDS encoding and 8 1337 * bit per color mode. 1338 */ 1339 if (pipe_config->has_hdmi_sink && 1340 drm_match_cea_mode(adjusted_mode) > 1) 1341 pipe_config->limited_color_range = true; 1342 } else { 1343 if (pipe_config->has_hdmi_sink && 1344 intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED) 1345 pipe_config->limited_color_range = true; 1346 } 1347 1348 /* Clock computation needs to happen after pixel multiplier. */ 1349 if (IS_TV(intel_sdvo_connector)) 1350 i9xx_adjust_sdvo_tv_clock(pipe_config); 1351 1352 /* Set user selected PAR to incoming mode's member */ 1353 if (intel_sdvo_connector->is_hdmi) 1354 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio; 1355 1356 if (!intel_sdvo_compute_avi_infoframe(intel_sdvo, 1357 pipe_config, conn_state)) { 1358 DRM_DEBUG_KMS("bad AVI infoframe\n"); 1359 return -EINVAL; 1360 } 1361 1362 return 0; 1363 } 1364 1365 #define UPDATE_PROPERTY(input, NAME) \ 1366 do { \ 1367 val = input; \ 1368 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \ 1369 } while (0) 1370 1371 static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo, 1372 const struct intel_sdvo_connector_state *sdvo_state) 1373 { 1374 const struct drm_connector_state *conn_state = &sdvo_state->base.base; 1375 struct intel_sdvo_connector *intel_sdvo_conn = 1376 to_intel_sdvo_connector(conn_state->connector); 1377 u16 val; 1378 1379 if (intel_sdvo_conn->left) 1380 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H); 1381 1382 if (intel_sdvo_conn->top) 1383 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V); 1384 1385 if (intel_sdvo_conn->hpos) 1386 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS); 1387 1388 if (intel_sdvo_conn->vpos) 1389 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS); 1390 1391 if (intel_sdvo_conn->saturation) 1392 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION); 1393 1394 if (intel_sdvo_conn->contrast) 1395 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST); 1396 1397 if (intel_sdvo_conn->hue) 1398 UPDATE_PROPERTY(conn_state->tv.hue, HUE); 1399 1400 if (intel_sdvo_conn->brightness) 1401 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS); 1402 1403 if (intel_sdvo_conn->sharpness) 1404 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS); 1405 1406 if (intel_sdvo_conn->flicker_filter) 1407 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER); 1408 1409 if (intel_sdvo_conn->flicker_filter_2d) 1410 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D); 1411 1412 if (intel_sdvo_conn->flicker_filter_adaptive) 1413 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 1414 1415 if (intel_sdvo_conn->tv_chroma_filter) 1416 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER); 1417 1418 if (intel_sdvo_conn->tv_luma_filter) 1419 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER); 1420 1421 if (intel_sdvo_conn->dot_crawl) 1422 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL); 1423 1424 #undef UPDATE_PROPERTY 1425 } 1426 1427 static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, 1428 const struct intel_crtc_state *crtc_state, 1429 const struct drm_connector_state *conn_state) 1430 { 1431 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 1432 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1433 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; 1434 const struct intel_sdvo_connector_state *sdvo_state = 1435 to_intel_sdvo_connector_state(conn_state); 1436 const struct intel_sdvo_connector *intel_sdvo_connector = 1437 to_intel_sdvo_connector(conn_state->connector); 1438 const struct drm_display_mode *mode = &crtc_state->base.mode; 1439 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); 1440 u32 sdvox; 1441 struct intel_sdvo_in_out_map in_out; 1442 struct intel_sdvo_dtd input_dtd, output_dtd; 1443 int rate; 1444 1445 intel_sdvo_update_props(intel_sdvo, sdvo_state); 1446 1447 /* 1448 * First, set the input mapping for the first input to our controlled 1449 * output. This is only correct if we're a single-input device, in 1450 * which case the first input is the output from the appropriate SDVO 1451 * channel on the motherboard. In a two-input device, the first input 1452 * will be SDVOB and the second SDVOC. 1453 */ 1454 in_out.in0 = intel_sdvo->attached_output; 1455 in_out.in1 = 0; 1456 1457 intel_sdvo_set_value(intel_sdvo, 1458 SDVO_CMD_SET_IN_OUT_MAP, 1459 &in_out, sizeof(in_out)); 1460 1461 /* Set the output timings to the screen */ 1462 if (!intel_sdvo_set_target_output(intel_sdvo, 1463 intel_sdvo->attached_output)) 1464 return; 1465 1466 /* lvds has a special fixed output timing. */ 1467 if (IS_LVDS(intel_sdvo_connector)) 1468 intel_sdvo_get_dtd_from_mode(&output_dtd, 1469 intel_sdvo_connector->base.panel.fixed_mode); 1470 else 1471 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1472 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1473 DRM_INFO("Setting output timings on %s failed\n", 1474 SDVO_NAME(intel_sdvo)); 1475 1476 /* Set the input timing to the screen. Assume always input 0. */ 1477 if (!intel_sdvo_set_target_input(intel_sdvo)) 1478 return; 1479 1480 if (crtc_state->has_hdmi_sink) { 1481 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 1482 intel_sdvo_set_colorimetry(intel_sdvo, 1483 SDVO_COLORIMETRY_RGB256); 1484 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state); 1485 } else 1486 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); 1487 1488 if (IS_TV(intel_sdvo_connector) && 1489 !intel_sdvo_set_tv_format(intel_sdvo, conn_state)) 1490 return; 1491 1492 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1493 1494 if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector)) 1495 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; 1496 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1497 DRM_INFO("Setting input timings on %s failed\n", 1498 SDVO_NAME(intel_sdvo)); 1499 1500 switch (crtc_state->pixel_multiplier) { 1501 default: 1502 WARN(1, "unknown pixel multiplier specified\n"); 1503 /* fall through */ 1504 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1505 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1506 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1507 } 1508 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1509 return; 1510 1511 /* Set the SDVO control regs. */ 1512 if (INTEL_GEN(dev_priv) >= 4) { 1513 /* The real mode polarity is set by the SDVO commands, using 1514 * struct intel_sdvo_dtd. */ 1515 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; 1516 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) 1517 sdvox |= HDMI_COLOR_RANGE_16_235; 1518 if (INTEL_GEN(dev_priv) < 5) 1519 sdvox |= SDVO_BORDER_ENABLE; 1520 } else { 1521 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1522 if (intel_sdvo->port == PORT_B) 1523 sdvox &= SDVOB_PRESERVE_MASK; 1524 else 1525 sdvox &= SDVOC_PRESERVE_MASK; 1526 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1527 } 1528 1529 if (HAS_PCH_CPT(dev_priv)) 1530 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1531 else 1532 sdvox |= SDVO_PIPE_SEL(crtc->pipe); 1533 1534 if (INTEL_GEN(dev_priv) >= 4) { 1535 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1536 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 1537 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 1538 /* done in crtc_mode_set as it lives inside the dpll register */ 1539 } else { 1540 sdvox |= (crtc_state->pixel_multiplier - 1) 1541 << SDVO_PORT_MULTIPLY_SHIFT; 1542 } 1543 1544 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && 1545 INTEL_GEN(dev_priv) < 5) 1546 sdvox |= SDVO_STALL_SELECT; 1547 intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1548 } 1549 1550 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) 1551 { 1552 struct intel_sdvo_connector *intel_sdvo_connector = 1553 to_intel_sdvo_connector(&connector->base); 1554 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); 1555 u16 active_outputs = 0; 1556 1557 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1558 1559 return active_outputs & intel_sdvo_connector->output_flag; 1560 } 1561 1562 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, 1563 i915_reg_t sdvo_reg, enum pipe *pipe) 1564 { 1565 u32 val; 1566 1567 val = I915_READ(sdvo_reg); 1568 1569 /* asserts want to know the pipe even if the port is disabled */ 1570 if (HAS_PCH_CPT(dev_priv)) 1571 *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT; 1572 else if (IS_CHERRYVIEW(dev_priv)) 1573 *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV; 1574 else 1575 *pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT; 1576 1577 return val & SDVO_ENABLE; 1578 } 1579 1580 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, 1581 enum pipe *pipe) 1582 { 1583 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1584 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1585 u16 active_outputs = 0; 1586 bool ret; 1587 1588 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1589 1590 ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe); 1591 1592 return ret || active_outputs; 1593 } 1594 1595 static void intel_sdvo_get_config(struct intel_encoder *encoder, 1596 struct intel_crtc_state *pipe_config) 1597 { 1598 struct drm_device *dev = encoder->base.dev; 1599 struct drm_i915_private *dev_priv = to_i915(dev); 1600 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1601 struct intel_sdvo_dtd dtd; 1602 int encoder_pixel_multiplier = 0; 1603 int dotclock; 1604 u32 flags = 0, sdvox; 1605 u8 val; 1606 bool ret; 1607 1608 pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO); 1609 1610 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1611 1612 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1613 if (!ret) { 1614 /* 1615 * Some sdvo encoders are not spec compliant and don't 1616 * implement the mandatory get_timings function. 1617 */ 1618 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n"); 1619 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; 1620 } else { 1621 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1622 flags |= DRM_MODE_FLAG_PHSYNC; 1623 else 1624 flags |= DRM_MODE_FLAG_NHSYNC; 1625 1626 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1627 flags |= DRM_MODE_FLAG_PVSYNC; 1628 else 1629 flags |= DRM_MODE_FLAG_NVSYNC; 1630 } 1631 1632 pipe_config->base.adjusted_mode.flags |= flags; 1633 1634 /* 1635 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in 1636 * the sdvo port register, on all other platforms it is part of the dpll 1637 * state. Since the general pipe state readout happens before the 1638 * encoder->get_config we so already have a valid pixel multplier on all 1639 * other platfroms. 1640 */ 1641 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 1642 pipe_config->pixel_multiplier = 1643 ((sdvox & SDVO_PORT_MULTIPLY_MASK) 1644 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1645 } 1646 1647 dotclock = pipe_config->port_clock; 1648 1649 if (pipe_config->pixel_multiplier) 1650 dotclock /= pipe_config->pixel_multiplier; 1651 1652 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 1653 1654 /* Cross check the port pixel multiplier with the sdvo encoder state. */ 1655 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, 1656 &val, 1)) { 1657 switch (val) { 1658 case SDVO_CLOCK_RATE_MULT_1X: 1659 encoder_pixel_multiplier = 1; 1660 break; 1661 case SDVO_CLOCK_RATE_MULT_2X: 1662 encoder_pixel_multiplier = 2; 1663 break; 1664 case SDVO_CLOCK_RATE_MULT_4X: 1665 encoder_pixel_multiplier = 4; 1666 break; 1667 } 1668 } 1669 1670 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier, 1671 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", 1672 pipe_config->pixel_multiplier, encoder_pixel_multiplier); 1673 1674 if (sdvox & HDMI_COLOR_RANGE_16_235) 1675 pipe_config->limited_color_range = true; 1676 1677 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, 1678 &val, 1)) { 1679 u8 mask = SDVO_AUDIO_ELD_VALID | SDVO_AUDIO_PRESENCE_DETECT; 1680 1681 if ((val & mask) == mask) 1682 pipe_config->has_audio = true; 1683 } 1684 1685 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, 1686 &val, 1)) { 1687 if (val == SDVO_ENCODE_HDMI) 1688 pipe_config->has_hdmi_sink = true; 1689 } 1690 1691 intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config); 1692 } 1693 1694 static void intel_sdvo_disable_audio(struct intel_sdvo *intel_sdvo) 1695 { 1696 intel_sdvo_set_audio_state(intel_sdvo, 0); 1697 } 1698 1699 static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo, 1700 const struct intel_crtc_state *crtc_state, 1701 const struct drm_connector_state *conn_state) 1702 { 1703 const struct drm_display_mode *adjusted_mode = 1704 &crtc_state->base.adjusted_mode; 1705 struct drm_connector *connector = conn_state->connector; 1706 u8 *eld = connector->eld; 1707 1708 eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 1709 1710 intel_sdvo_set_audio_state(intel_sdvo, 0); 1711 1712 intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD, 1713 SDVO_HBUF_TX_DISABLED, 1714 eld, drm_eld_size(eld)); 1715 1716 intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID | 1717 SDVO_AUDIO_PRESENCE_DETECT); 1718 } 1719 1720 static void intel_disable_sdvo(struct intel_encoder *encoder, 1721 const struct intel_crtc_state *old_crtc_state, 1722 const struct drm_connector_state *conn_state) 1723 { 1724 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1725 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1726 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); 1727 u32 temp; 1728 1729 if (old_crtc_state->has_audio) 1730 intel_sdvo_disable_audio(intel_sdvo); 1731 1732 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1733 if (0) 1734 intel_sdvo_set_encoder_power_state(intel_sdvo, 1735 DRM_MODE_DPMS_OFF); 1736 1737 temp = I915_READ(intel_sdvo->sdvo_reg); 1738 1739 temp &= ~SDVO_ENABLE; 1740 intel_sdvo_write_sdvox(intel_sdvo, temp); 1741 1742 /* 1743 * HW workaround for IBX, we need to move the port 1744 * to transcoder A after disabling it to allow the 1745 * matching DP port to be enabled on transcoder A. 1746 */ 1747 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 1748 /* 1749 * We get CPU/PCH FIFO underruns on the other pipe when 1750 * doing the workaround. Sweep them under the rug. 1751 */ 1752 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1753 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1754 1755 temp &= ~SDVO_PIPE_SEL_MASK; 1756 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 1757 intel_sdvo_write_sdvox(intel_sdvo, temp); 1758 1759 temp &= ~SDVO_ENABLE; 1760 intel_sdvo_write_sdvox(intel_sdvo, temp); 1761 1762 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 1763 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1764 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1765 } 1766 } 1767 1768 static void pch_disable_sdvo(struct intel_encoder *encoder, 1769 const struct intel_crtc_state *old_crtc_state, 1770 const struct drm_connector_state *old_conn_state) 1771 { 1772 } 1773 1774 static void pch_post_disable_sdvo(struct intel_encoder *encoder, 1775 const struct intel_crtc_state *old_crtc_state, 1776 const struct drm_connector_state *old_conn_state) 1777 { 1778 intel_disable_sdvo(encoder, old_crtc_state, old_conn_state); 1779 } 1780 1781 static void intel_enable_sdvo(struct intel_encoder *encoder, 1782 const struct intel_crtc_state *pipe_config, 1783 const struct drm_connector_state *conn_state) 1784 { 1785 struct drm_device *dev = encoder->base.dev; 1786 struct drm_i915_private *dev_priv = to_i915(dev); 1787 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1788 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 1789 u32 temp; 1790 bool input1, input2; 1791 int i; 1792 bool success; 1793 1794 temp = I915_READ(intel_sdvo->sdvo_reg); 1795 temp |= SDVO_ENABLE; 1796 intel_sdvo_write_sdvox(intel_sdvo, temp); 1797 1798 for (i = 0; i < 2; i++) 1799 intel_wait_for_vblank(dev_priv, intel_crtc->pipe); 1800 1801 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1802 /* 1803 * Warn if the device reported failure to sync. 1804 * 1805 * A lot of SDVO devices fail to notify of sync, but it's 1806 * a given it the status is a success, we succeeded. 1807 */ 1808 if (success && !input1) { 1809 DRM_DEBUG_KMS("First %s output reported failure to " 1810 "sync\n", SDVO_NAME(intel_sdvo)); 1811 } 1812 1813 if (0) 1814 intel_sdvo_set_encoder_power_state(intel_sdvo, 1815 DRM_MODE_DPMS_ON); 1816 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1817 1818 if (pipe_config->has_audio) 1819 intel_sdvo_enable_audio(intel_sdvo, pipe_config, conn_state); 1820 } 1821 1822 static enum drm_mode_status 1823 intel_sdvo_mode_valid(struct drm_connector *connector, 1824 struct drm_display_mode *mode) 1825 { 1826 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1827 struct intel_sdvo_connector *intel_sdvo_connector = 1828 to_intel_sdvo_connector(connector); 1829 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 1830 1831 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1832 return MODE_NO_DBLESCAN; 1833 1834 if (intel_sdvo->pixel_clock_min > mode->clock) 1835 return MODE_CLOCK_LOW; 1836 1837 if (intel_sdvo->pixel_clock_max < mode->clock) 1838 return MODE_CLOCK_HIGH; 1839 1840 if (mode->clock > max_dotclk) 1841 return MODE_CLOCK_HIGH; 1842 1843 if (IS_LVDS(intel_sdvo_connector)) { 1844 const struct drm_display_mode *fixed_mode = 1845 intel_sdvo_connector->base.panel.fixed_mode; 1846 1847 if (mode->hdisplay > fixed_mode->hdisplay) 1848 return MODE_PANEL; 1849 1850 if (mode->vdisplay > fixed_mode->vdisplay) 1851 return MODE_PANEL; 1852 } 1853 1854 return MODE_OK; 1855 } 1856 1857 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1858 { 1859 BUILD_BUG_ON(sizeof(*caps) != 8); 1860 if (!intel_sdvo_get_value(intel_sdvo, 1861 SDVO_CMD_GET_DEVICE_CAPS, 1862 caps, sizeof(*caps))) 1863 return false; 1864 1865 DRM_DEBUG_KMS("SDVO capabilities:\n" 1866 " vendor_id: %d\n" 1867 " device_id: %d\n" 1868 " device_rev_id: %d\n" 1869 " sdvo_version_major: %d\n" 1870 " sdvo_version_minor: %d\n" 1871 " sdvo_inputs_mask: %d\n" 1872 " smooth_scaling: %d\n" 1873 " sharp_scaling: %d\n" 1874 " up_scaling: %d\n" 1875 " down_scaling: %d\n" 1876 " stall_support: %d\n" 1877 " output_flags: %d\n", 1878 caps->vendor_id, 1879 caps->device_id, 1880 caps->device_rev_id, 1881 caps->sdvo_version_major, 1882 caps->sdvo_version_minor, 1883 caps->sdvo_inputs_mask, 1884 caps->smooth_scaling, 1885 caps->sharp_scaling, 1886 caps->up_scaling, 1887 caps->down_scaling, 1888 caps->stall_support, 1889 caps->output_flags); 1890 1891 return true; 1892 } 1893 1894 static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) 1895 { 1896 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 1897 u16 hotplug; 1898 1899 if (!I915_HAS_HOTPLUG(dev_priv)) 1900 return 0; 1901 1902 /* 1903 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise 1904 * on the line. 1905 */ 1906 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) 1907 return 0; 1908 1909 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, 1910 &hotplug, sizeof(hotplug))) 1911 return 0; 1912 1913 return hotplug; 1914 } 1915 1916 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) 1917 { 1918 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1919 1920 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, 1921 &intel_sdvo->hotplug_active, 2); 1922 } 1923 1924 static enum intel_hotplug_state 1925 intel_sdvo_hotplug(struct intel_encoder *encoder, 1926 struct intel_connector *connector, 1927 bool irq_received) 1928 { 1929 intel_sdvo_enable_hotplug(encoder); 1930 1931 return intel_encoder_hotplug(encoder, connector, irq_received); 1932 } 1933 1934 static bool 1935 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) 1936 { 1937 /* Is there more than one type of output? */ 1938 return hweight16(intel_sdvo->caps.output_flags) > 1; 1939 } 1940 1941 static struct edid * 1942 intel_sdvo_get_edid(struct drm_connector *connector) 1943 { 1944 struct intel_sdvo *sdvo = intel_attached_sdvo(connector); 1945 return drm_get_edid(connector, &sdvo->ddc); 1946 } 1947 1948 /* Mac mini hack -- use the same DDC as the analog connector */ 1949 static struct edid * 1950 intel_sdvo_get_analog_edid(struct drm_connector *connector) 1951 { 1952 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1953 1954 return drm_get_edid(connector, 1955 intel_gmbus_get_adapter(dev_priv, 1956 dev_priv->vbt.crt_ddc_pin)); 1957 } 1958 1959 static enum drm_connector_status 1960 intel_sdvo_tmds_sink_detect(struct drm_connector *connector) 1961 { 1962 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1963 struct intel_sdvo_connector *intel_sdvo_connector = 1964 to_intel_sdvo_connector(connector); 1965 enum drm_connector_status status; 1966 struct edid *edid; 1967 1968 edid = intel_sdvo_get_edid(connector); 1969 1970 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { 1971 u8 ddc, saved_ddc = intel_sdvo->ddc_bus; 1972 1973 /* 1974 * Don't use the 1 as the argument of DDC bus switch to get 1975 * the EDID. It is used for SDVO SPD ROM. 1976 */ 1977 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { 1978 intel_sdvo->ddc_bus = ddc; 1979 edid = intel_sdvo_get_edid(connector); 1980 if (edid) 1981 break; 1982 } 1983 /* 1984 * If we found the EDID on the other bus, 1985 * assume that is the correct DDC bus. 1986 */ 1987 if (edid == NULL) 1988 intel_sdvo->ddc_bus = saved_ddc; 1989 } 1990 1991 /* 1992 * When there is no edid and no monitor is connected with VGA 1993 * port, try to use the CRT ddc to read the EDID for DVI-connector. 1994 */ 1995 if (edid == NULL) 1996 edid = intel_sdvo_get_analog_edid(connector); 1997 1998 status = connector_status_unknown; 1999 if (edid != NULL) { 2000 /* DDC bus is shared, match EDID to connector type */ 2001 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 2002 status = connector_status_connected; 2003 if (intel_sdvo_connector->is_hdmi) { 2004 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); 2005 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); 2006 } 2007 } else 2008 status = connector_status_disconnected; 2009 kfree(edid); 2010 } 2011 2012 return status; 2013 } 2014 2015 static bool 2016 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, 2017 struct edid *edid) 2018 { 2019 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 2020 bool connector_is_digital = !!IS_DIGITAL(sdvo); 2021 2022 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", 2023 connector_is_digital, monitor_is_digital); 2024 return connector_is_digital == monitor_is_digital; 2025 } 2026 2027 static enum drm_connector_status 2028 intel_sdvo_detect(struct drm_connector *connector, bool force) 2029 { 2030 u16 response; 2031 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 2032 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2033 enum drm_connector_status ret; 2034 2035 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2036 connector->base.id, connector->name); 2037 2038 if (!intel_sdvo_get_value(intel_sdvo, 2039 SDVO_CMD_GET_ATTACHED_DISPLAYS, 2040 &response, 2)) 2041 return connector_status_unknown; 2042 2043 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", 2044 response & 0xff, response >> 8, 2045 intel_sdvo_connector->output_flag); 2046 2047 if (response == 0) 2048 return connector_status_disconnected; 2049 2050 intel_sdvo->attached_output = response; 2051 2052 intel_sdvo->has_hdmi_monitor = false; 2053 intel_sdvo->has_hdmi_audio = false; 2054 2055 if ((intel_sdvo_connector->output_flag & response) == 0) 2056 ret = connector_status_disconnected; 2057 else if (IS_TMDS(intel_sdvo_connector)) 2058 ret = intel_sdvo_tmds_sink_detect(connector); 2059 else { 2060 struct edid *edid; 2061 2062 /* if we have an edid check it matches the connection */ 2063 edid = intel_sdvo_get_edid(connector); 2064 if (edid == NULL) 2065 edid = intel_sdvo_get_analog_edid(connector); 2066 if (edid != NULL) { 2067 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, 2068 edid)) 2069 ret = connector_status_connected; 2070 else 2071 ret = connector_status_disconnected; 2072 2073 kfree(edid); 2074 } else 2075 ret = connector_status_connected; 2076 } 2077 2078 return ret; 2079 } 2080 2081 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) 2082 { 2083 struct edid *edid; 2084 2085 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2086 connector->base.id, connector->name); 2087 2088 /* set the bus switch and get the modes */ 2089 edid = intel_sdvo_get_edid(connector); 2090 2091 /* 2092 * Mac mini hack. On this device, the DVI-I connector shares one DDC 2093 * link between analog and digital outputs. So, if the regular SDVO 2094 * DDC fails, check to see if the analog output is disconnected, in 2095 * which case we'll look there for the digital DDC data. 2096 */ 2097 if (edid == NULL) 2098 edid = intel_sdvo_get_analog_edid(connector); 2099 2100 if (edid != NULL) { 2101 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), 2102 edid)) { 2103 drm_connector_update_edid_property(connector, edid); 2104 drm_add_edid_modes(connector, edid); 2105 } 2106 2107 kfree(edid); 2108 } 2109 } 2110 2111 /* 2112 * Set of SDVO TV modes. 2113 * Note! This is in reply order (see loop in get_tv_modes). 2114 * XXX: all 60Hz refresh? 2115 */ 2116 static const struct drm_display_mode sdvo_tv_modes[] = { 2117 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 2118 416, 0, 200, 201, 232, 233, 0, 2119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2120 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 2121 416, 0, 240, 241, 272, 273, 0, 2122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2123 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 2124 496, 0, 300, 301, 332, 333, 0, 2125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2126 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 2127 736, 0, 350, 351, 382, 383, 0, 2128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2129 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 2130 736, 0, 400, 401, 432, 433, 0, 2131 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2132 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 2133 736, 0, 480, 481, 512, 513, 0, 2134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2135 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 2136 800, 0, 480, 481, 512, 513, 0, 2137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2138 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 2139 800, 0, 576, 577, 608, 609, 0, 2140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2141 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 2142 816, 0, 350, 351, 382, 383, 0, 2143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2144 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 2145 816, 0, 400, 401, 432, 433, 0, 2146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2147 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 2148 816, 0, 480, 481, 512, 513, 0, 2149 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2150 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 2151 816, 0, 540, 541, 572, 573, 0, 2152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2153 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 2154 816, 0, 576, 577, 608, 609, 0, 2155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2156 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 2157 864, 0, 576, 577, 608, 609, 0, 2158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2159 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 2160 896, 0, 600, 601, 632, 633, 0, 2161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2162 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 2163 928, 0, 624, 625, 656, 657, 0, 2164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2165 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 2166 1016, 0, 766, 767, 798, 799, 0, 2167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2168 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 2169 1120, 0, 768, 769, 800, 801, 0, 2170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2171 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 2172 1376, 0, 1024, 1025, 1056, 1057, 0, 2173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2174 }; 2175 2176 static void intel_sdvo_get_tv_modes(struct drm_connector *connector) 2177 { 2178 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 2179 const struct drm_connector_state *conn_state = connector->state; 2180 struct intel_sdvo_sdtv_resolution_request tv_res; 2181 u32 reply = 0, format_map = 0; 2182 int i; 2183 2184 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2185 connector->base.id, connector->name); 2186 2187 /* 2188 * Read the list of supported input resolutions for the selected TV 2189 * format. 2190 */ 2191 format_map = 1 << conn_state->tv.mode; 2192 memcpy(&tv_res, &format_map, 2193 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 2194 2195 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) 2196 return; 2197 2198 BUILD_BUG_ON(sizeof(tv_res) != 3); 2199 if (!intel_sdvo_write_cmd(intel_sdvo, 2200 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 2201 &tv_res, sizeof(tv_res))) 2202 return; 2203 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 2204 return; 2205 2206 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) 2207 if (reply & (1 << i)) { 2208 struct drm_display_mode *nmode; 2209 nmode = drm_mode_duplicate(connector->dev, 2210 &sdvo_tv_modes[i]); 2211 if (nmode) 2212 drm_mode_probed_add(connector, nmode); 2213 } 2214 } 2215 2216 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) 2217 { 2218 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 2219 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2220 struct drm_display_mode *newmode; 2221 2222 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2223 connector->base.id, connector->name); 2224 2225 /* 2226 * Fetch modes from VBT. For SDVO prefer the VBT mode since some 2227 * SDVO->LVDS transcoders can't cope with the EDID mode. 2228 */ 2229 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) { 2230 newmode = drm_mode_duplicate(connector->dev, 2231 dev_priv->vbt.sdvo_lvds_vbt_mode); 2232 if (newmode != NULL) { 2233 /* Guarantee the mode is preferred */ 2234 newmode->type = (DRM_MODE_TYPE_PREFERRED | 2235 DRM_MODE_TYPE_DRIVER); 2236 drm_mode_probed_add(connector, newmode); 2237 } 2238 } 2239 2240 /* 2241 * Attempt to get the mode list from DDC. 2242 * Assume that the preferred modes are 2243 * arranged in priority order. 2244 */ 2245 intel_ddc_get_modes(connector, &intel_sdvo->ddc); 2246 } 2247 2248 static int intel_sdvo_get_modes(struct drm_connector *connector) 2249 { 2250 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2251 2252 if (IS_TV(intel_sdvo_connector)) 2253 intel_sdvo_get_tv_modes(connector); 2254 else if (IS_LVDS(intel_sdvo_connector)) 2255 intel_sdvo_get_lvds_modes(connector); 2256 else 2257 intel_sdvo_get_ddc_modes(connector); 2258 2259 return !list_empty(&connector->probed_modes); 2260 } 2261 2262 static int 2263 intel_sdvo_connector_atomic_get_property(struct drm_connector *connector, 2264 const struct drm_connector_state *state, 2265 struct drm_property *property, 2266 u64 *val) 2267 { 2268 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2269 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state); 2270 2271 if (property == intel_sdvo_connector->tv_format) { 2272 int i; 2273 2274 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2275 if (state->tv.mode == intel_sdvo_connector->tv_format_supported[i]) { 2276 *val = i; 2277 2278 return 0; 2279 } 2280 2281 WARN_ON(1); 2282 *val = 0; 2283 } else if (property == intel_sdvo_connector->top || 2284 property == intel_sdvo_connector->bottom) 2285 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v; 2286 else if (property == intel_sdvo_connector->left || 2287 property == intel_sdvo_connector->right) 2288 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h; 2289 else if (property == intel_sdvo_connector->hpos) 2290 *val = sdvo_state->tv.hpos; 2291 else if (property == intel_sdvo_connector->vpos) 2292 *val = sdvo_state->tv.vpos; 2293 else if (property == intel_sdvo_connector->saturation) 2294 *val = state->tv.saturation; 2295 else if (property == intel_sdvo_connector->contrast) 2296 *val = state->tv.contrast; 2297 else if (property == intel_sdvo_connector->hue) 2298 *val = state->tv.hue; 2299 else if (property == intel_sdvo_connector->brightness) 2300 *val = state->tv.brightness; 2301 else if (property == intel_sdvo_connector->sharpness) 2302 *val = sdvo_state->tv.sharpness; 2303 else if (property == intel_sdvo_connector->flicker_filter) 2304 *val = sdvo_state->tv.flicker_filter; 2305 else if (property == intel_sdvo_connector->flicker_filter_2d) 2306 *val = sdvo_state->tv.flicker_filter_2d; 2307 else if (property == intel_sdvo_connector->flicker_filter_adaptive) 2308 *val = sdvo_state->tv.flicker_filter_adaptive; 2309 else if (property == intel_sdvo_connector->tv_chroma_filter) 2310 *val = sdvo_state->tv.chroma_filter; 2311 else if (property == intel_sdvo_connector->tv_luma_filter) 2312 *val = sdvo_state->tv.luma_filter; 2313 else if (property == intel_sdvo_connector->dot_crawl) 2314 *val = sdvo_state->tv.dot_crawl; 2315 else 2316 return intel_digital_connector_atomic_get_property(connector, state, property, val); 2317 2318 return 0; 2319 } 2320 2321 static int 2322 intel_sdvo_connector_atomic_set_property(struct drm_connector *connector, 2323 struct drm_connector_state *state, 2324 struct drm_property *property, 2325 u64 val) 2326 { 2327 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2328 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state); 2329 2330 if (property == intel_sdvo_connector->tv_format) { 2331 state->tv.mode = intel_sdvo_connector->tv_format_supported[val]; 2332 2333 if (state->crtc) { 2334 struct drm_crtc_state *crtc_state = 2335 drm_atomic_get_new_crtc_state(state->state, state->crtc); 2336 2337 crtc_state->connectors_changed = true; 2338 } 2339 } else if (property == intel_sdvo_connector->top || 2340 property == intel_sdvo_connector->bottom) 2341 /* Cannot set these independent from each other */ 2342 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val; 2343 else if (property == intel_sdvo_connector->left || 2344 property == intel_sdvo_connector->right) 2345 /* Cannot set these independent from each other */ 2346 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val; 2347 else if (property == intel_sdvo_connector->hpos) 2348 sdvo_state->tv.hpos = val; 2349 else if (property == intel_sdvo_connector->vpos) 2350 sdvo_state->tv.vpos = val; 2351 else if (property == intel_sdvo_connector->saturation) 2352 state->tv.saturation = val; 2353 else if (property == intel_sdvo_connector->contrast) 2354 state->tv.contrast = val; 2355 else if (property == intel_sdvo_connector->hue) 2356 state->tv.hue = val; 2357 else if (property == intel_sdvo_connector->brightness) 2358 state->tv.brightness = val; 2359 else if (property == intel_sdvo_connector->sharpness) 2360 sdvo_state->tv.sharpness = val; 2361 else if (property == intel_sdvo_connector->flicker_filter) 2362 sdvo_state->tv.flicker_filter = val; 2363 else if (property == intel_sdvo_connector->flicker_filter_2d) 2364 sdvo_state->tv.flicker_filter_2d = val; 2365 else if (property == intel_sdvo_connector->flicker_filter_adaptive) 2366 sdvo_state->tv.flicker_filter_adaptive = val; 2367 else if (property == intel_sdvo_connector->tv_chroma_filter) 2368 sdvo_state->tv.chroma_filter = val; 2369 else if (property == intel_sdvo_connector->tv_luma_filter) 2370 sdvo_state->tv.luma_filter = val; 2371 else if (property == intel_sdvo_connector->dot_crawl) 2372 sdvo_state->tv.dot_crawl = val; 2373 else 2374 return intel_digital_connector_atomic_set_property(connector, state, property, val); 2375 2376 return 0; 2377 } 2378 2379 static int 2380 intel_sdvo_connector_register(struct drm_connector *connector) 2381 { 2382 struct intel_sdvo *sdvo = intel_attached_sdvo(connector); 2383 int ret; 2384 2385 ret = intel_connector_register(connector); 2386 if (ret) 2387 return ret; 2388 2389 return sysfs_create_link(&connector->kdev->kobj, 2390 &sdvo->ddc.dev.kobj, 2391 sdvo->ddc.dev.kobj.name); 2392 } 2393 2394 static void 2395 intel_sdvo_connector_unregister(struct drm_connector *connector) 2396 { 2397 struct intel_sdvo *sdvo = intel_attached_sdvo(connector); 2398 2399 sysfs_remove_link(&connector->kdev->kobj, 2400 sdvo->ddc.dev.kobj.name); 2401 intel_connector_unregister(connector); 2402 } 2403 2404 static struct drm_connector_state * 2405 intel_sdvo_connector_duplicate_state(struct drm_connector *connector) 2406 { 2407 struct intel_sdvo_connector_state *state; 2408 2409 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL); 2410 if (!state) 2411 return NULL; 2412 2413 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base); 2414 return &state->base.base; 2415 } 2416 2417 static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 2418 .detect = intel_sdvo_detect, 2419 .fill_modes = drm_helper_probe_single_connector_modes, 2420 .atomic_get_property = intel_sdvo_connector_atomic_get_property, 2421 .atomic_set_property = intel_sdvo_connector_atomic_set_property, 2422 .late_register = intel_sdvo_connector_register, 2423 .early_unregister = intel_sdvo_connector_unregister, 2424 .destroy = intel_connector_destroy, 2425 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2426 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state, 2427 }; 2428 2429 static int intel_sdvo_atomic_check(struct drm_connector *conn, 2430 struct drm_atomic_state *state) 2431 { 2432 struct drm_connector_state *new_conn_state = 2433 drm_atomic_get_new_connector_state(state, conn); 2434 struct drm_connector_state *old_conn_state = 2435 drm_atomic_get_old_connector_state(state, conn); 2436 struct intel_sdvo_connector_state *old_state = 2437 to_intel_sdvo_connector_state(old_conn_state); 2438 struct intel_sdvo_connector_state *new_state = 2439 to_intel_sdvo_connector_state(new_conn_state); 2440 2441 if (new_conn_state->crtc && 2442 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) || 2443 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) { 2444 struct drm_crtc_state *crtc_state = 2445 drm_atomic_get_new_crtc_state(state, 2446 new_conn_state->crtc); 2447 2448 crtc_state->connectors_changed = true; 2449 } 2450 2451 return intel_digital_connector_atomic_check(conn, state); 2452 } 2453 2454 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 2455 .get_modes = intel_sdvo_get_modes, 2456 .mode_valid = intel_sdvo_mode_valid, 2457 .atomic_check = intel_sdvo_atomic_check, 2458 }; 2459 2460 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) 2461 { 2462 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)); 2463 2464 i2c_del_adapter(&intel_sdvo->ddc); 2465 intel_encoder_destroy(encoder); 2466 } 2467 2468 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 2469 .destroy = intel_sdvo_enc_destroy, 2470 }; 2471 2472 static void 2473 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) 2474 { 2475 u16 mask = 0; 2476 unsigned int num_bits; 2477 2478 /* 2479 * Make a mask of outputs less than or equal to our own priority in the 2480 * list. 2481 */ 2482 switch (sdvo->controlled_output) { 2483 case SDVO_OUTPUT_LVDS1: 2484 mask |= SDVO_OUTPUT_LVDS1; 2485 /* fall through */ 2486 case SDVO_OUTPUT_LVDS0: 2487 mask |= SDVO_OUTPUT_LVDS0; 2488 /* fall through */ 2489 case SDVO_OUTPUT_TMDS1: 2490 mask |= SDVO_OUTPUT_TMDS1; 2491 /* fall through */ 2492 case SDVO_OUTPUT_TMDS0: 2493 mask |= SDVO_OUTPUT_TMDS0; 2494 /* fall through */ 2495 case SDVO_OUTPUT_RGB1: 2496 mask |= SDVO_OUTPUT_RGB1; 2497 /* fall through */ 2498 case SDVO_OUTPUT_RGB0: 2499 mask |= SDVO_OUTPUT_RGB0; 2500 break; 2501 } 2502 2503 /* Count bits to find what number we are in the priority list. */ 2504 mask &= sdvo->caps.output_flags; 2505 num_bits = hweight16(mask); 2506 /* If more than 3 outputs, default to DDC bus 3 for now. */ 2507 if (num_bits > 3) 2508 num_bits = 3; 2509 2510 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 2511 sdvo->ddc_bus = 1 << num_bits; 2512 } 2513 2514 /* 2515 * Choose the appropriate DDC bus for control bus switch command for this 2516 * SDVO output based on the controlled output. 2517 * 2518 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 2519 * outputs, then LVDS outputs. 2520 */ 2521 static void 2522 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, 2523 struct intel_sdvo *sdvo) 2524 { 2525 struct sdvo_device_mapping *mapping; 2526 2527 if (sdvo->port == PORT_B) 2528 mapping = &dev_priv->vbt.sdvo_mappings[0]; 2529 else 2530 mapping = &dev_priv->vbt.sdvo_mappings[1]; 2531 2532 if (mapping->initialized) 2533 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); 2534 else 2535 intel_sdvo_guess_ddc_bus(sdvo); 2536 } 2537 2538 static void 2539 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, 2540 struct intel_sdvo *sdvo) 2541 { 2542 struct sdvo_device_mapping *mapping; 2543 u8 pin; 2544 2545 if (sdvo->port == PORT_B) 2546 mapping = &dev_priv->vbt.sdvo_mappings[0]; 2547 else 2548 mapping = &dev_priv->vbt.sdvo_mappings[1]; 2549 2550 if (mapping->initialized && 2551 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin)) 2552 pin = mapping->i2c_pin; 2553 else 2554 pin = GMBUS_PIN_DPB; 2555 2556 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); 2557 2558 /* 2559 * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow 2560 * our code totally fails once we start using gmbus. Hence fall back to 2561 * bit banging for now. 2562 */ 2563 intel_gmbus_force_bit(sdvo->i2c, true); 2564 } 2565 2566 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ 2567 static void 2568 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) 2569 { 2570 intel_gmbus_force_bit(sdvo->i2c, false); 2571 } 2572 2573 static bool 2574 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) 2575 { 2576 return intel_sdvo_check_supp_encode(intel_sdvo); 2577 } 2578 2579 static u8 2580 intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv, 2581 struct intel_sdvo *sdvo) 2582 { 2583 struct sdvo_device_mapping *my_mapping, *other_mapping; 2584 2585 if (sdvo->port == PORT_B) { 2586 my_mapping = &dev_priv->vbt.sdvo_mappings[0]; 2587 other_mapping = &dev_priv->vbt.sdvo_mappings[1]; 2588 } else { 2589 my_mapping = &dev_priv->vbt.sdvo_mappings[1]; 2590 other_mapping = &dev_priv->vbt.sdvo_mappings[0]; 2591 } 2592 2593 /* If the BIOS described our SDVO device, take advantage of it. */ 2594 if (my_mapping->slave_addr) 2595 return my_mapping->slave_addr; 2596 2597 /* 2598 * If the BIOS only described a different SDVO device, use the 2599 * address that it isn't using. 2600 */ 2601 if (other_mapping->slave_addr) { 2602 if (other_mapping->slave_addr == 0x70) 2603 return 0x72; 2604 else 2605 return 0x70; 2606 } 2607 2608 /* 2609 * No SDVO device info is found for another DVO port, 2610 * so use mapping assumption we had before BIOS parsing. 2611 */ 2612 if (sdvo->port == PORT_B) 2613 return 0x70; 2614 else 2615 return 0x72; 2616 } 2617 2618 static int 2619 intel_sdvo_connector_init(struct intel_sdvo_connector *connector, 2620 struct intel_sdvo *encoder) 2621 { 2622 struct drm_connector *drm_connector; 2623 int ret; 2624 2625 drm_connector = &connector->base.base; 2626 ret = drm_connector_init(encoder->base.base.dev, 2627 drm_connector, 2628 &intel_sdvo_connector_funcs, 2629 connector->base.base.connector_type); 2630 if (ret < 0) 2631 return ret; 2632 2633 drm_connector_helper_add(drm_connector, 2634 &intel_sdvo_connector_helper_funcs); 2635 2636 connector->base.base.interlace_allowed = 1; 2637 connector->base.base.doublescan_allowed = 0; 2638 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 2639 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; 2640 2641 intel_connector_attach_encoder(&connector->base, &encoder->base); 2642 2643 return 0; 2644 } 2645 2646 static void 2647 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, 2648 struct intel_sdvo_connector *connector) 2649 { 2650 struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev); 2651 2652 intel_attach_force_audio_property(&connector->base.base); 2653 if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) { 2654 intel_attach_broadcast_rgb_property(&connector->base.base); 2655 } 2656 intel_attach_aspect_ratio_property(&connector->base.base); 2657 connector->base.base.state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 2658 } 2659 2660 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) 2661 { 2662 struct intel_sdvo_connector *sdvo_connector; 2663 struct intel_sdvo_connector_state *conn_state; 2664 2665 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL); 2666 if (!sdvo_connector) 2667 return NULL; 2668 2669 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL); 2670 if (!conn_state) { 2671 kfree(sdvo_connector); 2672 return NULL; 2673 } 2674 2675 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base, 2676 &conn_state->base.base); 2677 2678 return sdvo_connector; 2679 } 2680 2681 static bool 2682 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) 2683 { 2684 struct drm_encoder *encoder = &intel_sdvo->base.base; 2685 struct drm_connector *connector; 2686 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2687 struct intel_connector *intel_connector; 2688 struct intel_sdvo_connector *intel_sdvo_connector; 2689 2690 DRM_DEBUG_KMS("initialising DVI device %d\n", device); 2691 2692 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2693 if (!intel_sdvo_connector) 2694 return false; 2695 2696 if (device == 0) { 2697 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; 2698 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; 2699 } else if (device == 1) { 2700 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; 2701 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; 2702 } 2703 2704 intel_connector = &intel_sdvo_connector->base; 2705 connector = &intel_connector->base; 2706 if (intel_sdvo_get_hotplug_support(intel_sdvo) & 2707 intel_sdvo_connector->output_flag) { 2708 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; 2709 /* 2710 * Some SDVO devices have one-shot hotplug interrupts. 2711 * Ensure that they get re-enabled when an interrupt happens. 2712 */ 2713 intel_encoder->hotplug = intel_sdvo_hotplug; 2714 intel_sdvo_enable_hotplug(intel_encoder); 2715 } else { 2716 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2717 } 2718 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2719 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2720 2721 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { 2722 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2723 intel_sdvo_connector->is_hdmi = true; 2724 } 2725 2726 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2727 kfree(intel_sdvo_connector); 2728 return false; 2729 } 2730 2731 if (intel_sdvo_connector->is_hdmi) 2732 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); 2733 2734 return true; 2735 } 2736 2737 static bool 2738 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) 2739 { 2740 struct drm_encoder *encoder = &intel_sdvo->base.base; 2741 struct drm_connector *connector; 2742 struct intel_connector *intel_connector; 2743 struct intel_sdvo_connector *intel_sdvo_connector; 2744 2745 DRM_DEBUG_KMS("initialising TV type %d\n", type); 2746 2747 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2748 if (!intel_sdvo_connector) 2749 return false; 2750 2751 intel_connector = &intel_sdvo_connector->base; 2752 connector = &intel_connector->base; 2753 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2754 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2755 2756 intel_sdvo->controlled_output |= type; 2757 intel_sdvo_connector->output_flag = type; 2758 2759 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2760 kfree(intel_sdvo_connector); 2761 return false; 2762 } 2763 2764 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2765 goto err; 2766 2767 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2768 goto err; 2769 2770 return true; 2771 2772 err: 2773 intel_connector_destroy(connector); 2774 return false; 2775 } 2776 2777 static bool 2778 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) 2779 { 2780 struct drm_encoder *encoder = &intel_sdvo->base.base; 2781 struct drm_connector *connector; 2782 struct intel_connector *intel_connector; 2783 struct intel_sdvo_connector *intel_sdvo_connector; 2784 2785 DRM_DEBUG_KMS("initialising analog device %d\n", device); 2786 2787 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2788 if (!intel_sdvo_connector) 2789 return false; 2790 2791 intel_connector = &intel_sdvo_connector->base; 2792 connector = &intel_connector->base; 2793 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2794 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2795 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2796 2797 if (device == 0) { 2798 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; 2799 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; 2800 } else if (device == 1) { 2801 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; 2802 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2803 } 2804 2805 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2806 kfree(intel_sdvo_connector); 2807 return false; 2808 } 2809 2810 return true; 2811 } 2812 2813 static bool 2814 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) 2815 { 2816 struct drm_encoder *encoder = &intel_sdvo->base.base; 2817 struct drm_connector *connector; 2818 struct intel_connector *intel_connector; 2819 struct intel_sdvo_connector *intel_sdvo_connector; 2820 struct drm_display_mode *mode; 2821 2822 DRM_DEBUG_KMS("initialising LVDS device %d\n", device); 2823 2824 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2825 if (!intel_sdvo_connector) 2826 return false; 2827 2828 intel_connector = &intel_sdvo_connector->base; 2829 connector = &intel_connector->base; 2830 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2831 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2832 2833 if (device == 0) { 2834 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; 2835 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; 2836 } else if (device == 1) { 2837 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; 2838 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2839 } 2840 2841 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2842 kfree(intel_sdvo_connector); 2843 return false; 2844 } 2845 2846 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2847 goto err; 2848 2849 intel_sdvo_get_lvds_modes(connector); 2850 2851 list_for_each_entry(mode, &connector->probed_modes, head) { 2852 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 2853 struct drm_display_mode *fixed_mode = 2854 drm_mode_duplicate(connector->dev, mode); 2855 2856 intel_panel_init(&intel_connector->panel, 2857 fixed_mode, NULL); 2858 break; 2859 } 2860 } 2861 2862 if (!intel_connector->panel.fixed_mode) 2863 goto err; 2864 2865 return true; 2866 2867 err: 2868 intel_connector_destroy(connector); 2869 return false; 2870 } 2871 2872 static bool 2873 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, u16 flags) 2874 { 2875 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2876 2877 if (flags & SDVO_OUTPUT_TMDS0) 2878 if (!intel_sdvo_dvi_init(intel_sdvo, 0)) 2879 return false; 2880 2881 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) 2882 if (!intel_sdvo_dvi_init(intel_sdvo, 1)) 2883 return false; 2884 2885 /* TV has no XXX1 function block */ 2886 if (flags & SDVO_OUTPUT_SVID0) 2887 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) 2888 return false; 2889 2890 if (flags & SDVO_OUTPUT_CVBS0) 2891 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) 2892 return false; 2893 2894 if (flags & SDVO_OUTPUT_YPRPB0) 2895 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) 2896 return false; 2897 2898 if (flags & SDVO_OUTPUT_RGB0) 2899 if (!intel_sdvo_analog_init(intel_sdvo, 0)) 2900 return false; 2901 2902 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) 2903 if (!intel_sdvo_analog_init(intel_sdvo, 1)) 2904 return false; 2905 2906 if (flags & SDVO_OUTPUT_LVDS0) 2907 if (!intel_sdvo_lvds_init(intel_sdvo, 0)) 2908 return false; 2909 2910 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) 2911 if (!intel_sdvo_lvds_init(intel_sdvo, 1)) 2912 return false; 2913 2914 if ((flags & SDVO_OUTPUT_MASK) == 0) { 2915 unsigned char bytes[2]; 2916 2917 intel_sdvo->controlled_output = 0; 2918 memcpy(bytes, &intel_sdvo->caps.output_flags, 2); 2919 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", 2920 SDVO_NAME(intel_sdvo), 2921 bytes[0], bytes[1]); 2922 return false; 2923 } 2924 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2925 2926 return true; 2927 } 2928 2929 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) 2930 { 2931 struct drm_device *dev = intel_sdvo->base.base.dev; 2932 struct drm_connector *connector, *tmp; 2933 2934 list_for_each_entry_safe(connector, tmp, 2935 &dev->mode_config.connector_list, head) { 2936 if (intel_attached_encoder(connector) == &intel_sdvo->base) { 2937 drm_connector_unregister(connector); 2938 intel_connector_destroy(connector); 2939 } 2940 } 2941 } 2942 2943 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 2944 struct intel_sdvo_connector *intel_sdvo_connector, 2945 int type) 2946 { 2947 struct drm_device *dev = intel_sdvo->base.base.dev; 2948 struct intel_sdvo_tv_format format; 2949 u32 format_map, i; 2950 2951 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 2952 return false; 2953 2954 BUILD_BUG_ON(sizeof(format) != 6); 2955 if (!intel_sdvo_get_value(intel_sdvo, 2956 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 2957 &format, sizeof(format))) 2958 return false; 2959 2960 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 2961 2962 if (format_map == 0) 2963 return false; 2964 2965 intel_sdvo_connector->format_supported_num = 0; 2966 for (i = 0 ; i < TV_FORMAT_NUM; i++) 2967 if (format_map & (1 << i)) 2968 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 2969 2970 2971 intel_sdvo_connector->tv_format = 2972 drm_property_create(dev, DRM_MODE_PROP_ENUM, 2973 "mode", intel_sdvo_connector->format_supported_num); 2974 if (!intel_sdvo_connector->tv_format) 2975 return false; 2976 2977 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2978 drm_property_add_enum(intel_sdvo_connector->tv_format, i, 2979 tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 2980 2981 intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0]; 2982 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 2983 intel_sdvo_connector->tv_format, 0); 2984 return true; 2985 2986 } 2987 2988 #define _ENHANCEMENT(state_assignment, name, NAME) do { \ 2989 if (enhancements.name) { \ 2990 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 2991 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 2992 return false; \ 2993 intel_sdvo_connector->name = \ 2994 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ 2995 if (!intel_sdvo_connector->name) return false; \ 2996 state_assignment = response; \ 2997 drm_object_attach_property(&connector->base, \ 2998 intel_sdvo_connector->name, 0); \ 2999 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 3000 data_value[0], data_value[1], response); \ 3001 } \ 3002 } while (0) 3003 3004 #define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME) 3005 3006 static bool 3007 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 3008 struct intel_sdvo_connector *intel_sdvo_connector, 3009 struct intel_sdvo_enhancements_reply enhancements) 3010 { 3011 struct drm_device *dev = intel_sdvo->base.base.dev; 3012 struct drm_connector *connector = &intel_sdvo_connector->base.base; 3013 struct drm_connector_state *conn_state = connector->state; 3014 struct intel_sdvo_connector_state *sdvo_state = 3015 to_intel_sdvo_connector_state(conn_state); 3016 u16 response, data_value[2]; 3017 3018 /* when horizontal overscan is supported, Add the left/right property */ 3019 if (enhancements.overscan_h) { 3020 if (!intel_sdvo_get_value(intel_sdvo, 3021 SDVO_CMD_GET_MAX_OVERSCAN_H, 3022 &data_value, 4)) 3023 return false; 3024 3025 if (!intel_sdvo_get_value(intel_sdvo, 3026 SDVO_CMD_GET_OVERSCAN_H, 3027 &response, 2)) 3028 return false; 3029 3030 sdvo_state->tv.overscan_h = response; 3031 3032 intel_sdvo_connector->max_hscan = data_value[0]; 3033 intel_sdvo_connector->left = 3034 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); 3035 if (!intel_sdvo_connector->left) 3036 return false; 3037 3038 drm_object_attach_property(&connector->base, 3039 intel_sdvo_connector->left, 0); 3040 3041 intel_sdvo_connector->right = 3042 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); 3043 if (!intel_sdvo_connector->right) 3044 return false; 3045 3046 drm_object_attach_property(&connector->base, 3047 intel_sdvo_connector->right, 0); 3048 DRM_DEBUG_KMS("h_overscan: max %d, " 3049 "default %d, current %d\n", 3050 data_value[0], data_value[1], response); 3051 } 3052 3053 if (enhancements.overscan_v) { 3054 if (!intel_sdvo_get_value(intel_sdvo, 3055 SDVO_CMD_GET_MAX_OVERSCAN_V, 3056 &data_value, 4)) 3057 return false; 3058 3059 if (!intel_sdvo_get_value(intel_sdvo, 3060 SDVO_CMD_GET_OVERSCAN_V, 3061 &response, 2)) 3062 return false; 3063 3064 sdvo_state->tv.overscan_v = response; 3065 3066 intel_sdvo_connector->max_vscan = data_value[0]; 3067 intel_sdvo_connector->top = 3068 drm_property_create_range(dev, 0, 3069 "top_margin", 0, data_value[0]); 3070 if (!intel_sdvo_connector->top) 3071 return false; 3072 3073 drm_object_attach_property(&connector->base, 3074 intel_sdvo_connector->top, 0); 3075 3076 intel_sdvo_connector->bottom = 3077 drm_property_create_range(dev, 0, 3078 "bottom_margin", 0, data_value[0]); 3079 if (!intel_sdvo_connector->bottom) 3080 return false; 3081 3082 drm_object_attach_property(&connector->base, 3083 intel_sdvo_connector->bottom, 0); 3084 DRM_DEBUG_KMS("v_overscan: max %d, " 3085 "default %d, current %d\n", 3086 data_value[0], data_value[1], response); 3087 } 3088 3089 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS); 3090 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS); 3091 ENHANCEMENT(&conn_state->tv, saturation, SATURATION); 3092 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST); 3093 ENHANCEMENT(&conn_state->tv, hue, HUE); 3094 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS); 3095 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS); 3096 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER); 3097 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 3098 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D); 3099 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER); 3100 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER); 3101 3102 if (enhancements.dot_crawl) { 3103 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 3104 return false; 3105 3106 sdvo_state->tv.dot_crawl = response & 0x1; 3107 intel_sdvo_connector->dot_crawl = 3108 drm_property_create_range(dev, 0, "dot_crawl", 0, 1); 3109 if (!intel_sdvo_connector->dot_crawl) 3110 return false; 3111 3112 drm_object_attach_property(&connector->base, 3113 intel_sdvo_connector->dot_crawl, 0); 3114 DRM_DEBUG_KMS("dot crawl: current %d\n", response); 3115 } 3116 3117 return true; 3118 } 3119 3120 static bool 3121 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 3122 struct intel_sdvo_connector *intel_sdvo_connector, 3123 struct intel_sdvo_enhancements_reply enhancements) 3124 { 3125 struct drm_device *dev = intel_sdvo->base.base.dev; 3126 struct drm_connector *connector = &intel_sdvo_connector->base.base; 3127 u16 response, data_value[2]; 3128 3129 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS); 3130 3131 return true; 3132 } 3133 #undef ENHANCEMENT 3134 #undef _ENHANCEMENT 3135 3136 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 3137 struct intel_sdvo_connector *intel_sdvo_connector) 3138 { 3139 union { 3140 struct intel_sdvo_enhancements_reply reply; 3141 u16 response; 3142 } enhancements; 3143 3144 BUILD_BUG_ON(sizeof(enhancements) != 2); 3145 3146 if (!intel_sdvo_get_value(intel_sdvo, 3147 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 3148 &enhancements, sizeof(enhancements)) || 3149 enhancements.response == 0) { 3150 DRM_DEBUG_KMS("No enhancement is supported\n"); 3151 return true; 3152 } 3153 3154 if (IS_TV(intel_sdvo_connector)) 3155 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 3156 else if (IS_LVDS(intel_sdvo_connector)) 3157 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 3158 else 3159 return true; 3160 } 3161 3162 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, 3163 struct i2c_msg *msgs, 3164 int num) 3165 { 3166 struct intel_sdvo *sdvo = adapter->algo_data; 3167 3168 if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) 3169 return -EIO; 3170 3171 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); 3172 } 3173 3174 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) 3175 { 3176 struct intel_sdvo *sdvo = adapter->algo_data; 3177 return sdvo->i2c->algo->functionality(sdvo->i2c); 3178 } 3179 3180 static const struct i2c_algorithm intel_sdvo_ddc_proxy = { 3181 .master_xfer = intel_sdvo_ddc_proxy_xfer, 3182 .functionality = intel_sdvo_ddc_proxy_func 3183 }; 3184 3185 static void proxy_lock_bus(struct i2c_adapter *adapter, 3186 unsigned int flags) 3187 { 3188 struct intel_sdvo *sdvo = adapter->algo_data; 3189 sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags); 3190 } 3191 3192 static int proxy_trylock_bus(struct i2c_adapter *adapter, 3193 unsigned int flags) 3194 { 3195 struct intel_sdvo *sdvo = adapter->algo_data; 3196 return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags); 3197 } 3198 3199 static void proxy_unlock_bus(struct i2c_adapter *adapter, 3200 unsigned int flags) 3201 { 3202 struct intel_sdvo *sdvo = adapter->algo_data; 3203 sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags); 3204 } 3205 3206 static const struct i2c_lock_operations proxy_lock_ops = { 3207 .lock_bus = proxy_lock_bus, 3208 .trylock_bus = proxy_trylock_bus, 3209 .unlock_bus = proxy_unlock_bus, 3210 }; 3211 3212 static bool 3213 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, 3214 struct drm_i915_private *dev_priv) 3215 { 3216 struct pci_dev *pdev = dev_priv->drm.pdev; 3217 3218 sdvo->ddc.owner = THIS_MODULE; 3219 sdvo->ddc.class = I2C_CLASS_DDC; 3220 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); 3221 sdvo->ddc.dev.parent = &pdev->dev; 3222 sdvo->ddc.algo_data = sdvo; 3223 sdvo->ddc.algo = &intel_sdvo_ddc_proxy; 3224 sdvo->ddc.lock_ops = &proxy_lock_ops; 3225 3226 return i2c_add_adapter(&sdvo->ddc) == 0; 3227 } 3228 3229 static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv, 3230 enum port port) 3231 { 3232 if (HAS_PCH_SPLIT(dev_priv)) 3233 WARN_ON(port != PORT_B); 3234 else 3235 WARN_ON(port != PORT_B && port != PORT_C); 3236 } 3237 3238 bool intel_sdvo_init(struct drm_i915_private *dev_priv, 3239 i915_reg_t sdvo_reg, enum port port) 3240 { 3241 struct intel_encoder *intel_encoder; 3242 struct intel_sdvo *intel_sdvo; 3243 int i; 3244 3245 assert_sdvo_port_valid(dev_priv, port); 3246 3247 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); 3248 if (!intel_sdvo) 3249 return false; 3250 3251 intel_sdvo->sdvo_reg = sdvo_reg; 3252 intel_sdvo->port = port; 3253 intel_sdvo->slave_addr = 3254 intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1; 3255 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo); 3256 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv)) 3257 goto err_i2c_bus; 3258 3259 /* encoder type will be decided later */ 3260 intel_encoder = &intel_sdvo->base; 3261 intel_encoder->type = INTEL_OUTPUT_SDVO; 3262 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 3263 intel_encoder->port = port; 3264 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 3265 &intel_sdvo_enc_funcs, 0, 3266 "SDVO %c", port_name(port)); 3267 3268 /* Read the regs to test if we can talk to the device */ 3269 for (i = 0; i < 0x40; i++) { 3270 u8 byte; 3271 3272 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { 3273 DRM_DEBUG_KMS("No SDVO device found on %s\n", 3274 SDVO_NAME(intel_sdvo)); 3275 goto err; 3276 } 3277 } 3278 3279 intel_encoder->compute_config = intel_sdvo_compute_config; 3280 if (HAS_PCH_SPLIT(dev_priv)) { 3281 intel_encoder->disable = pch_disable_sdvo; 3282 intel_encoder->post_disable = pch_post_disable_sdvo; 3283 } else { 3284 intel_encoder->disable = intel_disable_sdvo; 3285 } 3286 intel_encoder->pre_enable = intel_sdvo_pre_enable; 3287 intel_encoder->enable = intel_enable_sdvo; 3288 intel_encoder->get_hw_state = intel_sdvo_get_hw_state; 3289 intel_encoder->get_config = intel_sdvo_get_config; 3290 3291 /* In default case sdvo lvds is false */ 3292 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 3293 goto err; 3294 3295 if (intel_sdvo_output_setup(intel_sdvo, 3296 intel_sdvo->caps.output_flags) != true) { 3297 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", 3298 SDVO_NAME(intel_sdvo)); 3299 /* Output_setup can leave behind connectors! */ 3300 goto err_output; 3301 } 3302 3303 /* 3304 * Only enable the hotplug irq if we need it, to work around noisy 3305 * hotplug lines. 3306 */ 3307 if (intel_sdvo->hotplug_active) { 3308 if (intel_sdvo->port == PORT_B) 3309 intel_encoder->hpd_pin = HPD_SDVO_B; 3310 else 3311 intel_encoder->hpd_pin = HPD_SDVO_C; 3312 } 3313 3314 /* 3315 * Cloning SDVO with anything is often impossible, since the SDVO 3316 * encoder can request a special input timing mode. And even if that's 3317 * not the case we have evidence that cloning a plain unscaled mode with 3318 * VGA doesn't really work. Furthermore the cloning flags are way too 3319 * simplistic anyway to express such constraints, so just give up on 3320 * cloning for SDVO encoders. 3321 */ 3322 intel_sdvo->base.cloneable = 0; 3323 3324 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo); 3325 3326 /* Set the input timing to the screen. Assume always input 0. */ 3327 if (!intel_sdvo_set_target_input(intel_sdvo)) 3328 goto err_output; 3329 3330 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 3331 &intel_sdvo->pixel_clock_min, 3332 &intel_sdvo->pixel_clock_max)) 3333 goto err_output; 3334 3335 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " 3336 "clock range %dMHz - %dMHz, " 3337 "input 1: %c, input 2: %c, " 3338 "output 1: %c, output 2: %c\n", 3339 SDVO_NAME(intel_sdvo), 3340 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 3341 intel_sdvo->caps.device_rev_id, 3342 intel_sdvo->pixel_clock_min / 1000, 3343 intel_sdvo->pixel_clock_max / 1000, 3344 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 3345 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 3346 /* check currently supported outputs */ 3347 intel_sdvo->caps.output_flags & 3348 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', 3349 intel_sdvo->caps.output_flags & 3350 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); 3351 return true; 3352 3353 err_output: 3354 intel_sdvo_output_cleanup(intel_sdvo); 3355 3356 err: 3357 drm_encoder_cleanup(&intel_encoder->base); 3358 i2c_del_adapter(&intel_sdvo->ddc); 3359 err_i2c_bus: 3360 intel_sdvo_unselect_i2c_bus(intel_sdvo); 3361 kfree(intel_sdvo); 3362 3363 return false; 3364 } 3365