1 /*
2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
3  * Copyright © 2006-2007 Intel Corporation
4  *   Jesse Barnes <jesse.barnes@intel.com>
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23  * DEALINGS IN THE SOFTWARE.
24  *
25  * Authors:
26  *	Eric Anholt <eric@anholt.net>
27  */
28 
29 #include <linux/delay.h>
30 #include <linux/export.h>
31 #include <linux/i2c.h>
32 #include <linux/slab.h>
33 
34 #include <drm/display/drm_hdmi_helper.h>
35 #include <drm/drm_atomic_helper.h>
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_edid.h>
38 
39 #include "i915_drv.h"
40 #include "i915_reg.h"
41 #include "intel_atomic.h"
42 #include "intel_audio.h"
43 #include "intel_connector.h"
44 #include "intel_crtc.h"
45 #include "intel_de.h"
46 #include "intel_display_types.h"
47 #include "intel_fifo_underrun.h"
48 #include "intel_gmbus.h"
49 #include "intel_hdmi.h"
50 #include "intel_hotplug.h"
51 #include "intel_panel.h"
52 #include "intel_sdvo.h"
53 #include "intel_sdvo_regs.h"
54 
55 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
56 #define SDVO_RGB_MASK  (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
57 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
58 #define SDVO_TV_MASK   (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
59 
60 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
61 			SDVO_TV_MASK)
62 
63 #define IS_TV(c)	(c->output_flag & SDVO_TV_MASK)
64 #define IS_TMDS(c)	(c->output_flag & SDVO_TMDS_MASK)
65 #define IS_LVDS(c)	(c->output_flag & SDVO_LVDS_MASK)
66 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
67 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
68 
69 
70 static const char * const tv_format_names[] = {
71 	"NTSC_M"   , "NTSC_J"  , "NTSC_443",
72 	"PAL_B"    , "PAL_D"   , "PAL_G"   ,
73 	"PAL_H"    , "PAL_I"   , "PAL_M"   ,
74 	"PAL_N"    , "PAL_NC"  , "PAL_60"  ,
75 	"SECAM_B"  , "SECAM_D" , "SECAM_G" ,
76 	"SECAM_K"  , "SECAM_K1", "SECAM_L" ,
77 	"SECAM_60"
78 };
79 
80 #define TV_FORMAT_NUM  ARRAY_SIZE(tv_format_names)
81 
82 struct intel_sdvo {
83 	struct intel_encoder base;
84 
85 	struct i2c_adapter *i2c;
86 	u8 slave_addr;
87 
88 	struct i2c_adapter ddc;
89 
90 	/* Register for the SDVO device: SDVOB or SDVOC */
91 	i915_reg_t sdvo_reg;
92 
93 	/* Active outputs controlled by this SDVO output */
94 	u16 controlled_output;
95 
96 	/*
97 	 * Capabilities of the SDVO device returned by
98 	 * intel_sdvo_get_capabilities()
99 	 */
100 	struct intel_sdvo_caps caps;
101 
102 	u8 colorimetry_cap;
103 
104 	/* Pixel clock limitations reported by the SDVO device, in kHz */
105 	int pixel_clock_min, pixel_clock_max;
106 
107 	/*
108 	* For multiple function SDVO device,
109 	* this is for current attached outputs.
110 	*/
111 	u16 attached_output;
112 
113 	/*
114 	 * Hotplug activation bits for this device
115 	 */
116 	u16 hotplug_active;
117 
118 	enum port port;
119 
120 	/* DDC bus used by this SDVO encoder */
121 	u8 ddc_bus;
122 
123 	/*
124 	 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
125 	 */
126 	u8 dtd_sdvo_flags;
127 };
128 
129 struct intel_sdvo_connector {
130 	struct intel_connector base;
131 
132 	/* Mark the type of connector */
133 	u16 output_flag;
134 
135 	/* This contains all current supported TV format */
136 	u8 tv_format_supported[TV_FORMAT_NUM];
137 	int   format_supported_num;
138 	struct drm_property *tv_format;
139 
140 	/* add the property for the SDVO-TV */
141 	struct drm_property *left;
142 	struct drm_property *right;
143 	struct drm_property *top;
144 	struct drm_property *bottom;
145 	struct drm_property *hpos;
146 	struct drm_property *vpos;
147 	struct drm_property *contrast;
148 	struct drm_property *saturation;
149 	struct drm_property *hue;
150 	struct drm_property *sharpness;
151 	struct drm_property *flicker_filter;
152 	struct drm_property *flicker_filter_adaptive;
153 	struct drm_property *flicker_filter_2d;
154 	struct drm_property *tv_chroma_filter;
155 	struct drm_property *tv_luma_filter;
156 	struct drm_property *dot_crawl;
157 
158 	/* add the property for the SDVO-TV/LVDS */
159 	struct drm_property *brightness;
160 
161 	/* this is to get the range of margin.*/
162 	u32 max_hscan, max_vscan;
163 
164 	/**
165 	 * This is set if we treat the device as HDMI, instead of DVI.
166 	 */
167 	bool is_hdmi;
168 };
169 
170 struct intel_sdvo_connector_state {
171 	/* base.base: tv.saturation/contrast/hue/brightness */
172 	struct intel_digital_connector_state base;
173 
174 	struct {
175 		unsigned overscan_h, overscan_v, hpos, vpos, sharpness;
176 		unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive;
177 		unsigned chroma_filter, luma_filter, dot_crawl;
178 	} tv;
179 };
180 
181 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
182 {
183 	return container_of(encoder, struct intel_sdvo, base);
184 }
185 
186 static struct intel_sdvo *intel_attached_sdvo(struct intel_connector *connector)
187 {
188 	return to_sdvo(intel_attached_encoder(connector));
189 }
190 
191 static struct intel_sdvo_connector *
192 to_intel_sdvo_connector(struct drm_connector *connector)
193 {
194 	return container_of(connector, struct intel_sdvo_connector, base.base);
195 }
196 
197 #define to_intel_sdvo_connector_state(conn_state) \
198 	container_of((conn_state), struct intel_sdvo_connector_state, base.base)
199 
200 static bool
201 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo);
202 static bool
203 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
204 			      struct intel_sdvo_connector *intel_sdvo_connector,
205 			      int type);
206 static bool
207 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
208 				   struct intel_sdvo_connector *intel_sdvo_connector);
209 
210 /*
211  * Writes the SDVOB or SDVOC with the given value, but always writes both
212  * SDVOB and SDVOC to work around apparent hardware issues (according to
213  * comments in the BIOS).
214  */
215 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
216 {
217 	struct drm_device *dev = intel_sdvo->base.base.dev;
218 	struct drm_i915_private *dev_priv = to_i915(dev);
219 	u32 bval = val, cval = val;
220 	int i;
221 
222 	if (HAS_PCH_SPLIT(dev_priv)) {
223 		intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val);
224 		intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg);
225 		/*
226 		 * HW workaround, need to write this twice for issue
227 		 * that may result in first write getting masked.
228 		 */
229 		if (HAS_PCH_IBX(dev_priv)) {
230 			intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val);
231 			intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg);
232 		}
233 		return;
234 	}
235 
236 	if (intel_sdvo->port == PORT_B)
237 		cval = intel_de_read(dev_priv, GEN3_SDVOC);
238 	else
239 		bval = intel_de_read(dev_priv, GEN3_SDVOB);
240 
241 	/*
242 	 * Write the registers twice for luck. Sometimes,
243 	 * writing them only once doesn't appear to 'stick'.
244 	 * The BIOS does this too. Yay, magic
245 	 */
246 	for (i = 0; i < 2; i++) {
247 		intel_de_write(dev_priv, GEN3_SDVOB, bval);
248 		intel_de_posting_read(dev_priv, GEN3_SDVOB);
249 
250 		intel_de_write(dev_priv, GEN3_SDVOC, cval);
251 		intel_de_posting_read(dev_priv, GEN3_SDVOC);
252 	}
253 }
254 
255 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
256 {
257 	struct i2c_msg msgs[] = {
258 		{
259 			.addr = intel_sdvo->slave_addr,
260 			.flags = 0,
261 			.len = 1,
262 			.buf = &addr,
263 		},
264 		{
265 			.addr = intel_sdvo->slave_addr,
266 			.flags = I2C_M_RD,
267 			.len = 1,
268 			.buf = ch,
269 		}
270 	};
271 	int ret;
272 
273 	if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
274 		return true;
275 
276 	DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
277 	return false;
278 }
279 
280 #define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ }
281 
282 /** Mapping of command numbers to names, for debug output */
283 static const struct {
284 	u8 cmd;
285 	const char *name;
286 } __packed sdvo_cmd_names[] = {
287 	SDVO_CMD_NAME_ENTRY(RESET),
288 	SDVO_CMD_NAME_ENTRY(GET_DEVICE_CAPS),
289 	SDVO_CMD_NAME_ENTRY(GET_FIRMWARE_REV),
290 	SDVO_CMD_NAME_ENTRY(GET_TRAINED_INPUTS),
291 	SDVO_CMD_NAME_ENTRY(GET_ACTIVE_OUTPUTS),
292 	SDVO_CMD_NAME_ENTRY(SET_ACTIVE_OUTPUTS),
293 	SDVO_CMD_NAME_ENTRY(GET_IN_OUT_MAP),
294 	SDVO_CMD_NAME_ENTRY(SET_IN_OUT_MAP),
295 	SDVO_CMD_NAME_ENTRY(GET_ATTACHED_DISPLAYS),
296 	SDVO_CMD_NAME_ENTRY(GET_HOT_PLUG_SUPPORT),
297 	SDVO_CMD_NAME_ENTRY(SET_ACTIVE_HOT_PLUG),
298 	SDVO_CMD_NAME_ENTRY(GET_ACTIVE_HOT_PLUG),
299 	SDVO_CMD_NAME_ENTRY(GET_INTERRUPT_EVENT_SOURCE),
300 	SDVO_CMD_NAME_ENTRY(SET_TARGET_INPUT),
301 	SDVO_CMD_NAME_ENTRY(SET_TARGET_OUTPUT),
302 	SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART1),
303 	SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART2),
304 	SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART1),
305 	SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART2),
306 	SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART1),
307 	SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART2),
308 	SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART1),
309 	SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART2),
310 	SDVO_CMD_NAME_ENTRY(CREATE_PREFERRED_INPUT_TIMING),
311 	SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART1),
312 	SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART2),
313 	SDVO_CMD_NAME_ENTRY(GET_INPUT_PIXEL_CLOCK_RANGE),
314 	SDVO_CMD_NAME_ENTRY(GET_OUTPUT_PIXEL_CLOCK_RANGE),
315 	SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_CLOCK_RATE_MULTS),
316 	SDVO_CMD_NAME_ENTRY(GET_CLOCK_RATE_MULT),
317 	SDVO_CMD_NAME_ENTRY(SET_CLOCK_RATE_MULT),
318 	SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_TV_FORMATS),
319 	SDVO_CMD_NAME_ENTRY(GET_TV_FORMAT),
320 	SDVO_CMD_NAME_ENTRY(SET_TV_FORMAT),
321 	SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_POWER_STATES),
322 	SDVO_CMD_NAME_ENTRY(GET_POWER_STATE),
323 	SDVO_CMD_NAME_ENTRY(SET_ENCODER_POWER_STATE),
324 	SDVO_CMD_NAME_ENTRY(SET_DISPLAY_POWER_STATE),
325 	SDVO_CMD_NAME_ENTRY(SET_CONTROL_BUS_SWITCH),
326 	SDVO_CMD_NAME_ENTRY(GET_SDTV_RESOLUTION_SUPPORT),
327 	SDVO_CMD_NAME_ENTRY(GET_SCALED_HDTV_RESOLUTION_SUPPORT),
328 	SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_ENHANCEMENTS),
329 
330 	/* Add the op code for SDVO enhancements */
331 	SDVO_CMD_NAME_ENTRY(GET_MAX_HPOS),
332 	SDVO_CMD_NAME_ENTRY(GET_HPOS),
333 	SDVO_CMD_NAME_ENTRY(SET_HPOS),
334 	SDVO_CMD_NAME_ENTRY(GET_MAX_VPOS),
335 	SDVO_CMD_NAME_ENTRY(GET_VPOS),
336 	SDVO_CMD_NAME_ENTRY(SET_VPOS),
337 	SDVO_CMD_NAME_ENTRY(GET_MAX_SATURATION),
338 	SDVO_CMD_NAME_ENTRY(GET_SATURATION),
339 	SDVO_CMD_NAME_ENTRY(SET_SATURATION),
340 	SDVO_CMD_NAME_ENTRY(GET_MAX_HUE),
341 	SDVO_CMD_NAME_ENTRY(GET_HUE),
342 	SDVO_CMD_NAME_ENTRY(SET_HUE),
343 	SDVO_CMD_NAME_ENTRY(GET_MAX_CONTRAST),
344 	SDVO_CMD_NAME_ENTRY(GET_CONTRAST),
345 	SDVO_CMD_NAME_ENTRY(SET_CONTRAST),
346 	SDVO_CMD_NAME_ENTRY(GET_MAX_BRIGHTNESS),
347 	SDVO_CMD_NAME_ENTRY(GET_BRIGHTNESS),
348 	SDVO_CMD_NAME_ENTRY(SET_BRIGHTNESS),
349 	SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_H),
350 	SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_H),
351 	SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_H),
352 	SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_V),
353 	SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_V),
354 	SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_V),
355 	SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER),
356 	SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER),
357 	SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER),
358 	SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_ADAPTIVE),
359 	SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_ADAPTIVE),
360 	SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_ADAPTIVE),
361 	SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_2D),
362 	SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_2D),
363 	SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_2D),
364 	SDVO_CMD_NAME_ENTRY(GET_MAX_SHARPNESS),
365 	SDVO_CMD_NAME_ENTRY(GET_SHARPNESS),
366 	SDVO_CMD_NAME_ENTRY(SET_SHARPNESS),
367 	SDVO_CMD_NAME_ENTRY(GET_DOT_CRAWL),
368 	SDVO_CMD_NAME_ENTRY(SET_DOT_CRAWL),
369 	SDVO_CMD_NAME_ENTRY(GET_MAX_TV_CHROMA_FILTER),
370 	SDVO_CMD_NAME_ENTRY(GET_TV_CHROMA_FILTER),
371 	SDVO_CMD_NAME_ENTRY(SET_TV_CHROMA_FILTER),
372 	SDVO_CMD_NAME_ENTRY(GET_MAX_TV_LUMA_FILTER),
373 	SDVO_CMD_NAME_ENTRY(GET_TV_LUMA_FILTER),
374 	SDVO_CMD_NAME_ENTRY(SET_TV_LUMA_FILTER),
375 
376 	/* HDMI op code */
377 	SDVO_CMD_NAME_ENTRY(GET_SUPP_ENCODE),
378 	SDVO_CMD_NAME_ENTRY(GET_ENCODE),
379 	SDVO_CMD_NAME_ENTRY(SET_ENCODE),
380 	SDVO_CMD_NAME_ENTRY(SET_PIXEL_REPLI),
381 	SDVO_CMD_NAME_ENTRY(GET_PIXEL_REPLI),
382 	SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY_CAP),
383 	SDVO_CMD_NAME_ENTRY(SET_COLORIMETRY),
384 	SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY),
385 	SDVO_CMD_NAME_ENTRY(GET_AUDIO_ENCRYPT_PREFER),
386 	SDVO_CMD_NAME_ENTRY(SET_AUDIO_STAT),
387 	SDVO_CMD_NAME_ENTRY(GET_AUDIO_STAT),
388 	SDVO_CMD_NAME_ENTRY(GET_HBUF_INDEX),
389 	SDVO_CMD_NAME_ENTRY(SET_HBUF_INDEX),
390 	SDVO_CMD_NAME_ENTRY(GET_HBUF_INFO),
391 	SDVO_CMD_NAME_ENTRY(GET_HBUF_AV_SPLIT),
392 	SDVO_CMD_NAME_ENTRY(SET_HBUF_AV_SPLIT),
393 	SDVO_CMD_NAME_ENTRY(GET_HBUF_TXRATE),
394 	SDVO_CMD_NAME_ENTRY(SET_HBUF_TXRATE),
395 	SDVO_CMD_NAME_ENTRY(SET_HBUF_DATA),
396 	SDVO_CMD_NAME_ENTRY(GET_HBUF_DATA),
397 };
398 
399 #undef SDVO_CMD_NAME_ENTRY
400 
401 static const char *sdvo_cmd_name(u8 cmd)
402 {
403 	int i;
404 
405 	for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
406 		if (cmd == sdvo_cmd_names[i].cmd)
407 			return sdvo_cmd_names[i].name;
408 	}
409 
410 	return NULL;
411 }
412 
413 #define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC")
414 
415 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
416 				   const void *args, int args_len)
417 {
418 	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
419 	const char *cmd_name;
420 	int i, pos = 0;
421 	char buffer[64];
422 
423 #define BUF_PRINT(args...) \
424 	pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args)
425 
426 	for (i = 0; i < args_len; i++) {
427 		BUF_PRINT("%02X ", ((u8 *)args)[i]);
428 	}
429 	for (; i < 8; i++) {
430 		BUF_PRINT("   ");
431 	}
432 
433 	cmd_name = sdvo_cmd_name(cmd);
434 	if (cmd_name)
435 		BUF_PRINT("(%s)", cmd_name);
436 	else
437 		BUF_PRINT("(%02X)", cmd);
438 
439 	drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
440 #undef BUF_PRINT
441 
442 	DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
443 }
444 
445 static const char * const cmd_status_names[] = {
446 	[SDVO_CMD_STATUS_POWER_ON] = "Power on",
447 	[SDVO_CMD_STATUS_SUCCESS] = "Success",
448 	[SDVO_CMD_STATUS_NOTSUPP] = "Not supported",
449 	[SDVO_CMD_STATUS_INVALID_ARG] = "Invalid arg",
450 	[SDVO_CMD_STATUS_PENDING] = "Pending",
451 	[SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED] = "Target not specified",
452 	[SDVO_CMD_STATUS_SCALING_NOT_SUPP] = "Scaling not supported",
453 };
454 
455 static const char *sdvo_cmd_status(u8 status)
456 {
457 	if (status < ARRAY_SIZE(cmd_status_names))
458 		return cmd_status_names[status];
459 	else
460 		return NULL;
461 }
462 
463 static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
464 				   const void *args, int args_len,
465 				   bool unlocked)
466 {
467 	u8 *buf, status;
468 	struct i2c_msg *msgs;
469 	int i, ret = true;
470 
471 	/* Would be simpler to allocate both in one go ? */
472 	buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
473 	if (!buf)
474 		return false;
475 
476 	msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
477 	if (!msgs) {
478 		kfree(buf);
479 		return false;
480 	}
481 
482 	intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
483 
484 	for (i = 0; i < args_len; i++) {
485 		msgs[i].addr = intel_sdvo->slave_addr;
486 		msgs[i].flags = 0;
487 		msgs[i].len = 2;
488 		msgs[i].buf = buf + 2 *i;
489 		buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
490 		buf[2*i + 1] = ((u8*)args)[i];
491 	}
492 	msgs[i].addr = intel_sdvo->slave_addr;
493 	msgs[i].flags = 0;
494 	msgs[i].len = 2;
495 	msgs[i].buf = buf + 2*i;
496 	buf[2*i + 0] = SDVO_I2C_OPCODE;
497 	buf[2*i + 1] = cmd;
498 
499 	/* the following two are to read the response */
500 	status = SDVO_I2C_CMD_STATUS;
501 	msgs[i+1].addr = intel_sdvo->slave_addr;
502 	msgs[i+1].flags = 0;
503 	msgs[i+1].len = 1;
504 	msgs[i+1].buf = &status;
505 
506 	msgs[i+2].addr = intel_sdvo->slave_addr;
507 	msgs[i+2].flags = I2C_M_RD;
508 	msgs[i+2].len = 1;
509 	msgs[i+2].buf = &status;
510 
511 	if (unlocked)
512 		ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
513 	else
514 		ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3);
515 	if (ret < 0) {
516 		DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
517 		ret = false;
518 		goto out;
519 	}
520 	if (ret != i+3) {
521 		/* failure in I2C transfer */
522 		DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
523 		ret = false;
524 	}
525 
526 out:
527 	kfree(msgs);
528 	kfree(buf);
529 	return ret;
530 }
531 
532 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
533 				 const void *args, int args_len)
534 {
535 	return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true);
536 }
537 
538 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
539 				     void *response, int response_len)
540 {
541 	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
542 	const char *cmd_status;
543 	u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
544 	u8 status;
545 	int i, pos = 0;
546 	char buffer[64];
547 
548 	buffer[0] = '\0';
549 
550 	/*
551 	 * The documentation states that all commands will be
552 	 * processed within 15µs, and that we need only poll
553 	 * the status byte a maximum of 3 times in order for the
554 	 * command to be complete.
555 	 *
556 	 * Check 5 times in case the hardware failed to read the docs.
557 	 *
558 	 * Also beware that the first response by many devices is to
559 	 * reply PENDING and stall for time. TVs are notorious for
560 	 * requiring longer than specified to complete their replies.
561 	 * Originally (in the DDX long ago), the delay was only ever 15ms
562 	 * with an additional delay of 30ms applied for TVs added later after
563 	 * many experiments. To accommodate both sets of delays, we do a
564 	 * sequence of slow checks if the device is falling behind and fails
565 	 * to reply within 5*15µs.
566 	 */
567 	if (!intel_sdvo_read_byte(intel_sdvo,
568 				  SDVO_I2C_CMD_STATUS,
569 				  &status))
570 		goto log_fail;
571 
572 	while ((status == SDVO_CMD_STATUS_PENDING ||
573 		status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
574 		if (retry < 10)
575 			msleep(15);
576 		else
577 			udelay(15);
578 
579 		if (!intel_sdvo_read_byte(intel_sdvo,
580 					  SDVO_I2C_CMD_STATUS,
581 					  &status))
582 			goto log_fail;
583 	}
584 
585 #define BUF_PRINT(args...) \
586 	pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args)
587 
588 	cmd_status = sdvo_cmd_status(status);
589 	if (cmd_status)
590 		BUF_PRINT("(%s)", cmd_status);
591 	else
592 		BUF_PRINT("(??? %d)", status);
593 
594 	if (status != SDVO_CMD_STATUS_SUCCESS)
595 		goto log_fail;
596 
597 	/* Read the command response */
598 	for (i = 0; i < response_len; i++) {
599 		if (!intel_sdvo_read_byte(intel_sdvo,
600 					  SDVO_I2C_RETURN_0 + i,
601 					  &((u8 *)response)[i]))
602 			goto log_fail;
603 		BUF_PRINT(" %02X", ((u8 *)response)[i]);
604 	}
605 
606 	drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
607 #undef BUF_PRINT
608 
609 	DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
610 	return true;
611 
612 log_fail:
613 	DRM_DEBUG_KMS("%s: R: ... failed %s\n",
614 		      SDVO_NAME(intel_sdvo), buffer);
615 	return false;
616 }
617 
618 static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode)
619 {
620 	if (adjusted_mode->crtc_clock >= 100000)
621 		return 1;
622 	else if (adjusted_mode->crtc_clock >= 50000)
623 		return 2;
624 	else
625 		return 4;
626 }
627 
628 static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
629 						u8 ddc_bus)
630 {
631 	/* This must be the immediately preceding write before the i2c xfer */
632 	return __intel_sdvo_write_cmd(intel_sdvo,
633 				      SDVO_CMD_SET_CONTROL_BUS_SWITCH,
634 				      &ddc_bus, 1, false);
635 }
636 
637 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
638 {
639 	if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
640 		return false;
641 
642 	return intel_sdvo_read_response(intel_sdvo, NULL, 0);
643 }
644 
645 static bool
646 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
647 {
648 	if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
649 		return false;
650 
651 	return intel_sdvo_read_response(intel_sdvo, value, len);
652 }
653 
654 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
655 {
656 	struct intel_sdvo_set_target_input_args targets = {0};
657 	return intel_sdvo_set_value(intel_sdvo,
658 				    SDVO_CMD_SET_TARGET_INPUT,
659 				    &targets, sizeof(targets));
660 }
661 
662 /*
663  * Return whether each input is trained.
664  *
665  * This function is making an assumption about the layout of the response,
666  * which should be checked against the docs.
667  */
668 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
669 {
670 	struct intel_sdvo_get_trained_inputs_response response;
671 
672 	BUILD_BUG_ON(sizeof(response) != 1);
673 	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
674 				  &response, sizeof(response)))
675 		return false;
676 
677 	*input_1 = response.input0_trained;
678 	*input_2 = response.input1_trained;
679 	return true;
680 }
681 
682 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
683 					  u16 outputs)
684 {
685 	return intel_sdvo_set_value(intel_sdvo,
686 				    SDVO_CMD_SET_ACTIVE_OUTPUTS,
687 				    &outputs, sizeof(outputs));
688 }
689 
690 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
691 					  u16 *outputs)
692 {
693 	return intel_sdvo_get_value(intel_sdvo,
694 				    SDVO_CMD_GET_ACTIVE_OUTPUTS,
695 				    outputs, sizeof(*outputs));
696 }
697 
698 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
699 					       int mode)
700 {
701 	u8 state = SDVO_ENCODER_STATE_ON;
702 
703 	switch (mode) {
704 	case DRM_MODE_DPMS_ON:
705 		state = SDVO_ENCODER_STATE_ON;
706 		break;
707 	case DRM_MODE_DPMS_STANDBY:
708 		state = SDVO_ENCODER_STATE_STANDBY;
709 		break;
710 	case DRM_MODE_DPMS_SUSPEND:
711 		state = SDVO_ENCODER_STATE_SUSPEND;
712 		break;
713 	case DRM_MODE_DPMS_OFF:
714 		state = SDVO_ENCODER_STATE_OFF;
715 		break;
716 	}
717 
718 	return intel_sdvo_set_value(intel_sdvo,
719 				    SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
720 }
721 
722 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
723 						   int *clock_min,
724 						   int *clock_max)
725 {
726 	struct intel_sdvo_pixel_clock_range clocks;
727 
728 	BUILD_BUG_ON(sizeof(clocks) != 4);
729 	if (!intel_sdvo_get_value(intel_sdvo,
730 				  SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
731 				  &clocks, sizeof(clocks)))
732 		return false;
733 
734 	/* Convert the values from units of 10 kHz to kHz. */
735 	*clock_min = clocks.min * 10;
736 	*clock_max = clocks.max * 10;
737 	return true;
738 }
739 
740 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
741 					 u16 outputs)
742 {
743 	return intel_sdvo_set_value(intel_sdvo,
744 				    SDVO_CMD_SET_TARGET_OUTPUT,
745 				    &outputs, sizeof(outputs));
746 }
747 
748 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
749 				  struct intel_sdvo_dtd *dtd)
750 {
751 	return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
752 		intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
753 }
754 
755 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
756 				  struct intel_sdvo_dtd *dtd)
757 {
758 	return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
759 		intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
760 }
761 
762 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
763 					 struct intel_sdvo_dtd *dtd)
764 {
765 	return intel_sdvo_set_timing(intel_sdvo,
766 				     SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
767 }
768 
769 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
770 					 struct intel_sdvo_dtd *dtd)
771 {
772 	return intel_sdvo_set_timing(intel_sdvo,
773 				     SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
774 }
775 
776 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
777 					struct intel_sdvo_dtd *dtd)
778 {
779 	return intel_sdvo_get_timing(intel_sdvo,
780 				     SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
781 }
782 
783 static bool
784 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
785 					 struct intel_sdvo_connector *intel_sdvo_connector,
786 					 const struct drm_display_mode *mode)
787 {
788 	struct intel_sdvo_preferred_input_timing_args args;
789 
790 	memset(&args, 0, sizeof(args));
791 	args.clock = mode->clock / 10;
792 	args.width = mode->hdisplay;
793 	args.height = mode->vdisplay;
794 	args.interlace = 0;
795 
796 	if (IS_LVDS(intel_sdvo_connector)) {
797 		const struct drm_display_mode *fixed_mode =
798 			intel_panel_fixed_mode(&intel_sdvo_connector->base, mode);
799 
800 		if (fixed_mode->hdisplay != args.width ||
801 		    fixed_mode->vdisplay != args.height)
802 			args.scaled = 1;
803 	}
804 
805 	return intel_sdvo_set_value(intel_sdvo,
806 				    SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
807 				    &args, sizeof(args));
808 }
809 
810 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
811 						  struct intel_sdvo_dtd *dtd)
812 {
813 	BUILD_BUG_ON(sizeof(dtd->part1) != 8);
814 	BUILD_BUG_ON(sizeof(dtd->part2) != 8);
815 	return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
816 				    &dtd->part1, sizeof(dtd->part1)) &&
817 		intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
818 				     &dtd->part2, sizeof(dtd->part2));
819 }
820 
821 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
822 {
823 	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
824 }
825 
826 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
827 					 const struct drm_display_mode *mode)
828 {
829 	u16 width, height;
830 	u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len;
831 	u16 h_sync_offset, v_sync_offset;
832 	int mode_clock;
833 
834 	memset(dtd, 0, sizeof(*dtd));
835 
836 	width = mode->hdisplay;
837 	height = mode->vdisplay;
838 
839 	/* do some mode translations */
840 	h_blank_len = mode->htotal - mode->hdisplay;
841 	h_sync_len = mode->hsync_end - mode->hsync_start;
842 
843 	v_blank_len = mode->vtotal - mode->vdisplay;
844 	v_sync_len = mode->vsync_end - mode->vsync_start;
845 
846 	h_sync_offset = mode->hsync_start - mode->hdisplay;
847 	v_sync_offset = mode->vsync_start - mode->vdisplay;
848 
849 	mode_clock = mode->clock;
850 	mode_clock /= 10;
851 	dtd->part1.clock = mode_clock;
852 
853 	dtd->part1.h_active = width & 0xff;
854 	dtd->part1.h_blank = h_blank_len & 0xff;
855 	dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
856 		((h_blank_len >> 8) & 0xf);
857 	dtd->part1.v_active = height & 0xff;
858 	dtd->part1.v_blank = v_blank_len & 0xff;
859 	dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
860 		((v_blank_len >> 8) & 0xf);
861 
862 	dtd->part2.h_sync_off = h_sync_offset & 0xff;
863 	dtd->part2.h_sync_width = h_sync_len & 0xff;
864 	dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
865 		(v_sync_len & 0xf);
866 	dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
867 		((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
868 		((v_sync_len & 0x30) >> 4);
869 
870 	dtd->part2.dtd_flags = 0x18;
871 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
872 		dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
873 	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
874 		dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
875 	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
876 		dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
877 
878 	dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
879 }
880 
881 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
882 					 const struct intel_sdvo_dtd *dtd)
883 {
884 	struct drm_display_mode mode = {};
885 
886 	mode.hdisplay = dtd->part1.h_active;
887 	mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
888 	mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
889 	mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
890 	mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
891 	mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
892 	mode.htotal = mode.hdisplay + dtd->part1.h_blank;
893 	mode.htotal += (dtd->part1.h_high & 0xf) << 8;
894 
895 	mode.vdisplay = dtd->part1.v_active;
896 	mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
897 	mode.vsync_start = mode.vdisplay;
898 	mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
899 	mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
900 	mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
901 	mode.vsync_end = mode.vsync_start +
902 		(dtd->part2.v_sync_off_width & 0xf);
903 	mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
904 	mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
905 	mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
906 
907 	mode.clock = dtd->part1.clock * 10;
908 
909 	if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
910 		mode.flags |= DRM_MODE_FLAG_INTERLACE;
911 	if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
912 		mode.flags |= DRM_MODE_FLAG_PHSYNC;
913 	else
914 		mode.flags |= DRM_MODE_FLAG_NHSYNC;
915 	if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
916 		mode.flags |= DRM_MODE_FLAG_PVSYNC;
917 	else
918 		mode.flags |= DRM_MODE_FLAG_NVSYNC;
919 
920 	drm_mode_set_crtcinfo(&mode, 0);
921 
922 	drm_mode_copy(pmode, &mode);
923 }
924 
925 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
926 {
927 	struct intel_sdvo_encode encode;
928 
929 	BUILD_BUG_ON(sizeof(encode) != 2);
930 	return intel_sdvo_get_value(intel_sdvo,
931 				  SDVO_CMD_GET_SUPP_ENCODE,
932 				  &encode, sizeof(encode));
933 }
934 
935 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
936 				  u8 mode)
937 {
938 	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
939 }
940 
941 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
942 				       u8 mode)
943 {
944 	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
945 }
946 
947 static bool intel_sdvo_set_pixel_replication(struct intel_sdvo *intel_sdvo,
948 					     u8 pixel_repeat)
949 {
950 	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_PIXEL_REPLI,
951 				    &pixel_repeat, 1);
952 }
953 
954 static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo,
955 				       u8 audio_state)
956 {
957 	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT,
958 				    &audio_state, 1);
959 }
960 
961 static bool intel_sdvo_get_hbuf_size(struct intel_sdvo *intel_sdvo,
962 				     u8 *hbuf_size)
963 {
964 	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
965 				  hbuf_size, 1))
966 		return false;
967 
968 	/* Buffer size is 0 based, hooray! However zero means zero. */
969 	if (*hbuf_size)
970 		(*hbuf_size)++;
971 
972 	return true;
973 }
974 
975 #if 0
976 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
977 {
978 	int i, j;
979 	u8 set_buf_index[2];
980 	u8 av_split;
981 	u8 buf_size;
982 	u8 buf[48];
983 	u8 *pos;
984 
985 	intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
986 
987 	for (i = 0; i <= av_split; i++) {
988 		set_buf_index[0] = i; set_buf_index[1] = 0;
989 		intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
990 				     set_buf_index, 2);
991 		intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
992 		intel_sdvo_read_response(encoder, &buf_size, 1);
993 
994 		pos = buf;
995 		for (j = 0; j <= buf_size; j += 8) {
996 			intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
997 					     NULL, 0);
998 			intel_sdvo_read_response(encoder, pos, 8);
999 			pos += 8;
1000 		}
1001 	}
1002 }
1003 #endif
1004 
1005 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
1006 				       unsigned int if_index, u8 tx_rate,
1007 				       const u8 *data, unsigned int length)
1008 {
1009 	u8 set_buf_index[2] = { if_index, 0 };
1010 	u8 hbuf_size, tmp[8];
1011 	int i;
1012 
1013 	if (!intel_sdvo_set_value(intel_sdvo,
1014 				  SDVO_CMD_SET_HBUF_INDEX,
1015 				  set_buf_index, 2))
1016 		return false;
1017 
1018 	if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
1019 		return false;
1020 
1021 	DRM_DEBUG_KMS("writing sdvo hbuf: %i, length %u, hbuf_size: %i\n",
1022 		      if_index, length, hbuf_size);
1023 
1024 	if (hbuf_size < length)
1025 		return false;
1026 
1027 	for (i = 0; i < hbuf_size; i += 8) {
1028 		memset(tmp, 0, 8);
1029 		if (i < length)
1030 			memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
1031 
1032 		if (!intel_sdvo_set_value(intel_sdvo,
1033 					  SDVO_CMD_SET_HBUF_DATA,
1034 					  tmp, 8))
1035 			return false;
1036 	}
1037 
1038 	return intel_sdvo_set_value(intel_sdvo,
1039 				    SDVO_CMD_SET_HBUF_TXRATE,
1040 				    &tx_rate, 1);
1041 }
1042 
1043 static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo,
1044 					 unsigned int if_index,
1045 					 u8 *data, unsigned int length)
1046 {
1047 	u8 set_buf_index[2] = { if_index, 0 };
1048 	u8 hbuf_size, tx_rate, av_split;
1049 	int i;
1050 
1051 	if (!intel_sdvo_get_value(intel_sdvo,
1052 				  SDVO_CMD_GET_HBUF_AV_SPLIT,
1053 				  &av_split, 1))
1054 		return -ENXIO;
1055 
1056 	if (av_split < if_index)
1057 		return 0;
1058 
1059 	if (!intel_sdvo_set_value(intel_sdvo,
1060 				  SDVO_CMD_SET_HBUF_INDEX,
1061 				  set_buf_index, 2))
1062 		return -ENXIO;
1063 
1064 	if (!intel_sdvo_get_value(intel_sdvo,
1065 				  SDVO_CMD_GET_HBUF_TXRATE,
1066 				  &tx_rate, 1))
1067 		return -ENXIO;
1068 
1069 	/* TX_DISABLED doesn't mean disabled for ELD */
1070 	if (if_index != SDVO_HBUF_INDEX_ELD && tx_rate == SDVO_HBUF_TX_DISABLED)
1071 		return 0;
1072 
1073 	if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
1074 		return false;
1075 
1076 	DRM_DEBUG_KMS("reading sdvo hbuf: %i, length %u, hbuf_size: %i\n",
1077 		      if_index, length, hbuf_size);
1078 
1079 	hbuf_size = min_t(unsigned int, length, hbuf_size);
1080 
1081 	for (i = 0; i < hbuf_size; i += 8) {
1082 		if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA, NULL, 0))
1083 			return -ENXIO;
1084 		if (!intel_sdvo_read_response(intel_sdvo, &data[i],
1085 					      min_t(unsigned int, 8, hbuf_size - i)))
1086 			return -ENXIO;
1087 	}
1088 
1089 	return hbuf_size;
1090 }
1091 
1092 static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
1093 					     struct intel_crtc_state *crtc_state,
1094 					     struct drm_connector_state *conn_state)
1095 {
1096 	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
1097 	struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
1098 	const struct drm_display_mode *adjusted_mode =
1099 		&crtc_state->hw.adjusted_mode;
1100 	int ret;
1101 
1102 	if (!crtc_state->has_hdmi_sink)
1103 		return true;
1104 
1105 	crtc_state->infoframes.enable |=
1106 		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
1107 
1108 	ret = drm_hdmi_avi_infoframe_from_display_mode(frame,
1109 						       conn_state->connector,
1110 						       adjusted_mode);
1111 	if (ret)
1112 		return false;
1113 
1114 	drm_hdmi_avi_infoframe_quant_range(frame,
1115 					   conn_state->connector,
1116 					   adjusted_mode,
1117 					   crtc_state->limited_color_range ?
1118 					   HDMI_QUANTIZATION_RANGE_LIMITED :
1119 					   HDMI_QUANTIZATION_RANGE_FULL);
1120 
1121 	ret = hdmi_avi_infoframe_check(frame);
1122 	if (drm_WARN_ON(&dev_priv->drm, ret))
1123 		return false;
1124 
1125 	return true;
1126 }
1127 
1128 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
1129 					 const struct intel_crtc_state *crtc_state)
1130 {
1131 	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
1132 	u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
1133 	const union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
1134 	ssize_t len;
1135 
1136 	if ((crtc_state->infoframes.enable &
1137 	     intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0)
1138 		return true;
1139 
1140 	if (drm_WARN_ON(&dev_priv->drm,
1141 			frame->any.type != HDMI_INFOFRAME_TYPE_AVI))
1142 		return false;
1143 
1144 	len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data));
1145 	if (drm_WARN_ON(&dev_priv->drm, len < 0))
1146 		return false;
1147 
1148 	return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1149 					  SDVO_HBUF_TX_VSYNC,
1150 					  sdvo_data, len);
1151 }
1152 
1153 static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo,
1154 					 struct intel_crtc_state *crtc_state)
1155 {
1156 	u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
1157 	union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
1158 	ssize_t len;
1159 	int ret;
1160 
1161 	if (!crtc_state->has_hdmi_sink)
1162 		return;
1163 
1164 	len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1165 					sdvo_data, sizeof(sdvo_data));
1166 	if (len < 0) {
1167 		DRM_DEBUG_KMS("failed to read AVI infoframe\n");
1168 		return;
1169 	} else if (len == 0) {
1170 		return;
1171 	}
1172 
1173 	crtc_state->infoframes.enable |=
1174 		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
1175 
1176 	ret = hdmi_infoframe_unpack(frame, sdvo_data, len);
1177 	if (ret) {
1178 		DRM_DEBUG_KMS("Failed to unpack AVI infoframe\n");
1179 		return;
1180 	}
1181 
1182 	if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI)
1183 		DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
1184 			      frame->any.type, HDMI_INFOFRAME_TYPE_AVI);
1185 }
1186 
1187 static void intel_sdvo_get_eld(struct intel_sdvo *intel_sdvo,
1188 			       struct intel_crtc_state *crtc_state)
1189 {
1190 	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
1191 	ssize_t len;
1192 	u8 val;
1193 
1194 	if (!crtc_state->has_audio)
1195 		return;
1196 
1197 	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, &val, 1))
1198 		return;
1199 
1200 	if ((val & SDVO_AUDIO_ELD_VALID) == 0)
1201 		return;
1202 
1203 	len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD,
1204 					crtc_state->eld, sizeof(crtc_state->eld));
1205 	if (len < 0)
1206 		drm_dbg_kms(&i915->drm, "failed to read ELD\n");
1207 }
1208 
1209 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
1210 				     const struct drm_connector_state *conn_state)
1211 {
1212 	struct intel_sdvo_tv_format format;
1213 	u32 format_map;
1214 
1215 	format_map = 1 << conn_state->tv.mode;
1216 	memset(&format, 0, sizeof(format));
1217 	memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
1218 
1219 	BUILD_BUG_ON(sizeof(format) != 6);
1220 	return intel_sdvo_set_value(intel_sdvo,
1221 				    SDVO_CMD_SET_TV_FORMAT,
1222 				    &format, sizeof(format));
1223 }
1224 
1225 static bool
1226 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1227 					const struct drm_display_mode *mode)
1228 {
1229 	struct intel_sdvo_dtd output_dtd;
1230 
1231 	if (!intel_sdvo_set_target_output(intel_sdvo,
1232 					  intel_sdvo->attached_output))
1233 		return false;
1234 
1235 	intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1236 	if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1237 		return false;
1238 
1239 	return true;
1240 }
1241 
1242 /*
1243  * Asks the sdvo controller for the preferred input mode given the output mode.
1244  * Unfortunately we have to set up the full output mode to do that.
1245  */
1246 static bool
1247 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
1248 				    struct intel_sdvo_connector *intel_sdvo_connector,
1249 				    const struct drm_display_mode *mode,
1250 				    struct drm_display_mode *adjusted_mode)
1251 {
1252 	struct intel_sdvo_dtd input_dtd;
1253 
1254 	/* Reset the input timing to the screen. Assume always input 0. */
1255 	if (!intel_sdvo_set_target_input(intel_sdvo))
1256 		return false;
1257 
1258 	if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1259 						      intel_sdvo_connector,
1260 						      mode))
1261 		return false;
1262 
1263 	if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
1264 						   &input_dtd))
1265 		return false;
1266 
1267 	intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1268 	intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
1269 
1270 	return true;
1271 }
1272 
1273 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
1274 {
1275 	struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc->dev);
1276 	unsigned dotclock = pipe_config->port_clock;
1277 	struct dpll *clock = &pipe_config->dpll;
1278 
1279 	/*
1280 	 * SDVO TV has fixed PLL values depend on its clock range,
1281 	 * this mirrors vbios setting.
1282 	 */
1283 	if (dotclock >= 100000 && dotclock < 140500) {
1284 		clock->p1 = 2;
1285 		clock->p2 = 10;
1286 		clock->n = 3;
1287 		clock->m1 = 16;
1288 		clock->m2 = 8;
1289 	} else if (dotclock >= 140500 && dotclock <= 200000) {
1290 		clock->p1 = 1;
1291 		clock->p2 = 10;
1292 		clock->n = 6;
1293 		clock->m1 = 12;
1294 		clock->m2 = 8;
1295 	} else {
1296 		drm_WARN(&dev_priv->drm, 1,
1297 			 "SDVO TV clock out of range: %i\n", dotclock);
1298 	}
1299 
1300 	pipe_config->clock_set = true;
1301 }
1302 
1303 static bool intel_has_hdmi_sink(struct intel_sdvo_connector *intel_sdvo_connector,
1304 				const struct drm_connector_state *conn_state)
1305 {
1306 	struct drm_connector *connector = conn_state->connector;
1307 
1308 	return intel_sdvo_connector->is_hdmi &&
1309 		connector->display_info.is_hdmi &&
1310 		READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1311 }
1312 
1313 static bool intel_sdvo_limited_color_range(struct intel_encoder *encoder,
1314 					   const struct intel_crtc_state *crtc_state,
1315 					   const struct drm_connector_state *conn_state)
1316 {
1317 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1318 
1319 	if ((intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220) == 0)
1320 		return false;
1321 
1322 	return intel_hdmi_limited_color_range(crtc_state, conn_state);
1323 }
1324 
1325 static bool intel_sdvo_has_audio(struct intel_encoder *encoder,
1326 				 const struct intel_crtc_state *crtc_state,
1327 				 const struct drm_connector_state *conn_state)
1328 {
1329 	struct drm_connector *connector = conn_state->connector;
1330 	struct intel_sdvo_connector *intel_sdvo_connector =
1331 		to_intel_sdvo_connector(connector);
1332 	const struct intel_digital_connector_state *intel_conn_state =
1333 		to_intel_digital_connector_state(conn_state);
1334 
1335 	if (!crtc_state->has_hdmi_sink)
1336 		return false;
1337 
1338 	if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1339 		return intel_sdvo_connector->is_hdmi &&
1340 			connector->display_info.has_audio;
1341 	else
1342 		return intel_conn_state->force_audio == HDMI_AUDIO_ON;
1343 }
1344 
1345 static int intel_sdvo_compute_config(struct intel_encoder *encoder,
1346 				     struct intel_crtc_state *pipe_config,
1347 				     struct drm_connector_state *conn_state)
1348 {
1349 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1350 	struct intel_sdvo_connector *intel_sdvo_connector =
1351 		to_intel_sdvo_connector(conn_state->connector);
1352 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1353 	struct drm_display_mode *mode = &pipe_config->hw.mode;
1354 
1355 	DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1356 	pipe_config->pipe_bpp = 8*3;
1357 	pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
1358 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1359 
1360 	if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
1361 		pipe_config->has_pch_encoder = true;
1362 
1363 	/*
1364 	 * We need to construct preferred input timings based on our
1365 	 * output timings.  To do that, we have to set the output
1366 	 * timings, even though this isn't really the right place in
1367 	 * the sequence to do it. Oh well.
1368 	 */
1369 	if (IS_TV(intel_sdvo_connector)) {
1370 		if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1371 			return -EINVAL;
1372 
1373 		(void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1374 							   intel_sdvo_connector,
1375 							   mode,
1376 							   adjusted_mode);
1377 		pipe_config->sdvo_tv_clock = true;
1378 	} else if (IS_LVDS(intel_sdvo_connector)) {
1379 		const struct drm_display_mode *fixed_mode =
1380 			intel_panel_fixed_mode(&intel_sdvo_connector->base, mode);
1381 		int ret;
1382 
1383 		ret = intel_panel_compute_config(&intel_sdvo_connector->base,
1384 						 adjusted_mode);
1385 		if (ret)
1386 			return ret;
1387 
1388 		if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, fixed_mode))
1389 			return -EINVAL;
1390 
1391 		(void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1392 							   intel_sdvo_connector,
1393 							   mode,
1394 							   adjusted_mode);
1395 	}
1396 
1397 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1398 		return -EINVAL;
1399 
1400 	/*
1401 	 * Make the CRTC code factor in the SDVO pixel multiplier.  The
1402 	 * SDVO device will factor out the multiplier during mode_set.
1403 	 */
1404 	pipe_config->pixel_multiplier =
1405 		intel_sdvo_get_pixel_multiplier(adjusted_mode);
1406 
1407 	pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, conn_state);
1408 
1409 	pipe_config->has_audio =
1410 		intel_sdvo_has_audio(encoder, pipe_config, conn_state) &&
1411 		intel_audio_compute_config(encoder, pipe_config, conn_state);
1412 
1413 	pipe_config->limited_color_range =
1414 		intel_sdvo_limited_color_range(encoder, pipe_config,
1415 					       conn_state);
1416 
1417 	/* Clock computation needs to happen after pixel multiplier. */
1418 	if (IS_TV(intel_sdvo_connector))
1419 		i9xx_adjust_sdvo_tv_clock(pipe_config);
1420 
1421 	if (conn_state->picture_aspect_ratio)
1422 		adjusted_mode->picture_aspect_ratio =
1423 			conn_state->picture_aspect_ratio;
1424 
1425 	if (!intel_sdvo_compute_avi_infoframe(intel_sdvo,
1426 					      pipe_config, conn_state)) {
1427 		DRM_DEBUG_KMS("bad AVI infoframe\n");
1428 		return -EINVAL;
1429 	}
1430 
1431 	return 0;
1432 }
1433 
1434 #define UPDATE_PROPERTY(input, NAME) \
1435 	do { \
1436 		val = input; \
1437 		intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \
1438 	} while (0)
1439 
1440 static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo,
1441 				    const struct intel_sdvo_connector_state *sdvo_state)
1442 {
1443 	const struct drm_connector_state *conn_state = &sdvo_state->base.base;
1444 	struct intel_sdvo_connector *intel_sdvo_conn =
1445 		to_intel_sdvo_connector(conn_state->connector);
1446 	u16 val;
1447 
1448 	if (intel_sdvo_conn->left)
1449 		UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H);
1450 
1451 	if (intel_sdvo_conn->top)
1452 		UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V);
1453 
1454 	if (intel_sdvo_conn->hpos)
1455 		UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS);
1456 
1457 	if (intel_sdvo_conn->vpos)
1458 		UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS);
1459 
1460 	if (intel_sdvo_conn->saturation)
1461 		UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION);
1462 
1463 	if (intel_sdvo_conn->contrast)
1464 		UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST);
1465 
1466 	if (intel_sdvo_conn->hue)
1467 		UPDATE_PROPERTY(conn_state->tv.hue, HUE);
1468 
1469 	if (intel_sdvo_conn->brightness)
1470 		UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS);
1471 
1472 	if (intel_sdvo_conn->sharpness)
1473 		UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS);
1474 
1475 	if (intel_sdvo_conn->flicker_filter)
1476 		UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER);
1477 
1478 	if (intel_sdvo_conn->flicker_filter_2d)
1479 		UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D);
1480 
1481 	if (intel_sdvo_conn->flicker_filter_adaptive)
1482 		UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
1483 
1484 	if (intel_sdvo_conn->tv_chroma_filter)
1485 		UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER);
1486 
1487 	if (intel_sdvo_conn->tv_luma_filter)
1488 		UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER);
1489 
1490 	if (intel_sdvo_conn->dot_crawl)
1491 		UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL);
1492 
1493 #undef UPDATE_PROPERTY
1494 }
1495 
1496 static void intel_sdvo_pre_enable(struct intel_atomic_state *state,
1497 				  struct intel_encoder *intel_encoder,
1498 				  const struct intel_crtc_state *crtc_state,
1499 				  const struct drm_connector_state *conn_state)
1500 {
1501 	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
1502 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1503 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1504 	const struct intel_sdvo_connector_state *sdvo_state =
1505 		to_intel_sdvo_connector_state(conn_state);
1506 	struct intel_sdvo_connector *intel_sdvo_connector =
1507 		to_intel_sdvo_connector(conn_state->connector);
1508 	const struct drm_display_mode *mode = &crtc_state->hw.mode;
1509 	struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
1510 	u32 sdvox;
1511 	struct intel_sdvo_in_out_map in_out;
1512 	struct intel_sdvo_dtd input_dtd, output_dtd;
1513 	int rate;
1514 
1515 	intel_sdvo_update_props(intel_sdvo, sdvo_state);
1516 
1517 	/*
1518 	 * First, set the input mapping for the first input to our controlled
1519 	 * output. This is only correct if we're a single-input device, in
1520 	 * which case the first input is the output from the appropriate SDVO
1521 	 * channel on the motherboard.  In a two-input device, the first input
1522 	 * will be SDVOB and the second SDVOC.
1523 	 */
1524 	in_out.in0 = intel_sdvo->attached_output;
1525 	in_out.in1 = 0;
1526 
1527 	intel_sdvo_set_value(intel_sdvo,
1528 			     SDVO_CMD_SET_IN_OUT_MAP,
1529 			     &in_out, sizeof(in_out));
1530 
1531 	/* Set the output timings to the screen */
1532 	if (!intel_sdvo_set_target_output(intel_sdvo,
1533 					  intel_sdvo->attached_output))
1534 		return;
1535 
1536 	/* lvds has a special fixed output timing. */
1537 	if (IS_LVDS(intel_sdvo_connector)) {
1538 		const struct drm_display_mode *fixed_mode =
1539 			intel_panel_fixed_mode(&intel_sdvo_connector->base, mode);
1540 
1541 		intel_sdvo_get_dtd_from_mode(&output_dtd, fixed_mode);
1542 	} else {
1543 		intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1544 	}
1545 	if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1546 		drm_info(&dev_priv->drm,
1547 			 "Setting output timings on %s failed\n",
1548 			 SDVO_NAME(intel_sdvo));
1549 
1550 	/* Set the input timing to the screen. Assume always input 0. */
1551 	if (!intel_sdvo_set_target_input(intel_sdvo))
1552 		return;
1553 
1554 	if (crtc_state->has_hdmi_sink) {
1555 		intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1556 		intel_sdvo_set_colorimetry(intel_sdvo,
1557 					   crtc_state->limited_color_range ?
1558 					   SDVO_COLORIMETRY_RGB220 :
1559 					   SDVO_COLORIMETRY_RGB256);
1560 		intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state);
1561 		intel_sdvo_set_pixel_replication(intel_sdvo,
1562 						 !!(adjusted_mode->flags &
1563 						    DRM_MODE_FLAG_DBLCLK));
1564 	} else
1565 		intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
1566 
1567 	if (IS_TV(intel_sdvo_connector) &&
1568 	    !intel_sdvo_set_tv_format(intel_sdvo, conn_state))
1569 		return;
1570 
1571 	intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1572 
1573 	if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector))
1574 		input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
1575 	if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1576 		drm_info(&dev_priv->drm,
1577 			 "Setting input timings on %s failed\n",
1578 			 SDVO_NAME(intel_sdvo));
1579 
1580 	switch (crtc_state->pixel_multiplier) {
1581 	default:
1582 		drm_WARN(&dev_priv->drm, 1,
1583 			 "unknown pixel multiplier specified\n");
1584 		fallthrough;
1585 	case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1586 	case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1587 	case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
1588 	}
1589 	if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1590 		return;
1591 
1592 	/* Set the SDVO control regs. */
1593 	if (DISPLAY_VER(dev_priv) >= 4) {
1594 		/* The real mode polarity is set by the SDVO commands, using
1595 		 * struct intel_sdvo_dtd. */
1596 		sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
1597 		if (DISPLAY_VER(dev_priv) < 5)
1598 			sdvox |= SDVO_BORDER_ENABLE;
1599 	} else {
1600 		sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1601 		if (intel_sdvo->port == PORT_B)
1602 			sdvox &= SDVOB_PRESERVE_MASK;
1603 		else
1604 			sdvox &= SDVOC_PRESERVE_MASK;
1605 		sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1606 	}
1607 
1608 	if (HAS_PCH_CPT(dev_priv))
1609 		sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1610 	else
1611 		sdvox |= SDVO_PIPE_SEL(crtc->pipe);
1612 
1613 	if (DISPLAY_VER(dev_priv) >= 4) {
1614 		/* done in crtc_mode_set as the dpll_md reg must be written early */
1615 	} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
1616 		   IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
1617 		/* done in crtc_mode_set as it lives inside the dpll register */
1618 	} else {
1619 		sdvox |= (crtc_state->pixel_multiplier - 1)
1620 			<< SDVO_PORT_MULTIPLY_SHIFT;
1621 	}
1622 
1623 	if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1624 	    DISPLAY_VER(dev_priv) < 5)
1625 		sdvox |= SDVO_STALL_SELECT;
1626 	intel_sdvo_write_sdvox(intel_sdvo, sdvox);
1627 }
1628 
1629 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
1630 {
1631 	struct intel_sdvo_connector *intel_sdvo_connector =
1632 		to_intel_sdvo_connector(&connector->base);
1633 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1634 	u16 active_outputs = 0;
1635 
1636 	intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1637 
1638 	return active_outputs & intel_sdvo_connector->output_flag;
1639 }
1640 
1641 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
1642 			     i915_reg_t sdvo_reg, enum pipe *pipe)
1643 {
1644 	u32 val;
1645 
1646 	val = intel_de_read(dev_priv, sdvo_reg);
1647 
1648 	/* asserts want to know the pipe even if the port is disabled */
1649 	if (HAS_PCH_CPT(dev_priv))
1650 		*pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT;
1651 	else if (IS_CHERRYVIEW(dev_priv))
1652 		*pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV;
1653 	else
1654 		*pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT;
1655 
1656 	return val & SDVO_ENABLE;
1657 }
1658 
1659 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1660 				    enum pipe *pipe)
1661 {
1662 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1663 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1664 	u16 active_outputs = 0;
1665 	bool ret;
1666 
1667 	intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1668 
1669 	ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe);
1670 
1671 	return ret || active_outputs;
1672 }
1673 
1674 static void intel_sdvo_get_config(struct intel_encoder *encoder,
1675 				  struct intel_crtc_state *pipe_config)
1676 {
1677 	struct drm_device *dev = encoder->base.dev;
1678 	struct drm_i915_private *dev_priv = to_i915(dev);
1679 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1680 	struct intel_sdvo_dtd dtd;
1681 	int encoder_pixel_multiplier = 0;
1682 	int dotclock;
1683 	u32 flags = 0, sdvox;
1684 	u8 val;
1685 	bool ret;
1686 
1687 	pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO);
1688 
1689 	sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1690 
1691 	ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1692 	if (!ret) {
1693 		/*
1694 		 * Some sdvo encoders are not spec compliant and don't
1695 		 * implement the mandatory get_timings function.
1696 		 */
1697 		drm_dbg(&dev_priv->drm, "failed to retrieve SDVO DTD\n");
1698 		pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1699 	} else {
1700 		if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1701 			flags |= DRM_MODE_FLAG_PHSYNC;
1702 		else
1703 			flags |= DRM_MODE_FLAG_NHSYNC;
1704 
1705 		if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1706 			flags |= DRM_MODE_FLAG_PVSYNC;
1707 		else
1708 			flags |= DRM_MODE_FLAG_NVSYNC;
1709 	}
1710 
1711 	pipe_config->hw.adjusted_mode.flags |= flags;
1712 
1713 	/*
1714 	 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1715 	 * the sdvo port register, on all other platforms it is part of the dpll
1716 	 * state. Since the general pipe state readout happens before the
1717 	 * encoder->get_config we so already have a valid pixel multplier on all
1718 	 * other platfroms.
1719 	 */
1720 	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
1721 		pipe_config->pixel_multiplier =
1722 			((sdvox & SDVO_PORT_MULTIPLY_MASK)
1723 			 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1724 	}
1725 
1726 	dotclock = pipe_config->port_clock;
1727 
1728 	if (pipe_config->pixel_multiplier)
1729 		dotclock /= pipe_config->pixel_multiplier;
1730 
1731 	pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
1732 
1733 	/* Cross check the port pixel multiplier with the sdvo encoder state. */
1734 	if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1735 				 &val, 1)) {
1736 		switch (val) {
1737 		case SDVO_CLOCK_RATE_MULT_1X:
1738 			encoder_pixel_multiplier = 1;
1739 			break;
1740 		case SDVO_CLOCK_RATE_MULT_2X:
1741 			encoder_pixel_multiplier = 2;
1742 			break;
1743 		case SDVO_CLOCK_RATE_MULT_4X:
1744 			encoder_pixel_multiplier = 4;
1745 			break;
1746 		}
1747 	}
1748 
1749 	drm_WARN(dev,
1750 		 encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1751 		 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1752 		 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
1753 
1754 	if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY,
1755 				 &val, 1)) {
1756 		if (val == SDVO_COLORIMETRY_RGB220)
1757 			pipe_config->limited_color_range = true;
1758 	}
1759 
1760 	if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT,
1761 				 &val, 1)) {
1762 		if (val & SDVO_AUDIO_PRESENCE_DETECT)
1763 			pipe_config->has_audio = true;
1764 	}
1765 
1766 	if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1767 				 &val, 1)) {
1768 		if (val == SDVO_ENCODE_HDMI)
1769 			pipe_config->has_hdmi_sink = true;
1770 	}
1771 
1772 	intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config);
1773 
1774 	intel_sdvo_get_eld(intel_sdvo, pipe_config);
1775 }
1776 
1777 static void intel_sdvo_disable_audio(struct intel_sdvo *intel_sdvo)
1778 {
1779 	intel_sdvo_set_audio_state(intel_sdvo, 0);
1780 }
1781 
1782 static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo,
1783 				    const struct intel_crtc_state *crtc_state,
1784 				    const struct drm_connector_state *conn_state)
1785 {
1786 	const u8 *eld = crtc_state->eld;
1787 
1788 	intel_sdvo_set_audio_state(intel_sdvo, 0);
1789 
1790 	intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD,
1791 				   SDVO_HBUF_TX_DISABLED,
1792 				   eld, drm_eld_size(eld));
1793 
1794 	intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID |
1795 				   SDVO_AUDIO_PRESENCE_DETECT);
1796 }
1797 
1798 static void intel_disable_sdvo(struct intel_atomic_state *state,
1799 			       struct intel_encoder *encoder,
1800 			       const struct intel_crtc_state *old_crtc_state,
1801 			       const struct drm_connector_state *conn_state)
1802 {
1803 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1804 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1805 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1806 	u32 temp;
1807 
1808 	if (old_crtc_state->has_audio)
1809 		intel_sdvo_disable_audio(intel_sdvo);
1810 
1811 	intel_sdvo_set_active_outputs(intel_sdvo, 0);
1812 	if (0)
1813 		intel_sdvo_set_encoder_power_state(intel_sdvo,
1814 						   DRM_MODE_DPMS_OFF);
1815 
1816 	temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1817 
1818 	temp &= ~SDVO_ENABLE;
1819 	intel_sdvo_write_sdvox(intel_sdvo, temp);
1820 
1821 	/*
1822 	 * HW workaround for IBX, we need to move the port
1823 	 * to transcoder A after disabling it to allow the
1824 	 * matching DP port to be enabled on transcoder A.
1825 	 */
1826 	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1827 		/*
1828 		 * We get CPU/PCH FIFO underruns on the other pipe when
1829 		 * doing the workaround. Sweep them under the rug.
1830 		 */
1831 		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1832 		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1833 
1834 		temp &= ~SDVO_PIPE_SEL_MASK;
1835 		temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1836 		intel_sdvo_write_sdvox(intel_sdvo, temp);
1837 
1838 		temp &= ~SDVO_ENABLE;
1839 		intel_sdvo_write_sdvox(intel_sdvo, temp);
1840 
1841 		intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1842 		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1843 		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1844 	}
1845 }
1846 
1847 static void pch_disable_sdvo(struct intel_atomic_state *state,
1848 			     struct intel_encoder *encoder,
1849 			     const struct intel_crtc_state *old_crtc_state,
1850 			     const struct drm_connector_state *old_conn_state)
1851 {
1852 }
1853 
1854 static void pch_post_disable_sdvo(struct intel_atomic_state *state,
1855 				  struct intel_encoder *encoder,
1856 				  const struct intel_crtc_state *old_crtc_state,
1857 				  const struct drm_connector_state *old_conn_state)
1858 {
1859 	intel_disable_sdvo(state, encoder, old_crtc_state, old_conn_state);
1860 }
1861 
1862 static void intel_enable_sdvo(struct intel_atomic_state *state,
1863 			      struct intel_encoder *encoder,
1864 			      const struct intel_crtc_state *pipe_config,
1865 			      const struct drm_connector_state *conn_state)
1866 {
1867 	struct drm_device *dev = encoder->base.dev;
1868 	struct drm_i915_private *dev_priv = to_i915(dev);
1869 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1870 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1871 	u32 temp;
1872 	bool input1, input2;
1873 	int i;
1874 	bool success;
1875 
1876 	temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1877 	temp |= SDVO_ENABLE;
1878 	intel_sdvo_write_sdvox(intel_sdvo, temp);
1879 
1880 	for (i = 0; i < 2; i++)
1881 		intel_crtc_wait_for_next_vblank(crtc);
1882 
1883 	success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1884 	/*
1885 	 * Warn if the device reported failure to sync.
1886 	 *
1887 	 * A lot of SDVO devices fail to notify of sync, but it's
1888 	 * a given it the status is a success, we succeeded.
1889 	 */
1890 	if (success && !input1) {
1891 		drm_dbg_kms(&dev_priv->drm,
1892 			    "First %s output reported failure to "
1893 			    "sync\n", SDVO_NAME(intel_sdvo));
1894 	}
1895 
1896 	if (0)
1897 		intel_sdvo_set_encoder_power_state(intel_sdvo,
1898 						   DRM_MODE_DPMS_ON);
1899 	intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1900 
1901 	if (pipe_config->has_audio)
1902 		intel_sdvo_enable_audio(intel_sdvo, pipe_config, conn_state);
1903 }
1904 
1905 static enum drm_mode_status
1906 intel_sdvo_mode_valid(struct drm_connector *connector,
1907 		      struct drm_display_mode *mode)
1908 {
1909 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
1910 	struct intel_sdvo_connector *intel_sdvo_connector =
1911 		to_intel_sdvo_connector(connector);
1912 	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1913 	bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, connector->state);
1914 	int clock = mode->clock;
1915 
1916 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1917 		return MODE_NO_DBLESCAN;
1918 
1919 	if (clock > max_dotclk)
1920 		return MODE_CLOCK_HIGH;
1921 
1922 	if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1923 		if (!has_hdmi_sink)
1924 			return MODE_CLOCK_LOW;
1925 		clock *= 2;
1926 	}
1927 
1928 	if (intel_sdvo->pixel_clock_min > clock)
1929 		return MODE_CLOCK_LOW;
1930 
1931 	if (intel_sdvo->pixel_clock_max < clock)
1932 		return MODE_CLOCK_HIGH;
1933 
1934 	if (IS_LVDS(intel_sdvo_connector)) {
1935 		enum drm_mode_status status;
1936 
1937 		status = intel_panel_mode_valid(&intel_sdvo_connector->base, mode);
1938 		if (status != MODE_OK)
1939 			return status;
1940 	}
1941 
1942 	return MODE_OK;
1943 }
1944 
1945 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
1946 {
1947 	BUILD_BUG_ON(sizeof(*caps) != 8);
1948 	if (!intel_sdvo_get_value(intel_sdvo,
1949 				  SDVO_CMD_GET_DEVICE_CAPS,
1950 				  caps, sizeof(*caps)))
1951 		return false;
1952 
1953 	DRM_DEBUG_KMS("SDVO capabilities:\n"
1954 		      "  vendor_id: %d\n"
1955 		      "  device_id: %d\n"
1956 		      "  device_rev_id: %d\n"
1957 		      "  sdvo_version_major: %d\n"
1958 		      "  sdvo_version_minor: %d\n"
1959 		      "  sdvo_inputs_mask: %d\n"
1960 		      "  smooth_scaling: %d\n"
1961 		      "  sharp_scaling: %d\n"
1962 		      "  up_scaling: %d\n"
1963 		      "  down_scaling: %d\n"
1964 		      "  stall_support: %d\n"
1965 		      "  output_flags: %d\n",
1966 		      caps->vendor_id,
1967 		      caps->device_id,
1968 		      caps->device_rev_id,
1969 		      caps->sdvo_version_major,
1970 		      caps->sdvo_version_minor,
1971 		      caps->sdvo_inputs_mask,
1972 		      caps->smooth_scaling,
1973 		      caps->sharp_scaling,
1974 		      caps->up_scaling,
1975 		      caps->down_scaling,
1976 		      caps->stall_support,
1977 		      caps->output_flags);
1978 
1979 	return true;
1980 }
1981 
1982 static u8 intel_sdvo_get_colorimetry_cap(struct intel_sdvo *intel_sdvo)
1983 {
1984 	u8 cap;
1985 
1986 	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY_CAP,
1987 				  &cap, sizeof(cap)))
1988 		return SDVO_COLORIMETRY_RGB256;
1989 
1990 	return cap;
1991 }
1992 
1993 static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
1994 {
1995 	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
1996 	u16 hotplug;
1997 
1998 	if (!I915_HAS_HOTPLUG(dev_priv))
1999 		return 0;
2000 
2001 	/*
2002 	 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
2003 	 * on the line.
2004 	 */
2005 	if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
2006 		return 0;
2007 
2008 	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
2009 					&hotplug, sizeof(hotplug)))
2010 		return 0;
2011 
2012 	return hotplug;
2013 }
2014 
2015 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
2016 {
2017 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2018 
2019 	intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
2020 			     &intel_sdvo->hotplug_active, 2);
2021 }
2022 
2023 static enum intel_hotplug_state
2024 intel_sdvo_hotplug(struct intel_encoder *encoder,
2025 		   struct intel_connector *connector)
2026 {
2027 	intel_sdvo_enable_hotplug(encoder);
2028 
2029 	return intel_encoder_hotplug(encoder, connector);
2030 }
2031 
2032 static bool
2033 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
2034 {
2035 	/* Is there more than one type of output? */
2036 	return hweight16(intel_sdvo->caps.output_flags) > 1;
2037 }
2038 
2039 static const struct drm_edid *
2040 intel_sdvo_get_edid(struct drm_connector *connector)
2041 {
2042 	struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector));
2043 	return drm_edid_read_ddc(connector, &sdvo->ddc);
2044 }
2045 
2046 /* Mac mini hack -- use the same DDC as the analog connector */
2047 static const struct drm_edid *
2048 intel_sdvo_get_analog_edid(struct drm_connector *connector)
2049 {
2050 	struct drm_i915_private *i915 = to_i915(connector->dev);
2051 	struct i2c_adapter *i2c;
2052 
2053 	i2c = intel_gmbus_get_adapter(i915, i915->display.vbt.crt_ddc_pin);
2054 
2055 	return drm_edid_read_ddc(connector, i2c);
2056 }
2057 
2058 static enum drm_connector_status
2059 intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
2060 {
2061 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
2062 	enum drm_connector_status status;
2063 	const struct drm_edid *drm_edid;
2064 
2065 	drm_edid = intel_sdvo_get_edid(connector);
2066 
2067 	if (!drm_edid && intel_sdvo_multifunc_encoder(intel_sdvo)) {
2068 		u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
2069 
2070 		/*
2071 		 * Don't use the 1 as the argument of DDC bus switch to get
2072 		 * the EDID. It is used for SDVO SPD ROM.
2073 		 */
2074 		for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
2075 			intel_sdvo->ddc_bus = ddc;
2076 			drm_edid = intel_sdvo_get_edid(connector);
2077 			if (drm_edid)
2078 				break;
2079 		}
2080 		/*
2081 		 * If we found the EDID on the other bus,
2082 		 * assume that is the correct DDC bus.
2083 		 */
2084 		if (!drm_edid)
2085 			intel_sdvo->ddc_bus = saved_ddc;
2086 	}
2087 
2088 	/*
2089 	 * When there is no edid and no monitor is connected with VGA
2090 	 * port, try to use the CRT ddc to read the EDID for DVI-connector.
2091 	 */
2092 	if (!drm_edid)
2093 		drm_edid = intel_sdvo_get_analog_edid(connector);
2094 
2095 	status = connector_status_unknown;
2096 	if (drm_edid) {
2097 		const struct edid *edid = drm_edid_raw(drm_edid);
2098 
2099 		/* DDC bus is shared, match EDID to connector type */
2100 		if (edid->input & DRM_EDID_INPUT_DIGITAL)
2101 			status = connector_status_connected;
2102 		else
2103 			status = connector_status_disconnected;
2104 		drm_edid_free(drm_edid);
2105 	}
2106 
2107 	return status;
2108 }
2109 
2110 static bool
2111 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
2112 				  const struct drm_edid *drm_edid)
2113 {
2114 	const struct edid *edid = drm_edid_raw(drm_edid);
2115 	bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
2116 	bool connector_is_digital = !!IS_DIGITAL(sdvo);
2117 
2118 	DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
2119 		      connector_is_digital, monitor_is_digital);
2120 	return connector_is_digital == monitor_is_digital;
2121 }
2122 
2123 static enum drm_connector_status
2124 intel_sdvo_detect(struct drm_connector *connector, bool force)
2125 {
2126 	struct drm_i915_private *i915 = to_i915(connector->dev);
2127 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
2128 	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2129 	enum drm_connector_status ret;
2130 	u16 response;
2131 
2132 	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2133 		      connector->base.id, connector->name);
2134 
2135 	if (!INTEL_DISPLAY_ENABLED(i915))
2136 		return connector_status_disconnected;
2137 
2138 	if (!intel_sdvo_get_value(intel_sdvo,
2139 				  SDVO_CMD_GET_ATTACHED_DISPLAYS,
2140 				  &response, 2))
2141 		return connector_status_unknown;
2142 
2143 	DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
2144 		      response & 0xff, response >> 8,
2145 		      intel_sdvo_connector->output_flag);
2146 
2147 	if (response == 0)
2148 		return connector_status_disconnected;
2149 
2150 	intel_sdvo->attached_output = response;
2151 
2152 	if ((intel_sdvo_connector->output_flag & response) == 0)
2153 		ret = connector_status_disconnected;
2154 	else if (IS_TMDS(intel_sdvo_connector))
2155 		ret = intel_sdvo_tmds_sink_detect(connector);
2156 	else {
2157 		const struct drm_edid *drm_edid;
2158 
2159 		/* if we have an edid check it matches the connection */
2160 		drm_edid = intel_sdvo_get_edid(connector);
2161 		if (!drm_edid)
2162 			drm_edid = intel_sdvo_get_analog_edid(connector);
2163 		if (drm_edid) {
2164 			if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
2165 							      drm_edid))
2166 				ret = connector_status_connected;
2167 			else
2168 				ret = connector_status_disconnected;
2169 
2170 			drm_edid_free(drm_edid);
2171 		} else {
2172 			ret = connector_status_connected;
2173 		}
2174 	}
2175 
2176 	return ret;
2177 }
2178 
2179 static int intel_sdvo_get_ddc_modes(struct drm_connector *connector)
2180 {
2181 	int num_modes = 0;
2182 	const struct drm_edid *drm_edid;
2183 
2184 	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2185 		      connector->base.id, connector->name);
2186 
2187 	/* set the bus switch and get the modes */
2188 	drm_edid = intel_sdvo_get_edid(connector);
2189 
2190 	/*
2191 	 * Mac mini hack.  On this device, the DVI-I connector shares one DDC
2192 	 * link between analog and digital outputs. So, if the regular SDVO
2193 	 * DDC fails, check to see if the analog output is disconnected, in
2194 	 * which case we'll look there for the digital DDC data.
2195 	 */
2196 	if (!drm_edid)
2197 		drm_edid = intel_sdvo_get_analog_edid(connector);
2198 
2199 	if (!drm_edid)
2200 		return 0;
2201 
2202 	if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
2203 					      drm_edid))
2204 		num_modes += intel_connector_update_modes(connector, drm_edid);
2205 
2206 	drm_edid_free(drm_edid);
2207 
2208 	return num_modes;
2209 }
2210 
2211 /*
2212  * Set of SDVO TV modes.
2213  * Note!  This is in reply order (see loop in get_tv_modes).
2214  * XXX: all 60Hz refresh?
2215  */
2216 static const struct drm_display_mode sdvo_tv_modes[] = {
2217 	{ DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
2218 		   416, 0, 200, 201, 232, 233, 0,
2219 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2220 	{ DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
2221 		   416, 0, 240, 241, 272, 273, 0,
2222 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2223 	{ DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
2224 		   496, 0, 300, 301, 332, 333, 0,
2225 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2226 	{ DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
2227 		   736, 0, 350, 351, 382, 383, 0,
2228 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2229 	{ DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
2230 		   736, 0, 400, 401, 432, 433, 0,
2231 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2232 	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
2233 		   736, 0, 480, 481, 512, 513, 0,
2234 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2235 	{ DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
2236 		   800, 0, 480, 481, 512, 513, 0,
2237 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2238 	{ DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
2239 		   800, 0, 576, 577, 608, 609, 0,
2240 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2241 	{ DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
2242 		   816, 0, 350, 351, 382, 383, 0,
2243 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2244 	{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
2245 		   816, 0, 400, 401, 432, 433, 0,
2246 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2247 	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
2248 		   816, 0, 480, 481, 512, 513, 0,
2249 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2250 	{ DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
2251 		   816, 0, 540, 541, 572, 573, 0,
2252 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2253 	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
2254 		   816, 0, 576, 577, 608, 609, 0,
2255 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2256 	{ DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
2257 		   864, 0, 576, 577, 608, 609, 0,
2258 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2259 	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
2260 		   896, 0, 600, 601, 632, 633, 0,
2261 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2262 	{ DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
2263 		   928, 0, 624, 625, 656, 657, 0,
2264 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2265 	{ DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
2266 		   1016, 0, 766, 767, 798, 799, 0,
2267 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2268 	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
2269 		   1120, 0, 768, 769, 800, 801, 0,
2270 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2271 	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
2272 		   1376, 0, 1024, 1025, 1056, 1057, 0,
2273 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2274 };
2275 
2276 static int intel_sdvo_get_tv_modes(struct drm_connector *connector)
2277 {
2278 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
2279 	const struct drm_connector_state *conn_state = connector->state;
2280 	struct intel_sdvo_sdtv_resolution_request tv_res;
2281 	u32 reply = 0, format_map = 0;
2282 	int num_modes = 0;
2283 	int i;
2284 
2285 	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2286 		      connector->base.id, connector->name);
2287 
2288 	/*
2289 	 * Read the list of supported input resolutions for the selected TV
2290 	 * format.
2291 	 */
2292 	format_map = 1 << conn_state->tv.mode;
2293 	memcpy(&tv_res, &format_map,
2294 	       min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
2295 
2296 	if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
2297 		return 0;
2298 
2299 	BUILD_BUG_ON(sizeof(tv_res) != 3);
2300 	if (!intel_sdvo_write_cmd(intel_sdvo,
2301 				  SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
2302 				  &tv_res, sizeof(tv_res)))
2303 		return 0;
2304 	if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
2305 		return 0;
2306 
2307 	for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) {
2308 		if (reply & (1 << i)) {
2309 			struct drm_display_mode *nmode;
2310 			nmode = drm_mode_duplicate(connector->dev,
2311 						   &sdvo_tv_modes[i]);
2312 			if (nmode) {
2313 				drm_mode_probed_add(connector, nmode);
2314 				num_modes++;
2315 			}
2316 		}
2317 	}
2318 
2319 	return num_modes;
2320 }
2321 
2322 static int intel_sdvo_get_lvds_modes(struct drm_connector *connector)
2323 {
2324 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2325 
2326 	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2327 		    connector->base.id, connector->name);
2328 
2329 	return intel_panel_get_modes(to_intel_connector(connector));
2330 }
2331 
2332 static int intel_sdvo_get_modes(struct drm_connector *connector)
2333 {
2334 	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2335 
2336 	if (IS_TV(intel_sdvo_connector))
2337 		return intel_sdvo_get_tv_modes(connector);
2338 	else if (IS_LVDS(intel_sdvo_connector))
2339 		return intel_sdvo_get_lvds_modes(connector);
2340 	else
2341 		return intel_sdvo_get_ddc_modes(connector);
2342 }
2343 
2344 static int
2345 intel_sdvo_connector_atomic_get_property(struct drm_connector *connector,
2346 					 const struct drm_connector_state *state,
2347 					 struct drm_property *property,
2348 					 u64 *val)
2349 {
2350 	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2351 	const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state);
2352 
2353 	if (property == intel_sdvo_connector->tv_format) {
2354 		int i;
2355 
2356 		for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2357 			if (state->tv.mode == intel_sdvo_connector->tv_format_supported[i]) {
2358 				*val = i;
2359 
2360 				return 0;
2361 			}
2362 
2363 		drm_WARN_ON(connector->dev, 1);
2364 		*val = 0;
2365 	} else if (property == intel_sdvo_connector->top ||
2366 		   property == intel_sdvo_connector->bottom)
2367 		*val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v;
2368 	else if (property == intel_sdvo_connector->left ||
2369 		 property == intel_sdvo_connector->right)
2370 		*val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h;
2371 	else if (property == intel_sdvo_connector->hpos)
2372 		*val = sdvo_state->tv.hpos;
2373 	else if (property == intel_sdvo_connector->vpos)
2374 		*val = sdvo_state->tv.vpos;
2375 	else if (property == intel_sdvo_connector->saturation)
2376 		*val = state->tv.saturation;
2377 	else if (property == intel_sdvo_connector->contrast)
2378 		*val = state->tv.contrast;
2379 	else if (property == intel_sdvo_connector->hue)
2380 		*val = state->tv.hue;
2381 	else if (property == intel_sdvo_connector->brightness)
2382 		*val = state->tv.brightness;
2383 	else if (property == intel_sdvo_connector->sharpness)
2384 		*val = sdvo_state->tv.sharpness;
2385 	else if (property == intel_sdvo_connector->flicker_filter)
2386 		*val = sdvo_state->tv.flicker_filter;
2387 	else if (property == intel_sdvo_connector->flicker_filter_2d)
2388 		*val = sdvo_state->tv.flicker_filter_2d;
2389 	else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2390 		*val = sdvo_state->tv.flicker_filter_adaptive;
2391 	else if (property == intel_sdvo_connector->tv_chroma_filter)
2392 		*val = sdvo_state->tv.chroma_filter;
2393 	else if (property == intel_sdvo_connector->tv_luma_filter)
2394 		*val = sdvo_state->tv.luma_filter;
2395 	else if (property == intel_sdvo_connector->dot_crawl)
2396 		*val = sdvo_state->tv.dot_crawl;
2397 	else
2398 		return intel_digital_connector_atomic_get_property(connector, state, property, val);
2399 
2400 	return 0;
2401 }
2402 
2403 static int
2404 intel_sdvo_connector_atomic_set_property(struct drm_connector *connector,
2405 					 struct drm_connector_state *state,
2406 					 struct drm_property *property,
2407 					 u64 val)
2408 {
2409 	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2410 	struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state);
2411 
2412 	if (property == intel_sdvo_connector->tv_format) {
2413 		state->tv.mode = intel_sdvo_connector->tv_format_supported[val];
2414 
2415 		if (state->crtc) {
2416 			struct drm_crtc_state *crtc_state =
2417 				drm_atomic_get_new_crtc_state(state->state, state->crtc);
2418 
2419 			crtc_state->connectors_changed = true;
2420 		}
2421 	} else if (property == intel_sdvo_connector->top ||
2422 		   property == intel_sdvo_connector->bottom)
2423 		/* Cannot set these independent from each other */
2424 		sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val;
2425 	else if (property == intel_sdvo_connector->left ||
2426 		 property == intel_sdvo_connector->right)
2427 		/* Cannot set these independent from each other */
2428 		sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val;
2429 	else if (property == intel_sdvo_connector->hpos)
2430 		sdvo_state->tv.hpos = val;
2431 	else if (property == intel_sdvo_connector->vpos)
2432 		sdvo_state->tv.vpos = val;
2433 	else if (property == intel_sdvo_connector->saturation)
2434 		state->tv.saturation = val;
2435 	else if (property == intel_sdvo_connector->contrast)
2436 		state->tv.contrast = val;
2437 	else if (property == intel_sdvo_connector->hue)
2438 		state->tv.hue = val;
2439 	else if (property == intel_sdvo_connector->brightness)
2440 		state->tv.brightness = val;
2441 	else if (property == intel_sdvo_connector->sharpness)
2442 		sdvo_state->tv.sharpness = val;
2443 	else if (property == intel_sdvo_connector->flicker_filter)
2444 		sdvo_state->tv.flicker_filter = val;
2445 	else if (property == intel_sdvo_connector->flicker_filter_2d)
2446 		sdvo_state->tv.flicker_filter_2d = val;
2447 	else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2448 		sdvo_state->tv.flicker_filter_adaptive = val;
2449 	else if (property == intel_sdvo_connector->tv_chroma_filter)
2450 		sdvo_state->tv.chroma_filter = val;
2451 	else if (property == intel_sdvo_connector->tv_luma_filter)
2452 		sdvo_state->tv.luma_filter = val;
2453 	else if (property == intel_sdvo_connector->dot_crawl)
2454 		sdvo_state->tv.dot_crawl = val;
2455 	else
2456 		return intel_digital_connector_atomic_set_property(connector, state, property, val);
2457 
2458 	return 0;
2459 }
2460 
2461 static int
2462 intel_sdvo_connector_register(struct drm_connector *connector)
2463 {
2464 	struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector));
2465 	int ret;
2466 
2467 	ret = intel_connector_register(connector);
2468 	if (ret)
2469 		return ret;
2470 
2471 	return sysfs_create_link(&connector->kdev->kobj,
2472 				 &sdvo->ddc.dev.kobj,
2473 				 sdvo->ddc.dev.kobj.name);
2474 }
2475 
2476 static void
2477 intel_sdvo_connector_unregister(struct drm_connector *connector)
2478 {
2479 	struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector));
2480 
2481 	sysfs_remove_link(&connector->kdev->kobj,
2482 			  sdvo->ddc.dev.kobj.name);
2483 	intel_connector_unregister(connector);
2484 }
2485 
2486 static struct drm_connector_state *
2487 intel_sdvo_connector_duplicate_state(struct drm_connector *connector)
2488 {
2489 	struct intel_sdvo_connector_state *state;
2490 
2491 	state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
2492 	if (!state)
2493 		return NULL;
2494 
2495 	__drm_atomic_helper_connector_duplicate_state(connector, &state->base.base);
2496 	return &state->base.base;
2497 }
2498 
2499 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2500 	.detect = intel_sdvo_detect,
2501 	.fill_modes = drm_helper_probe_single_connector_modes,
2502 	.atomic_get_property = intel_sdvo_connector_atomic_get_property,
2503 	.atomic_set_property = intel_sdvo_connector_atomic_set_property,
2504 	.late_register = intel_sdvo_connector_register,
2505 	.early_unregister = intel_sdvo_connector_unregister,
2506 	.destroy = intel_connector_destroy,
2507 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2508 	.atomic_duplicate_state = intel_sdvo_connector_duplicate_state,
2509 };
2510 
2511 static int intel_sdvo_atomic_check(struct drm_connector *conn,
2512 				   struct drm_atomic_state *state)
2513 {
2514 	struct drm_connector_state *new_conn_state =
2515 		drm_atomic_get_new_connector_state(state, conn);
2516 	struct drm_connector_state *old_conn_state =
2517 		drm_atomic_get_old_connector_state(state, conn);
2518 	struct intel_sdvo_connector_state *old_state =
2519 		to_intel_sdvo_connector_state(old_conn_state);
2520 	struct intel_sdvo_connector_state *new_state =
2521 		to_intel_sdvo_connector_state(new_conn_state);
2522 
2523 	if (new_conn_state->crtc &&
2524 	    (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) ||
2525 	     memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) {
2526 		struct drm_crtc_state *crtc_state =
2527 			drm_atomic_get_new_crtc_state(state,
2528 						      new_conn_state->crtc);
2529 
2530 		crtc_state->connectors_changed = true;
2531 	}
2532 
2533 	return intel_digital_connector_atomic_check(conn, state);
2534 }
2535 
2536 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2537 	.get_modes = intel_sdvo_get_modes,
2538 	.mode_valid = intel_sdvo_mode_valid,
2539 	.atomic_check = intel_sdvo_atomic_check,
2540 };
2541 
2542 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
2543 {
2544 	struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
2545 
2546 	i2c_del_adapter(&intel_sdvo->ddc);
2547 	intel_encoder_destroy(encoder);
2548 }
2549 
2550 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2551 	.destroy = intel_sdvo_enc_destroy,
2552 };
2553 
2554 static void
2555 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2556 {
2557 	u16 mask = 0;
2558 	unsigned int num_bits;
2559 
2560 	/*
2561 	 * Make a mask of outputs less than or equal to our own priority in the
2562 	 * list.
2563 	 */
2564 	switch (sdvo->controlled_output) {
2565 	case SDVO_OUTPUT_LVDS1:
2566 		mask |= SDVO_OUTPUT_LVDS1;
2567 		fallthrough;
2568 	case SDVO_OUTPUT_LVDS0:
2569 		mask |= SDVO_OUTPUT_LVDS0;
2570 		fallthrough;
2571 	case SDVO_OUTPUT_TMDS1:
2572 		mask |= SDVO_OUTPUT_TMDS1;
2573 		fallthrough;
2574 	case SDVO_OUTPUT_TMDS0:
2575 		mask |= SDVO_OUTPUT_TMDS0;
2576 		fallthrough;
2577 	case SDVO_OUTPUT_RGB1:
2578 		mask |= SDVO_OUTPUT_RGB1;
2579 		fallthrough;
2580 	case SDVO_OUTPUT_RGB0:
2581 		mask |= SDVO_OUTPUT_RGB0;
2582 		break;
2583 	}
2584 
2585 	/* Count bits to find what number we are in the priority list. */
2586 	mask &= sdvo->caps.output_flags;
2587 	num_bits = hweight16(mask);
2588 	/* If more than 3 outputs, default to DDC bus 3 for now. */
2589 	if (num_bits > 3)
2590 		num_bits = 3;
2591 
2592 	/* Corresponds to SDVO_CONTROL_BUS_DDCx */
2593 	sdvo->ddc_bus = 1 << num_bits;
2594 }
2595 
2596 /*
2597  * Choose the appropriate DDC bus for control bus switch command for this
2598  * SDVO output based on the controlled output.
2599  *
2600  * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2601  * outputs, then LVDS outputs.
2602  */
2603 static void
2604 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
2605 			  struct intel_sdvo *sdvo)
2606 {
2607 	struct sdvo_device_mapping *mapping;
2608 
2609 	if (sdvo->port == PORT_B)
2610 		mapping = &dev_priv->display.vbt.sdvo_mappings[0];
2611 	else
2612 		mapping = &dev_priv->display.vbt.sdvo_mappings[1];
2613 
2614 	if (mapping->initialized)
2615 		sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2616 	else
2617 		intel_sdvo_guess_ddc_bus(sdvo);
2618 }
2619 
2620 static void
2621 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2622 			  struct intel_sdvo *sdvo)
2623 {
2624 	struct sdvo_device_mapping *mapping;
2625 	u8 pin;
2626 
2627 	if (sdvo->port == PORT_B)
2628 		mapping = &dev_priv->display.vbt.sdvo_mappings[0];
2629 	else
2630 		mapping = &dev_priv->display.vbt.sdvo_mappings[1];
2631 
2632 	if (mapping->initialized &&
2633 	    intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
2634 		pin = mapping->i2c_pin;
2635 	else
2636 		pin = GMBUS_PIN_DPB;
2637 
2638 	sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2639 
2640 	/*
2641 	 * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2642 	 * our code totally fails once we start using gmbus. Hence fall back to
2643 	 * bit banging for now.
2644 	 */
2645 	intel_gmbus_force_bit(sdvo->i2c, true);
2646 }
2647 
2648 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2649 static void
2650 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2651 {
2652 	intel_gmbus_force_bit(sdvo->i2c, false);
2653 }
2654 
2655 static bool
2656 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo)
2657 {
2658 	return intel_sdvo_check_supp_encode(intel_sdvo);
2659 }
2660 
2661 static u8
2662 intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv,
2663 			  struct intel_sdvo *sdvo)
2664 {
2665 	struct sdvo_device_mapping *my_mapping, *other_mapping;
2666 
2667 	if (sdvo->port == PORT_B) {
2668 		my_mapping = &dev_priv->display.vbt.sdvo_mappings[0];
2669 		other_mapping = &dev_priv->display.vbt.sdvo_mappings[1];
2670 	} else {
2671 		my_mapping = &dev_priv->display.vbt.sdvo_mappings[1];
2672 		other_mapping = &dev_priv->display.vbt.sdvo_mappings[0];
2673 	}
2674 
2675 	/* If the BIOS described our SDVO device, take advantage of it. */
2676 	if (my_mapping->slave_addr)
2677 		return my_mapping->slave_addr;
2678 
2679 	/*
2680 	 * If the BIOS only described a different SDVO device, use the
2681 	 * address that it isn't using.
2682 	 */
2683 	if (other_mapping->slave_addr) {
2684 		if (other_mapping->slave_addr == 0x70)
2685 			return 0x72;
2686 		else
2687 			return 0x70;
2688 	}
2689 
2690 	/*
2691 	 * No SDVO device info is found for another DVO port,
2692 	 * so use mapping assumption we had before BIOS parsing.
2693 	 */
2694 	if (sdvo->port == PORT_B)
2695 		return 0x70;
2696 	else
2697 		return 0x72;
2698 }
2699 
2700 static int
2701 intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2702 			  struct intel_sdvo *encoder)
2703 {
2704 	struct drm_connector *drm_connector;
2705 	int ret;
2706 
2707 	drm_connector = &connector->base.base;
2708 	ret = drm_connector_init(encoder->base.base.dev,
2709 			   drm_connector,
2710 			   &intel_sdvo_connector_funcs,
2711 			   connector->base.base.connector_type);
2712 	if (ret < 0)
2713 		return ret;
2714 
2715 	drm_connector_helper_add(drm_connector,
2716 				 &intel_sdvo_connector_helper_funcs);
2717 
2718 	connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
2719 	connector->base.base.interlace_allowed = true;
2720 	connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
2721 
2722 	intel_connector_attach_encoder(&connector->base, &encoder->base);
2723 
2724 	return 0;
2725 }
2726 
2727 static void
2728 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2729 			       struct intel_sdvo_connector *connector)
2730 {
2731 	intel_attach_force_audio_property(&connector->base.base);
2732 	if (intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220)
2733 		intel_attach_broadcast_rgb_property(&connector->base.base);
2734 	intel_attach_aspect_ratio_property(&connector->base.base);
2735 }
2736 
2737 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
2738 {
2739 	struct intel_sdvo_connector *sdvo_connector;
2740 	struct intel_sdvo_connector_state *conn_state;
2741 
2742 	sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL);
2743 	if (!sdvo_connector)
2744 		return NULL;
2745 
2746 	conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
2747 	if (!conn_state) {
2748 		kfree(sdvo_connector);
2749 		return NULL;
2750 	}
2751 
2752 	__drm_atomic_helper_connector_reset(&sdvo_connector->base.base,
2753 					    &conn_state->base.base);
2754 
2755 	INIT_LIST_HEAD(&sdvo_connector->base.panel.fixed_modes);
2756 
2757 	return sdvo_connector;
2758 }
2759 
2760 static bool
2761 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, u16 type)
2762 {
2763 	struct drm_encoder *encoder = &intel_sdvo->base.base;
2764 	struct drm_connector *connector;
2765 	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2766 	struct intel_connector *intel_connector;
2767 	struct intel_sdvo_connector *intel_sdvo_connector;
2768 
2769 	DRM_DEBUG_KMS("initialising DVI type 0x%x\n", type);
2770 
2771 	intel_sdvo_connector = intel_sdvo_connector_alloc();
2772 	if (!intel_sdvo_connector)
2773 		return false;
2774 
2775 	intel_sdvo_connector->output_flag = type;
2776 
2777 	intel_connector = &intel_sdvo_connector->base;
2778 	connector = &intel_connector->base;
2779 	if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2780 		intel_sdvo_connector->output_flag) {
2781 		intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
2782 		/*
2783 		 * Some SDVO devices have one-shot hotplug interrupts.
2784 		 * Ensure that they get re-enabled when an interrupt happens.
2785 		 */
2786 		intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
2787 		intel_encoder->hotplug = intel_sdvo_hotplug;
2788 		intel_sdvo_enable_hotplug(intel_encoder);
2789 	} else {
2790 		intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
2791 	}
2792 	encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2793 	connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2794 
2795 	if (intel_sdvo_is_hdmi_connector(intel_sdvo)) {
2796 		connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2797 		intel_sdvo_connector->is_hdmi = true;
2798 	}
2799 
2800 	if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2801 		kfree(intel_sdvo_connector);
2802 		return false;
2803 	}
2804 
2805 	if (intel_sdvo_connector->is_hdmi)
2806 		intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
2807 
2808 	return true;
2809 }
2810 
2811 static bool
2812 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, u16 type)
2813 {
2814 	struct drm_encoder *encoder = &intel_sdvo->base.base;
2815 	struct drm_connector *connector;
2816 	struct intel_connector *intel_connector;
2817 	struct intel_sdvo_connector *intel_sdvo_connector;
2818 
2819 	DRM_DEBUG_KMS("initialising TV type 0x%x\n", type);
2820 
2821 	intel_sdvo_connector = intel_sdvo_connector_alloc();
2822 	if (!intel_sdvo_connector)
2823 		return false;
2824 
2825 	intel_connector = &intel_sdvo_connector->base;
2826 	connector = &intel_connector->base;
2827 	encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2828 	connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2829 
2830 	intel_sdvo_connector->output_flag = type;
2831 
2832 	if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2833 		kfree(intel_sdvo_connector);
2834 		return false;
2835 	}
2836 
2837 	if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2838 		goto err;
2839 
2840 	if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2841 		goto err;
2842 
2843 	return true;
2844 
2845 err:
2846 	intel_connector_destroy(connector);
2847 	return false;
2848 }
2849 
2850 static bool
2851 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, u16 type)
2852 {
2853 	struct drm_encoder *encoder = &intel_sdvo->base.base;
2854 	struct drm_connector *connector;
2855 	struct intel_connector *intel_connector;
2856 	struct intel_sdvo_connector *intel_sdvo_connector;
2857 
2858 	DRM_DEBUG_KMS("initialising analog type 0x%x\n", type);
2859 
2860 	intel_sdvo_connector = intel_sdvo_connector_alloc();
2861 	if (!intel_sdvo_connector)
2862 		return false;
2863 
2864 	intel_connector = &intel_sdvo_connector->base;
2865 	connector = &intel_connector->base;
2866 	intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2867 	encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2868 	connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2869 
2870 	intel_sdvo_connector->output_flag = type;
2871 
2872 	if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2873 		kfree(intel_sdvo_connector);
2874 		return false;
2875 	}
2876 
2877 	return true;
2878 }
2879 
2880 static bool
2881 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, u16 type)
2882 {
2883 	struct drm_encoder *encoder = &intel_sdvo->base.base;
2884 	struct drm_i915_private *i915 = to_i915(encoder->dev);
2885 	struct drm_connector *connector;
2886 	struct intel_connector *intel_connector;
2887 	struct intel_sdvo_connector *intel_sdvo_connector;
2888 
2889 	DRM_DEBUG_KMS("initialising LVDS type 0x%x\n", type);
2890 
2891 	intel_sdvo_connector = intel_sdvo_connector_alloc();
2892 	if (!intel_sdvo_connector)
2893 		return false;
2894 
2895 	intel_connector = &intel_sdvo_connector->base;
2896 	connector = &intel_connector->base;
2897 	encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2898 	connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2899 
2900 	intel_sdvo_connector->output_flag = type;
2901 
2902 	if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2903 		kfree(intel_sdvo_connector);
2904 		return false;
2905 	}
2906 
2907 	if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2908 		goto err;
2909 
2910 	intel_bios_init_panel_late(i915, &intel_connector->panel, NULL, NULL);
2911 
2912 	/*
2913 	 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
2914 	 * SDVO->LVDS transcoders can't cope with the EDID mode.
2915 	 */
2916 	intel_panel_add_vbt_sdvo_fixed_mode(intel_connector);
2917 
2918 	if (!intel_panel_preferred_fixed_mode(intel_connector)) {
2919 		mutex_lock(&i915->drm.mode_config.mutex);
2920 
2921 		intel_ddc_get_modes(connector, &intel_sdvo->ddc);
2922 		intel_panel_add_edid_fixed_modes(intel_connector, false);
2923 
2924 		mutex_unlock(&i915->drm.mode_config.mutex);
2925 	}
2926 
2927 	intel_panel_init(intel_connector, NULL);
2928 
2929 	if (!intel_panel_preferred_fixed_mode(intel_connector))
2930 		goto err;
2931 
2932 	return true;
2933 
2934 err:
2935 	intel_connector_destroy(connector);
2936 	return false;
2937 }
2938 
2939 static u16 intel_sdvo_filter_output_flags(u16 flags)
2940 {
2941 	flags &= SDVO_OUTPUT_MASK;
2942 
2943 	/* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
2944 	if (!(flags & SDVO_OUTPUT_TMDS0))
2945 		flags &= ~SDVO_OUTPUT_TMDS1;
2946 
2947 	if (!(flags & SDVO_OUTPUT_RGB0))
2948 		flags &= ~SDVO_OUTPUT_RGB1;
2949 
2950 	if (!(flags & SDVO_OUTPUT_LVDS0))
2951 		flags &= ~SDVO_OUTPUT_LVDS1;
2952 
2953 	return flags;
2954 }
2955 
2956 static bool intel_sdvo_output_init(struct intel_sdvo *sdvo, u16 type)
2957 {
2958 	if (type & SDVO_TMDS_MASK)
2959 		return intel_sdvo_dvi_init(sdvo, type);
2960 	else if (type & SDVO_TV_MASK)
2961 		return intel_sdvo_tv_init(sdvo, type);
2962 	else if (type & SDVO_RGB_MASK)
2963 		return intel_sdvo_analog_init(sdvo, type);
2964 	else if (type & SDVO_LVDS_MASK)
2965 		return intel_sdvo_lvds_init(sdvo, type);
2966 	else
2967 		return false;
2968 }
2969 
2970 static bool
2971 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo)
2972 {
2973 	static const u16 probe_order[] = {
2974 		SDVO_OUTPUT_TMDS0,
2975 		SDVO_OUTPUT_TMDS1,
2976 		/* TV has no XXX1 function block */
2977 		SDVO_OUTPUT_SVID0,
2978 		SDVO_OUTPUT_CVBS0,
2979 		SDVO_OUTPUT_YPRPB0,
2980 		SDVO_OUTPUT_RGB0,
2981 		SDVO_OUTPUT_RGB1,
2982 		SDVO_OUTPUT_LVDS0,
2983 		SDVO_OUTPUT_LVDS1,
2984 	};
2985 	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
2986 	u16 flags;
2987 	int i;
2988 
2989 	flags = intel_sdvo_filter_output_flags(intel_sdvo->caps.output_flags);
2990 
2991 	if (flags == 0) {
2992 		DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%04x)\n",
2993 			      SDVO_NAME(intel_sdvo), intel_sdvo->caps.output_flags);
2994 		return false;
2995 	}
2996 
2997 	intel_sdvo->controlled_output = flags;
2998 
2999 	intel_sdvo_select_ddc_bus(i915, intel_sdvo);
3000 
3001 	for (i = 0; i < ARRAY_SIZE(probe_order); i++) {
3002 		u16 type = flags & probe_order[i];
3003 
3004 		if (!type)
3005 			continue;
3006 
3007 		if (!intel_sdvo_output_init(intel_sdvo, type))
3008 			return false;
3009 	}
3010 
3011 	intel_sdvo->base.pipe_mask = ~0;
3012 
3013 	return true;
3014 }
3015 
3016 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
3017 {
3018 	struct drm_device *dev = intel_sdvo->base.base.dev;
3019 	struct drm_connector *connector, *tmp;
3020 
3021 	list_for_each_entry_safe(connector, tmp,
3022 				 &dev->mode_config.connector_list, head) {
3023 		if (intel_attached_encoder(to_intel_connector(connector)) == &intel_sdvo->base) {
3024 			drm_connector_unregister(connector);
3025 			intel_connector_destroy(connector);
3026 		}
3027 	}
3028 }
3029 
3030 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
3031 					  struct intel_sdvo_connector *intel_sdvo_connector,
3032 					  int type)
3033 {
3034 	struct drm_device *dev = intel_sdvo->base.base.dev;
3035 	struct intel_sdvo_tv_format format;
3036 	u32 format_map, i;
3037 
3038 	if (!intel_sdvo_set_target_output(intel_sdvo, type))
3039 		return false;
3040 
3041 	BUILD_BUG_ON(sizeof(format) != 6);
3042 	if (!intel_sdvo_get_value(intel_sdvo,
3043 				  SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
3044 				  &format, sizeof(format)))
3045 		return false;
3046 
3047 	memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
3048 
3049 	if (format_map == 0)
3050 		return false;
3051 
3052 	intel_sdvo_connector->format_supported_num = 0;
3053 	for (i = 0 ; i < TV_FORMAT_NUM; i++)
3054 		if (format_map & (1 << i))
3055 			intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
3056 
3057 
3058 	intel_sdvo_connector->tv_format =
3059 			drm_property_create(dev, DRM_MODE_PROP_ENUM,
3060 					    "mode", intel_sdvo_connector->format_supported_num);
3061 	if (!intel_sdvo_connector->tv_format)
3062 		return false;
3063 
3064 	for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
3065 		drm_property_add_enum(intel_sdvo_connector->tv_format, i,
3066 				      tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
3067 
3068 	intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0];
3069 	drm_object_attach_property(&intel_sdvo_connector->base.base.base,
3070 				   intel_sdvo_connector->tv_format, 0);
3071 	return true;
3072 
3073 }
3074 
3075 #define _ENHANCEMENT(state_assignment, name, NAME) do { \
3076 	if (enhancements.name) { \
3077 		if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
3078 		    !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
3079 			return false; \
3080 		intel_sdvo_connector->name = \
3081 			drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
3082 		if (!intel_sdvo_connector->name) return false; \
3083 		state_assignment = response; \
3084 		drm_object_attach_property(&connector->base, \
3085 					   intel_sdvo_connector->name, 0); \
3086 		DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
3087 			      data_value[0], data_value[1], response); \
3088 	} \
3089 } while (0)
3090 
3091 #define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME)
3092 
3093 static bool
3094 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
3095 				      struct intel_sdvo_connector *intel_sdvo_connector,
3096 				      struct intel_sdvo_enhancements_reply enhancements)
3097 {
3098 	struct drm_device *dev = intel_sdvo->base.base.dev;
3099 	struct drm_connector *connector = &intel_sdvo_connector->base.base;
3100 	struct drm_connector_state *conn_state = connector->state;
3101 	struct intel_sdvo_connector_state *sdvo_state =
3102 		to_intel_sdvo_connector_state(conn_state);
3103 	u16 response, data_value[2];
3104 
3105 	/* when horizontal overscan is supported, Add the left/right property */
3106 	if (enhancements.overscan_h) {
3107 		if (!intel_sdvo_get_value(intel_sdvo,
3108 					  SDVO_CMD_GET_MAX_OVERSCAN_H,
3109 					  &data_value, 4))
3110 			return false;
3111 
3112 		if (!intel_sdvo_get_value(intel_sdvo,
3113 					  SDVO_CMD_GET_OVERSCAN_H,
3114 					  &response, 2))
3115 			return false;
3116 
3117 		sdvo_state->tv.overscan_h = response;
3118 
3119 		intel_sdvo_connector->max_hscan = data_value[0];
3120 		intel_sdvo_connector->left =
3121 			drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
3122 		if (!intel_sdvo_connector->left)
3123 			return false;
3124 
3125 		drm_object_attach_property(&connector->base,
3126 					   intel_sdvo_connector->left, 0);
3127 
3128 		intel_sdvo_connector->right =
3129 			drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
3130 		if (!intel_sdvo_connector->right)
3131 			return false;
3132 
3133 		drm_object_attach_property(&connector->base,
3134 					      intel_sdvo_connector->right, 0);
3135 		DRM_DEBUG_KMS("h_overscan: max %d, "
3136 			      "default %d, current %d\n",
3137 			      data_value[0], data_value[1], response);
3138 	}
3139 
3140 	if (enhancements.overscan_v) {
3141 		if (!intel_sdvo_get_value(intel_sdvo,
3142 					  SDVO_CMD_GET_MAX_OVERSCAN_V,
3143 					  &data_value, 4))
3144 			return false;
3145 
3146 		if (!intel_sdvo_get_value(intel_sdvo,
3147 					  SDVO_CMD_GET_OVERSCAN_V,
3148 					  &response, 2))
3149 			return false;
3150 
3151 		sdvo_state->tv.overscan_v = response;
3152 
3153 		intel_sdvo_connector->max_vscan = data_value[0];
3154 		intel_sdvo_connector->top =
3155 			drm_property_create_range(dev, 0,
3156 					    "top_margin", 0, data_value[0]);
3157 		if (!intel_sdvo_connector->top)
3158 			return false;
3159 
3160 		drm_object_attach_property(&connector->base,
3161 					   intel_sdvo_connector->top, 0);
3162 
3163 		intel_sdvo_connector->bottom =
3164 			drm_property_create_range(dev, 0,
3165 					    "bottom_margin", 0, data_value[0]);
3166 		if (!intel_sdvo_connector->bottom)
3167 			return false;
3168 
3169 		drm_object_attach_property(&connector->base,
3170 					      intel_sdvo_connector->bottom, 0);
3171 		DRM_DEBUG_KMS("v_overscan: max %d, "
3172 			      "default %d, current %d\n",
3173 			      data_value[0], data_value[1], response);
3174 	}
3175 
3176 	ENHANCEMENT(&sdvo_state->tv, hpos, HPOS);
3177 	ENHANCEMENT(&sdvo_state->tv, vpos, VPOS);
3178 	ENHANCEMENT(&conn_state->tv, saturation, SATURATION);
3179 	ENHANCEMENT(&conn_state->tv, contrast, CONTRAST);
3180 	ENHANCEMENT(&conn_state->tv, hue, HUE);
3181 	ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS);
3182 	ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS);
3183 	ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER);
3184 	ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
3185 	ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D);
3186 	_ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER);
3187 	_ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER);
3188 
3189 	if (enhancements.dot_crawl) {
3190 		if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
3191 			return false;
3192 
3193 		sdvo_state->tv.dot_crawl = response & 0x1;
3194 		intel_sdvo_connector->dot_crawl =
3195 			drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
3196 		if (!intel_sdvo_connector->dot_crawl)
3197 			return false;
3198 
3199 		drm_object_attach_property(&connector->base,
3200 					   intel_sdvo_connector->dot_crawl, 0);
3201 		DRM_DEBUG_KMS("dot crawl: current %d\n", response);
3202 	}
3203 
3204 	return true;
3205 }
3206 
3207 static bool
3208 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
3209 					struct intel_sdvo_connector *intel_sdvo_connector,
3210 					struct intel_sdvo_enhancements_reply enhancements)
3211 {
3212 	struct drm_device *dev = intel_sdvo->base.base.dev;
3213 	struct drm_connector *connector = &intel_sdvo_connector->base.base;
3214 	u16 response, data_value[2];
3215 
3216 	ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS);
3217 
3218 	return true;
3219 }
3220 #undef ENHANCEMENT
3221 #undef _ENHANCEMENT
3222 
3223 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
3224 					       struct intel_sdvo_connector *intel_sdvo_connector)
3225 {
3226 	union {
3227 		struct intel_sdvo_enhancements_reply reply;
3228 		u16 response;
3229 	} enhancements;
3230 
3231 	BUILD_BUG_ON(sizeof(enhancements) != 2);
3232 
3233 	if (!intel_sdvo_get_value(intel_sdvo,
3234 				  SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
3235 				  &enhancements, sizeof(enhancements)) ||
3236 	    enhancements.response == 0) {
3237 		DRM_DEBUG_KMS("No enhancement is supported\n");
3238 		return true;
3239 	}
3240 
3241 	if (IS_TV(intel_sdvo_connector))
3242 		return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
3243 	else if (IS_LVDS(intel_sdvo_connector))
3244 		return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
3245 	else
3246 		return true;
3247 }
3248 
3249 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
3250 				     struct i2c_msg *msgs,
3251 				     int num)
3252 {
3253 	struct intel_sdvo *sdvo = adapter->algo_data;
3254 
3255 	if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
3256 		return -EIO;
3257 
3258 	return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
3259 }
3260 
3261 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
3262 {
3263 	struct intel_sdvo *sdvo = adapter->algo_data;
3264 	return sdvo->i2c->algo->functionality(sdvo->i2c);
3265 }
3266 
3267 static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
3268 	.master_xfer	= intel_sdvo_ddc_proxy_xfer,
3269 	.functionality	= intel_sdvo_ddc_proxy_func
3270 };
3271 
3272 static void proxy_lock_bus(struct i2c_adapter *adapter,
3273 			   unsigned int flags)
3274 {
3275 	struct intel_sdvo *sdvo = adapter->algo_data;
3276 	sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags);
3277 }
3278 
3279 static int proxy_trylock_bus(struct i2c_adapter *adapter,
3280 			     unsigned int flags)
3281 {
3282 	struct intel_sdvo *sdvo = adapter->algo_data;
3283 	return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags);
3284 }
3285 
3286 static void proxy_unlock_bus(struct i2c_adapter *adapter,
3287 			     unsigned int flags)
3288 {
3289 	struct intel_sdvo *sdvo = adapter->algo_data;
3290 	sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags);
3291 }
3292 
3293 static const struct i2c_lock_operations proxy_lock_ops = {
3294 	.lock_bus =    proxy_lock_bus,
3295 	.trylock_bus = proxy_trylock_bus,
3296 	.unlock_bus =  proxy_unlock_bus,
3297 };
3298 
3299 static bool
3300 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
3301 			  struct drm_i915_private *dev_priv)
3302 {
3303 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
3304 
3305 	sdvo->ddc.owner = THIS_MODULE;
3306 	sdvo->ddc.class = I2C_CLASS_DDC;
3307 	snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
3308 	sdvo->ddc.dev.parent = &pdev->dev;
3309 	sdvo->ddc.algo_data = sdvo;
3310 	sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
3311 	sdvo->ddc.lock_ops = &proxy_lock_ops;
3312 
3313 	return i2c_add_adapter(&sdvo->ddc) == 0;
3314 }
3315 
3316 static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv,
3317 				   enum port port)
3318 {
3319 	if (HAS_PCH_SPLIT(dev_priv))
3320 		drm_WARN_ON(&dev_priv->drm, port != PORT_B);
3321 	else
3322 		drm_WARN_ON(&dev_priv->drm, port != PORT_B && port != PORT_C);
3323 }
3324 
3325 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
3326 		     i915_reg_t sdvo_reg, enum port port)
3327 {
3328 	struct intel_encoder *intel_encoder;
3329 	struct intel_sdvo *intel_sdvo;
3330 	int i;
3331 
3332 	assert_sdvo_port_valid(dev_priv, port);
3333 
3334 	intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
3335 	if (!intel_sdvo)
3336 		return false;
3337 
3338 	intel_sdvo->sdvo_reg = sdvo_reg;
3339 	intel_sdvo->port = port;
3340 	intel_sdvo->slave_addr =
3341 		intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1;
3342 	intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
3343 	if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv))
3344 		goto err_i2c_bus;
3345 
3346 	/* encoder type will be decided later */
3347 	intel_encoder = &intel_sdvo->base;
3348 	intel_encoder->type = INTEL_OUTPUT_SDVO;
3349 	intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
3350 	intel_encoder->port = port;
3351 	drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3352 			 &intel_sdvo_enc_funcs, 0,
3353 			 "SDVO %c", port_name(port));
3354 
3355 	/* Read the regs to test if we can talk to the device */
3356 	for (i = 0; i < 0x40; i++) {
3357 		u8 byte;
3358 
3359 		if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
3360 			drm_dbg_kms(&dev_priv->drm,
3361 				    "No SDVO device found on %s\n",
3362 				    SDVO_NAME(intel_sdvo));
3363 			goto err;
3364 		}
3365 	}
3366 
3367 	intel_encoder->compute_config = intel_sdvo_compute_config;
3368 	if (HAS_PCH_SPLIT(dev_priv)) {
3369 		intel_encoder->disable = pch_disable_sdvo;
3370 		intel_encoder->post_disable = pch_post_disable_sdvo;
3371 	} else {
3372 		intel_encoder->disable = intel_disable_sdvo;
3373 	}
3374 	intel_encoder->pre_enable = intel_sdvo_pre_enable;
3375 	intel_encoder->enable = intel_enable_sdvo;
3376 	intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
3377 	intel_encoder->get_config = intel_sdvo_get_config;
3378 
3379 	/* In default case sdvo lvds is false */
3380 	if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
3381 		goto err;
3382 
3383 	intel_sdvo->colorimetry_cap =
3384 		intel_sdvo_get_colorimetry_cap(intel_sdvo);
3385 
3386 	if (!intel_sdvo_output_setup(intel_sdvo)) {
3387 		drm_dbg_kms(&dev_priv->drm,
3388 			    "SDVO output failed to setup on %s\n",
3389 			    SDVO_NAME(intel_sdvo));
3390 		/* Output_setup can leave behind connectors! */
3391 		goto err_output;
3392 	}
3393 
3394 	/*
3395 	 * Only enable the hotplug irq if we need it, to work around noisy
3396 	 * hotplug lines.
3397 	 */
3398 	if (intel_sdvo->hotplug_active) {
3399 		if (intel_sdvo->port == PORT_B)
3400 			intel_encoder->hpd_pin = HPD_SDVO_B;
3401 		else
3402 			intel_encoder->hpd_pin = HPD_SDVO_C;
3403 	}
3404 
3405 	/*
3406 	 * Cloning SDVO with anything is often impossible, since the SDVO
3407 	 * encoder can request a special input timing mode. And even if that's
3408 	 * not the case we have evidence that cloning a plain unscaled mode with
3409 	 * VGA doesn't really work. Furthermore the cloning flags are way too
3410 	 * simplistic anyway to express such constraints, so just give up on
3411 	 * cloning for SDVO encoders.
3412 	 */
3413 	intel_sdvo->base.cloneable = 0;
3414 
3415 	/* Set the input timing to the screen. Assume always input 0. */
3416 	if (!intel_sdvo_set_target_input(intel_sdvo))
3417 		goto err_output;
3418 
3419 	if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3420 						    &intel_sdvo->pixel_clock_min,
3421 						    &intel_sdvo->pixel_clock_max))
3422 		goto err_output;
3423 
3424 	drm_dbg_kms(&dev_priv->drm, "%s device VID/DID: %02X:%02X.%02X, "
3425 			"clock range %dMHz - %dMHz, "
3426 			"input 1: %c, input 2: %c, "
3427 			"output 1: %c, output 2: %c\n",
3428 			SDVO_NAME(intel_sdvo),
3429 			intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3430 			intel_sdvo->caps.device_rev_id,
3431 			intel_sdvo->pixel_clock_min / 1000,
3432 			intel_sdvo->pixel_clock_max / 1000,
3433 			(intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
3434 			(intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
3435 			/* check currently supported outputs */
3436 			intel_sdvo->caps.output_flags &
3437 			(SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0 |
3438 			 SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_SVID0 |
3439 			 SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_YPRPB0) ? 'Y' : 'N',
3440 			intel_sdvo->caps.output_flags &
3441 			(SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1 |
3442 			 SDVO_OUTPUT_LVDS1) ? 'Y' : 'N');
3443 	return true;
3444 
3445 err_output:
3446 	intel_sdvo_output_cleanup(intel_sdvo);
3447 
3448 err:
3449 	drm_encoder_cleanup(&intel_encoder->base);
3450 	i2c_del_adapter(&intel_sdvo->ddc);
3451 err_i2c_bus:
3452 	intel_sdvo_unselect_i2c_bus(intel_sdvo);
3453 	kfree(intel_sdvo);
3454 
3455 	return false;
3456 }
3457