1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/export.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 34 #include <drm/display/drm_hdmi_helper.h> 35 #include <drm/drm_atomic_helper.h> 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_edid.h> 38 39 #include "i915_drv.h" 40 #include "i915_reg.h" 41 #include "intel_atomic.h" 42 #include "intel_audio.h" 43 #include "intel_connector.h" 44 #include "intel_crtc.h" 45 #include "intel_de.h" 46 #include "intel_display_types.h" 47 #include "intel_fifo_underrun.h" 48 #include "intel_gmbus.h" 49 #include "intel_hdmi.h" 50 #include "intel_hotplug.h" 51 #include "intel_panel.h" 52 #include "intel_sdvo.h" 53 #include "intel_sdvo_regs.h" 54 55 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 56 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 57 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 58 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) 59 60 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ 61 SDVO_TV_MASK) 62 63 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 64 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) 65 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 66 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 67 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) 68 69 70 static const char * const tv_format_names[] = { 71 "NTSC_M" , "NTSC_J" , "NTSC_443", 72 "PAL_B" , "PAL_D" , "PAL_G" , 73 "PAL_H" , "PAL_I" , "PAL_M" , 74 "PAL_N" , "PAL_NC" , "PAL_60" , 75 "SECAM_B" , "SECAM_D" , "SECAM_G" , 76 "SECAM_K" , "SECAM_K1", "SECAM_L" , 77 "SECAM_60" 78 }; 79 80 #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names) 81 82 struct intel_sdvo { 83 struct intel_encoder base; 84 85 struct i2c_adapter *i2c; 86 u8 slave_addr; 87 88 struct i2c_adapter ddc; 89 90 /* Register for the SDVO device: SDVOB or SDVOC */ 91 i915_reg_t sdvo_reg; 92 93 /* Active outputs controlled by this SDVO output */ 94 u16 controlled_output; 95 96 /* 97 * Capabilities of the SDVO device returned by 98 * intel_sdvo_get_capabilities() 99 */ 100 struct intel_sdvo_caps caps; 101 102 u8 colorimetry_cap; 103 104 /* Pixel clock limitations reported by the SDVO device, in kHz */ 105 int pixel_clock_min, pixel_clock_max; 106 107 /* 108 * For multiple function SDVO device, 109 * this is for current attached outputs. 110 */ 111 u16 attached_output; 112 113 /* 114 * Hotplug activation bits for this device 115 */ 116 u16 hotplug_active; 117 118 enum port port; 119 120 bool has_hdmi_monitor; 121 bool has_hdmi_audio; 122 123 /* DDC bus used by this SDVO encoder */ 124 u8 ddc_bus; 125 126 /* 127 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd 128 */ 129 u8 dtd_sdvo_flags; 130 }; 131 132 struct intel_sdvo_connector { 133 struct intel_connector base; 134 135 /* Mark the type of connector */ 136 u16 output_flag; 137 138 /* This contains all current supported TV format */ 139 u8 tv_format_supported[TV_FORMAT_NUM]; 140 int format_supported_num; 141 struct drm_property *tv_format; 142 143 /* add the property for the SDVO-TV */ 144 struct drm_property *left; 145 struct drm_property *right; 146 struct drm_property *top; 147 struct drm_property *bottom; 148 struct drm_property *hpos; 149 struct drm_property *vpos; 150 struct drm_property *contrast; 151 struct drm_property *saturation; 152 struct drm_property *hue; 153 struct drm_property *sharpness; 154 struct drm_property *flicker_filter; 155 struct drm_property *flicker_filter_adaptive; 156 struct drm_property *flicker_filter_2d; 157 struct drm_property *tv_chroma_filter; 158 struct drm_property *tv_luma_filter; 159 struct drm_property *dot_crawl; 160 161 /* add the property for the SDVO-TV/LVDS */ 162 struct drm_property *brightness; 163 164 /* this is to get the range of margin.*/ 165 u32 max_hscan, max_vscan; 166 167 /** 168 * This is set if we treat the device as HDMI, instead of DVI. 169 */ 170 bool is_hdmi; 171 }; 172 173 struct intel_sdvo_connector_state { 174 /* base.base: tv.saturation/contrast/hue/brightness */ 175 struct intel_digital_connector_state base; 176 177 struct { 178 unsigned overscan_h, overscan_v, hpos, vpos, sharpness; 179 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive; 180 unsigned chroma_filter, luma_filter, dot_crawl; 181 } tv; 182 }; 183 184 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) 185 { 186 return container_of(encoder, struct intel_sdvo, base); 187 } 188 189 static struct intel_sdvo *intel_attached_sdvo(struct intel_connector *connector) 190 { 191 return to_sdvo(intel_attached_encoder(connector)); 192 } 193 194 static struct intel_sdvo_connector * 195 to_intel_sdvo_connector(struct drm_connector *connector) 196 { 197 return container_of(connector, struct intel_sdvo_connector, base.base); 198 } 199 200 #define to_intel_sdvo_connector_state(conn_state) \ 201 container_of((conn_state), struct intel_sdvo_connector_state, base.base) 202 203 static bool 204 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo); 205 static bool 206 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 207 struct intel_sdvo_connector *intel_sdvo_connector, 208 int type); 209 static bool 210 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 211 struct intel_sdvo_connector *intel_sdvo_connector); 212 213 /* 214 * Writes the SDVOB or SDVOC with the given value, but always writes both 215 * SDVOB and SDVOC to work around apparent hardware issues (according to 216 * comments in the BIOS). 217 */ 218 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 219 { 220 struct drm_device *dev = intel_sdvo->base.base.dev; 221 struct drm_i915_private *dev_priv = to_i915(dev); 222 u32 bval = val, cval = val; 223 int i; 224 225 if (HAS_PCH_SPLIT(dev_priv)) { 226 intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val); 227 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); 228 /* 229 * HW workaround, need to write this twice for issue 230 * that may result in first write getting masked. 231 */ 232 if (HAS_PCH_IBX(dev_priv)) { 233 intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val); 234 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); 235 } 236 return; 237 } 238 239 if (intel_sdvo->port == PORT_B) 240 cval = intel_de_read(dev_priv, GEN3_SDVOC); 241 else 242 bval = intel_de_read(dev_priv, GEN3_SDVOB); 243 244 /* 245 * Write the registers twice for luck. Sometimes, 246 * writing them only once doesn't appear to 'stick'. 247 * The BIOS does this too. Yay, magic 248 */ 249 for (i = 0; i < 2; i++) { 250 intel_de_write(dev_priv, GEN3_SDVOB, bval); 251 intel_de_posting_read(dev_priv, GEN3_SDVOB); 252 253 intel_de_write(dev_priv, GEN3_SDVOC, cval); 254 intel_de_posting_read(dev_priv, GEN3_SDVOC); 255 } 256 } 257 258 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 259 { 260 struct i2c_msg msgs[] = { 261 { 262 .addr = intel_sdvo->slave_addr, 263 .flags = 0, 264 .len = 1, 265 .buf = &addr, 266 }, 267 { 268 .addr = intel_sdvo->slave_addr, 269 .flags = I2C_M_RD, 270 .len = 1, 271 .buf = ch, 272 } 273 }; 274 int ret; 275 276 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) 277 return true; 278 279 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); 280 return false; 281 } 282 283 #define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ } 284 285 /** Mapping of command numbers to names, for debug output */ 286 static const struct { 287 u8 cmd; 288 const char *name; 289 } __packed sdvo_cmd_names[] = { 290 SDVO_CMD_NAME_ENTRY(RESET), 291 SDVO_CMD_NAME_ENTRY(GET_DEVICE_CAPS), 292 SDVO_CMD_NAME_ENTRY(GET_FIRMWARE_REV), 293 SDVO_CMD_NAME_ENTRY(GET_TRAINED_INPUTS), 294 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_OUTPUTS), 295 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_OUTPUTS), 296 SDVO_CMD_NAME_ENTRY(GET_IN_OUT_MAP), 297 SDVO_CMD_NAME_ENTRY(SET_IN_OUT_MAP), 298 SDVO_CMD_NAME_ENTRY(GET_ATTACHED_DISPLAYS), 299 SDVO_CMD_NAME_ENTRY(GET_HOT_PLUG_SUPPORT), 300 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_HOT_PLUG), 301 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_HOT_PLUG), 302 SDVO_CMD_NAME_ENTRY(GET_INTERRUPT_EVENT_SOURCE), 303 SDVO_CMD_NAME_ENTRY(SET_TARGET_INPUT), 304 SDVO_CMD_NAME_ENTRY(SET_TARGET_OUTPUT), 305 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART1), 306 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART2), 307 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART1), 308 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART2), 309 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART1), 310 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART2), 311 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART1), 312 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART2), 313 SDVO_CMD_NAME_ENTRY(CREATE_PREFERRED_INPUT_TIMING), 314 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART1), 315 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART2), 316 SDVO_CMD_NAME_ENTRY(GET_INPUT_PIXEL_CLOCK_RANGE), 317 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_PIXEL_CLOCK_RANGE), 318 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_CLOCK_RATE_MULTS), 319 SDVO_CMD_NAME_ENTRY(GET_CLOCK_RATE_MULT), 320 SDVO_CMD_NAME_ENTRY(SET_CLOCK_RATE_MULT), 321 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_TV_FORMATS), 322 SDVO_CMD_NAME_ENTRY(GET_TV_FORMAT), 323 SDVO_CMD_NAME_ENTRY(SET_TV_FORMAT), 324 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_POWER_STATES), 325 SDVO_CMD_NAME_ENTRY(GET_POWER_STATE), 326 SDVO_CMD_NAME_ENTRY(SET_ENCODER_POWER_STATE), 327 SDVO_CMD_NAME_ENTRY(SET_DISPLAY_POWER_STATE), 328 SDVO_CMD_NAME_ENTRY(SET_CONTROL_BUS_SWITCH), 329 SDVO_CMD_NAME_ENTRY(GET_SDTV_RESOLUTION_SUPPORT), 330 SDVO_CMD_NAME_ENTRY(GET_SCALED_HDTV_RESOLUTION_SUPPORT), 331 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_ENHANCEMENTS), 332 333 /* Add the op code for SDVO enhancements */ 334 SDVO_CMD_NAME_ENTRY(GET_MAX_HPOS), 335 SDVO_CMD_NAME_ENTRY(GET_HPOS), 336 SDVO_CMD_NAME_ENTRY(SET_HPOS), 337 SDVO_CMD_NAME_ENTRY(GET_MAX_VPOS), 338 SDVO_CMD_NAME_ENTRY(GET_VPOS), 339 SDVO_CMD_NAME_ENTRY(SET_VPOS), 340 SDVO_CMD_NAME_ENTRY(GET_MAX_SATURATION), 341 SDVO_CMD_NAME_ENTRY(GET_SATURATION), 342 SDVO_CMD_NAME_ENTRY(SET_SATURATION), 343 SDVO_CMD_NAME_ENTRY(GET_MAX_HUE), 344 SDVO_CMD_NAME_ENTRY(GET_HUE), 345 SDVO_CMD_NAME_ENTRY(SET_HUE), 346 SDVO_CMD_NAME_ENTRY(GET_MAX_CONTRAST), 347 SDVO_CMD_NAME_ENTRY(GET_CONTRAST), 348 SDVO_CMD_NAME_ENTRY(SET_CONTRAST), 349 SDVO_CMD_NAME_ENTRY(GET_MAX_BRIGHTNESS), 350 SDVO_CMD_NAME_ENTRY(GET_BRIGHTNESS), 351 SDVO_CMD_NAME_ENTRY(SET_BRIGHTNESS), 352 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_H), 353 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_H), 354 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_H), 355 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_V), 356 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_V), 357 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_V), 358 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER), 359 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER), 360 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER), 361 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_ADAPTIVE), 362 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_ADAPTIVE), 363 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_ADAPTIVE), 364 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_2D), 365 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_2D), 366 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_2D), 367 SDVO_CMD_NAME_ENTRY(GET_MAX_SHARPNESS), 368 SDVO_CMD_NAME_ENTRY(GET_SHARPNESS), 369 SDVO_CMD_NAME_ENTRY(SET_SHARPNESS), 370 SDVO_CMD_NAME_ENTRY(GET_DOT_CRAWL), 371 SDVO_CMD_NAME_ENTRY(SET_DOT_CRAWL), 372 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_CHROMA_FILTER), 373 SDVO_CMD_NAME_ENTRY(GET_TV_CHROMA_FILTER), 374 SDVO_CMD_NAME_ENTRY(SET_TV_CHROMA_FILTER), 375 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_LUMA_FILTER), 376 SDVO_CMD_NAME_ENTRY(GET_TV_LUMA_FILTER), 377 SDVO_CMD_NAME_ENTRY(SET_TV_LUMA_FILTER), 378 379 /* HDMI op code */ 380 SDVO_CMD_NAME_ENTRY(GET_SUPP_ENCODE), 381 SDVO_CMD_NAME_ENTRY(GET_ENCODE), 382 SDVO_CMD_NAME_ENTRY(SET_ENCODE), 383 SDVO_CMD_NAME_ENTRY(SET_PIXEL_REPLI), 384 SDVO_CMD_NAME_ENTRY(GET_PIXEL_REPLI), 385 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY_CAP), 386 SDVO_CMD_NAME_ENTRY(SET_COLORIMETRY), 387 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY), 388 SDVO_CMD_NAME_ENTRY(GET_AUDIO_ENCRYPT_PREFER), 389 SDVO_CMD_NAME_ENTRY(SET_AUDIO_STAT), 390 SDVO_CMD_NAME_ENTRY(GET_AUDIO_STAT), 391 SDVO_CMD_NAME_ENTRY(GET_HBUF_INDEX), 392 SDVO_CMD_NAME_ENTRY(SET_HBUF_INDEX), 393 SDVO_CMD_NAME_ENTRY(GET_HBUF_INFO), 394 SDVO_CMD_NAME_ENTRY(GET_HBUF_AV_SPLIT), 395 SDVO_CMD_NAME_ENTRY(SET_HBUF_AV_SPLIT), 396 SDVO_CMD_NAME_ENTRY(GET_HBUF_TXRATE), 397 SDVO_CMD_NAME_ENTRY(SET_HBUF_TXRATE), 398 SDVO_CMD_NAME_ENTRY(SET_HBUF_DATA), 399 SDVO_CMD_NAME_ENTRY(GET_HBUF_DATA), 400 }; 401 402 #undef SDVO_CMD_NAME_ENTRY 403 404 static const char *sdvo_cmd_name(u8 cmd) 405 { 406 int i; 407 408 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 409 if (cmd == sdvo_cmd_names[i].cmd) 410 return sdvo_cmd_names[i].name; 411 } 412 413 return NULL; 414 } 415 416 #define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC") 417 418 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 419 const void *args, int args_len) 420 { 421 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 422 const char *cmd_name; 423 int i, pos = 0; 424 char buffer[64]; 425 426 #define BUF_PRINT(args...) \ 427 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) 428 429 for (i = 0; i < args_len; i++) { 430 BUF_PRINT("%02X ", ((u8 *)args)[i]); 431 } 432 for (; i < 8; i++) { 433 BUF_PRINT(" "); 434 } 435 436 cmd_name = sdvo_cmd_name(cmd); 437 if (cmd_name) 438 BUF_PRINT("(%s)", cmd_name); 439 else 440 BUF_PRINT("(%02X)", cmd); 441 442 drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1); 443 #undef BUF_PRINT 444 445 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); 446 } 447 448 static const char * const cmd_status_names[] = { 449 [SDVO_CMD_STATUS_POWER_ON] = "Power on", 450 [SDVO_CMD_STATUS_SUCCESS] = "Success", 451 [SDVO_CMD_STATUS_NOTSUPP] = "Not supported", 452 [SDVO_CMD_STATUS_INVALID_ARG] = "Invalid arg", 453 [SDVO_CMD_STATUS_PENDING] = "Pending", 454 [SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED] = "Target not specified", 455 [SDVO_CMD_STATUS_SCALING_NOT_SUPP] = "Scaling not supported", 456 }; 457 458 static const char *sdvo_cmd_status(u8 status) 459 { 460 if (status < ARRAY_SIZE(cmd_status_names)) 461 return cmd_status_names[status]; 462 else 463 return NULL; 464 } 465 466 static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 467 const void *args, int args_len, 468 bool unlocked) 469 { 470 u8 *buf, status; 471 struct i2c_msg *msgs; 472 int i, ret = true; 473 474 /* Would be simpler to allocate both in one go ? */ 475 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); 476 if (!buf) 477 return false; 478 479 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); 480 if (!msgs) { 481 kfree(buf); 482 return false; 483 } 484 485 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 486 487 for (i = 0; i < args_len; i++) { 488 msgs[i].addr = intel_sdvo->slave_addr; 489 msgs[i].flags = 0; 490 msgs[i].len = 2; 491 msgs[i].buf = buf + 2 *i; 492 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 493 buf[2*i + 1] = ((u8*)args)[i]; 494 } 495 msgs[i].addr = intel_sdvo->slave_addr; 496 msgs[i].flags = 0; 497 msgs[i].len = 2; 498 msgs[i].buf = buf + 2*i; 499 buf[2*i + 0] = SDVO_I2C_OPCODE; 500 buf[2*i + 1] = cmd; 501 502 /* the following two are to read the response */ 503 status = SDVO_I2C_CMD_STATUS; 504 msgs[i+1].addr = intel_sdvo->slave_addr; 505 msgs[i+1].flags = 0; 506 msgs[i+1].len = 1; 507 msgs[i+1].buf = &status; 508 509 msgs[i+2].addr = intel_sdvo->slave_addr; 510 msgs[i+2].flags = I2C_M_RD; 511 msgs[i+2].len = 1; 512 msgs[i+2].buf = &status; 513 514 if (unlocked) 515 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); 516 else 517 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3); 518 if (ret < 0) { 519 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 520 ret = false; 521 goto out; 522 } 523 if (ret != i+3) { 524 /* failure in I2C transfer */ 525 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); 526 ret = false; 527 } 528 529 out: 530 kfree(msgs); 531 kfree(buf); 532 return ret; 533 } 534 535 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 536 const void *args, int args_len) 537 { 538 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true); 539 } 540 541 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 542 void *response, int response_len) 543 { 544 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 545 const char *cmd_status; 546 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ 547 u8 status; 548 int i, pos = 0; 549 char buffer[64]; 550 551 buffer[0] = '\0'; 552 553 /* 554 * The documentation states that all commands will be 555 * processed within 15µs, and that we need only poll 556 * the status byte a maximum of 3 times in order for the 557 * command to be complete. 558 * 559 * Check 5 times in case the hardware failed to read the docs. 560 * 561 * Also beware that the first response by many devices is to 562 * reply PENDING and stall for time. TVs are notorious for 563 * requiring longer than specified to complete their replies. 564 * Originally (in the DDX long ago), the delay was only ever 15ms 565 * with an additional delay of 30ms applied for TVs added later after 566 * many experiments. To accommodate both sets of delays, we do a 567 * sequence of slow checks if the device is falling behind and fails 568 * to reply within 5*15µs. 569 */ 570 if (!intel_sdvo_read_byte(intel_sdvo, 571 SDVO_I2C_CMD_STATUS, 572 &status)) 573 goto log_fail; 574 575 while ((status == SDVO_CMD_STATUS_PENDING || 576 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { 577 if (retry < 10) 578 msleep(15); 579 else 580 udelay(15); 581 582 if (!intel_sdvo_read_byte(intel_sdvo, 583 SDVO_I2C_CMD_STATUS, 584 &status)) 585 goto log_fail; 586 } 587 588 #define BUF_PRINT(args...) \ 589 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) 590 591 cmd_status = sdvo_cmd_status(status); 592 if (cmd_status) 593 BUF_PRINT("(%s)", cmd_status); 594 else 595 BUF_PRINT("(??? %d)", status); 596 597 if (status != SDVO_CMD_STATUS_SUCCESS) 598 goto log_fail; 599 600 /* Read the command response */ 601 for (i = 0; i < response_len; i++) { 602 if (!intel_sdvo_read_byte(intel_sdvo, 603 SDVO_I2C_RETURN_0 + i, 604 &((u8 *)response)[i])) 605 goto log_fail; 606 BUF_PRINT(" %02X", ((u8 *)response)[i]); 607 } 608 609 drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1); 610 #undef BUF_PRINT 611 612 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); 613 return true; 614 615 log_fail: 616 DRM_DEBUG_KMS("%s: R: ... failed %s\n", 617 SDVO_NAME(intel_sdvo), buffer); 618 return false; 619 } 620 621 static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode) 622 { 623 if (adjusted_mode->crtc_clock >= 100000) 624 return 1; 625 else if (adjusted_mode->crtc_clock >= 50000) 626 return 2; 627 else 628 return 4; 629 } 630 631 static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 632 u8 ddc_bus) 633 { 634 /* This must be the immediately preceding write before the i2c xfer */ 635 return __intel_sdvo_write_cmd(intel_sdvo, 636 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 637 &ddc_bus, 1, false); 638 } 639 640 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 641 { 642 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 643 return false; 644 645 return intel_sdvo_read_response(intel_sdvo, NULL, 0); 646 } 647 648 static bool 649 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 650 { 651 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 652 return false; 653 654 return intel_sdvo_read_response(intel_sdvo, value, len); 655 } 656 657 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 658 { 659 struct intel_sdvo_set_target_input_args targets = {0}; 660 return intel_sdvo_set_value(intel_sdvo, 661 SDVO_CMD_SET_TARGET_INPUT, 662 &targets, sizeof(targets)); 663 } 664 665 /* 666 * Return whether each input is trained. 667 * 668 * This function is making an assumption about the layout of the response, 669 * which should be checked against the docs. 670 */ 671 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 672 { 673 struct intel_sdvo_get_trained_inputs_response response; 674 675 BUILD_BUG_ON(sizeof(response) != 1); 676 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 677 &response, sizeof(response))) 678 return false; 679 680 *input_1 = response.input0_trained; 681 *input_2 = response.input1_trained; 682 return true; 683 } 684 685 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 686 u16 outputs) 687 { 688 return intel_sdvo_set_value(intel_sdvo, 689 SDVO_CMD_SET_ACTIVE_OUTPUTS, 690 &outputs, sizeof(outputs)); 691 } 692 693 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, 694 u16 *outputs) 695 { 696 return intel_sdvo_get_value(intel_sdvo, 697 SDVO_CMD_GET_ACTIVE_OUTPUTS, 698 outputs, sizeof(*outputs)); 699 } 700 701 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 702 int mode) 703 { 704 u8 state = SDVO_ENCODER_STATE_ON; 705 706 switch (mode) { 707 case DRM_MODE_DPMS_ON: 708 state = SDVO_ENCODER_STATE_ON; 709 break; 710 case DRM_MODE_DPMS_STANDBY: 711 state = SDVO_ENCODER_STATE_STANDBY; 712 break; 713 case DRM_MODE_DPMS_SUSPEND: 714 state = SDVO_ENCODER_STATE_SUSPEND; 715 break; 716 case DRM_MODE_DPMS_OFF: 717 state = SDVO_ENCODER_STATE_OFF; 718 break; 719 } 720 721 return intel_sdvo_set_value(intel_sdvo, 722 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 723 } 724 725 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 726 int *clock_min, 727 int *clock_max) 728 { 729 struct intel_sdvo_pixel_clock_range clocks; 730 731 BUILD_BUG_ON(sizeof(clocks) != 4); 732 if (!intel_sdvo_get_value(intel_sdvo, 733 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 734 &clocks, sizeof(clocks))) 735 return false; 736 737 /* Convert the values from units of 10 kHz to kHz. */ 738 *clock_min = clocks.min * 10; 739 *clock_max = clocks.max * 10; 740 return true; 741 } 742 743 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 744 u16 outputs) 745 { 746 return intel_sdvo_set_value(intel_sdvo, 747 SDVO_CMD_SET_TARGET_OUTPUT, 748 &outputs, sizeof(outputs)); 749 } 750 751 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 752 struct intel_sdvo_dtd *dtd) 753 { 754 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 755 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 756 } 757 758 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 759 struct intel_sdvo_dtd *dtd) 760 { 761 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 762 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 763 } 764 765 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 766 struct intel_sdvo_dtd *dtd) 767 { 768 return intel_sdvo_set_timing(intel_sdvo, 769 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 770 } 771 772 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 773 struct intel_sdvo_dtd *dtd) 774 { 775 return intel_sdvo_set_timing(intel_sdvo, 776 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 777 } 778 779 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, 780 struct intel_sdvo_dtd *dtd) 781 { 782 return intel_sdvo_get_timing(intel_sdvo, 783 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); 784 } 785 786 static bool 787 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 788 struct intel_sdvo_connector *intel_sdvo_connector, 789 const struct drm_display_mode *mode) 790 { 791 struct intel_sdvo_preferred_input_timing_args args; 792 793 memset(&args, 0, sizeof(args)); 794 args.clock = mode->clock / 10; 795 args.width = mode->hdisplay; 796 args.height = mode->vdisplay; 797 args.interlace = 0; 798 799 if (IS_LVDS(intel_sdvo_connector)) { 800 const struct drm_display_mode *fixed_mode = 801 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); 802 803 if (fixed_mode->hdisplay != args.width || 804 fixed_mode->vdisplay != args.height) 805 args.scaled = 1; 806 } 807 808 return intel_sdvo_set_value(intel_sdvo, 809 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 810 &args, sizeof(args)); 811 } 812 813 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 814 struct intel_sdvo_dtd *dtd) 815 { 816 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 817 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 818 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 819 &dtd->part1, sizeof(dtd->part1)) && 820 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 821 &dtd->part2, sizeof(dtd->part2)); 822 } 823 824 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 825 { 826 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 827 } 828 829 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 830 const struct drm_display_mode *mode) 831 { 832 u16 width, height; 833 u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len; 834 u16 h_sync_offset, v_sync_offset; 835 int mode_clock; 836 837 memset(dtd, 0, sizeof(*dtd)); 838 839 width = mode->hdisplay; 840 height = mode->vdisplay; 841 842 /* do some mode translations */ 843 h_blank_len = mode->htotal - mode->hdisplay; 844 h_sync_len = mode->hsync_end - mode->hsync_start; 845 846 v_blank_len = mode->vtotal - mode->vdisplay; 847 v_sync_len = mode->vsync_end - mode->vsync_start; 848 849 h_sync_offset = mode->hsync_start - mode->hdisplay; 850 v_sync_offset = mode->vsync_start - mode->vdisplay; 851 852 mode_clock = mode->clock; 853 mode_clock /= 10; 854 dtd->part1.clock = mode_clock; 855 856 dtd->part1.h_active = width & 0xff; 857 dtd->part1.h_blank = h_blank_len & 0xff; 858 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 859 ((h_blank_len >> 8) & 0xf); 860 dtd->part1.v_active = height & 0xff; 861 dtd->part1.v_blank = v_blank_len & 0xff; 862 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 863 ((v_blank_len >> 8) & 0xf); 864 865 dtd->part2.h_sync_off = h_sync_offset & 0xff; 866 dtd->part2.h_sync_width = h_sync_len & 0xff; 867 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 868 (v_sync_len & 0xf); 869 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 870 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 871 ((v_sync_len & 0x30) >> 4); 872 873 dtd->part2.dtd_flags = 0x18; 874 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 875 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; 876 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 877 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; 878 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 879 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; 880 881 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 882 } 883 884 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, 885 const struct intel_sdvo_dtd *dtd) 886 { 887 struct drm_display_mode mode = {}; 888 889 mode.hdisplay = dtd->part1.h_active; 890 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 891 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; 892 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 893 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; 894 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 895 mode.htotal = mode.hdisplay + dtd->part1.h_blank; 896 mode.htotal += (dtd->part1.h_high & 0xf) << 8; 897 898 mode.vdisplay = dtd->part1.v_active; 899 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 900 mode.vsync_start = mode.vdisplay; 901 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 902 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 903 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; 904 mode.vsync_end = mode.vsync_start + 905 (dtd->part2.v_sync_off_width & 0xf); 906 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 907 mode.vtotal = mode.vdisplay + dtd->part1.v_blank; 908 mode.vtotal += (dtd->part1.v_high & 0xf) << 8; 909 910 mode.clock = dtd->part1.clock * 10; 911 912 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) 913 mode.flags |= DRM_MODE_FLAG_INTERLACE; 914 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 915 mode.flags |= DRM_MODE_FLAG_PHSYNC; 916 else 917 mode.flags |= DRM_MODE_FLAG_NHSYNC; 918 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 919 mode.flags |= DRM_MODE_FLAG_PVSYNC; 920 else 921 mode.flags |= DRM_MODE_FLAG_NVSYNC; 922 923 drm_mode_set_crtcinfo(&mode, 0); 924 925 drm_mode_copy(pmode, &mode); 926 } 927 928 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) 929 { 930 struct intel_sdvo_encode encode; 931 932 BUILD_BUG_ON(sizeof(encode) != 2); 933 return intel_sdvo_get_value(intel_sdvo, 934 SDVO_CMD_GET_SUPP_ENCODE, 935 &encode, sizeof(encode)); 936 } 937 938 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 939 u8 mode) 940 { 941 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 942 } 943 944 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 945 u8 mode) 946 { 947 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 948 } 949 950 static bool intel_sdvo_set_pixel_replication(struct intel_sdvo *intel_sdvo, 951 u8 pixel_repeat) 952 { 953 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_PIXEL_REPLI, 954 &pixel_repeat, 1); 955 } 956 957 static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo, 958 u8 audio_state) 959 { 960 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT, 961 &audio_state, 1); 962 } 963 964 static bool intel_sdvo_get_hbuf_size(struct intel_sdvo *intel_sdvo, 965 u8 *hbuf_size) 966 { 967 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, 968 hbuf_size, 1)) 969 return false; 970 971 /* Buffer size is 0 based, hooray! However zero means zero. */ 972 if (*hbuf_size) 973 (*hbuf_size)++; 974 975 return true; 976 } 977 978 #if 0 979 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) 980 { 981 int i, j; 982 u8 set_buf_index[2]; 983 u8 av_split; 984 u8 buf_size; 985 u8 buf[48]; 986 u8 *pos; 987 988 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 989 990 for (i = 0; i <= av_split; i++) { 991 set_buf_index[0] = i; set_buf_index[1] = 0; 992 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 993 set_buf_index, 2); 994 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 995 intel_sdvo_read_response(encoder, &buf_size, 1); 996 997 pos = buf; 998 for (j = 0; j <= buf_size; j += 8) { 999 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 1000 NULL, 0); 1001 intel_sdvo_read_response(encoder, pos, 8); 1002 pos += 8; 1003 } 1004 } 1005 } 1006 #endif 1007 1008 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, 1009 unsigned int if_index, u8 tx_rate, 1010 const u8 *data, unsigned int length) 1011 { 1012 u8 set_buf_index[2] = { if_index, 0 }; 1013 u8 hbuf_size, tmp[8]; 1014 int i; 1015 1016 if (!intel_sdvo_set_value(intel_sdvo, 1017 SDVO_CMD_SET_HBUF_INDEX, 1018 set_buf_index, 2)) 1019 return false; 1020 1021 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) 1022 return false; 1023 1024 DRM_DEBUG_KMS("writing sdvo hbuf: %i, length %u, hbuf_size: %i\n", 1025 if_index, length, hbuf_size); 1026 1027 if (hbuf_size < length) 1028 return false; 1029 1030 for (i = 0; i < hbuf_size; i += 8) { 1031 memset(tmp, 0, 8); 1032 if (i < length) 1033 memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); 1034 1035 if (!intel_sdvo_set_value(intel_sdvo, 1036 SDVO_CMD_SET_HBUF_DATA, 1037 tmp, 8)) 1038 return false; 1039 } 1040 1041 return intel_sdvo_set_value(intel_sdvo, 1042 SDVO_CMD_SET_HBUF_TXRATE, 1043 &tx_rate, 1); 1044 } 1045 1046 static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo, 1047 unsigned int if_index, 1048 u8 *data, unsigned int length) 1049 { 1050 u8 set_buf_index[2] = { if_index, 0 }; 1051 u8 hbuf_size, tx_rate, av_split; 1052 int i; 1053 1054 if (!intel_sdvo_get_value(intel_sdvo, 1055 SDVO_CMD_GET_HBUF_AV_SPLIT, 1056 &av_split, 1)) 1057 return -ENXIO; 1058 1059 if (av_split < if_index) 1060 return 0; 1061 1062 if (!intel_sdvo_set_value(intel_sdvo, 1063 SDVO_CMD_SET_HBUF_INDEX, 1064 set_buf_index, 2)) 1065 return -ENXIO; 1066 1067 if (!intel_sdvo_get_value(intel_sdvo, 1068 SDVO_CMD_GET_HBUF_TXRATE, 1069 &tx_rate, 1)) 1070 return -ENXIO; 1071 1072 /* TX_DISABLED doesn't mean disabled for ELD */ 1073 if (if_index != SDVO_HBUF_INDEX_ELD && tx_rate == SDVO_HBUF_TX_DISABLED) 1074 return 0; 1075 1076 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) 1077 return false; 1078 1079 DRM_DEBUG_KMS("reading sdvo hbuf: %i, length %u, hbuf_size: %i\n", 1080 if_index, length, hbuf_size); 1081 1082 hbuf_size = min_t(unsigned int, length, hbuf_size); 1083 1084 for (i = 0; i < hbuf_size; i += 8) { 1085 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA, NULL, 0)) 1086 return -ENXIO; 1087 if (!intel_sdvo_read_response(intel_sdvo, &data[i], 1088 min_t(unsigned int, 8, hbuf_size - i))) 1089 return -ENXIO; 1090 } 1091 1092 return hbuf_size; 1093 } 1094 1095 static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo, 1096 struct intel_crtc_state *crtc_state, 1097 struct drm_connector_state *conn_state) 1098 { 1099 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 1100 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 1101 const struct drm_display_mode *adjusted_mode = 1102 &crtc_state->hw.adjusted_mode; 1103 int ret; 1104 1105 if (!crtc_state->has_hdmi_sink) 1106 return true; 1107 1108 crtc_state->infoframes.enable |= 1109 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 1110 1111 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, 1112 conn_state->connector, 1113 adjusted_mode); 1114 if (ret) 1115 return false; 1116 1117 drm_hdmi_avi_infoframe_quant_range(frame, 1118 conn_state->connector, 1119 adjusted_mode, 1120 crtc_state->limited_color_range ? 1121 HDMI_QUANTIZATION_RANGE_LIMITED : 1122 HDMI_QUANTIZATION_RANGE_FULL); 1123 1124 ret = hdmi_avi_infoframe_check(frame); 1125 if (drm_WARN_ON(&dev_priv->drm, ret)) 1126 return false; 1127 1128 return true; 1129 } 1130 1131 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 1132 const struct intel_crtc_state *crtc_state) 1133 { 1134 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 1135 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1136 const union hdmi_infoframe *frame = &crtc_state->infoframes.avi; 1137 ssize_t len; 1138 1139 if ((crtc_state->infoframes.enable & 1140 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0) 1141 return true; 1142 1143 if (drm_WARN_ON(&dev_priv->drm, 1144 frame->any.type != HDMI_INFOFRAME_TYPE_AVI)) 1145 return false; 1146 1147 len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data)); 1148 if (drm_WARN_ON(&dev_priv->drm, len < 0)) 1149 return false; 1150 1151 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1152 SDVO_HBUF_TX_VSYNC, 1153 sdvo_data, len); 1154 } 1155 1156 static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo, 1157 struct intel_crtc_state *crtc_state) 1158 { 1159 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1160 union hdmi_infoframe *frame = &crtc_state->infoframes.avi; 1161 ssize_t len; 1162 int ret; 1163 1164 if (!crtc_state->has_hdmi_sink) 1165 return; 1166 1167 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1168 sdvo_data, sizeof(sdvo_data)); 1169 if (len < 0) { 1170 DRM_DEBUG_KMS("failed to read AVI infoframe\n"); 1171 return; 1172 } else if (len == 0) { 1173 return; 1174 } 1175 1176 crtc_state->infoframes.enable |= 1177 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 1178 1179 ret = hdmi_infoframe_unpack(frame, sdvo_data, len); 1180 if (ret) { 1181 DRM_DEBUG_KMS("Failed to unpack AVI infoframe\n"); 1182 return; 1183 } 1184 1185 if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI) 1186 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 1187 frame->any.type, HDMI_INFOFRAME_TYPE_AVI); 1188 } 1189 1190 static void intel_sdvo_get_eld(struct intel_sdvo *intel_sdvo, 1191 struct intel_crtc_state *crtc_state) 1192 { 1193 struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); 1194 ssize_t len; 1195 u8 val; 1196 1197 if (!crtc_state->has_audio) 1198 return; 1199 1200 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, &val, 1)) 1201 return; 1202 1203 if ((val & SDVO_AUDIO_ELD_VALID) == 0) 1204 return; 1205 1206 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD, 1207 crtc_state->eld, sizeof(crtc_state->eld)); 1208 if (len < 0) 1209 drm_dbg_kms(&i915->drm, "failed to read ELD\n"); 1210 } 1211 1212 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo, 1213 const struct drm_connector_state *conn_state) 1214 { 1215 struct intel_sdvo_tv_format format; 1216 u32 format_map; 1217 1218 format_map = 1 << conn_state->tv.mode; 1219 memset(&format, 0, sizeof(format)); 1220 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 1221 1222 BUILD_BUG_ON(sizeof(format) != 6); 1223 return intel_sdvo_set_value(intel_sdvo, 1224 SDVO_CMD_SET_TV_FORMAT, 1225 &format, sizeof(format)); 1226 } 1227 1228 static bool 1229 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 1230 const struct drm_display_mode *mode) 1231 { 1232 struct intel_sdvo_dtd output_dtd; 1233 1234 if (!intel_sdvo_set_target_output(intel_sdvo, 1235 intel_sdvo->attached_output)) 1236 return false; 1237 1238 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1239 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1240 return false; 1241 1242 return true; 1243 } 1244 1245 /* 1246 * Asks the sdvo controller for the preferred input mode given the output mode. 1247 * Unfortunately we have to set up the full output mode to do that. 1248 */ 1249 static bool 1250 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, 1251 struct intel_sdvo_connector *intel_sdvo_connector, 1252 const struct drm_display_mode *mode, 1253 struct drm_display_mode *adjusted_mode) 1254 { 1255 struct intel_sdvo_dtd input_dtd; 1256 1257 /* Reset the input timing to the screen. Assume always input 0. */ 1258 if (!intel_sdvo_set_target_input(intel_sdvo)) 1259 return false; 1260 1261 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 1262 intel_sdvo_connector, 1263 mode)) 1264 return false; 1265 1266 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1267 &input_dtd)) 1268 return false; 1269 1270 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1271 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; 1272 1273 return true; 1274 } 1275 1276 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) 1277 { 1278 struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc->dev); 1279 unsigned dotclock = pipe_config->port_clock; 1280 struct dpll *clock = &pipe_config->dpll; 1281 1282 /* 1283 * SDVO TV has fixed PLL values depend on its clock range, 1284 * this mirrors vbios setting. 1285 */ 1286 if (dotclock >= 100000 && dotclock < 140500) { 1287 clock->p1 = 2; 1288 clock->p2 = 10; 1289 clock->n = 3; 1290 clock->m1 = 16; 1291 clock->m2 = 8; 1292 } else if (dotclock >= 140500 && dotclock <= 200000) { 1293 clock->p1 = 1; 1294 clock->p2 = 10; 1295 clock->n = 6; 1296 clock->m1 = 12; 1297 clock->m2 = 8; 1298 } else { 1299 drm_WARN(&dev_priv->drm, 1, 1300 "SDVO TV clock out of range: %i\n", dotclock); 1301 } 1302 1303 pipe_config->clock_set = true; 1304 } 1305 1306 static bool intel_has_hdmi_sink(struct intel_sdvo *sdvo, 1307 const struct drm_connector_state *conn_state) 1308 { 1309 return sdvo->has_hdmi_monitor && 1310 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1311 } 1312 1313 static bool intel_sdvo_limited_color_range(struct intel_encoder *encoder, 1314 const struct intel_crtc_state *crtc_state, 1315 const struct drm_connector_state *conn_state) 1316 { 1317 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1318 1319 if ((intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220) == 0) 1320 return false; 1321 1322 return intel_hdmi_limited_color_range(crtc_state, conn_state); 1323 } 1324 1325 static bool intel_sdvo_has_audio(struct intel_encoder *encoder, 1326 const struct intel_crtc_state *crtc_state, 1327 const struct drm_connector_state *conn_state) 1328 { 1329 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1330 const struct intel_digital_connector_state *intel_conn_state = 1331 to_intel_digital_connector_state(conn_state); 1332 1333 if (!crtc_state->has_hdmi_sink) 1334 return false; 1335 1336 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 1337 return intel_sdvo->has_hdmi_audio; 1338 else 1339 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 1340 } 1341 1342 static int intel_sdvo_compute_config(struct intel_encoder *encoder, 1343 struct intel_crtc_state *pipe_config, 1344 struct drm_connector_state *conn_state) 1345 { 1346 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1347 struct intel_sdvo_connector *intel_sdvo_connector = 1348 to_intel_sdvo_connector(conn_state->connector); 1349 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1350 struct drm_display_mode *mode = &pipe_config->hw.mode; 1351 1352 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); 1353 pipe_config->pipe_bpp = 8*3; 1354 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 1355 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1356 1357 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) 1358 pipe_config->has_pch_encoder = true; 1359 1360 /* 1361 * We need to construct preferred input timings based on our 1362 * output timings. To do that, we have to set the output 1363 * timings, even though this isn't really the right place in 1364 * the sequence to do it. Oh well. 1365 */ 1366 if (IS_TV(intel_sdvo_connector)) { 1367 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) 1368 return -EINVAL; 1369 1370 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1371 intel_sdvo_connector, 1372 mode, 1373 adjusted_mode); 1374 pipe_config->sdvo_tv_clock = true; 1375 } else if (IS_LVDS(intel_sdvo_connector)) { 1376 const struct drm_display_mode *fixed_mode = 1377 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); 1378 int ret; 1379 1380 ret = intel_panel_compute_config(&intel_sdvo_connector->base, 1381 adjusted_mode); 1382 if (ret) 1383 return ret; 1384 1385 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, fixed_mode)) 1386 return -EINVAL; 1387 1388 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1389 intel_sdvo_connector, 1390 mode, 1391 adjusted_mode); 1392 } 1393 1394 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 1395 return -EINVAL; 1396 1397 /* 1398 * Make the CRTC code factor in the SDVO pixel multiplier. The 1399 * SDVO device will factor out the multiplier during mode_set. 1400 */ 1401 pipe_config->pixel_multiplier = 1402 intel_sdvo_get_pixel_multiplier(adjusted_mode); 1403 1404 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo, conn_state); 1405 1406 pipe_config->has_audio = 1407 intel_sdvo_has_audio(encoder, pipe_config, conn_state) && 1408 intel_audio_compute_config(encoder, pipe_config, conn_state); 1409 1410 pipe_config->limited_color_range = 1411 intel_sdvo_limited_color_range(encoder, pipe_config, 1412 conn_state); 1413 1414 /* Clock computation needs to happen after pixel multiplier. */ 1415 if (IS_TV(intel_sdvo_connector)) 1416 i9xx_adjust_sdvo_tv_clock(pipe_config); 1417 1418 if (conn_state->picture_aspect_ratio) 1419 adjusted_mode->picture_aspect_ratio = 1420 conn_state->picture_aspect_ratio; 1421 1422 if (!intel_sdvo_compute_avi_infoframe(intel_sdvo, 1423 pipe_config, conn_state)) { 1424 DRM_DEBUG_KMS("bad AVI infoframe\n"); 1425 return -EINVAL; 1426 } 1427 1428 return 0; 1429 } 1430 1431 #define UPDATE_PROPERTY(input, NAME) \ 1432 do { \ 1433 val = input; \ 1434 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \ 1435 } while (0) 1436 1437 static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo, 1438 const struct intel_sdvo_connector_state *sdvo_state) 1439 { 1440 const struct drm_connector_state *conn_state = &sdvo_state->base.base; 1441 struct intel_sdvo_connector *intel_sdvo_conn = 1442 to_intel_sdvo_connector(conn_state->connector); 1443 u16 val; 1444 1445 if (intel_sdvo_conn->left) 1446 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H); 1447 1448 if (intel_sdvo_conn->top) 1449 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V); 1450 1451 if (intel_sdvo_conn->hpos) 1452 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS); 1453 1454 if (intel_sdvo_conn->vpos) 1455 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS); 1456 1457 if (intel_sdvo_conn->saturation) 1458 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION); 1459 1460 if (intel_sdvo_conn->contrast) 1461 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST); 1462 1463 if (intel_sdvo_conn->hue) 1464 UPDATE_PROPERTY(conn_state->tv.hue, HUE); 1465 1466 if (intel_sdvo_conn->brightness) 1467 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS); 1468 1469 if (intel_sdvo_conn->sharpness) 1470 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS); 1471 1472 if (intel_sdvo_conn->flicker_filter) 1473 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER); 1474 1475 if (intel_sdvo_conn->flicker_filter_2d) 1476 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D); 1477 1478 if (intel_sdvo_conn->flicker_filter_adaptive) 1479 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 1480 1481 if (intel_sdvo_conn->tv_chroma_filter) 1482 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER); 1483 1484 if (intel_sdvo_conn->tv_luma_filter) 1485 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER); 1486 1487 if (intel_sdvo_conn->dot_crawl) 1488 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL); 1489 1490 #undef UPDATE_PROPERTY 1491 } 1492 1493 static void intel_sdvo_pre_enable(struct intel_atomic_state *state, 1494 struct intel_encoder *intel_encoder, 1495 const struct intel_crtc_state *crtc_state, 1496 const struct drm_connector_state *conn_state) 1497 { 1498 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 1499 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1500 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1501 const struct intel_sdvo_connector_state *sdvo_state = 1502 to_intel_sdvo_connector_state(conn_state); 1503 struct intel_sdvo_connector *intel_sdvo_connector = 1504 to_intel_sdvo_connector(conn_state->connector); 1505 const struct drm_display_mode *mode = &crtc_state->hw.mode; 1506 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); 1507 u32 sdvox; 1508 struct intel_sdvo_in_out_map in_out; 1509 struct intel_sdvo_dtd input_dtd, output_dtd; 1510 int rate; 1511 1512 intel_sdvo_update_props(intel_sdvo, sdvo_state); 1513 1514 /* 1515 * First, set the input mapping for the first input to our controlled 1516 * output. This is only correct if we're a single-input device, in 1517 * which case the first input is the output from the appropriate SDVO 1518 * channel on the motherboard. In a two-input device, the first input 1519 * will be SDVOB and the second SDVOC. 1520 */ 1521 in_out.in0 = intel_sdvo->attached_output; 1522 in_out.in1 = 0; 1523 1524 intel_sdvo_set_value(intel_sdvo, 1525 SDVO_CMD_SET_IN_OUT_MAP, 1526 &in_out, sizeof(in_out)); 1527 1528 /* Set the output timings to the screen */ 1529 if (!intel_sdvo_set_target_output(intel_sdvo, 1530 intel_sdvo->attached_output)) 1531 return; 1532 1533 /* lvds has a special fixed output timing. */ 1534 if (IS_LVDS(intel_sdvo_connector)) { 1535 const struct drm_display_mode *fixed_mode = 1536 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); 1537 1538 intel_sdvo_get_dtd_from_mode(&output_dtd, fixed_mode); 1539 } else { 1540 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1541 } 1542 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1543 drm_info(&dev_priv->drm, 1544 "Setting output timings on %s failed\n", 1545 SDVO_NAME(intel_sdvo)); 1546 1547 /* Set the input timing to the screen. Assume always input 0. */ 1548 if (!intel_sdvo_set_target_input(intel_sdvo)) 1549 return; 1550 1551 if (crtc_state->has_hdmi_sink) { 1552 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 1553 intel_sdvo_set_colorimetry(intel_sdvo, 1554 crtc_state->limited_color_range ? 1555 SDVO_COLORIMETRY_RGB220 : 1556 SDVO_COLORIMETRY_RGB256); 1557 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state); 1558 intel_sdvo_set_pixel_replication(intel_sdvo, 1559 !!(adjusted_mode->flags & 1560 DRM_MODE_FLAG_DBLCLK)); 1561 } else 1562 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); 1563 1564 if (IS_TV(intel_sdvo_connector) && 1565 !intel_sdvo_set_tv_format(intel_sdvo, conn_state)) 1566 return; 1567 1568 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1569 1570 if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector)) 1571 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; 1572 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1573 drm_info(&dev_priv->drm, 1574 "Setting input timings on %s failed\n", 1575 SDVO_NAME(intel_sdvo)); 1576 1577 switch (crtc_state->pixel_multiplier) { 1578 default: 1579 drm_WARN(&dev_priv->drm, 1, 1580 "unknown pixel multiplier specified\n"); 1581 fallthrough; 1582 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1583 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1584 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1585 } 1586 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1587 return; 1588 1589 /* Set the SDVO control regs. */ 1590 if (DISPLAY_VER(dev_priv) >= 4) { 1591 /* The real mode polarity is set by the SDVO commands, using 1592 * struct intel_sdvo_dtd. */ 1593 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; 1594 if (DISPLAY_VER(dev_priv) < 5) 1595 sdvox |= SDVO_BORDER_ENABLE; 1596 } else { 1597 sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1598 if (intel_sdvo->port == PORT_B) 1599 sdvox &= SDVOB_PRESERVE_MASK; 1600 else 1601 sdvox &= SDVOC_PRESERVE_MASK; 1602 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1603 } 1604 1605 if (HAS_PCH_CPT(dev_priv)) 1606 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1607 else 1608 sdvox |= SDVO_PIPE_SEL(crtc->pipe); 1609 1610 if (DISPLAY_VER(dev_priv) >= 4) { 1611 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1612 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 1613 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 1614 /* done in crtc_mode_set as it lives inside the dpll register */ 1615 } else { 1616 sdvox |= (crtc_state->pixel_multiplier - 1) 1617 << SDVO_PORT_MULTIPLY_SHIFT; 1618 } 1619 1620 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && 1621 DISPLAY_VER(dev_priv) < 5) 1622 sdvox |= SDVO_STALL_SELECT; 1623 intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1624 } 1625 1626 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) 1627 { 1628 struct intel_sdvo_connector *intel_sdvo_connector = 1629 to_intel_sdvo_connector(&connector->base); 1630 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1631 u16 active_outputs = 0; 1632 1633 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1634 1635 return active_outputs & intel_sdvo_connector->output_flag; 1636 } 1637 1638 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, 1639 i915_reg_t sdvo_reg, enum pipe *pipe) 1640 { 1641 u32 val; 1642 1643 val = intel_de_read(dev_priv, sdvo_reg); 1644 1645 /* asserts want to know the pipe even if the port is disabled */ 1646 if (HAS_PCH_CPT(dev_priv)) 1647 *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT; 1648 else if (IS_CHERRYVIEW(dev_priv)) 1649 *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV; 1650 else 1651 *pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT; 1652 1653 return val & SDVO_ENABLE; 1654 } 1655 1656 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, 1657 enum pipe *pipe) 1658 { 1659 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1660 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1661 u16 active_outputs = 0; 1662 bool ret; 1663 1664 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1665 1666 ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe); 1667 1668 return ret || active_outputs; 1669 } 1670 1671 static void intel_sdvo_get_config(struct intel_encoder *encoder, 1672 struct intel_crtc_state *pipe_config) 1673 { 1674 struct drm_device *dev = encoder->base.dev; 1675 struct drm_i915_private *dev_priv = to_i915(dev); 1676 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1677 struct intel_sdvo_dtd dtd; 1678 int encoder_pixel_multiplier = 0; 1679 int dotclock; 1680 u32 flags = 0, sdvox; 1681 u8 val; 1682 bool ret; 1683 1684 pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO); 1685 1686 sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1687 1688 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1689 if (!ret) { 1690 /* 1691 * Some sdvo encoders are not spec compliant and don't 1692 * implement the mandatory get_timings function. 1693 */ 1694 drm_dbg(&dev_priv->drm, "failed to retrieve SDVO DTD\n"); 1695 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; 1696 } else { 1697 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1698 flags |= DRM_MODE_FLAG_PHSYNC; 1699 else 1700 flags |= DRM_MODE_FLAG_NHSYNC; 1701 1702 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1703 flags |= DRM_MODE_FLAG_PVSYNC; 1704 else 1705 flags |= DRM_MODE_FLAG_NVSYNC; 1706 } 1707 1708 pipe_config->hw.adjusted_mode.flags |= flags; 1709 1710 /* 1711 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in 1712 * the sdvo port register, on all other platforms it is part of the dpll 1713 * state. Since the general pipe state readout happens before the 1714 * encoder->get_config we so already have a valid pixel multplier on all 1715 * other platfroms. 1716 */ 1717 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 1718 pipe_config->pixel_multiplier = 1719 ((sdvox & SDVO_PORT_MULTIPLY_MASK) 1720 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1721 } 1722 1723 dotclock = pipe_config->port_clock; 1724 1725 if (pipe_config->pixel_multiplier) 1726 dotclock /= pipe_config->pixel_multiplier; 1727 1728 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1729 1730 /* Cross check the port pixel multiplier with the sdvo encoder state. */ 1731 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, 1732 &val, 1)) { 1733 switch (val) { 1734 case SDVO_CLOCK_RATE_MULT_1X: 1735 encoder_pixel_multiplier = 1; 1736 break; 1737 case SDVO_CLOCK_RATE_MULT_2X: 1738 encoder_pixel_multiplier = 2; 1739 break; 1740 case SDVO_CLOCK_RATE_MULT_4X: 1741 encoder_pixel_multiplier = 4; 1742 break; 1743 } 1744 } 1745 1746 drm_WARN(dev, 1747 encoder_pixel_multiplier != pipe_config->pixel_multiplier, 1748 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", 1749 pipe_config->pixel_multiplier, encoder_pixel_multiplier); 1750 1751 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY, 1752 &val, 1)) { 1753 if (val == SDVO_COLORIMETRY_RGB220) 1754 pipe_config->limited_color_range = true; 1755 } 1756 1757 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, 1758 &val, 1)) { 1759 if (val & SDVO_AUDIO_PRESENCE_DETECT) 1760 pipe_config->has_audio = true; 1761 } 1762 1763 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, 1764 &val, 1)) { 1765 if (val == SDVO_ENCODE_HDMI) 1766 pipe_config->has_hdmi_sink = true; 1767 } 1768 1769 intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config); 1770 1771 intel_sdvo_get_eld(intel_sdvo, pipe_config); 1772 } 1773 1774 static void intel_sdvo_disable_audio(struct intel_sdvo *intel_sdvo) 1775 { 1776 intel_sdvo_set_audio_state(intel_sdvo, 0); 1777 } 1778 1779 static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo, 1780 const struct intel_crtc_state *crtc_state, 1781 const struct drm_connector_state *conn_state) 1782 { 1783 const u8 *eld = crtc_state->eld; 1784 1785 intel_sdvo_set_audio_state(intel_sdvo, 0); 1786 1787 intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD, 1788 SDVO_HBUF_TX_DISABLED, 1789 eld, drm_eld_size(eld)); 1790 1791 intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID | 1792 SDVO_AUDIO_PRESENCE_DETECT); 1793 } 1794 1795 static void intel_disable_sdvo(struct intel_atomic_state *state, 1796 struct intel_encoder *encoder, 1797 const struct intel_crtc_state *old_crtc_state, 1798 const struct drm_connector_state *conn_state) 1799 { 1800 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1801 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1802 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1803 u32 temp; 1804 1805 if (old_crtc_state->has_audio) 1806 intel_sdvo_disable_audio(intel_sdvo); 1807 1808 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1809 if (0) 1810 intel_sdvo_set_encoder_power_state(intel_sdvo, 1811 DRM_MODE_DPMS_OFF); 1812 1813 temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1814 1815 temp &= ~SDVO_ENABLE; 1816 intel_sdvo_write_sdvox(intel_sdvo, temp); 1817 1818 /* 1819 * HW workaround for IBX, we need to move the port 1820 * to transcoder A after disabling it to allow the 1821 * matching DP port to be enabled on transcoder A. 1822 */ 1823 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 1824 /* 1825 * We get CPU/PCH FIFO underruns on the other pipe when 1826 * doing the workaround. Sweep them under the rug. 1827 */ 1828 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1829 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1830 1831 temp &= ~SDVO_PIPE_SEL_MASK; 1832 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 1833 intel_sdvo_write_sdvox(intel_sdvo, temp); 1834 1835 temp &= ~SDVO_ENABLE; 1836 intel_sdvo_write_sdvox(intel_sdvo, temp); 1837 1838 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 1839 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1840 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1841 } 1842 } 1843 1844 static void pch_disable_sdvo(struct intel_atomic_state *state, 1845 struct intel_encoder *encoder, 1846 const struct intel_crtc_state *old_crtc_state, 1847 const struct drm_connector_state *old_conn_state) 1848 { 1849 } 1850 1851 static void pch_post_disable_sdvo(struct intel_atomic_state *state, 1852 struct intel_encoder *encoder, 1853 const struct intel_crtc_state *old_crtc_state, 1854 const struct drm_connector_state *old_conn_state) 1855 { 1856 intel_disable_sdvo(state, encoder, old_crtc_state, old_conn_state); 1857 } 1858 1859 static void intel_enable_sdvo(struct intel_atomic_state *state, 1860 struct intel_encoder *encoder, 1861 const struct intel_crtc_state *pipe_config, 1862 const struct drm_connector_state *conn_state) 1863 { 1864 struct drm_device *dev = encoder->base.dev; 1865 struct drm_i915_private *dev_priv = to_i915(dev); 1866 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1867 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1868 u32 temp; 1869 bool input1, input2; 1870 int i; 1871 bool success; 1872 1873 temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1874 temp |= SDVO_ENABLE; 1875 intel_sdvo_write_sdvox(intel_sdvo, temp); 1876 1877 for (i = 0; i < 2; i++) 1878 intel_crtc_wait_for_next_vblank(crtc); 1879 1880 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1881 /* 1882 * Warn if the device reported failure to sync. 1883 * 1884 * A lot of SDVO devices fail to notify of sync, but it's 1885 * a given it the status is a success, we succeeded. 1886 */ 1887 if (success && !input1) { 1888 drm_dbg_kms(&dev_priv->drm, 1889 "First %s output reported failure to " 1890 "sync\n", SDVO_NAME(intel_sdvo)); 1891 } 1892 1893 if (0) 1894 intel_sdvo_set_encoder_power_state(intel_sdvo, 1895 DRM_MODE_DPMS_ON); 1896 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1897 1898 if (pipe_config->has_audio) 1899 intel_sdvo_enable_audio(intel_sdvo, pipe_config, conn_state); 1900 } 1901 1902 static enum drm_mode_status 1903 intel_sdvo_mode_valid(struct drm_connector *connector, 1904 struct drm_display_mode *mode) 1905 { 1906 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 1907 struct intel_sdvo_connector *intel_sdvo_connector = 1908 to_intel_sdvo_connector(connector); 1909 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 1910 bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo, connector->state); 1911 int clock = mode->clock; 1912 1913 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1914 return MODE_NO_DBLESCAN; 1915 1916 if (clock > max_dotclk) 1917 return MODE_CLOCK_HIGH; 1918 1919 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1920 if (!has_hdmi_sink) 1921 return MODE_CLOCK_LOW; 1922 clock *= 2; 1923 } 1924 1925 if (intel_sdvo->pixel_clock_min > clock) 1926 return MODE_CLOCK_LOW; 1927 1928 if (intel_sdvo->pixel_clock_max < clock) 1929 return MODE_CLOCK_HIGH; 1930 1931 if (IS_LVDS(intel_sdvo_connector)) { 1932 enum drm_mode_status status; 1933 1934 status = intel_panel_mode_valid(&intel_sdvo_connector->base, mode); 1935 if (status != MODE_OK) 1936 return status; 1937 } 1938 1939 return MODE_OK; 1940 } 1941 1942 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1943 { 1944 BUILD_BUG_ON(sizeof(*caps) != 8); 1945 if (!intel_sdvo_get_value(intel_sdvo, 1946 SDVO_CMD_GET_DEVICE_CAPS, 1947 caps, sizeof(*caps))) 1948 return false; 1949 1950 DRM_DEBUG_KMS("SDVO capabilities:\n" 1951 " vendor_id: %d\n" 1952 " device_id: %d\n" 1953 " device_rev_id: %d\n" 1954 " sdvo_version_major: %d\n" 1955 " sdvo_version_minor: %d\n" 1956 " sdvo_inputs_mask: %d\n" 1957 " smooth_scaling: %d\n" 1958 " sharp_scaling: %d\n" 1959 " up_scaling: %d\n" 1960 " down_scaling: %d\n" 1961 " stall_support: %d\n" 1962 " output_flags: %d\n", 1963 caps->vendor_id, 1964 caps->device_id, 1965 caps->device_rev_id, 1966 caps->sdvo_version_major, 1967 caps->sdvo_version_minor, 1968 caps->sdvo_inputs_mask, 1969 caps->smooth_scaling, 1970 caps->sharp_scaling, 1971 caps->up_scaling, 1972 caps->down_scaling, 1973 caps->stall_support, 1974 caps->output_flags); 1975 1976 return true; 1977 } 1978 1979 static u8 intel_sdvo_get_colorimetry_cap(struct intel_sdvo *intel_sdvo) 1980 { 1981 u8 cap; 1982 1983 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY_CAP, 1984 &cap, sizeof(cap))) 1985 return SDVO_COLORIMETRY_RGB256; 1986 1987 return cap; 1988 } 1989 1990 static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) 1991 { 1992 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 1993 u16 hotplug; 1994 1995 if (!I915_HAS_HOTPLUG(dev_priv)) 1996 return 0; 1997 1998 /* 1999 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise 2000 * on the line. 2001 */ 2002 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) 2003 return 0; 2004 2005 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, 2006 &hotplug, sizeof(hotplug))) 2007 return 0; 2008 2009 return hotplug; 2010 } 2011 2012 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) 2013 { 2014 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 2015 2016 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, 2017 &intel_sdvo->hotplug_active, 2); 2018 } 2019 2020 static enum intel_hotplug_state 2021 intel_sdvo_hotplug(struct intel_encoder *encoder, 2022 struct intel_connector *connector) 2023 { 2024 intel_sdvo_enable_hotplug(encoder); 2025 2026 return intel_encoder_hotplug(encoder, connector); 2027 } 2028 2029 static bool 2030 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) 2031 { 2032 /* Is there more than one type of output? */ 2033 return hweight16(intel_sdvo->caps.output_flags) > 1; 2034 } 2035 2036 static struct edid * 2037 intel_sdvo_get_edid(struct drm_connector *connector) 2038 { 2039 struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2040 return drm_get_edid(connector, &sdvo->ddc); 2041 } 2042 2043 /* Mac mini hack -- use the same DDC as the analog connector */ 2044 static struct edid * 2045 intel_sdvo_get_analog_edid(struct drm_connector *connector) 2046 { 2047 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2048 2049 return drm_get_edid(connector, 2050 intel_gmbus_get_adapter(dev_priv, 2051 dev_priv->display.vbt.crt_ddc_pin)); 2052 } 2053 2054 static enum drm_connector_status 2055 intel_sdvo_tmds_sink_detect(struct drm_connector *connector) 2056 { 2057 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2058 struct intel_sdvo_connector *intel_sdvo_connector = 2059 to_intel_sdvo_connector(connector); 2060 enum drm_connector_status status; 2061 struct edid *edid; 2062 2063 edid = intel_sdvo_get_edid(connector); 2064 2065 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { 2066 u8 ddc, saved_ddc = intel_sdvo->ddc_bus; 2067 2068 /* 2069 * Don't use the 1 as the argument of DDC bus switch to get 2070 * the EDID. It is used for SDVO SPD ROM. 2071 */ 2072 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { 2073 intel_sdvo->ddc_bus = ddc; 2074 edid = intel_sdvo_get_edid(connector); 2075 if (edid) 2076 break; 2077 } 2078 /* 2079 * If we found the EDID on the other bus, 2080 * assume that is the correct DDC bus. 2081 */ 2082 if (edid == NULL) 2083 intel_sdvo->ddc_bus = saved_ddc; 2084 } 2085 2086 /* 2087 * When there is no edid and no monitor is connected with VGA 2088 * port, try to use the CRT ddc to read the EDID for DVI-connector. 2089 */ 2090 if (edid == NULL) 2091 edid = intel_sdvo_get_analog_edid(connector); 2092 2093 status = connector_status_unknown; 2094 if (edid != NULL) { 2095 /* DDC bus is shared, match EDID to connector type */ 2096 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 2097 status = connector_status_connected; 2098 if (intel_sdvo_connector->is_hdmi) { 2099 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); 2100 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); 2101 } 2102 } else 2103 status = connector_status_disconnected; 2104 kfree(edid); 2105 } 2106 2107 return status; 2108 } 2109 2110 static bool 2111 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, 2112 struct edid *edid) 2113 { 2114 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 2115 bool connector_is_digital = !!IS_DIGITAL(sdvo); 2116 2117 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", 2118 connector_is_digital, monitor_is_digital); 2119 return connector_is_digital == monitor_is_digital; 2120 } 2121 2122 static enum drm_connector_status 2123 intel_sdvo_detect(struct drm_connector *connector, bool force) 2124 { 2125 struct drm_i915_private *i915 = to_i915(connector->dev); 2126 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2127 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2128 enum drm_connector_status ret; 2129 u16 response; 2130 2131 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2132 connector->base.id, connector->name); 2133 2134 if (!INTEL_DISPLAY_ENABLED(i915)) 2135 return connector_status_disconnected; 2136 2137 if (!intel_sdvo_get_value(intel_sdvo, 2138 SDVO_CMD_GET_ATTACHED_DISPLAYS, 2139 &response, 2)) 2140 return connector_status_unknown; 2141 2142 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", 2143 response & 0xff, response >> 8, 2144 intel_sdvo_connector->output_flag); 2145 2146 if (response == 0) 2147 return connector_status_disconnected; 2148 2149 intel_sdvo->attached_output = response; 2150 2151 intel_sdvo->has_hdmi_monitor = false; 2152 intel_sdvo->has_hdmi_audio = false; 2153 2154 if ((intel_sdvo_connector->output_flag & response) == 0) 2155 ret = connector_status_disconnected; 2156 else if (IS_TMDS(intel_sdvo_connector)) 2157 ret = intel_sdvo_tmds_sink_detect(connector); 2158 else { 2159 struct edid *edid; 2160 2161 /* if we have an edid check it matches the connection */ 2162 edid = intel_sdvo_get_edid(connector); 2163 if (edid == NULL) 2164 edid = intel_sdvo_get_analog_edid(connector); 2165 if (edid != NULL) { 2166 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, 2167 edid)) 2168 ret = connector_status_connected; 2169 else 2170 ret = connector_status_disconnected; 2171 2172 kfree(edid); 2173 } else 2174 ret = connector_status_connected; 2175 } 2176 2177 return ret; 2178 } 2179 2180 static int intel_sdvo_get_ddc_modes(struct drm_connector *connector) 2181 { 2182 int num_modes = 0; 2183 struct edid *edid; 2184 2185 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2186 connector->base.id, connector->name); 2187 2188 /* set the bus switch and get the modes */ 2189 edid = intel_sdvo_get_edid(connector); 2190 2191 /* 2192 * Mac mini hack. On this device, the DVI-I connector shares one DDC 2193 * link between analog and digital outputs. So, if the regular SDVO 2194 * DDC fails, check to see if the analog output is disconnected, in 2195 * which case we'll look there for the digital DDC data. 2196 */ 2197 if (!edid) 2198 edid = intel_sdvo_get_analog_edid(connector); 2199 2200 if (!edid) 2201 return 0; 2202 2203 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), 2204 edid)) 2205 num_modes += intel_connector_update_modes(connector, edid); 2206 2207 kfree(edid); 2208 2209 return num_modes; 2210 } 2211 2212 /* 2213 * Set of SDVO TV modes. 2214 * Note! This is in reply order (see loop in get_tv_modes). 2215 * XXX: all 60Hz refresh? 2216 */ 2217 static const struct drm_display_mode sdvo_tv_modes[] = { 2218 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 2219 416, 0, 200, 201, 232, 233, 0, 2220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2221 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 2222 416, 0, 240, 241, 272, 273, 0, 2223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2224 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 2225 496, 0, 300, 301, 332, 333, 0, 2226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2227 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 2228 736, 0, 350, 351, 382, 383, 0, 2229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2230 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 2231 736, 0, 400, 401, 432, 433, 0, 2232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2233 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 2234 736, 0, 480, 481, 512, 513, 0, 2235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2236 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 2237 800, 0, 480, 481, 512, 513, 0, 2238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2239 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 2240 800, 0, 576, 577, 608, 609, 0, 2241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2242 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 2243 816, 0, 350, 351, 382, 383, 0, 2244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2245 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 2246 816, 0, 400, 401, 432, 433, 0, 2247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2248 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 2249 816, 0, 480, 481, 512, 513, 0, 2250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2251 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 2252 816, 0, 540, 541, 572, 573, 0, 2253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2254 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 2255 816, 0, 576, 577, 608, 609, 0, 2256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2257 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 2258 864, 0, 576, 577, 608, 609, 0, 2259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2260 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 2261 896, 0, 600, 601, 632, 633, 0, 2262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2263 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 2264 928, 0, 624, 625, 656, 657, 0, 2265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2266 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 2267 1016, 0, 766, 767, 798, 799, 0, 2268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2269 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 2270 1120, 0, 768, 769, 800, 801, 0, 2271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2272 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 2273 1376, 0, 1024, 1025, 1056, 1057, 0, 2274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2275 }; 2276 2277 static int intel_sdvo_get_tv_modes(struct drm_connector *connector) 2278 { 2279 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2280 const struct drm_connector_state *conn_state = connector->state; 2281 struct intel_sdvo_sdtv_resolution_request tv_res; 2282 u32 reply = 0, format_map = 0; 2283 int num_modes = 0; 2284 int i; 2285 2286 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2287 connector->base.id, connector->name); 2288 2289 /* 2290 * Read the list of supported input resolutions for the selected TV 2291 * format. 2292 */ 2293 format_map = 1 << conn_state->tv.mode; 2294 memcpy(&tv_res, &format_map, 2295 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 2296 2297 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) 2298 return 0; 2299 2300 BUILD_BUG_ON(sizeof(tv_res) != 3); 2301 if (!intel_sdvo_write_cmd(intel_sdvo, 2302 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 2303 &tv_res, sizeof(tv_res))) 2304 return 0; 2305 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 2306 return 0; 2307 2308 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) { 2309 if (reply & (1 << i)) { 2310 struct drm_display_mode *nmode; 2311 nmode = drm_mode_duplicate(connector->dev, 2312 &sdvo_tv_modes[i]); 2313 if (nmode) { 2314 drm_mode_probed_add(connector, nmode); 2315 num_modes++; 2316 } 2317 } 2318 } 2319 2320 return num_modes; 2321 } 2322 2323 static int intel_sdvo_get_lvds_modes(struct drm_connector *connector) 2324 { 2325 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2326 2327 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 2328 connector->base.id, connector->name); 2329 2330 return intel_panel_get_modes(to_intel_connector(connector)); 2331 } 2332 2333 static int intel_sdvo_get_modes(struct drm_connector *connector) 2334 { 2335 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2336 2337 if (IS_TV(intel_sdvo_connector)) 2338 return intel_sdvo_get_tv_modes(connector); 2339 else if (IS_LVDS(intel_sdvo_connector)) 2340 return intel_sdvo_get_lvds_modes(connector); 2341 else 2342 return intel_sdvo_get_ddc_modes(connector); 2343 } 2344 2345 static int 2346 intel_sdvo_connector_atomic_get_property(struct drm_connector *connector, 2347 const struct drm_connector_state *state, 2348 struct drm_property *property, 2349 u64 *val) 2350 { 2351 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2352 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state); 2353 2354 if (property == intel_sdvo_connector->tv_format) { 2355 int i; 2356 2357 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2358 if (state->tv.mode == intel_sdvo_connector->tv_format_supported[i]) { 2359 *val = i; 2360 2361 return 0; 2362 } 2363 2364 drm_WARN_ON(connector->dev, 1); 2365 *val = 0; 2366 } else if (property == intel_sdvo_connector->top || 2367 property == intel_sdvo_connector->bottom) 2368 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v; 2369 else if (property == intel_sdvo_connector->left || 2370 property == intel_sdvo_connector->right) 2371 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h; 2372 else if (property == intel_sdvo_connector->hpos) 2373 *val = sdvo_state->tv.hpos; 2374 else if (property == intel_sdvo_connector->vpos) 2375 *val = sdvo_state->tv.vpos; 2376 else if (property == intel_sdvo_connector->saturation) 2377 *val = state->tv.saturation; 2378 else if (property == intel_sdvo_connector->contrast) 2379 *val = state->tv.contrast; 2380 else if (property == intel_sdvo_connector->hue) 2381 *val = state->tv.hue; 2382 else if (property == intel_sdvo_connector->brightness) 2383 *val = state->tv.brightness; 2384 else if (property == intel_sdvo_connector->sharpness) 2385 *val = sdvo_state->tv.sharpness; 2386 else if (property == intel_sdvo_connector->flicker_filter) 2387 *val = sdvo_state->tv.flicker_filter; 2388 else if (property == intel_sdvo_connector->flicker_filter_2d) 2389 *val = sdvo_state->tv.flicker_filter_2d; 2390 else if (property == intel_sdvo_connector->flicker_filter_adaptive) 2391 *val = sdvo_state->tv.flicker_filter_adaptive; 2392 else if (property == intel_sdvo_connector->tv_chroma_filter) 2393 *val = sdvo_state->tv.chroma_filter; 2394 else if (property == intel_sdvo_connector->tv_luma_filter) 2395 *val = sdvo_state->tv.luma_filter; 2396 else if (property == intel_sdvo_connector->dot_crawl) 2397 *val = sdvo_state->tv.dot_crawl; 2398 else 2399 return intel_digital_connector_atomic_get_property(connector, state, property, val); 2400 2401 return 0; 2402 } 2403 2404 static int 2405 intel_sdvo_connector_atomic_set_property(struct drm_connector *connector, 2406 struct drm_connector_state *state, 2407 struct drm_property *property, 2408 u64 val) 2409 { 2410 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2411 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state); 2412 2413 if (property == intel_sdvo_connector->tv_format) { 2414 state->tv.mode = intel_sdvo_connector->tv_format_supported[val]; 2415 2416 if (state->crtc) { 2417 struct drm_crtc_state *crtc_state = 2418 drm_atomic_get_new_crtc_state(state->state, state->crtc); 2419 2420 crtc_state->connectors_changed = true; 2421 } 2422 } else if (property == intel_sdvo_connector->top || 2423 property == intel_sdvo_connector->bottom) 2424 /* Cannot set these independent from each other */ 2425 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val; 2426 else if (property == intel_sdvo_connector->left || 2427 property == intel_sdvo_connector->right) 2428 /* Cannot set these independent from each other */ 2429 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val; 2430 else if (property == intel_sdvo_connector->hpos) 2431 sdvo_state->tv.hpos = val; 2432 else if (property == intel_sdvo_connector->vpos) 2433 sdvo_state->tv.vpos = val; 2434 else if (property == intel_sdvo_connector->saturation) 2435 state->tv.saturation = val; 2436 else if (property == intel_sdvo_connector->contrast) 2437 state->tv.contrast = val; 2438 else if (property == intel_sdvo_connector->hue) 2439 state->tv.hue = val; 2440 else if (property == intel_sdvo_connector->brightness) 2441 state->tv.brightness = val; 2442 else if (property == intel_sdvo_connector->sharpness) 2443 sdvo_state->tv.sharpness = val; 2444 else if (property == intel_sdvo_connector->flicker_filter) 2445 sdvo_state->tv.flicker_filter = val; 2446 else if (property == intel_sdvo_connector->flicker_filter_2d) 2447 sdvo_state->tv.flicker_filter_2d = val; 2448 else if (property == intel_sdvo_connector->flicker_filter_adaptive) 2449 sdvo_state->tv.flicker_filter_adaptive = val; 2450 else if (property == intel_sdvo_connector->tv_chroma_filter) 2451 sdvo_state->tv.chroma_filter = val; 2452 else if (property == intel_sdvo_connector->tv_luma_filter) 2453 sdvo_state->tv.luma_filter = val; 2454 else if (property == intel_sdvo_connector->dot_crawl) 2455 sdvo_state->tv.dot_crawl = val; 2456 else 2457 return intel_digital_connector_atomic_set_property(connector, state, property, val); 2458 2459 return 0; 2460 } 2461 2462 static int 2463 intel_sdvo_connector_register(struct drm_connector *connector) 2464 { 2465 struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2466 int ret; 2467 2468 ret = intel_connector_register(connector); 2469 if (ret) 2470 return ret; 2471 2472 return sysfs_create_link(&connector->kdev->kobj, 2473 &sdvo->ddc.dev.kobj, 2474 sdvo->ddc.dev.kobj.name); 2475 } 2476 2477 static void 2478 intel_sdvo_connector_unregister(struct drm_connector *connector) 2479 { 2480 struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2481 2482 sysfs_remove_link(&connector->kdev->kobj, 2483 sdvo->ddc.dev.kobj.name); 2484 intel_connector_unregister(connector); 2485 } 2486 2487 static struct drm_connector_state * 2488 intel_sdvo_connector_duplicate_state(struct drm_connector *connector) 2489 { 2490 struct intel_sdvo_connector_state *state; 2491 2492 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL); 2493 if (!state) 2494 return NULL; 2495 2496 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base); 2497 return &state->base.base; 2498 } 2499 2500 static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 2501 .detect = intel_sdvo_detect, 2502 .fill_modes = drm_helper_probe_single_connector_modes, 2503 .atomic_get_property = intel_sdvo_connector_atomic_get_property, 2504 .atomic_set_property = intel_sdvo_connector_atomic_set_property, 2505 .late_register = intel_sdvo_connector_register, 2506 .early_unregister = intel_sdvo_connector_unregister, 2507 .destroy = intel_connector_destroy, 2508 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2509 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state, 2510 }; 2511 2512 static int intel_sdvo_atomic_check(struct drm_connector *conn, 2513 struct drm_atomic_state *state) 2514 { 2515 struct drm_connector_state *new_conn_state = 2516 drm_atomic_get_new_connector_state(state, conn); 2517 struct drm_connector_state *old_conn_state = 2518 drm_atomic_get_old_connector_state(state, conn); 2519 struct intel_sdvo_connector_state *old_state = 2520 to_intel_sdvo_connector_state(old_conn_state); 2521 struct intel_sdvo_connector_state *new_state = 2522 to_intel_sdvo_connector_state(new_conn_state); 2523 2524 if (new_conn_state->crtc && 2525 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) || 2526 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) { 2527 struct drm_crtc_state *crtc_state = 2528 drm_atomic_get_new_crtc_state(state, 2529 new_conn_state->crtc); 2530 2531 crtc_state->connectors_changed = true; 2532 } 2533 2534 return intel_digital_connector_atomic_check(conn, state); 2535 } 2536 2537 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 2538 .get_modes = intel_sdvo_get_modes, 2539 .mode_valid = intel_sdvo_mode_valid, 2540 .atomic_check = intel_sdvo_atomic_check, 2541 }; 2542 2543 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) 2544 { 2545 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)); 2546 2547 i2c_del_adapter(&intel_sdvo->ddc); 2548 intel_encoder_destroy(encoder); 2549 } 2550 2551 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 2552 .destroy = intel_sdvo_enc_destroy, 2553 }; 2554 2555 static void 2556 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) 2557 { 2558 u16 mask = 0; 2559 unsigned int num_bits; 2560 2561 /* 2562 * Make a mask of outputs less than or equal to our own priority in the 2563 * list. 2564 */ 2565 switch (sdvo->controlled_output) { 2566 case SDVO_OUTPUT_LVDS1: 2567 mask |= SDVO_OUTPUT_LVDS1; 2568 fallthrough; 2569 case SDVO_OUTPUT_LVDS0: 2570 mask |= SDVO_OUTPUT_LVDS0; 2571 fallthrough; 2572 case SDVO_OUTPUT_TMDS1: 2573 mask |= SDVO_OUTPUT_TMDS1; 2574 fallthrough; 2575 case SDVO_OUTPUT_TMDS0: 2576 mask |= SDVO_OUTPUT_TMDS0; 2577 fallthrough; 2578 case SDVO_OUTPUT_RGB1: 2579 mask |= SDVO_OUTPUT_RGB1; 2580 fallthrough; 2581 case SDVO_OUTPUT_RGB0: 2582 mask |= SDVO_OUTPUT_RGB0; 2583 break; 2584 } 2585 2586 /* Count bits to find what number we are in the priority list. */ 2587 mask &= sdvo->caps.output_flags; 2588 num_bits = hweight16(mask); 2589 /* If more than 3 outputs, default to DDC bus 3 for now. */ 2590 if (num_bits > 3) 2591 num_bits = 3; 2592 2593 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 2594 sdvo->ddc_bus = 1 << num_bits; 2595 } 2596 2597 /* 2598 * Choose the appropriate DDC bus for control bus switch command for this 2599 * SDVO output based on the controlled output. 2600 * 2601 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 2602 * outputs, then LVDS outputs. 2603 */ 2604 static void 2605 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, 2606 struct intel_sdvo *sdvo) 2607 { 2608 struct sdvo_device_mapping *mapping; 2609 2610 if (sdvo->port == PORT_B) 2611 mapping = &dev_priv->display.vbt.sdvo_mappings[0]; 2612 else 2613 mapping = &dev_priv->display.vbt.sdvo_mappings[1]; 2614 2615 if (mapping->initialized) 2616 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); 2617 else 2618 intel_sdvo_guess_ddc_bus(sdvo); 2619 } 2620 2621 static void 2622 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, 2623 struct intel_sdvo *sdvo) 2624 { 2625 struct sdvo_device_mapping *mapping; 2626 u8 pin; 2627 2628 if (sdvo->port == PORT_B) 2629 mapping = &dev_priv->display.vbt.sdvo_mappings[0]; 2630 else 2631 mapping = &dev_priv->display.vbt.sdvo_mappings[1]; 2632 2633 if (mapping->initialized && 2634 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin)) 2635 pin = mapping->i2c_pin; 2636 else 2637 pin = GMBUS_PIN_DPB; 2638 2639 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); 2640 2641 /* 2642 * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow 2643 * our code totally fails once we start using gmbus. Hence fall back to 2644 * bit banging for now. 2645 */ 2646 intel_gmbus_force_bit(sdvo->i2c, true); 2647 } 2648 2649 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ 2650 static void 2651 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) 2652 { 2653 intel_gmbus_force_bit(sdvo->i2c, false); 2654 } 2655 2656 static bool 2657 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo) 2658 { 2659 return intel_sdvo_check_supp_encode(intel_sdvo); 2660 } 2661 2662 static u8 2663 intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv, 2664 struct intel_sdvo *sdvo) 2665 { 2666 struct sdvo_device_mapping *my_mapping, *other_mapping; 2667 2668 if (sdvo->port == PORT_B) { 2669 my_mapping = &dev_priv->display.vbt.sdvo_mappings[0]; 2670 other_mapping = &dev_priv->display.vbt.sdvo_mappings[1]; 2671 } else { 2672 my_mapping = &dev_priv->display.vbt.sdvo_mappings[1]; 2673 other_mapping = &dev_priv->display.vbt.sdvo_mappings[0]; 2674 } 2675 2676 /* If the BIOS described our SDVO device, take advantage of it. */ 2677 if (my_mapping->slave_addr) 2678 return my_mapping->slave_addr; 2679 2680 /* 2681 * If the BIOS only described a different SDVO device, use the 2682 * address that it isn't using. 2683 */ 2684 if (other_mapping->slave_addr) { 2685 if (other_mapping->slave_addr == 0x70) 2686 return 0x72; 2687 else 2688 return 0x70; 2689 } 2690 2691 /* 2692 * No SDVO device info is found for another DVO port, 2693 * so use mapping assumption we had before BIOS parsing. 2694 */ 2695 if (sdvo->port == PORT_B) 2696 return 0x70; 2697 else 2698 return 0x72; 2699 } 2700 2701 static int 2702 intel_sdvo_connector_init(struct intel_sdvo_connector *connector, 2703 struct intel_sdvo *encoder) 2704 { 2705 struct drm_connector *drm_connector; 2706 int ret; 2707 2708 drm_connector = &connector->base.base; 2709 ret = drm_connector_init(encoder->base.base.dev, 2710 drm_connector, 2711 &intel_sdvo_connector_funcs, 2712 connector->base.base.connector_type); 2713 if (ret < 0) 2714 return ret; 2715 2716 drm_connector_helper_add(drm_connector, 2717 &intel_sdvo_connector_helper_funcs); 2718 2719 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 2720 connector->base.base.interlace_allowed = true; 2721 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; 2722 2723 intel_connector_attach_encoder(&connector->base, &encoder->base); 2724 2725 return 0; 2726 } 2727 2728 static void 2729 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, 2730 struct intel_sdvo_connector *connector) 2731 { 2732 intel_attach_force_audio_property(&connector->base.base); 2733 if (intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220) 2734 intel_attach_broadcast_rgb_property(&connector->base.base); 2735 intel_attach_aspect_ratio_property(&connector->base.base); 2736 } 2737 2738 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) 2739 { 2740 struct intel_sdvo_connector *sdvo_connector; 2741 struct intel_sdvo_connector_state *conn_state; 2742 2743 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL); 2744 if (!sdvo_connector) 2745 return NULL; 2746 2747 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL); 2748 if (!conn_state) { 2749 kfree(sdvo_connector); 2750 return NULL; 2751 } 2752 2753 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base, 2754 &conn_state->base.base); 2755 2756 INIT_LIST_HEAD(&sdvo_connector->base.panel.fixed_modes); 2757 2758 return sdvo_connector; 2759 } 2760 2761 static bool 2762 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, u16 type) 2763 { 2764 struct drm_encoder *encoder = &intel_sdvo->base.base; 2765 struct drm_connector *connector; 2766 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2767 struct intel_connector *intel_connector; 2768 struct intel_sdvo_connector *intel_sdvo_connector; 2769 2770 DRM_DEBUG_KMS("initialising DVI type 0x%x\n", type); 2771 2772 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2773 if (!intel_sdvo_connector) 2774 return false; 2775 2776 intel_sdvo_connector->output_flag = type; 2777 2778 intel_connector = &intel_sdvo_connector->base; 2779 connector = &intel_connector->base; 2780 if (intel_sdvo_get_hotplug_support(intel_sdvo) & 2781 intel_sdvo_connector->output_flag) { 2782 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; 2783 /* 2784 * Some SDVO devices have one-shot hotplug interrupts. 2785 * Ensure that they get re-enabled when an interrupt happens. 2786 */ 2787 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 2788 intel_encoder->hotplug = intel_sdvo_hotplug; 2789 intel_sdvo_enable_hotplug(intel_encoder); 2790 } else { 2791 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2792 } 2793 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2794 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2795 2796 if (intel_sdvo_is_hdmi_connector(intel_sdvo)) { 2797 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2798 intel_sdvo_connector->is_hdmi = true; 2799 } 2800 2801 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2802 kfree(intel_sdvo_connector); 2803 return false; 2804 } 2805 2806 if (intel_sdvo_connector->is_hdmi) 2807 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); 2808 2809 return true; 2810 } 2811 2812 static bool 2813 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, u16 type) 2814 { 2815 struct drm_encoder *encoder = &intel_sdvo->base.base; 2816 struct drm_connector *connector; 2817 struct intel_connector *intel_connector; 2818 struct intel_sdvo_connector *intel_sdvo_connector; 2819 2820 DRM_DEBUG_KMS("initialising TV type 0x%x\n", type); 2821 2822 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2823 if (!intel_sdvo_connector) 2824 return false; 2825 2826 intel_connector = &intel_sdvo_connector->base; 2827 connector = &intel_connector->base; 2828 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2829 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2830 2831 intel_sdvo_connector->output_flag = type; 2832 2833 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2834 kfree(intel_sdvo_connector); 2835 return false; 2836 } 2837 2838 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2839 goto err; 2840 2841 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2842 goto err; 2843 2844 return true; 2845 2846 err: 2847 intel_connector_destroy(connector); 2848 return false; 2849 } 2850 2851 static bool 2852 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, u16 type) 2853 { 2854 struct drm_encoder *encoder = &intel_sdvo->base.base; 2855 struct drm_connector *connector; 2856 struct intel_connector *intel_connector; 2857 struct intel_sdvo_connector *intel_sdvo_connector; 2858 2859 DRM_DEBUG_KMS("initialising analog type 0x%x\n", type); 2860 2861 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2862 if (!intel_sdvo_connector) 2863 return false; 2864 2865 intel_connector = &intel_sdvo_connector->base; 2866 connector = &intel_connector->base; 2867 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2868 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2869 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2870 2871 intel_sdvo_connector->output_flag = type; 2872 2873 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2874 kfree(intel_sdvo_connector); 2875 return false; 2876 } 2877 2878 return true; 2879 } 2880 2881 static bool 2882 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, u16 type) 2883 { 2884 struct drm_encoder *encoder = &intel_sdvo->base.base; 2885 struct drm_i915_private *i915 = to_i915(encoder->dev); 2886 struct drm_connector *connector; 2887 struct intel_connector *intel_connector; 2888 struct intel_sdvo_connector *intel_sdvo_connector; 2889 2890 DRM_DEBUG_KMS("initialising LVDS type 0x%x\n", type); 2891 2892 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2893 if (!intel_sdvo_connector) 2894 return false; 2895 2896 intel_connector = &intel_sdvo_connector->base; 2897 connector = &intel_connector->base; 2898 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2899 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2900 2901 intel_sdvo_connector->output_flag = type; 2902 2903 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2904 kfree(intel_sdvo_connector); 2905 return false; 2906 } 2907 2908 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2909 goto err; 2910 2911 intel_bios_init_panel_late(i915, &intel_connector->panel, NULL, NULL); 2912 2913 /* 2914 * Fetch modes from VBT. For SDVO prefer the VBT mode since some 2915 * SDVO->LVDS transcoders can't cope with the EDID mode. 2916 */ 2917 intel_panel_add_vbt_sdvo_fixed_mode(intel_connector); 2918 2919 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 2920 mutex_lock(&i915->drm.mode_config.mutex); 2921 2922 intel_ddc_get_modes(connector, &intel_sdvo->ddc); 2923 intel_panel_add_edid_fixed_modes(intel_connector, false); 2924 2925 mutex_unlock(&i915->drm.mode_config.mutex); 2926 } 2927 2928 intel_panel_init(intel_connector, NULL); 2929 2930 if (!intel_panel_preferred_fixed_mode(intel_connector)) 2931 goto err; 2932 2933 return true; 2934 2935 err: 2936 intel_connector_destroy(connector); 2937 return false; 2938 } 2939 2940 static u16 intel_sdvo_filter_output_flags(u16 flags) 2941 { 2942 flags &= SDVO_OUTPUT_MASK; 2943 2944 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2945 if (!(flags & SDVO_OUTPUT_TMDS0)) 2946 flags &= ~SDVO_OUTPUT_TMDS1; 2947 2948 if (!(flags & SDVO_OUTPUT_RGB0)) 2949 flags &= ~SDVO_OUTPUT_RGB1; 2950 2951 if (!(flags & SDVO_OUTPUT_LVDS0)) 2952 flags &= ~SDVO_OUTPUT_LVDS1; 2953 2954 return flags; 2955 } 2956 2957 static bool intel_sdvo_output_init(struct intel_sdvo *sdvo, u16 type) 2958 { 2959 if (type & SDVO_TMDS_MASK) 2960 return intel_sdvo_dvi_init(sdvo, type); 2961 else if (type & SDVO_TV_MASK) 2962 return intel_sdvo_tv_init(sdvo, type); 2963 else if (type & SDVO_RGB_MASK) 2964 return intel_sdvo_analog_init(sdvo, type); 2965 else if (type & SDVO_LVDS_MASK) 2966 return intel_sdvo_lvds_init(sdvo, type); 2967 else 2968 return false; 2969 } 2970 2971 static bool 2972 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo) 2973 { 2974 static const u16 probe_order[] = { 2975 SDVO_OUTPUT_TMDS0, 2976 SDVO_OUTPUT_TMDS1, 2977 /* TV has no XXX1 function block */ 2978 SDVO_OUTPUT_SVID0, 2979 SDVO_OUTPUT_CVBS0, 2980 SDVO_OUTPUT_YPRPB0, 2981 SDVO_OUTPUT_RGB0, 2982 SDVO_OUTPUT_RGB1, 2983 SDVO_OUTPUT_LVDS0, 2984 SDVO_OUTPUT_LVDS1, 2985 }; 2986 struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); 2987 u16 flags; 2988 int i; 2989 2990 flags = intel_sdvo_filter_output_flags(intel_sdvo->caps.output_flags); 2991 2992 if (flags == 0) { 2993 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%04x)\n", 2994 SDVO_NAME(intel_sdvo), intel_sdvo->caps.output_flags); 2995 return false; 2996 } 2997 2998 intel_sdvo->controlled_output = flags; 2999 3000 intel_sdvo_select_ddc_bus(i915, intel_sdvo); 3001 3002 for (i = 0; i < ARRAY_SIZE(probe_order); i++) { 3003 u16 type = flags & probe_order[i]; 3004 3005 if (!type) 3006 continue; 3007 3008 if (!intel_sdvo_output_init(intel_sdvo, type)) 3009 return false; 3010 } 3011 3012 intel_sdvo->base.pipe_mask = ~0; 3013 3014 return true; 3015 } 3016 3017 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) 3018 { 3019 struct drm_device *dev = intel_sdvo->base.base.dev; 3020 struct drm_connector *connector, *tmp; 3021 3022 list_for_each_entry_safe(connector, tmp, 3023 &dev->mode_config.connector_list, head) { 3024 if (intel_attached_encoder(to_intel_connector(connector)) == &intel_sdvo->base) { 3025 drm_connector_unregister(connector); 3026 intel_connector_destroy(connector); 3027 } 3028 } 3029 } 3030 3031 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 3032 struct intel_sdvo_connector *intel_sdvo_connector, 3033 int type) 3034 { 3035 struct drm_device *dev = intel_sdvo->base.base.dev; 3036 struct intel_sdvo_tv_format format; 3037 u32 format_map, i; 3038 3039 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 3040 return false; 3041 3042 BUILD_BUG_ON(sizeof(format) != 6); 3043 if (!intel_sdvo_get_value(intel_sdvo, 3044 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 3045 &format, sizeof(format))) 3046 return false; 3047 3048 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 3049 3050 if (format_map == 0) 3051 return false; 3052 3053 intel_sdvo_connector->format_supported_num = 0; 3054 for (i = 0 ; i < TV_FORMAT_NUM; i++) 3055 if (format_map & (1 << i)) 3056 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 3057 3058 3059 intel_sdvo_connector->tv_format = 3060 drm_property_create(dev, DRM_MODE_PROP_ENUM, 3061 "mode", intel_sdvo_connector->format_supported_num); 3062 if (!intel_sdvo_connector->tv_format) 3063 return false; 3064 3065 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 3066 drm_property_add_enum(intel_sdvo_connector->tv_format, i, 3067 tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 3068 3069 intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0]; 3070 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 3071 intel_sdvo_connector->tv_format, 0); 3072 return true; 3073 3074 } 3075 3076 #define _ENHANCEMENT(state_assignment, name, NAME) do { \ 3077 if (enhancements.name) { \ 3078 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 3079 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 3080 return false; \ 3081 intel_sdvo_connector->name = \ 3082 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ 3083 if (!intel_sdvo_connector->name) return false; \ 3084 state_assignment = response; \ 3085 drm_object_attach_property(&connector->base, \ 3086 intel_sdvo_connector->name, 0); \ 3087 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 3088 data_value[0], data_value[1], response); \ 3089 } \ 3090 } while (0) 3091 3092 #define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME) 3093 3094 static bool 3095 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 3096 struct intel_sdvo_connector *intel_sdvo_connector, 3097 struct intel_sdvo_enhancements_reply enhancements) 3098 { 3099 struct drm_device *dev = intel_sdvo->base.base.dev; 3100 struct drm_connector *connector = &intel_sdvo_connector->base.base; 3101 struct drm_connector_state *conn_state = connector->state; 3102 struct intel_sdvo_connector_state *sdvo_state = 3103 to_intel_sdvo_connector_state(conn_state); 3104 u16 response, data_value[2]; 3105 3106 /* when horizontal overscan is supported, Add the left/right property */ 3107 if (enhancements.overscan_h) { 3108 if (!intel_sdvo_get_value(intel_sdvo, 3109 SDVO_CMD_GET_MAX_OVERSCAN_H, 3110 &data_value, 4)) 3111 return false; 3112 3113 if (!intel_sdvo_get_value(intel_sdvo, 3114 SDVO_CMD_GET_OVERSCAN_H, 3115 &response, 2)) 3116 return false; 3117 3118 sdvo_state->tv.overscan_h = response; 3119 3120 intel_sdvo_connector->max_hscan = data_value[0]; 3121 intel_sdvo_connector->left = 3122 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); 3123 if (!intel_sdvo_connector->left) 3124 return false; 3125 3126 drm_object_attach_property(&connector->base, 3127 intel_sdvo_connector->left, 0); 3128 3129 intel_sdvo_connector->right = 3130 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); 3131 if (!intel_sdvo_connector->right) 3132 return false; 3133 3134 drm_object_attach_property(&connector->base, 3135 intel_sdvo_connector->right, 0); 3136 DRM_DEBUG_KMS("h_overscan: max %d, " 3137 "default %d, current %d\n", 3138 data_value[0], data_value[1], response); 3139 } 3140 3141 if (enhancements.overscan_v) { 3142 if (!intel_sdvo_get_value(intel_sdvo, 3143 SDVO_CMD_GET_MAX_OVERSCAN_V, 3144 &data_value, 4)) 3145 return false; 3146 3147 if (!intel_sdvo_get_value(intel_sdvo, 3148 SDVO_CMD_GET_OVERSCAN_V, 3149 &response, 2)) 3150 return false; 3151 3152 sdvo_state->tv.overscan_v = response; 3153 3154 intel_sdvo_connector->max_vscan = data_value[0]; 3155 intel_sdvo_connector->top = 3156 drm_property_create_range(dev, 0, 3157 "top_margin", 0, data_value[0]); 3158 if (!intel_sdvo_connector->top) 3159 return false; 3160 3161 drm_object_attach_property(&connector->base, 3162 intel_sdvo_connector->top, 0); 3163 3164 intel_sdvo_connector->bottom = 3165 drm_property_create_range(dev, 0, 3166 "bottom_margin", 0, data_value[0]); 3167 if (!intel_sdvo_connector->bottom) 3168 return false; 3169 3170 drm_object_attach_property(&connector->base, 3171 intel_sdvo_connector->bottom, 0); 3172 DRM_DEBUG_KMS("v_overscan: max %d, " 3173 "default %d, current %d\n", 3174 data_value[0], data_value[1], response); 3175 } 3176 3177 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS); 3178 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS); 3179 ENHANCEMENT(&conn_state->tv, saturation, SATURATION); 3180 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST); 3181 ENHANCEMENT(&conn_state->tv, hue, HUE); 3182 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS); 3183 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS); 3184 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER); 3185 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 3186 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D); 3187 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER); 3188 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER); 3189 3190 if (enhancements.dot_crawl) { 3191 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 3192 return false; 3193 3194 sdvo_state->tv.dot_crawl = response & 0x1; 3195 intel_sdvo_connector->dot_crawl = 3196 drm_property_create_range(dev, 0, "dot_crawl", 0, 1); 3197 if (!intel_sdvo_connector->dot_crawl) 3198 return false; 3199 3200 drm_object_attach_property(&connector->base, 3201 intel_sdvo_connector->dot_crawl, 0); 3202 DRM_DEBUG_KMS("dot crawl: current %d\n", response); 3203 } 3204 3205 return true; 3206 } 3207 3208 static bool 3209 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 3210 struct intel_sdvo_connector *intel_sdvo_connector, 3211 struct intel_sdvo_enhancements_reply enhancements) 3212 { 3213 struct drm_device *dev = intel_sdvo->base.base.dev; 3214 struct drm_connector *connector = &intel_sdvo_connector->base.base; 3215 u16 response, data_value[2]; 3216 3217 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS); 3218 3219 return true; 3220 } 3221 #undef ENHANCEMENT 3222 #undef _ENHANCEMENT 3223 3224 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 3225 struct intel_sdvo_connector *intel_sdvo_connector) 3226 { 3227 union { 3228 struct intel_sdvo_enhancements_reply reply; 3229 u16 response; 3230 } enhancements; 3231 3232 BUILD_BUG_ON(sizeof(enhancements) != 2); 3233 3234 if (!intel_sdvo_get_value(intel_sdvo, 3235 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 3236 &enhancements, sizeof(enhancements)) || 3237 enhancements.response == 0) { 3238 DRM_DEBUG_KMS("No enhancement is supported\n"); 3239 return true; 3240 } 3241 3242 if (IS_TV(intel_sdvo_connector)) 3243 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 3244 else if (IS_LVDS(intel_sdvo_connector)) 3245 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 3246 else 3247 return true; 3248 } 3249 3250 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, 3251 struct i2c_msg *msgs, 3252 int num) 3253 { 3254 struct intel_sdvo *sdvo = adapter->algo_data; 3255 3256 if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) 3257 return -EIO; 3258 3259 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); 3260 } 3261 3262 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) 3263 { 3264 struct intel_sdvo *sdvo = adapter->algo_data; 3265 return sdvo->i2c->algo->functionality(sdvo->i2c); 3266 } 3267 3268 static const struct i2c_algorithm intel_sdvo_ddc_proxy = { 3269 .master_xfer = intel_sdvo_ddc_proxy_xfer, 3270 .functionality = intel_sdvo_ddc_proxy_func 3271 }; 3272 3273 static void proxy_lock_bus(struct i2c_adapter *adapter, 3274 unsigned int flags) 3275 { 3276 struct intel_sdvo *sdvo = adapter->algo_data; 3277 sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags); 3278 } 3279 3280 static int proxy_trylock_bus(struct i2c_adapter *adapter, 3281 unsigned int flags) 3282 { 3283 struct intel_sdvo *sdvo = adapter->algo_data; 3284 return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags); 3285 } 3286 3287 static void proxy_unlock_bus(struct i2c_adapter *adapter, 3288 unsigned int flags) 3289 { 3290 struct intel_sdvo *sdvo = adapter->algo_data; 3291 sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags); 3292 } 3293 3294 static const struct i2c_lock_operations proxy_lock_ops = { 3295 .lock_bus = proxy_lock_bus, 3296 .trylock_bus = proxy_trylock_bus, 3297 .unlock_bus = proxy_unlock_bus, 3298 }; 3299 3300 static bool 3301 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, 3302 struct drm_i915_private *dev_priv) 3303 { 3304 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 3305 3306 sdvo->ddc.owner = THIS_MODULE; 3307 sdvo->ddc.class = I2C_CLASS_DDC; 3308 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); 3309 sdvo->ddc.dev.parent = &pdev->dev; 3310 sdvo->ddc.algo_data = sdvo; 3311 sdvo->ddc.algo = &intel_sdvo_ddc_proxy; 3312 sdvo->ddc.lock_ops = &proxy_lock_ops; 3313 3314 return i2c_add_adapter(&sdvo->ddc) == 0; 3315 } 3316 3317 static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv, 3318 enum port port) 3319 { 3320 if (HAS_PCH_SPLIT(dev_priv)) 3321 drm_WARN_ON(&dev_priv->drm, port != PORT_B); 3322 else 3323 drm_WARN_ON(&dev_priv->drm, port != PORT_B && port != PORT_C); 3324 } 3325 3326 bool intel_sdvo_init(struct drm_i915_private *dev_priv, 3327 i915_reg_t sdvo_reg, enum port port) 3328 { 3329 struct intel_encoder *intel_encoder; 3330 struct intel_sdvo *intel_sdvo; 3331 int i; 3332 3333 assert_sdvo_port_valid(dev_priv, port); 3334 3335 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); 3336 if (!intel_sdvo) 3337 return false; 3338 3339 intel_sdvo->sdvo_reg = sdvo_reg; 3340 intel_sdvo->port = port; 3341 intel_sdvo->slave_addr = 3342 intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1; 3343 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo); 3344 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv)) 3345 goto err_i2c_bus; 3346 3347 /* encoder type will be decided later */ 3348 intel_encoder = &intel_sdvo->base; 3349 intel_encoder->type = INTEL_OUTPUT_SDVO; 3350 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 3351 intel_encoder->port = port; 3352 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 3353 &intel_sdvo_enc_funcs, 0, 3354 "SDVO %c", port_name(port)); 3355 3356 /* Read the regs to test if we can talk to the device */ 3357 for (i = 0; i < 0x40; i++) { 3358 u8 byte; 3359 3360 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { 3361 drm_dbg_kms(&dev_priv->drm, 3362 "No SDVO device found on %s\n", 3363 SDVO_NAME(intel_sdvo)); 3364 goto err; 3365 } 3366 } 3367 3368 intel_encoder->compute_config = intel_sdvo_compute_config; 3369 if (HAS_PCH_SPLIT(dev_priv)) { 3370 intel_encoder->disable = pch_disable_sdvo; 3371 intel_encoder->post_disable = pch_post_disable_sdvo; 3372 } else { 3373 intel_encoder->disable = intel_disable_sdvo; 3374 } 3375 intel_encoder->pre_enable = intel_sdvo_pre_enable; 3376 intel_encoder->enable = intel_enable_sdvo; 3377 intel_encoder->get_hw_state = intel_sdvo_get_hw_state; 3378 intel_encoder->get_config = intel_sdvo_get_config; 3379 3380 /* In default case sdvo lvds is false */ 3381 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 3382 goto err; 3383 3384 intel_sdvo->colorimetry_cap = 3385 intel_sdvo_get_colorimetry_cap(intel_sdvo); 3386 3387 if (!intel_sdvo_output_setup(intel_sdvo)) { 3388 drm_dbg_kms(&dev_priv->drm, 3389 "SDVO output failed to setup on %s\n", 3390 SDVO_NAME(intel_sdvo)); 3391 /* Output_setup can leave behind connectors! */ 3392 goto err_output; 3393 } 3394 3395 /* 3396 * Only enable the hotplug irq if we need it, to work around noisy 3397 * hotplug lines. 3398 */ 3399 if (intel_sdvo->hotplug_active) { 3400 if (intel_sdvo->port == PORT_B) 3401 intel_encoder->hpd_pin = HPD_SDVO_B; 3402 else 3403 intel_encoder->hpd_pin = HPD_SDVO_C; 3404 } 3405 3406 /* 3407 * Cloning SDVO with anything is often impossible, since the SDVO 3408 * encoder can request a special input timing mode. And even if that's 3409 * not the case we have evidence that cloning a plain unscaled mode with 3410 * VGA doesn't really work. Furthermore the cloning flags are way too 3411 * simplistic anyway to express such constraints, so just give up on 3412 * cloning for SDVO encoders. 3413 */ 3414 intel_sdvo->base.cloneable = 0; 3415 3416 /* Set the input timing to the screen. Assume always input 0. */ 3417 if (!intel_sdvo_set_target_input(intel_sdvo)) 3418 goto err_output; 3419 3420 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 3421 &intel_sdvo->pixel_clock_min, 3422 &intel_sdvo->pixel_clock_max)) 3423 goto err_output; 3424 3425 drm_dbg_kms(&dev_priv->drm, "%s device VID/DID: %02X:%02X.%02X, " 3426 "clock range %dMHz - %dMHz, " 3427 "input 1: %c, input 2: %c, " 3428 "output 1: %c, output 2: %c\n", 3429 SDVO_NAME(intel_sdvo), 3430 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 3431 intel_sdvo->caps.device_rev_id, 3432 intel_sdvo->pixel_clock_min / 1000, 3433 intel_sdvo->pixel_clock_max / 1000, 3434 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 3435 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 3436 /* check currently supported outputs */ 3437 intel_sdvo->caps.output_flags & 3438 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0 | 3439 SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_SVID0 | 3440 SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_YPRPB0) ? 'Y' : 'N', 3441 intel_sdvo->caps.output_flags & 3442 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1 | 3443 SDVO_OUTPUT_LVDS1) ? 'Y' : 'N'); 3444 return true; 3445 3446 err_output: 3447 intel_sdvo_output_cleanup(intel_sdvo); 3448 3449 err: 3450 drm_encoder_cleanup(&intel_encoder->base); 3451 i2c_del_adapter(&intel_sdvo->ddc); 3452 err_i2c_bus: 3453 intel_sdvo_unselect_i2c_bus(intel_sdvo); 3454 kfree(intel_sdvo); 3455 3456 return false; 3457 } 3458