1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_PSR_REGS_H__ 7 #define __INTEL_PSR_REGS_H__ 8 9 #include "intel_display_reg_defs.h" 10 11 #define TRANS_EXITLINE(trans) _MMIO_TRANS2((trans), _TRANS_EXITLINE_A) 12 #define EXITLINE_ENABLE REG_BIT(31) 13 #define EXITLINE_MASK REG_GENMASK(12, 0) 14 #define EXITLINE_SHIFT 0 15 16 /* 17 * HSW+ eDP PSR registers 18 * 19 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one 20 * instance of it 21 */ 22 #define _SRD_CTL_A 0x60800 23 #define _SRD_CTL_EDP 0x6f800 24 #define EDP_PSR_CTL(tran) _MMIO_TRANS2(tran, _SRD_CTL_A) 25 #define EDP_PSR_ENABLE (1 << 31) 26 #define BDW_PSR_SINGLE_FRAME (1 << 30) 27 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */ 28 #define EDP_PSR_LINK_STANDBY (1 << 27) 29 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25) 30 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25) 31 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25) 32 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25) 33 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25) 34 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 35 #define EDP_PSR_SKIP_AUX_EXIT (1 << 12) 36 #define EDP_PSR_TP1_TP2_SEL (0 << 11) 37 #define EDP_PSR_TP1_TP3_SEL (1 << 11) 38 #define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */ 39 #define EDP_PSR_TP2_TP3_TIME_500us (0 << 8) 40 #define EDP_PSR_TP2_TP3_TIME_100us (1 << 8) 41 #define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8) 42 #define EDP_PSR_TP2_TP3_TIME_0us (3 << 8) 43 #define EDP_PSR_TP4_TIME_0US (3 << 6) /* ICL+ */ 44 #define EDP_PSR_TP1_TIME_500us (0 << 4) 45 #define EDP_PSR_TP1_TIME_100us (1 << 4) 46 #define EDP_PSR_TP1_TIME_2500us (2 << 4) 47 #define EDP_PSR_TP1_TIME_0us (3 << 4) 48 #define EDP_PSR_IDLE_FRAME_SHIFT 0 49 50 /* 51 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative 52 * to transcoder and bits defined for each one as if using no shift (i.e. as if 53 * it was for TRANSCODER_EDP) 54 */ 55 #define EDP_PSR_IMR _MMIO(0x64834) 56 #define EDP_PSR_IIR _MMIO(0x64838) 57 #define _PSR_IMR_A 0x60814 58 #define _PSR_IIR_A 0x60818 59 #define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A) 60 #define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A) 61 #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \ 62 0 : ((trans) - TRANSCODER_A + 1) * 8) 63 #define TGL_PSR_MASK REG_GENMASK(2, 0) 64 #define TGL_PSR_ERROR REG_BIT(2) 65 #define TGL_PSR_POST_EXIT REG_BIT(1) 66 #define TGL_PSR_PRE_ENTRY REG_BIT(0) 67 #define EDP_PSR_MASK(trans) (TGL_PSR_MASK << \ 68 _EDP_PSR_TRANS_SHIFT(trans)) 69 #define EDP_PSR_ERROR(trans) (TGL_PSR_ERROR << \ 70 _EDP_PSR_TRANS_SHIFT(trans)) 71 #define EDP_PSR_POST_EXIT(trans) (TGL_PSR_POST_EXIT << \ 72 _EDP_PSR_TRANS_SHIFT(trans)) 73 #define EDP_PSR_PRE_ENTRY(trans) (TGL_PSR_PRE_ENTRY << \ 74 _EDP_PSR_TRANS_SHIFT(trans)) 75 76 #define _SRD_AUX_DATA_A 0x60814 77 #define _SRD_AUX_DATA_EDP 0x6f814 78 #define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) + 4) /* 5 registers */ 79 80 #define _SRD_STATUS_A 0x60840 81 #define _SRD_STATUS_EDP 0x6f840 82 #define EDP_PSR_STATUS(tran) _MMIO_TRANS2(tran, _SRD_STATUS_A) 83 #define EDP_PSR_STATUS_STATE_MASK (7 << 29) 84 #define EDP_PSR_STATUS_STATE_SHIFT 29 85 #define EDP_PSR_STATUS_STATE_IDLE (0 << 29) 86 #define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29) 87 #define EDP_PSR_STATUS_STATE_SRDENT (2 << 29) 88 #define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29) 89 #define EDP_PSR_STATUS_STATE_BUFON (4 << 29) 90 #define EDP_PSR_STATUS_STATE_AUXACK (5 << 29) 91 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29) 92 #define EDP_PSR_STATUS_LINK_MASK (3 << 26) 93 #define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26) 94 #define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26) 95 #define EDP_PSR_STATUS_LINK_STANDBY (2 << 26) 96 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 97 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f 98 #define EDP_PSR_STATUS_COUNT_SHIFT 16 99 #define EDP_PSR_STATUS_COUNT_MASK 0xf 100 #define EDP_PSR_STATUS_AUX_ERROR (1 << 15) 101 #define EDP_PSR_STATUS_AUX_SENDING (1 << 12) 102 #define EDP_PSR_STATUS_SENDING_IDLE (1 << 9) 103 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8) 104 #define EDP_PSR_STATUS_SENDING_TP1 (1 << 4) 105 #define EDP_PSR_STATUS_IDLE_MASK 0xf 106 107 #define _SRD_PERF_CNT_A 0x60844 108 #define _SRD_PERF_CNT_EDP 0x6f844 109 #define EDP_PSR_PERF_CNT(tran) _MMIO_TRANS2(tran, _SRD_PERF_CNT_A) 110 #define EDP_PSR_PERF_CNT_MASK 0xffffff 111 112 /* PSR_MASK on SKL+ */ 113 #define _SRD_DEBUG_A 0x60860 114 #define _SRD_DEBUG_EDP 0x6f860 115 #define EDP_PSR_DEBUG(tran) _MMIO_TRANS2(tran, _SRD_DEBUG_A) 116 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28) 117 #define EDP_PSR_DEBUG_MASK_LPSP (1 << 27) 118 #define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26) 119 #define EDP_PSR_DEBUG_MASK_HPD (1 << 25) 120 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */ 121 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ 122 123 #define _PSR2_CTL_A 0x60900 124 #define _PSR2_CTL_EDP 0x6f900 125 #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) 126 #define EDP_PSR2_ENABLE (1 << 31) 127 #define EDP_SU_TRACK_ENABLE (1 << 30) /* up to adl-p */ 128 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) 129 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) 130 #define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */ 131 #define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25) /* display 13+ */ 132 #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) 133 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) 134 #define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8 135 #define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13) 136 #define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13) 137 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 138 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT 13 139 #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT) 140 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13) 141 #define EDP_PSR2_FAST_WAKE_MAX_LINES 8 142 #define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11) 143 #define EDP_PSR2_FAST_WAKE_MASK (3 << 11) 144 #define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5 145 #define TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT 10 146 #define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT) 147 #define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10) 148 #define EDP_PSR2_TP2_TIME_500us (0 << 8) 149 #define EDP_PSR2_TP2_TIME_100us (1 << 8) 150 #define EDP_PSR2_TP2_TIME_2500us (2 << 8) 151 #define EDP_PSR2_TP2_TIME_50us (3 << 8) 152 #define EDP_PSR2_TP2_TIME_MASK (3 << 8) 153 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 154 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) 155 #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) 156 #define EDP_PSR2_IDLE_FRAME_MASK 0xf 157 #define EDP_PSR2_IDLE_FRAME_SHIFT 0 158 159 #define _PSR_EVENT_TRANS_A 0x60848 160 #define _PSR_EVENT_TRANS_B 0x61848 161 #define _PSR_EVENT_TRANS_C 0x62848 162 #define _PSR_EVENT_TRANS_D 0x63848 163 #define _PSR_EVENT_TRANS_EDP 0x6f848 164 #define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A) 165 #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17) 166 #define PSR_EVENT_PSR2_DISABLED (1 << 16) 167 #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15) 168 #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14) 169 #define PSR_EVENT_GRAPHICS_RESET (1 << 12) 170 #define PSR_EVENT_PCH_INTERRUPT (1 << 11) 171 #define PSR_EVENT_MEMORY_UP (1 << 10) 172 #define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9) 173 #define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8) 174 #define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6) 175 #define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */ 176 #define PSR_EVENT_HDCP_ENABLE (1 << 4) 177 #define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3) 178 #define PSR_EVENT_VBI_ENABLE (1 << 2) 179 #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1) 180 #define PSR_EVENT_PSR_DISABLE (1 << 0) 181 182 #define _PSR2_STATUS_A 0x60940 183 #define _PSR2_STATUS_EDP 0x6f940 184 #define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A) 185 #define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28) 186 #define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8) 187 188 #define _PSR2_SU_STATUS_A 0x60914 189 #define _PSR2_SU_STATUS_EDP 0x6f914 190 #define _PSR2_SU_STATUS(tran, index) _MMIO_TRANS2(tran, _PSR2_SU_STATUS_A + (index) * 4) 191 #define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3)) 192 #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10) 193 #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame)) 194 #define PSR2_SU_STATUS_FRAMES 8 195 196 #define _PSR2_MAN_TRK_CTL_A 0x60910 197 #define _PSR2_MAN_TRK_CTL_EDP 0x6f910 198 #define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A) 199 #define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) 200 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21) 201 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) 202 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11) 203 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) 204 #define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3) 205 #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2) 206 #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1) 207 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16) 208 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) 209 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0) 210 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) 211 #define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31) 212 #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14) 213 #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13) 214 215 #define _SEL_FETCH_PLANE_BASE_1_A 0x70890 216 #define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 217 #define _SEL_FETCH_PLANE_BASE_3_A 0x708D0 218 #define _SEL_FETCH_PLANE_BASE_4_A 0x708F0 219 #define _SEL_FETCH_PLANE_BASE_5_A 0x70920 220 #define _SEL_FETCH_PLANE_BASE_6_A 0x70940 221 #define _SEL_FETCH_PLANE_BASE_7_A 0x70960 222 #define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880 223 #define _SEL_FETCH_PLANE_BASE_1_B 0x71890 224 225 #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \ 226 _SEL_FETCH_PLANE_BASE_1_A, \ 227 _SEL_FETCH_PLANE_BASE_2_A, \ 228 _SEL_FETCH_PLANE_BASE_3_A, \ 229 _SEL_FETCH_PLANE_BASE_4_A, \ 230 _SEL_FETCH_PLANE_BASE_5_A, \ 231 _SEL_FETCH_PLANE_BASE_6_A, \ 232 _SEL_FETCH_PLANE_BASE_7_A, \ 233 _SEL_FETCH_PLANE_BASE_CUR_A) 234 #define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B) 235 #define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \ 236 _SEL_FETCH_PLANE_BASE_1_A + \ 237 _SEL_FETCH_PLANE_BASE_A(plane)) 238 239 #define _SEL_FETCH_PLANE_CTL_1_A 0x70890 240 #define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 241 _SEL_FETCH_PLANE_CTL_1_A - \ 242 _SEL_FETCH_PLANE_BASE_1_A) 243 #define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31) 244 245 #define _SEL_FETCH_PLANE_POS_1_A 0x70894 246 #define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 247 _SEL_FETCH_PLANE_POS_1_A - \ 248 _SEL_FETCH_PLANE_BASE_1_A) 249 250 #define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 251 #define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 252 _SEL_FETCH_PLANE_SIZE_1_A - \ 253 _SEL_FETCH_PLANE_BASE_1_A) 254 255 #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C 256 #define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 257 _SEL_FETCH_PLANE_OFFSET_1_A - \ 258 _SEL_FETCH_PLANE_BASE_1_A) 259 260 #endif /* __INTEL_PSR_REGS_H__ */ 261