1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_PSR_REGS_H__ 7 #define __INTEL_PSR_REGS_H__ 8 9 #include "intel_display_reg_defs.h" 10 11 #define TRANS_EXITLINE(trans) _MMIO_TRANS2((trans), _TRANS_EXITLINE_A) 12 #define EXITLINE_ENABLE REG_BIT(31) 13 #define EXITLINE_MASK REG_GENMASK(12, 0) 14 #define EXITLINE_SHIFT 0 15 16 /* 17 * HSW+ eDP PSR registers 18 * 19 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one 20 * instance of it 21 */ 22 #define _SRD_CTL_A 0x60800 23 #define _SRD_CTL_EDP 0x6f800 24 #define EDP_PSR_CTL(tran) _MMIO_TRANS2(tran, _SRD_CTL_A) 25 #define EDP_PSR_ENABLE REG_BIT(31) 26 #define BDW_PSR_SINGLE_FRAME REG_BIT(30) 27 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK REG_BIT(29) /* SW can't modify */ 28 #define EDP_PSR_LINK_STANDBY REG_BIT(27) 29 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK REG_GENMASK(26, 25) 30 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 0) 31 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 1) 32 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 2) 33 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 3) 34 #define EDP_PSR_MAX_SLEEP_TIME_MASK REG_GENMASK(24, 20) 35 #define EDP_PSR_MAX_SLEEP_TIME(x) REG_FIELD_PREP(EDP_PSR_MAX_SLEEP_TIME_MASK, (x)) 36 #define EDP_PSR_SKIP_AUX_EXIT REG_BIT(12) 37 #define EDP_PSR_TP_MASK REG_BIT(11) 38 #define EDP_PSR_TP_TP1_TP2 REG_FIELD_PREP(EDP_PSR_TP_MASK, 0) 39 #define EDP_PSR_TP_TP1_TP3 REG_FIELD_PREP(EDP_PSR_TP_MASK, 1) 40 #define EDP_PSR_CRC_ENABLE REG_BIT(10) /* BDW+ */ 41 #define EDP_PSR_TP2_TP3_TIME_MASK REG_GENMASK(9, 8) 42 #define EDP_PSR_TP2_TP3_TIME_500us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 0) 43 #define EDP_PSR_TP2_TP3_TIME_100us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 1) 44 #define EDP_PSR_TP2_TP3_TIME_2500us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 2) 45 #define EDP_PSR_TP2_TP3_TIME_0us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 3) 46 #define EDP_PSR_TP4_TIME_MASK REG_GENMASK(7, 6) 47 #define EDP_PSR_TP4_TIME_0us REG_FIELD_PREP(EDP_PSR_TP4_TIME_MASK, 3) /* ICL+ */ 48 #define EDP_PSR_TP1_TIME_MASK REG_GENMASK(5, 4) 49 #define EDP_PSR_TP1_TIME_500us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 0) 50 #define EDP_PSR_TP1_TIME_100us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 1) 51 #define EDP_PSR_TP1_TIME_2500us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 2) 52 #define EDP_PSR_TP1_TIME_0us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 3) 53 #define EDP_PSR_IDLE_FRAMES_MASK REG_GENMASK(3, 0) 54 #define EDP_PSR_IDLE_FRAMES(x) REG_FIELD_PREP(EDP_PSR_IDLE_FRAMES_MASK, (x)) 55 56 /* 57 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative 58 * to transcoder and bits defined for each one as if using no shift (i.e. as if 59 * it was for TRANSCODER_EDP) 60 */ 61 #define EDP_PSR_IMR _MMIO(0x64834) 62 #define EDP_PSR_IIR _MMIO(0x64838) 63 #define _PSR_IMR_A 0x60814 64 #define _PSR_IIR_A 0x60818 65 #define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A) 66 #define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A) 67 #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \ 68 0 : ((trans) - TRANSCODER_A + 1) * 8) 69 #define TGL_PSR_MASK REG_GENMASK(2, 0) 70 #define TGL_PSR_ERROR REG_BIT(2) 71 #define TGL_PSR_POST_EXIT REG_BIT(1) 72 #define TGL_PSR_PRE_ENTRY REG_BIT(0) 73 #define EDP_PSR_MASK(trans) (TGL_PSR_MASK << \ 74 _EDP_PSR_TRANS_SHIFT(trans)) 75 #define EDP_PSR_ERROR(trans) (TGL_PSR_ERROR << \ 76 _EDP_PSR_TRANS_SHIFT(trans)) 77 #define EDP_PSR_POST_EXIT(trans) (TGL_PSR_POST_EXIT << \ 78 _EDP_PSR_TRANS_SHIFT(trans)) 79 #define EDP_PSR_PRE_ENTRY(trans) (TGL_PSR_PRE_ENTRY << \ 80 _EDP_PSR_TRANS_SHIFT(trans)) 81 82 #define _SRD_AUX_DATA_A 0x60814 83 #define _SRD_AUX_DATA_EDP 0x6f814 84 #define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */ 85 86 #define _SRD_STATUS_A 0x60840 87 #define _SRD_STATUS_EDP 0x6f840 88 #define EDP_PSR_STATUS(tran) _MMIO_TRANS2(tran, _SRD_STATUS_A) 89 #define EDP_PSR_STATUS_STATE_MASK REG_GENMASK(31, 29) 90 #define EDP_PSR_STATUS_STATE_IDLE REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 0) 91 #define EDP_PSR_STATUS_STATE_SRDONACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 1) 92 #define EDP_PSR_STATUS_STATE_SRDENT REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 2) 93 #define EDP_PSR_STATUS_STATE_BUFOFF REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 3) 94 #define EDP_PSR_STATUS_STATE_BUFON REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 4) 95 #define EDP_PSR_STATUS_STATE_AUXACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 5) 96 #define EDP_PSR_STATUS_STATE_SRDOFFACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 6) 97 #define EDP_PSR_STATUS_LINK_MASK REG_GENMASK(27, 26) 98 #define EDP_PSR_STATUS_LINK_FULL_OFF REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 0) 99 #define EDP_PSR_STATUS_LINK_FULL_ON REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 1) 100 #define EDP_PSR_STATUS_LINK_STANDBY REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 2) 101 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK REG_GENMASK(24, 20) 102 #define EDP_PSR_STATUS_COUNT_MASK REG_GENMASK(19, 16) 103 #define EDP_PSR_STATUS_AUX_ERROR REG_BIT(15) 104 #define EDP_PSR_STATUS_AUX_SENDING REG_BIT(12) 105 #define EDP_PSR_STATUS_SENDING_IDLE REG_BIT(9) 106 #define EDP_PSR_STATUS_SENDING_TP2_TP3 REG_BIT(8) 107 #define EDP_PSR_STATUS_SENDING_TP1 REG_BIT(4) 108 #define EDP_PSR_STATUS_IDLE_MASK REG_GENMASK(3, 0) 109 110 #define _SRD_PERF_CNT_A 0x60844 111 #define _SRD_PERF_CNT_EDP 0x6f844 112 #define EDP_PSR_PERF_CNT(tran) _MMIO_TRANS2(tran, _SRD_PERF_CNT_A) 113 #define EDP_PSR_PERF_CNT_MASK REG_GENMASK(23, 0) 114 115 /* PSR_MASK on SKL+ */ 116 #define _SRD_DEBUG_A 0x60860 117 #define _SRD_DEBUG_EDP 0x6f860 118 #define EDP_PSR_DEBUG(tran) _MMIO_TRANS2(tran, _SRD_DEBUG_A) 119 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP REG_BIT(28) 120 #define EDP_PSR_DEBUG_MASK_LPSP REG_BIT(27) 121 #define EDP_PSR_DEBUG_MASK_MEMUP REG_BIT(26) 122 #define EDP_PSR_DEBUG_MASK_HPD REG_BIT(25) 123 #define EDP_PSR_DEBUG_MASK_FBC_MODIFY REG_BIT(24) 124 #define EDP_PSR_DEBUG_MASK_PRIMARY_FLIP REG_BIT(23) /* hsw */ 125 #define EDP_PSR_DEBUG_MASK_HDCP_ENABLE REG_BIT(22) /* hsw/bdw */ 126 #define EDP_PSR_DEBUG_MASK_SPRITE_ENABLE REG_BIT(21) /* hsw */ 127 #define EDP_PSR_DEBUG_MASK_CURSOR_MOVE REG_BIT(20) /* hsw */ 128 #define EDP_PSR_DEBUG_MASK_VBLANK_VSYNC_INT REG_BIT(19) /* hsw */ 129 #define EDP_PSR_DEBUG_MASK_DPST_PHASE_IN REG_BIT(18) /* hsw */ 130 #define EDP_PSR_DEBUG_MASK_KVMR_SESSION_EN REG_BIT(17) 131 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE REG_BIT(16) /* hsw-skl */ 132 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN REG_BIT(15) /* skl+ */ 133 #define EDP_PSR_DEBUG_RFB_UPDATE_SENT REG_BIT(2) /* bdw */ 134 #define EDP_PSR_DEBUG_ENTRY_COMPLETION REG_BIT(1) /* hsw/bdw */ 135 136 #define _PSR2_CTL_A 0x60900 137 #define _PSR2_CTL_EDP 0x6f900 138 #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) 139 #define EDP_PSR2_ENABLE REG_BIT(31) 140 #define EDP_SU_TRACK_ENABLE REG_BIT(30) /* up to adl-p */ 141 #define TGL_EDP_PSR2_BLOCK_COUNT_MASK REG_BIT(28) 142 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 REG_FIELD_PREP(TGL_EDP_PSR2_BLOCK_COUNT_MASK, 0) 143 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 REG_FIELD_PREP(TGL_EDP_PSR2_BLOCK_COUNT_MASK, 1) 144 #define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */ 145 #define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25) /* display 13+ */ 146 #define EDP_MAX_SU_DISABLE_TIME_MASK REG_GENMASK(24, 20) 147 #define EDP_MAX_SU_DISABLE_TIME(t) REG_FIELD_PREP(EDP_MAX_SU_DISABLE_TIME, (t)) 148 #define EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(14, 13) 149 #define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8 150 #define EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(EDP_PSR2_IO_BUFFER_WAKE_MASK, \ 151 EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) 152 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(15, 13) 153 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 154 #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK, \ 155 (lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) 156 #define EDP_PSR2_FAST_WAKE_MASK REG_GENMASK(12, 11) 157 #define EDP_PSR2_FAST_WAKE_MAX_LINES 8 158 #define EDP_PSR2_FAST_WAKE(lines) REG_FIELD_PREP(EDP_PSR2_FAST_WAKE_MASK, \ 159 EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) 160 #define TGL_EDP_PSR2_FAST_WAKE_MASK REG_GENMASK(12, 10) 161 #define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5 162 #define TGL_EDP_PSR2_FAST_WAKE(lines) REG_FIELD_PREP(TGL_EDP_PSR2_FAST_WAKE_MASK, \ 163 (lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) 164 #define EDP_PSR2_TP2_TIME_MASK REG_GENMASK(9, 8) 165 #define EDP_PSR2_TP2_TIME_500us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 0) 166 #define EDP_PSR2_TP2_TIME_100us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 1) 167 #define EDP_PSR2_TP2_TIME_2500us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 2) 168 #define EDP_PSR2_TP2_TIME_50us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 3) 169 #define EDP_PSR2_FRAME_BEFORE_SU_MASK REG_GENMASK(7, 4) 170 #define EDP_PSR2_FRAME_BEFORE_SU(a) REG_FIELD_PREP(EDP_PSR2_FRAME_BEFORE_SU_MASK, (a)) 171 #define EDP_PSR2_IDLE_FRAMES_MASK REG_GENMASK(3, 0) 172 #define EDP_PSR2_IDLE_FRAMES(x) REG_FIELD_PREP(EDP_PSR2_IDLE_FRAMES_MASK, (x)) 173 174 #define _PSR_EVENT_TRANS_A 0x60848 175 #define _PSR_EVENT_TRANS_B 0x61848 176 #define _PSR_EVENT_TRANS_C 0x62848 177 #define _PSR_EVENT_TRANS_D 0x63848 178 #define _PSR_EVENT_TRANS_EDP 0x6f848 179 #define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A) 180 #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE REG_BIT(17) 181 #define PSR_EVENT_PSR2_DISABLED REG_BIT(16) 182 #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN REG_BIT(15) 183 #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN REG_BIT(14) 184 #define PSR_EVENT_GRAPHICS_RESET REG_BIT(12) 185 #define PSR_EVENT_PCH_INTERRUPT REG_BIT(11) 186 #define PSR_EVENT_MEMORY_UP REG_BIT(10) 187 #define PSR_EVENT_FRONT_BUFFER_MODIFY REG_BIT(9) 188 #define PSR_EVENT_WD_TIMER_EXPIRE REG_BIT(8) 189 #define PSR_EVENT_PIPE_REGISTERS_UPDATE REG_BIT(6) 190 #define PSR_EVENT_REGISTER_UPDATE REG_BIT(5) /* Reserved in ICL+ */ 191 #define PSR_EVENT_HDCP_ENABLE REG_BIT(4) 192 #define PSR_EVENT_KVMR_SESSION_ENABLE REG_BIT(3) 193 #define PSR_EVENT_VBI_ENABLE REG_BIT(2) 194 #define PSR_EVENT_LPSP_MODE_EXIT REG_BIT(1) 195 #define PSR_EVENT_PSR_DISABLE REG_BIT(0) 196 197 #define _PSR2_STATUS_A 0x60940 198 #define _PSR2_STATUS_EDP 0x6f940 199 #define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A) 200 #define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28) 201 #define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8) 202 203 #define _PSR2_SU_STATUS_A 0x60914 204 #define _PSR2_SU_STATUS_EDP 0x6f914 205 #define _PSR2_SU_STATUS(tran, index) _MMIO_TRANS2(tran, _PSR2_SU_STATUS_A + (index) * 4) 206 #define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3)) 207 #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10) 208 #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame)) 209 #define PSR2_SU_STATUS_FRAMES 8 210 211 #define _PSR2_MAN_TRK_CTL_A 0x60910 212 #define _PSR2_MAN_TRK_CTL_EDP 0x6f910 213 #define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A) 214 #define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) 215 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21) 216 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) 217 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11) 218 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) 219 #define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3) 220 #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2) 221 #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1) 222 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16) 223 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) 224 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0) 225 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) 226 #define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31) 227 #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14) 228 #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13) 229 230 #define _SEL_FETCH_PLANE_BASE_1_A 0x70890 231 #define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 232 #define _SEL_FETCH_PLANE_BASE_3_A 0x708D0 233 #define _SEL_FETCH_PLANE_BASE_4_A 0x708F0 234 #define _SEL_FETCH_PLANE_BASE_5_A 0x70920 235 #define _SEL_FETCH_PLANE_BASE_6_A 0x70940 236 #define _SEL_FETCH_PLANE_BASE_7_A 0x70960 237 #define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880 238 #define _SEL_FETCH_PLANE_BASE_1_B 0x71890 239 240 #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \ 241 _SEL_FETCH_PLANE_BASE_1_A, \ 242 _SEL_FETCH_PLANE_BASE_2_A, \ 243 _SEL_FETCH_PLANE_BASE_3_A, \ 244 _SEL_FETCH_PLANE_BASE_4_A, \ 245 _SEL_FETCH_PLANE_BASE_5_A, \ 246 _SEL_FETCH_PLANE_BASE_6_A, \ 247 _SEL_FETCH_PLANE_BASE_7_A, \ 248 _SEL_FETCH_PLANE_BASE_CUR_A) 249 #define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B) 250 #define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \ 251 _SEL_FETCH_PLANE_BASE_1_A + \ 252 _SEL_FETCH_PLANE_BASE_A(plane)) 253 254 #define _SEL_FETCH_PLANE_CTL_1_A 0x70890 255 #define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 256 _SEL_FETCH_PLANE_CTL_1_A - \ 257 _SEL_FETCH_PLANE_BASE_1_A) 258 #define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31) 259 260 #define _SEL_FETCH_PLANE_POS_1_A 0x70894 261 #define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 262 _SEL_FETCH_PLANE_POS_1_A - \ 263 _SEL_FETCH_PLANE_BASE_1_A) 264 265 #define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 266 #define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 267 _SEL_FETCH_PLANE_SIZE_1_A - \ 268 _SEL_FETCH_PLANE_BASE_1_A) 269 270 #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C 271 #define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 272 _SEL_FETCH_PLANE_OFFSET_1_A - \ 273 _SEL_FETCH_PLANE_BASE_1_A) 274 275 #endif /* __INTEL_PSR_REGS_H__ */ 276