1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_damage_helper.h> 26 27 #include "display/intel_dp.h" 28 29 #include "i915_drv.h" 30 #include "intel_atomic.h" 31 #include "intel_crtc.h" 32 #include "intel_de.h" 33 #include "intel_display_types.h" 34 #include "intel_dp_aux.h" 35 #include "intel_hdmi.h" 36 #include "intel_psr.h" 37 #include "intel_snps_phy.h" 38 #include "skl_universal_plane.h" 39 40 /** 41 * DOC: Panel Self Refresh (PSR/SRD) 42 * 43 * Since Haswell Display controller supports Panel Self-Refresh on display 44 * panels witch have a remote frame buffer (RFB) implemented according to PSR 45 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 46 * when system is idle but display is on as it eliminates display refresh 47 * request to DDR memory completely as long as the frame buffer for that 48 * display is unchanged. 49 * 50 * Panel Self Refresh must be supported by both Hardware (source) and 51 * Panel (sink). 52 * 53 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 54 * to power down the link and memory controller. For DSI panels the same idea 55 * is called "manual mode". 56 * 57 * The implementation uses the hardware-based PSR support which automatically 58 * enters/exits self-refresh mode. The hardware takes care of sending the 59 * required DP aux message and could even retrain the link (that part isn't 60 * enabled yet though). The hardware also keeps track of any frontbuffer 61 * changes to know when to exit self-refresh mode again. Unfortunately that 62 * part doesn't work too well, hence why the i915 PSR support uses the 63 * software frontbuffer tracking to make sure it doesn't miss a screen 64 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 65 * get called by the frontbuffer tracking code. Note that because of locking 66 * issues the self-refresh re-enable code is done from a work queue, which 67 * must be correctly synchronized/cancelled when shutting down the pipe." 68 * 69 * DC3CO (DC3 clock off) 70 * 71 * On top of PSR2, GEN12 adds a intermediate power savings state that turns 72 * clock off automatically during PSR2 idle state. 73 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep 74 * entry/exit allows the HW to enter a low-power state even when page flipping 75 * periodically (for instance a 30fps video playback scenario). 76 * 77 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), 78 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 79 * frames, if no other flip occurs and the function above is executed, DC3CO is 80 * disabled and PSR2 is configured to enter deep sleep, resetting again in case 81 * of another flip. 82 * Front buffer modifications do not trigger DC3CO activation on purpose as it 83 * would bring a lot of complexity and most of the moderns systems will only 84 * use page flips. 85 */ 86 87 static bool psr_global_enabled(struct intel_dp *intel_dp) 88 { 89 struct intel_connector *connector = intel_dp->attached_connector; 90 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 91 92 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 93 case I915_PSR_DEBUG_DEFAULT: 94 if (i915->params.enable_psr == -1) 95 return connector->panel.vbt.psr.enable; 96 return i915->params.enable_psr; 97 case I915_PSR_DEBUG_DISABLE: 98 return false; 99 default: 100 return true; 101 } 102 } 103 104 static bool psr2_global_enabled(struct intel_dp *intel_dp) 105 { 106 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 107 108 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 109 case I915_PSR_DEBUG_DISABLE: 110 case I915_PSR_DEBUG_FORCE_PSR1: 111 return false; 112 default: 113 if (i915->params.enable_psr == 1) 114 return false; 115 return true; 116 } 117 } 118 119 static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp) 120 { 121 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 122 123 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_ERROR : 124 EDP_PSR_ERROR(intel_dp->psr.transcoder); 125 } 126 127 static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp) 128 { 129 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 130 131 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_POST_EXIT : 132 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder); 133 } 134 135 static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp) 136 { 137 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 138 139 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_PRE_ENTRY : 140 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder); 141 } 142 143 static u32 psr_irq_mask_get(struct intel_dp *intel_dp) 144 { 145 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 146 147 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_MASK : 148 EDP_PSR_MASK(intel_dp->psr.transcoder); 149 } 150 151 static void psr_irq_control(struct intel_dp *intel_dp) 152 { 153 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 154 i915_reg_t imr_reg; 155 u32 mask, val; 156 157 if (DISPLAY_VER(dev_priv) >= 12) 158 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 159 else 160 imr_reg = EDP_PSR_IMR; 161 162 mask = psr_irq_psr_error_bit_get(intel_dp); 163 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) 164 mask |= psr_irq_post_exit_bit_get(intel_dp) | 165 psr_irq_pre_entry_bit_get(intel_dp); 166 167 val = intel_de_read(dev_priv, imr_reg); 168 val &= ~psr_irq_mask_get(intel_dp); 169 val |= ~mask; 170 intel_de_write(dev_priv, imr_reg, val); 171 } 172 173 static void psr_event_print(struct drm_i915_private *i915, 174 u32 val, bool psr2_enabled) 175 { 176 drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val); 177 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 178 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n"); 179 if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) 180 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n"); 181 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 182 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n"); 183 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 184 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n"); 185 if (val & PSR_EVENT_GRAPHICS_RESET) 186 drm_dbg_kms(&i915->drm, "\tGraphics reset\n"); 187 if (val & PSR_EVENT_PCH_INTERRUPT) 188 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n"); 189 if (val & PSR_EVENT_MEMORY_UP) 190 drm_dbg_kms(&i915->drm, "\tMemory up\n"); 191 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 192 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n"); 193 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 194 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n"); 195 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 196 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n"); 197 if (val & PSR_EVENT_REGISTER_UPDATE) 198 drm_dbg_kms(&i915->drm, "\tRegister updated\n"); 199 if (val & PSR_EVENT_HDCP_ENABLE) 200 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n"); 201 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 202 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n"); 203 if (val & PSR_EVENT_VBI_ENABLE) 204 drm_dbg_kms(&i915->drm, "\tVBI enabled\n"); 205 if (val & PSR_EVENT_LPSP_MODE_EXIT) 206 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n"); 207 if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) 208 drm_dbg_kms(&i915->drm, "\tPSR disabled\n"); 209 } 210 211 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) 212 { 213 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 214 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 215 ktime_t time_ns = ktime_get(); 216 i915_reg_t imr_reg; 217 218 if (DISPLAY_VER(dev_priv) >= 12) 219 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 220 else 221 imr_reg = EDP_PSR_IMR; 222 223 if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) { 224 intel_dp->psr.last_entry_attempt = time_ns; 225 drm_dbg_kms(&dev_priv->drm, 226 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 227 transcoder_name(cpu_transcoder)); 228 } 229 230 if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) { 231 intel_dp->psr.last_exit = time_ns; 232 drm_dbg_kms(&dev_priv->drm, 233 "[transcoder %s] PSR exit completed\n", 234 transcoder_name(cpu_transcoder)); 235 236 if (DISPLAY_VER(dev_priv) >= 9) { 237 u32 val = intel_de_read(dev_priv, 238 PSR_EVENT(cpu_transcoder)); 239 bool psr2_enabled = intel_dp->psr.psr2_enabled; 240 241 intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder), 242 val); 243 psr_event_print(dev_priv, val, psr2_enabled); 244 } 245 } 246 247 if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) { 248 u32 val; 249 250 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", 251 transcoder_name(cpu_transcoder)); 252 253 intel_dp->psr.irq_aux_error = true; 254 255 /* 256 * If this interruption is not masked it will keep 257 * interrupting so fast that it prevents the scheduled 258 * work to run. 259 * Also after a PSR error, we don't want to arm PSR 260 * again so we don't care about unmask the interruption 261 * or unset irq_aux_error. 262 */ 263 val = intel_de_read(dev_priv, imr_reg); 264 val |= psr_irq_psr_error_bit_get(intel_dp); 265 intel_de_write(dev_priv, imr_reg, val); 266 267 schedule_work(&intel_dp->psr.work); 268 } 269 } 270 271 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) 272 { 273 u8 alpm_caps = 0; 274 275 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, 276 &alpm_caps) != 1) 277 return false; 278 return alpm_caps & DP_ALPM_CAP; 279 } 280 281 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 282 { 283 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 284 u8 val = 8; /* assume the worst if we can't read the value */ 285 286 if (drm_dp_dpcd_readb(&intel_dp->aux, 287 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 288 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 289 else 290 drm_dbg_kms(&i915->drm, 291 "Unable to get sink synchronization latency, assuming 8 frames\n"); 292 return val; 293 } 294 295 static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) 296 { 297 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 298 ssize_t r; 299 u16 w; 300 u8 y; 301 302 /* If sink don't have specific granularity requirements set legacy ones */ 303 if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { 304 /* As PSR2 HW sends full lines, we do not care about x granularity */ 305 w = 4; 306 y = 4; 307 goto exit; 308 } 309 310 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2); 311 if (r != 2) 312 drm_dbg_kms(&i915->drm, 313 "Unable to read DP_PSR2_SU_X_GRANULARITY\n"); 314 /* 315 * Spec says that if the value read is 0 the default granularity should 316 * be used instead. 317 */ 318 if (r != 2 || w == 0) 319 w = 4; 320 321 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); 322 if (r != 1) { 323 drm_dbg_kms(&i915->drm, 324 "Unable to read DP_PSR2_SU_Y_GRANULARITY\n"); 325 y = 4; 326 } 327 if (y == 0) 328 y = 1; 329 330 exit: 331 intel_dp->psr.su_w_granularity = w; 332 intel_dp->psr.su_y_granularity = y; 333 } 334 335 void intel_psr_init_dpcd(struct intel_dp *intel_dp) 336 { 337 struct drm_i915_private *dev_priv = 338 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 339 340 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, 341 sizeof(intel_dp->psr_dpcd)); 342 343 if (!intel_dp->psr_dpcd[0]) 344 return; 345 drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n", 346 intel_dp->psr_dpcd[0]); 347 348 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { 349 drm_dbg_kms(&dev_priv->drm, 350 "PSR support not currently available for this panel\n"); 351 return; 352 } 353 354 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 355 drm_dbg_kms(&dev_priv->drm, 356 "Panel lacks power state control, PSR cannot be enabled\n"); 357 return; 358 } 359 360 intel_dp->psr.sink_support = true; 361 intel_dp->psr.sink_sync_latency = 362 intel_dp_get_sink_sync_latency(intel_dp); 363 364 if (DISPLAY_VER(dev_priv) >= 9 && 365 (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { 366 bool y_req = intel_dp->psr_dpcd[1] & 367 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 368 bool alpm = intel_dp_get_alpm_status(intel_dp); 369 370 /* 371 * All panels that supports PSR version 03h (PSR2 + 372 * Y-coordinate) can handle Y-coordinates in VSC but we are 373 * only sure that it is going to be used when required by the 374 * panel. This way panel is capable to do selective update 375 * without a aux frame sync. 376 * 377 * To support PSR version 02h and PSR version 03h without 378 * Y-coordinate requirement panels we would need to enable 379 * GTC first. 380 */ 381 intel_dp->psr.sink_psr2_support = y_req && alpm; 382 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n", 383 intel_dp->psr.sink_psr2_support ? "" : "not "); 384 385 if (intel_dp->psr.sink_psr2_support) { 386 intel_dp->psr.colorimetry_support = 387 intel_dp_get_colorimetry_status(intel_dp); 388 intel_dp_get_su_granularity(intel_dp); 389 } 390 } 391 } 392 393 static void intel_psr_enable_sink(struct intel_dp *intel_dp) 394 { 395 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 396 u8 dpcd_val = DP_PSR_ENABLE; 397 398 /* Enable ALPM at sink for psr2 */ 399 if (intel_dp->psr.psr2_enabled) { 400 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 401 DP_ALPM_ENABLE | 402 DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); 403 404 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 405 } else { 406 if (intel_dp->psr.link_standby) 407 dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; 408 409 if (DISPLAY_VER(dev_priv) >= 8) 410 dpcd_val |= DP_PSR_CRC_VERIFICATION; 411 } 412 413 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 414 dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; 415 416 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); 417 418 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 419 } 420 421 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 422 { 423 struct intel_connector *connector = intel_dp->attached_connector; 424 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 425 u32 val = 0; 426 427 if (DISPLAY_VER(dev_priv) >= 11) 428 val |= EDP_PSR_TP4_TIME_0US; 429 430 if (dev_priv->params.psr_safest_params) { 431 val |= EDP_PSR_TP1_TIME_2500us; 432 val |= EDP_PSR_TP2_TP3_TIME_2500us; 433 goto check_tp3_sel; 434 } 435 436 if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0) 437 val |= EDP_PSR_TP1_TIME_0us; 438 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100) 439 val |= EDP_PSR_TP1_TIME_100us; 440 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500) 441 val |= EDP_PSR_TP1_TIME_500us; 442 else 443 val |= EDP_PSR_TP1_TIME_2500us; 444 445 if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) 446 val |= EDP_PSR_TP2_TP3_TIME_0us; 447 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100) 448 val |= EDP_PSR_TP2_TP3_TIME_100us; 449 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500) 450 val |= EDP_PSR_TP2_TP3_TIME_500us; 451 else 452 val |= EDP_PSR_TP2_TP3_TIME_2500us; 453 454 check_tp3_sel: 455 if (intel_dp_source_supports_tps3(dev_priv) && 456 drm_dp_tps3_supported(intel_dp->dpcd)) 457 val |= EDP_PSR_TP1_TP3_SEL; 458 else 459 val |= EDP_PSR_TP1_TP2_SEL; 460 461 return val; 462 } 463 464 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 465 { 466 struct intel_connector *connector = intel_dp->attached_connector; 467 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 468 int idle_frames; 469 470 /* Let's use 6 as the minimum to cover all known cases including the 471 * off-by-one issue that HW has in some cases. 472 */ 473 idle_frames = max(6, connector->panel.vbt.psr.idle_frames); 474 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1); 475 476 if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf)) 477 idle_frames = 0xf; 478 479 return idle_frames; 480 } 481 482 static void hsw_activate_psr1(struct intel_dp *intel_dp) 483 { 484 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 485 u32 max_sleep_time = 0x1f; 486 u32 val = EDP_PSR_ENABLE; 487 488 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT; 489 490 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; 491 if (IS_HASWELL(dev_priv)) 492 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 493 494 if (intel_dp->psr.link_standby) 495 val |= EDP_PSR_LINK_STANDBY; 496 497 val |= intel_psr1_get_tp_time(intel_dp); 498 499 if (DISPLAY_VER(dev_priv) >= 8) 500 val |= EDP_PSR_CRC_ENABLE; 501 502 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) & 503 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK); 504 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val); 505 } 506 507 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 508 { 509 struct intel_connector *connector = intel_dp->attached_connector; 510 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 511 u32 val = 0; 512 513 if (dev_priv->params.psr_safest_params) 514 return EDP_PSR2_TP2_TIME_2500us; 515 516 if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 517 connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 518 val |= EDP_PSR2_TP2_TIME_50us; 519 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 520 val |= EDP_PSR2_TP2_TIME_100us; 521 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 522 val |= EDP_PSR2_TP2_TIME_500us; 523 else 524 val |= EDP_PSR2_TP2_TIME_2500us; 525 526 return val; 527 } 528 529 static void hsw_activate_psr2(struct intel_dp *intel_dp) 530 { 531 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 532 u32 val = EDP_PSR2_ENABLE; 533 534 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT; 535 536 if (DISPLAY_VER(dev_priv) <= 13 && !IS_ALDERLAKE_P(dev_priv)) 537 val |= EDP_SU_TRACK_ENABLE; 538 539 if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12) 540 val |= EDP_Y_COORDINATE_ENABLE; 541 542 val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2)); 543 val |= intel_psr2_get_tp_time(intel_dp); 544 545 /* Wa_22012278275:adl-p */ 546 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { 547 static const u8 map[] = { 548 2, /* 5 lines */ 549 1, /* 6 lines */ 550 0, /* 7 lines */ 551 3, /* 8 lines */ 552 6, /* 9 lines */ 553 5, /* 10 lines */ 554 4, /* 11 lines */ 555 7, /* 12 lines */ 556 }; 557 /* 558 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see 559 * comments bellow for more information 560 */ 561 u32 tmp, lines = 7; 562 563 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 564 565 tmp = map[lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; 566 tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT; 567 val |= tmp; 568 569 tmp = map[lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; 570 tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT; 571 val |= tmp; 572 } else if (DISPLAY_VER(dev_priv) >= 12) { 573 /* 574 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default 575 * values from BSpec. In order to setting an optimal power 576 * consumption, lower than 4k resolution mode needs to decrease 577 * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution 578 * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE. 579 */ 580 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 581 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7); 582 val |= TGL_EDP_PSR2_FAST_WAKE(7); 583 } else if (DISPLAY_VER(dev_priv) >= 9) { 584 val |= EDP_PSR2_IO_BUFFER_WAKE(7); 585 val |= EDP_PSR2_FAST_WAKE(7); 586 } 587 588 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 589 val |= EDP_PSR2_SU_SDP_SCANLINE; 590 591 if (intel_dp->psr.psr2_sel_fetch_enabled) { 592 u32 tmp; 593 594 /* Wa_1408330847 */ 595 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 596 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 597 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 598 DIS_RAM_BYPASS_PSR2_MAN_TRACK); 599 600 tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); 601 drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); 602 } else if (HAS_PSR2_SEL_FETCH(dev_priv)) { 603 intel_de_write(dev_priv, 604 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0); 605 } 606 607 /* 608 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 609 * recommending keep this bit unset while PSR2 is enabled. 610 */ 611 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0); 612 613 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 614 } 615 616 static bool 617 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) 618 { 619 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 620 return trans == TRANSCODER_A || trans == TRANSCODER_B; 621 else if (DISPLAY_VER(dev_priv) >= 12) 622 return trans == TRANSCODER_A; 623 else 624 return trans == TRANSCODER_EDP; 625 } 626 627 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate) 628 { 629 if (!cstate || !cstate->hw.active) 630 return 0; 631 632 return DIV_ROUND_UP(1000 * 1000, 633 drm_mode_vrefresh(&cstate->hw.adjusted_mode)); 634 } 635 636 static void psr2_program_idle_frames(struct intel_dp *intel_dp, 637 u32 idle_frames) 638 { 639 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 640 u32 val; 641 642 idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; 643 val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder)); 644 val &= ~EDP_PSR2_IDLE_FRAME_MASK; 645 val |= idle_frames; 646 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 647 } 648 649 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) 650 { 651 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 652 653 psr2_program_idle_frames(intel_dp, 0); 654 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO); 655 } 656 657 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp) 658 { 659 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 660 661 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 662 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp)); 663 } 664 665 static void tgl_dc3co_disable_work(struct work_struct *work) 666 { 667 struct intel_dp *intel_dp = 668 container_of(work, typeof(*intel_dp), psr.dc3co_work.work); 669 670 mutex_lock(&intel_dp->psr.lock); 671 /* If delayed work is pending, it is not idle */ 672 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) 673 goto unlock; 674 675 tgl_psr2_disable_dc3co(intel_dp); 676 unlock: 677 mutex_unlock(&intel_dp->psr.lock); 678 } 679 680 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) 681 { 682 if (!intel_dp->psr.dc3co_exitline) 683 return; 684 685 cancel_delayed_work(&intel_dp->psr.dc3co_work); 686 /* Before PSR2 exit disallow dc3co*/ 687 tgl_psr2_disable_dc3co(intel_dp); 688 } 689 690 static bool 691 dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp, 692 struct intel_crtc_state *crtc_state) 693 { 694 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 695 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 696 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 697 enum port port = dig_port->base.port; 698 699 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 700 return pipe <= PIPE_B && port <= PORT_B; 701 else 702 return pipe == PIPE_A && port == PORT_A; 703 } 704 705 static void 706 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 707 struct intel_crtc_state *crtc_state) 708 { 709 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; 710 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 711 u32 exit_scanlines; 712 713 /* 714 * FIXME: Due to the changed sequence of activating/deactivating DC3CO, 715 * disable DC3CO until the changed dc3co activating/deactivating sequence 716 * is applied. B.Specs:49196 717 */ 718 return; 719 720 /* 721 * DMC's DC3CO exit mechanism has an issue with Selective Fecth 722 * TODO: when the issue is addressed, this restriction should be removed. 723 */ 724 if (crtc_state->enable_psr2_sel_fetch) 725 return; 726 727 if (!(dev_priv->display.dmc.allowed_dc_mask & DC_STATE_EN_DC3CO)) 728 return; 729 730 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) 731 return; 732 733 /* Wa_16011303918:adl-p */ 734 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 735 return; 736 737 /* 738 * DC3CO Exit time 200us B.Spec 49196 739 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 740 */ 741 exit_scanlines = 742 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; 743 744 if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay)) 745 return; 746 747 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; 748 } 749 750 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, 751 struct intel_crtc_state *crtc_state) 752 { 753 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 754 755 if (!dev_priv->params.enable_psr2_sel_fetch && 756 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 757 drm_dbg_kms(&dev_priv->drm, 758 "PSR2 sel fetch not enabled, disabled by parameter\n"); 759 return false; 760 } 761 762 if (crtc_state->uapi.async_flip) { 763 drm_dbg_kms(&dev_priv->drm, 764 "PSR2 sel fetch not enabled, async flip enabled\n"); 765 return false; 766 } 767 768 /* Wa_14010254185 Wa_14010103792 */ 769 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { 770 drm_dbg_kms(&dev_priv->drm, 771 "PSR2 sel fetch not enabled, missing the implementation of WAs\n"); 772 return false; 773 } 774 775 return crtc_state->enable_psr2_sel_fetch = true; 776 } 777 778 static bool psr2_granularity_check(struct intel_dp *intel_dp, 779 struct intel_crtc_state *crtc_state) 780 { 781 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 782 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 783 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 784 u16 y_granularity = 0; 785 786 /* PSR2 HW only send full lines so we only need to validate the width */ 787 if (crtc_hdisplay % intel_dp->psr.su_w_granularity) 788 return false; 789 790 if (crtc_vdisplay % intel_dp->psr.su_y_granularity) 791 return false; 792 793 /* HW tracking is only aligned to 4 lines */ 794 if (!crtc_state->enable_psr2_sel_fetch) 795 return intel_dp->psr.su_y_granularity == 4; 796 797 /* 798 * adl_p and display 14+ platforms has 1 line granularity. 799 * For other platforms with SW tracking we can adjust the y coordinates 800 * to match sink requirement if multiple of 4. 801 */ 802 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 803 y_granularity = intel_dp->psr.su_y_granularity; 804 else if (intel_dp->psr.su_y_granularity <= 2) 805 y_granularity = 4; 806 else if ((intel_dp->psr.su_y_granularity % 4) == 0) 807 y_granularity = intel_dp->psr.su_y_granularity; 808 809 if (y_granularity == 0 || crtc_vdisplay % y_granularity) 810 return false; 811 812 crtc_state->su_y_granularity = y_granularity; 813 return true; 814 } 815 816 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp, 817 struct intel_crtc_state *crtc_state) 818 { 819 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; 820 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 821 u32 hblank_total, hblank_ns, req_ns; 822 823 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; 824 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); 825 826 /* From spec: ((60 / number of lanes) + 11) * 1000 / symbol clock frequency MHz */ 827 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); 828 829 if ((hblank_ns - req_ns) > 100) 830 return true; 831 832 /* Not supported <13 / Wa_22012279113:adl-p */ 833 if (DISPLAY_VER(dev_priv) <= 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b) 834 return false; 835 836 crtc_state->req_psr2_sdp_prior_scanline = true; 837 return true; 838 } 839 840 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 841 struct intel_crtc_state *crtc_state) 842 { 843 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 844 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 845 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 846 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 847 848 if (!intel_dp->psr.sink_psr2_support) 849 return false; 850 851 /* JSL and EHL only supports eDP 1.3 */ 852 if (IS_JSL_EHL(dev_priv)) { 853 drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n"); 854 return false; 855 } 856 857 /* Wa_16011181250 */ 858 if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) || 859 IS_DG2(dev_priv)) { 860 drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n"); 861 return false; 862 } 863 864 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 865 drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n"); 866 return false; 867 } 868 869 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { 870 drm_dbg_kms(&dev_priv->drm, 871 "PSR2 not supported in transcoder %s\n", 872 transcoder_name(crtc_state->cpu_transcoder)); 873 return false; 874 } 875 876 if (!psr2_global_enabled(intel_dp)) { 877 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); 878 return false; 879 } 880 881 /* 882 * DSC and PSR2 cannot be enabled simultaneously. If a requested 883 * resolution requires DSC to be enabled, priority is given to DSC 884 * over PSR2. 885 */ 886 if (crtc_state->dsc.compression_enable && 887 (DISPLAY_VER(dev_priv) <= 13 && !IS_ALDERLAKE_P(dev_priv))) { 888 drm_dbg_kms(&dev_priv->drm, 889 "PSR2 cannot be enabled since DSC is enabled\n"); 890 return false; 891 } 892 893 if (crtc_state->crc_enabled) { 894 drm_dbg_kms(&dev_priv->drm, 895 "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); 896 return false; 897 } 898 899 if (DISPLAY_VER(dev_priv) >= 12) { 900 psr_max_h = 5120; 901 psr_max_v = 3200; 902 max_bpp = 30; 903 } else if (DISPLAY_VER(dev_priv) >= 10) { 904 psr_max_h = 4096; 905 psr_max_v = 2304; 906 max_bpp = 24; 907 } else if (DISPLAY_VER(dev_priv) == 9) { 908 psr_max_h = 3640; 909 psr_max_v = 2304; 910 max_bpp = 24; 911 } 912 913 if (crtc_state->pipe_bpp > max_bpp) { 914 drm_dbg_kms(&dev_priv->drm, 915 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 916 crtc_state->pipe_bpp, max_bpp); 917 return false; 918 } 919 920 /* Wa_16011303918:adl-p */ 921 if (crtc_state->vrr.enable && 922 IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 923 drm_dbg_kms(&dev_priv->drm, 924 "PSR2 not enabled, not compatible with HW stepping + VRR\n"); 925 return false; 926 } 927 928 if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) { 929 drm_dbg_kms(&dev_priv->drm, 930 "PSR2 not enabled, PSR2 SDP indication do not fit in hblank\n"); 931 return false; 932 } 933 934 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 935 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && 936 !HAS_PSR_HW_TRACKING(dev_priv)) { 937 drm_dbg_kms(&dev_priv->drm, 938 "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); 939 return false; 940 } 941 } 942 943 /* Wa_2209313811 */ 944 if (!crtc_state->enable_psr2_sel_fetch && 945 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { 946 drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n"); 947 goto unsupported; 948 } 949 950 if (!psr2_granularity_check(intel_dp, crtc_state)) { 951 drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n"); 952 goto unsupported; 953 } 954 955 if (!crtc_state->enable_psr2_sel_fetch && 956 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { 957 drm_dbg_kms(&dev_priv->drm, 958 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 959 crtc_hdisplay, crtc_vdisplay, 960 psr_max_h, psr_max_v); 961 goto unsupported; 962 } 963 964 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); 965 return true; 966 967 unsupported: 968 crtc_state->enable_psr2_sel_fetch = false; 969 return false; 970 } 971 972 void intel_psr_compute_config(struct intel_dp *intel_dp, 973 struct intel_crtc_state *crtc_state, 974 struct drm_connector_state *conn_state) 975 { 976 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 977 const struct drm_display_mode *adjusted_mode = 978 &crtc_state->hw.adjusted_mode; 979 int psr_setup_time; 980 981 /* 982 * Current PSR panels don't work reliably with VRR enabled 983 * So if VRR is enabled, do not enable PSR. 984 */ 985 if (crtc_state->vrr.enable) 986 return; 987 988 if (!CAN_PSR(intel_dp)) 989 return; 990 991 if (!psr_global_enabled(intel_dp)) { 992 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); 993 return; 994 } 995 996 if (intel_dp->psr.sink_not_reliable) { 997 drm_dbg_kms(&dev_priv->drm, 998 "PSR sink implementation is not reliable\n"); 999 return; 1000 } 1001 1002 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 1003 drm_dbg_kms(&dev_priv->drm, 1004 "PSR condition failed: Interlaced mode enabled\n"); 1005 return; 1006 } 1007 1008 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); 1009 if (psr_setup_time < 0) { 1010 drm_dbg_kms(&dev_priv->drm, 1011 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 1012 intel_dp->psr_dpcd[1]); 1013 return; 1014 } 1015 1016 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 1017 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 1018 drm_dbg_kms(&dev_priv->drm, 1019 "PSR condition failed: PSR setup time (%d us) too long\n", 1020 psr_setup_time); 1021 return; 1022 } 1023 1024 crtc_state->has_psr = true; 1025 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); 1026 1027 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1028 intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, 1029 &crtc_state->psr_vsc); 1030 } 1031 1032 void intel_psr_get_config(struct intel_encoder *encoder, 1033 struct intel_crtc_state *pipe_config) 1034 { 1035 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1036 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1037 struct intel_dp *intel_dp; 1038 u32 val; 1039 1040 if (!dig_port) 1041 return; 1042 1043 intel_dp = &dig_port->dp; 1044 if (!CAN_PSR(intel_dp)) 1045 return; 1046 1047 mutex_lock(&intel_dp->psr.lock); 1048 if (!intel_dp->psr.enabled) 1049 goto unlock; 1050 1051 /* 1052 * Not possible to read EDP_PSR/PSR2_CTL registers as it is 1053 * enabled/disabled because of frontbuffer tracking and others. 1054 */ 1055 pipe_config->has_psr = true; 1056 pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; 1057 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1058 1059 if (!intel_dp->psr.psr2_enabled) 1060 goto unlock; 1061 1062 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 1063 val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); 1064 if (val & PSR2_MAN_TRK_CTL_ENABLE) 1065 pipe_config->enable_psr2_sel_fetch = true; 1066 } 1067 1068 if (DISPLAY_VER(dev_priv) >= 12) { 1069 val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder)); 1070 val &= EXITLINE_MASK; 1071 pipe_config->dc3co_exitline = val; 1072 } 1073 unlock: 1074 mutex_unlock(&intel_dp->psr.lock); 1075 } 1076 1077 static void intel_psr_activate(struct intel_dp *intel_dp) 1078 { 1079 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1080 enum transcoder transcoder = intel_dp->psr.transcoder; 1081 1082 if (transcoder_has_psr2(dev_priv, transcoder)) 1083 drm_WARN_ON(&dev_priv->drm, 1084 intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE); 1085 1086 drm_WARN_ON(&dev_priv->drm, 1087 intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE); 1088 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active); 1089 lockdep_assert_held(&intel_dp->psr.lock); 1090 1091 /* psr1 and psr2 are mutually exclusive.*/ 1092 if (intel_dp->psr.psr2_enabled) 1093 hsw_activate_psr2(intel_dp); 1094 else 1095 hsw_activate_psr1(intel_dp); 1096 1097 intel_dp->psr.active = true; 1098 } 1099 1100 static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp) 1101 { 1102 switch (intel_dp->psr.pipe) { 1103 case PIPE_A: 1104 return LATENCY_REPORTING_REMOVED_PIPE_A; 1105 case PIPE_B: 1106 return LATENCY_REPORTING_REMOVED_PIPE_B; 1107 case PIPE_C: 1108 return LATENCY_REPORTING_REMOVED_PIPE_C; 1109 default: 1110 MISSING_CASE(intel_dp->psr.pipe); 1111 return 0; 1112 } 1113 } 1114 1115 static void intel_psr_enable_source(struct intel_dp *intel_dp, 1116 const struct intel_crtc_state *crtc_state) 1117 { 1118 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1119 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1120 u32 mask; 1121 1122 /* 1123 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 1124 * mask LPSP to avoid dependency on other drivers that might block 1125 * runtime_pm besides preventing other hw tracking issues now we 1126 * can rely on frontbuffer tracking. 1127 */ 1128 mask = EDP_PSR_DEBUG_MASK_MEMUP | 1129 EDP_PSR_DEBUG_MASK_HPD | 1130 EDP_PSR_DEBUG_MASK_LPSP | 1131 EDP_PSR_DEBUG_MASK_MAX_SLEEP; 1132 1133 if (DISPLAY_VER(dev_priv) < 11) 1134 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 1135 1136 intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder), 1137 mask); 1138 1139 psr_irq_control(intel_dp); 1140 1141 if (intel_dp->psr.dc3co_exitline) { 1142 u32 val; 1143 1144 /* 1145 * TODO: if future platforms supports DC3CO in more than one 1146 * transcoder, EXITLINE will need to be unset when disabling PSR 1147 */ 1148 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder)); 1149 val &= ~EXITLINE_MASK; 1150 val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT; 1151 val |= EXITLINE_ENABLE; 1152 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); 1153 } 1154 1155 if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv)) 1156 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, 1157 intel_dp->psr.psr2_sel_fetch_enabled ? 1158 IGNORE_PSR2_HW_TRACKING : 0); 1159 1160 if (intel_dp->psr.psr2_enabled) { 1161 if (DISPLAY_VER(dev_priv) == 9) 1162 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, 1163 PSR2_VSC_ENABLE_PROG_HEADER | 1164 PSR2_ADD_VERTICAL_LINE_COUNT); 1165 1166 /* 1167 * Wa_16014451276:adlp 1168 * All supported adlp panels have 1-based X granularity, this may 1169 * cause issues if non-supported panels are used. 1170 */ 1171 if (IS_ALDERLAKE_P(dev_priv)) 1172 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, 1173 ADLP_1_BASED_X_GRANULARITY); 1174 1175 /* Wa_16011168373:adl-p */ 1176 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1177 intel_de_rmw(dev_priv, 1178 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), 1179 TRANS_SET_CONTEXT_LATENCY_MASK, 1180 TRANS_SET_CONTEXT_LATENCY_VALUE(1)); 1181 1182 /* Wa_16012604467:adlp */ 1183 if (IS_ALDERLAKE_P(dev_priv)) 1184 intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0, 1185 CLKGATE_DIS_MISC_DMASC_GATING_DIS); 1186 1187 /* Wa_16013835468:tgl[b0+], dg1 */ 1188 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) || 1189 IS_DG1(dev_priv)) { 1190 u16 vtotal, vblank; 1191 1192 vtotal = crtc_state->uapi.adjusted_mode.crtc_vtotal - 1193 crtc_state->uapi.adjusted_mode.crtc_vdisplay; 1194 vblank = crtc_state->uapi.adjusted_mode.crtc_vblank_end - 1195 crtc_state->uapi.adjusted_mode.crtc_vblank_start; 1196 if (vblank > vtotal) 1197 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, 1198 wa_16013835468_bit_get(intel_dp)); 1199 } 1200 } 1201 } 1202 1203 static bool psr_interrupt_error_check(struct intel_dp *intel_dp) 1204 { 1205 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1206 u32 val; 1207 1208 /* 1209 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 1210 * will still keep the error set even after the reset done in the 1211 * irq_preinstall and irq_uninstall hooks. 1212 * And enabling in this situation cause the screen to freeze in the 1213 * first time that PSR HW tries to activate so lets keep PSR disabled 1214 * to avoid any rendering problems. 1215 */ 1216 if (DISPLAY_VER(dev_priv) >= 12) 1217 val = intel_de_read(dev_priv, 1218 TRANS_PSR_IIR(intel_dp->psr.transcoder)); 1219 else 1220 val = intel_de_read(dev_priv, EDP_PSR_IIR); 1221 val &= psr_irq_psr_error_bit_get(intel_dp); 1222 if (val) { 1223 intel_dp->psr.sink_not_reliable = true; 1224 drm_dbg_kms(&dev_priv->drm, 1225 "PSR interruption error set, not enabling PSR\n"); 1226 return false; 1227 } 1228 1229 return true; 1230 } 1231 1232 static void intel_psr_enable_locked(struct intel_dp *intel_dp, 1233 const struct intel_crtc_state *crtc_state) 1234 { 1235 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1236 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1237 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 1238 struct intel_encoder *encoder = &dig_port->base; 1239 u32 val; 1240 1241 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); 1242 1243 intel_dp->psr.psr2_enabled = crtc_state->has_psr2; 1244 intel_dp->psr.busy_frontbuffer_bits = 0; 1245 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1246 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; 1247 /* DC5/DC6 requires at least 6 idle frames */ 1248 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 1249 intel_dp->psr.dc3co_exit_delay = val; 1250 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; 1251 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; 1252 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 1253 intel_dp->psr.req_psr2_sdp_prior_scanline = 1254 crtc_state->req_psr2_sdp_prior_scanline; 1255 1256 if (!psr_interrupt_error_check(intel_dp)) 1257 return; 1258 1259 drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", 1260 intel_dp->psr.psr2_enabled ? "2" : "1"); 1261 intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc); 1262 intel_snps_phy_update_psr_power_state(dev_priv, phy, true); 1263 intel_psr_enable_sink(intel_dp); 1264 intel_psr_enable_source(intel_dp, crtc_state); 1265 intel_dp->psr.enabled = true; 1266 intel_dp->psr.paused = false; 1267 1268 intel_psr_activate(intel_dp); 1269 } 1270 1271 static void intel_psr_exit(struct intel_dp *intel_dp) 1272 { 1273 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1274 u32 val; 1275 1276 if (!intel_dp->psr.active) { 1277 if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) { 1278 val = intel_de_read(dev_priv, 1279 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1280 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE); 1281 } 1282 1283 val = intel_de_read(dev_priv, 1284 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1285 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE); 1286 1287 return; 1288 } 1289 1290 if (intel_dp->psr.psr2_enabled) { 1291 tgl_disallow_dc3co_on_psr2_exit(intel_dp); 1292 val = intel_de_read(dev_priv, 1293 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1294 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE)); 1295 val &= ~EDP_PSR2_ENABLE; 1296 intel_de_write(dev_priv, 1297 EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 1298 } else { 1299 val = intel_de_read(dev_priv, 1300 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1301 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE)); 1302 val &= ~EDP_PSR_ENABLE; 1303 intel_de_write(dev_priv, 1304 EDP_PSR_CTL(intel_dp->psr.transcoder), val); 1305 } 1306 intel_dp->psr.active = false; 1307 } 1308 1309 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) 1310 { 1311 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1312 i915_reg_t psr_status; 1313 u32 psr_status_mask; 1314 1315 if (intel_dp->psr.psr2_enabled) { 1316 psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 1317 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 1318 } else { 1319 psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder); 1320 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 1321 } 1322 1323 /* Wait till PSR is idle */ 1324 if (intel_de_wait_for_clear(dev_priv, psr_status, 1325 psr_status_mask, 2000)) 1326 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n"); 1327 } 1328 1329 static void intel_psr_disable_locked(struct intel_dp *intel_dp) 1330 { 1331 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1332 enum phy phy = intel_port_to_phy(dev_priv, 1333 dp_to_dig_port(intel_dp)->base.port); 1334 1335 lockdep_assert_held(&intel_dp->psr.lock); 1336 1337 if (!intel_dp->psr.enabled) 1338 return; 1339 1340 drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", 1341 intel_dp->psr.psr2_enabled ? "2" : "1"); 1342 1343 intel_psr_exit(intel_dp); 1344 intel_psr_wait_exit_locked(intel_dp); 1345 1346 /* Wa_1408330847 */ 1347 if (intel_dp->psr.psr2_sel_fetch_enabled && 1348 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1349 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1350 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0); 1351 1352 if (intel_dp->psr.psr2_enabled) { 1353 /* Wa_16011168373:adl-p */ 1354 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1355 intel_de_rmw(dev_priv, 1356 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), 1357 TRANS_SET_CONTEXT_LATENCY_MASK, 0); 1358 1359 /* Wa_16012604467:adlp */ 1360 if (IS_ALDERLAKE_P(dev_priv)) 1361 intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 1362 CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0); 1363 1364 /* Wa_16013835468:tgl[b0+], dg1 */ 1365 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) || 1366 IS_DG1(dev_priv)) 1367 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 1368 wa_16013835468_bit_get(intel_dp), 0); 1369 } 1370 1371 intel_snps_phy_update_psr_power_state(dev_priv, phy, false); 1372 1373 /* Disable PSR on Sink */ 1374 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 1375 1376 if (intel_dp->psr.psr2_enabled) 1377 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); 1378 1379 intel_dp->psr.enabled = false; 1380 intel_dp->psr.psr2_enabled = false; 1381 intel_dp->psr.psr2_sel_fetch_enabled = false; 1382 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 1383 } 1384 1385 /** 1386 * intel_psr_disable - Disable PSR 1387 * @intel_dp: Intel DP 1388 * @old_crtc_state: old CRTC state 1389 * 1390 * This function needs to be called before disabling pipe. 1391 */ 1392 void intel_psr_disable(struct intel_dp *intel_dp, 1393 const struct intel_crtc_state *old_crtc_state) 1394 { 1395 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1396 1397 if (!old_crtc_state->has_psr) 1398 return; 1399 1400 if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp))) 1401 return; 1402 1403 mutex_lock(&intel_dp->psr.lock); 1404 1405 intel_psr_disable_locked(intel_dp); 1406 1407 mutex_unlock(&intel_dp->psr.lock); 1408 cancel_work_sync(&intel_dp->psr.work); 1409 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); 1410 } 1411 1412 /** 1413 * intel_psr_pause - Pause PSR 1414 * @intel_dp: Intel DP 1415 * 1416 * This function need to be called after enabling psr. 1417 */ 1418 void intel_psr_pause(struct intel_dp *intel_dp) 1419 { 1420 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1421 struct intel_psr *psr = &intel_dp->psr; 1422 1423 if (!CAN_PSR(intel_dp)) 1424 return; 1425 1426 mutex_lock(&psr->lock); 1427 1428 if (!psr->enabled) { 1429 mutex_unlock(&psr->lock); 1430 return; 1431 } 1432 1433 /* If we ever hit this, we will need to add refcount to pause/resume */ 1434 drm_WARN_ON(&dev_priv->drm, psr->paused); 1435 1436 intel_psr_exit(intel_dp); 1437 intel_psr_wait_exit_locked(intel_dp); 1438 psr->paused = true; 1439 1440 mutex_unlock(&psr->lock); 1441 1442 cancel_work_sync(&psr->work); 1443 cancel_delayed_work_sync(&psr->dc3co_work); 1444 } 1445 1446 /** 1447 * intel_psr_resume - Resume PSR 1448 * @intel_dp: Intel DP 1449 * 1450 * This function need to be called after pausing psr. 1451 */ 1452 void intel_psr_resume(struct intel_dp *intel_dp) 1453 { 1454 struct intel_psr *psr = &intel_dp->psr; 1455 1456 if (!CAN_PSR(intel_dp)) 1457 return; 1458 1459 mutex_lock(&psr->lock); 1460 1461 if (!psr->paused) 1462 goto unlock; 1463 1464 psr->paused = false; 1465 intel_psr_activate(intel_dp); 1466 1467 unlock: 1468 mutex_unlock(&psr->lock); 1469 } 1470 1471 static u32 man_trk_ctl_enable_bit_get(struct drm_i915_private *dev_priv) 1472 { 1473 return IS_ALDERLAKE_P(dev_priv) ? 0 : PSR2_MAN_TRK_CTL_ENABLE; 1474 } 1475 1476 static u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private *dev_priv) 1477 { 1478 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ? 1479 ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME : 1480 PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 1481 } 1482 1483 static u32 man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev_priv) 1484 { 1485 return IS_ALDERLAKE_P(dev_priv) ? 1486 ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE : 1487 PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; 1488 } 1489 1490 static u32 man_trk_ctl_continuos_full_frame(struct drm_i915_private *dev_priv) 1491 { 1492 return IS_ALDERLAKE_P(dev_priv) ? 1493 ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME : 1494 PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME; 1495 } 1496 1497 static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) 1498 { 1499 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1500 1501 if (intel_dp->psr.psr2_sel_fetch_enabled) 1502 intel_de_write(dev_priv, 1503 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 1504 man_trk_ctl_enable_bit_get(dev_priv) | 1505 man_trk_ctl_partial_frame_bit_get(dev_priv) | 1506 man_trk_ctl_single_full_frame_bit_get(dev_priv)); 1507 1508 /* 1509 * Display WA #0884: skl+ 1510 * This documented WA for bxt can be safely applied 1511 * broadly so we can force HW tracking to exit PSR 1512 * instead of disabling and re-enabling. 1513 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 1514 * but it makes more sense write to the current active 1515 * pipe. 1516 * 1517 * This workaround do not exist for platforms with display 10 or newer 1518 * but testing proved that it works for up display 13, for newer 1519 * than that testing will be needed. 1520 */ 1521 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 1522 } 1523 1524 void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane, 1525 const struct intel_crtc_state *crtc_state) 1526 { 1527 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1528 enum pipe pipe = plane->pipe; 1529 1530 if (!crtc_state->enable_psr2_sel_fetch) 1531 return; 1532 1533 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0); 1534 } 1535 1536 void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, 1537 const struct intel_crtc_state *crtc_state, 1538 const struct intel_plane_state *plane_state, 1539 int color_plane) 1540 { 1541 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1542 enum pipe pipe = plane->pipe; 1543 const struct drm_rect *clip; 1544 u32 val; 1545 int x, y; 1546 1547 if (!crtc_state->enable_psr2_sel_fetch) 1548 return; 1549 1550 if (plane->id == PLANE_CURSOR) { 1551 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 1552 plane_state->ctl); 1553 return; 1554 } 1555 1556 clip = &plane_state->psr2_sel_fetch_area; 1557 1558 val = (clip->y1 + plane_state->uapi.dst.y1) << 16; 1559 val |= plane_state->uapi.dst.x1; 1560 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); 1561 1562 x = plane_state->view.color_plane[color_plane].x; 1563 1564 /* 1565 * From Bspec: UV surface Start Y Position = half of Y plane Y 1566 * start position. 1567 */ 1568 if (!color_plane) 1569 y = plane_state->view.color_plane[color_plane].y + clip->y1; 1570 else 1571 y = plane_state->view.color_plane[color_plane].y + clip->y1 / 2; 1572 1573 val = y << 16 | x; 1574 1575 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), 1576 val); 1577 1578 /* Sizes are 0 based */ 1579 val = (drm_rect_height(clip) - 1) << 16; 1580 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; 1581 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); 1582 1583 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 1584 PLANE_SEL_FETCH_CTL_ENABLE); 1585 } 1586 1587 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) 1588 { 1589 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1590 struct intel_encoder *encoder; 1591 1592 if (!crtc_state->enable_psr2_sel_fetch) 1593 return; 1594 1595 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, 1596 crtc_state->uapi.encoder_mask) { 1597 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1598 1599 lockdep_assert_held(&intel_dp->psr.lock); 1600 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) 1601 return; 1602 break; 1603 } 1604 1605 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder), 1606 crtc_state->psr2_man_track_ctl); 1607 } 1608 1609 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, 1610 struct drm_rect *clip, bool full_update) 1611 { 1612 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1613 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1614 u32 val = man_trk_ctl_enable_bit_get(dev_priv); 1615 1616 /* SF partial frame enable has to be set even on full update */ 1617 val |= man_trk_ctl_partial_frame_bit_get(dev_priv); 1618 1619 if (full_update) { 1620 /* 1621 * Not applying Wa_14014971508:adlp as we do not support the 1622 * feature that requires this workaround. 1623 */ 1624 val |= man_trk_ctl_single_full_frame_bit_get(dev_priv); 1625 goto exit; 1626 } 1627 1628 if (clip->y1 == -1) 1629 goto exit; 1630 1631 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) { 1632 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1); 1633 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 - 1); 1634 } else { 1635 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4); 1636 1637 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1); 1638 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1); 1639 } 1640 exit: 1641 crtc_state->psr2_man_track_ctl = val; 1642 } 1643 1644 static void clip_area_update(struct drm_rect *overlap_damage_area, 1645 struct drm_rect *damage_area, 1646 struct drm_rect *pipe_src) 1647 { 1648 if (!drm_rect_intersect(damage_area, pipe_src)) 1649 return; 1650 1651 if (overlap_damage_area->y1 == -1) { 1652 overlap_damage_area->y1 = damage_area->y1; 1653 overlap_damage_area->y2 = damage_area->y2; 1654 return; 1655 } 1656 1657 if (damage_area->y1 < overlap_damage_area->y1) 1658 overlap_damage_area->y1 = damage_area->y1; 1659 1660 if (damage_area->y2 > overlap_damage_area->y2) 1661 overlap_damage_area->y2 = damage_area->y2; 1662 } 1663 1664 static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state, 1665 struct drm_rect *pipe_clip) 1666 { 1667 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1668 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1669 u16 y_alignment; 1670 1671 /* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */ 1672 if (crtc_state->dsc.compression_enable && 1673 (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)) 1674 y_alignment = vdsc_cfg->slice_height; 1675 else 1676 y_alignment = crtc_state->su_y_granularity; 1677 1678 pipe_clip->y1 -= pipe_clip->y1 % y_alignment; 1679 if (pipe_clip->y2 % y_alignment) 1680 pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment; 1681 1682 if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable) 1683 drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n"); 1684 } 1685 1686 /* 1687 * TODO: Not clear how to handle planes with negative position, 1688 * also planes are not updated if they have a negative X 1689 * position so for now doing a full update in this cases 1690 * 1691 * Plane scaling and rotation is not supported by selective fetch and both 1692 * properties can change without a modeset, so need to be check at every 1693 * atomic commit. 1694 */ 1695 static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state) 1696 { 1697 if (plane_state->uapi.dst.y1 < 0 || 1698 plane_state->uapi.dst.x1 < 0 || 1699 plane_state->scaler_id >= 0 || 1700 plane_state->uapi.rotation != DRM_MODE_ROTATE_0) 1701 return false; 1702 1703 return true; 1704 } 1705 1706 /* 1707 * Check for pipe properties that is not supported by selective fetch. 1708 * 1709 * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed 1710 * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch 1711 * enabled and going to the full update path. 1712 */ 1713 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state) 1714 { 1715 if (crtc_state->scaler_state.scaler_id >= 0) 1716 return false; 1717 1718 return true; 1719 } 1720 1721 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 1722 struct intel_crtc *crtc) 1723 { 1724 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1725 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 1726 struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 }; 1727 struct intel_plane_state *new_plane_state, *old_plane_state; 1728 struct intel_plane *plane; 1729 bool full_update = false; 1730 int i, ret; 1731 1732 if (!crtc_state->enable_psr2_sel_fetch) 1733 return 0; 1734 1735 if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) { 1736 full_update = true; 1737 goto skip_sel_fetch_set_loop; 1738 } 1739 1740 /* 1741 * Calculate minimal selective fetch area of each plane and calculate 1742 * the pipe damaged area. 1743 * In the next loop the plane selective fetch area will actually be set 1744 * using whole pipe damaged area. 1745 */ 1746 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1747 new_plane_state, i) { 1748 struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1, 1749 .x2 = INT_MAX }; 1750 1751 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) 1752 continue; 1753 1754 if (!new_plane_state->uapi.visible && 1755 !old_plane_state->uapi.visible) 1756 continue; 1757 1758 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 1759 full_update = true; 1760 break; 1761 } 1762 1763 /* 1764 * If visibility or plane moved, mark the whole plane area as 1765 * damaged as it needs to be complete redraw in the new and old 1766 * position. 1767 */ 1768 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || 1769 !drm_rect_equals(&new_plane_state->uapi.dst, 1770 &old_plane_state->uapi.dst)) { 1771 if (old_plane_state->uapi.visible) { 1772 damaged_area.y1 = old_plane_state->uapi.dst.y1; 1773 damaged_area.y2 = old_plane_state->uapi.dst.y2; 1774 clip_area_update(&pipe_clip, &damaged_area, 1775 &crtc_state->pipe_src); 1776 } 1777 1778 if (new_plane_state->uapi.visible) { 1779 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1780 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1781 clip_area_update(&pipe_clip, &damaged_area, 1782 &crtc_state->pipe_src); 1783 } 1784 continue; 1785 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { 1786 /* If alpha changed mark the whole plane area as damaged */ 1787 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1788 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1789 clip_area_update(&pipe_clip, &damaged_area, 1790 &crtc_state->pipe_src); 1791 continue; 1792 } 1793 1794 src = drm_plane_state_src(&new_plane_state->uapi); 1795 drm_rect_fp_to_int(&src, &src); 1796 1797 if (!drm_atomic_helper_damage_merged(&old_plane_state->uapi, 1798 &new_plane_state->uapi, &damaged_area)) 1799 continue; 1800 1801 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; 1802 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; 1803 damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1; 1804 damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1; 1805 1806 clip_area_update(&pipe_clip, &damaged_area, &crtc_state->pipe_src); 1807 } 1808 1809 /* 1810 * TODO: For now we are just using full update in case 1811 * selective fetch area calculation fails. To optimize this we 1812 * should identify cases where this happens and fix the area 1813 * calculation for those. 1814 */ 1815 if (pipe_clip.y1 == -1) { 1816 drm_info_once(&dev_priv->drm, 1817 "Selective fetch area calculation failed in pipe %c\n", 1818 pipe_name(crtc->pipe)); 1819 full_update = true; 1820 } 1821 1822 if (full_update) 1823 goto skip_sel_fetch_set_loop; 1824 1825 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 1826 if (ret) 1827 return ret; 1828 1829 intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip); 1830 1831 /* 1832 * Now that we have the pipe damaged area check if it intersect with 1833 * every plane, if it does set the plane selective fetch area. 1834 */ 1835 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1836 new_plane_state, i) { 1837 struct drm_rect *sel_fetch_area, inter; 1838 struct intel_plane *linked = new_plane_state->planar_linked_plane; 1839 1840 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || 1841 !new_plane_state->uapi.visible) 1842 continue; 1843 1844 inter = pipe_clip; 1845 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) 1846 continue; 1847 1848 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 1849 full_update = true; 1850 break; 1851 } 1852 1853 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 1854 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; 1855 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; 1856 crtc_state->update_planes |= BIT(plane->id); 1857 1858 /* 1859 * Sel_fetch_area is calculated for UV plane. Use 1860 * same area for Y plane as well. 1861 */ 1862 if (linked) { 1863 struct intel_plane_state *linked_new_plane_state; 1864 struct drm_rect *linked_sel_fetch_area; 1865 1866 linked_new_plane_state = intel_atomic_get_plane_state(state, linked); 1867 if (IS_ERR(linked_new_plane_state)) 1868 return PTR_ERR(linked_new_plane_state); 1869 1870 linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area; 1871 linked_sel_fetch_area->y1 = sel_fetch_area->y1; 1872 linked_sel_fetch_area->y2 = sel_fetch_area->y2; 1873 crtc_state->update_planes |= BIT(linked->id); 1874 } 1875 } 1876 1877 skip_sel_fetch_set_loop: 1878 psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update); 1879 return 0; 1880 } 1881 1882 void intel_psr_pre_plane_update(struct intel_atomic_state *state, 1883 struct intel_crtc *crtc) 1884 { 1885 struct drm_i915_private *i915 = to_i915(state->base.dev); 1886 const struct intel_crtc_state *old_crtc_state = 1887 intel_atomic_get_old_crtc_state(state, crtc); 1888 const struct intel_crtc_state *new_crtc_state = 1889 intel_atomic_get_new_crtc_state(state, crtc); 1890 struct intel_encoder *encoder; 1891 1892 if (!HAS_PSR(i915)) 1893 return; 1894 1895 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 1896 old_crtc_state->uapi.encoder_mask) { 1897 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1898 struct intel_psr *psr = &intel_dp->psr; 1899 bool needs_to_disable = false; 1900 1901 mutex_lock(&psr->lock); 1902 1903 /* 1904 * Reasons to disable: 1905 * - PSR disabled in new state 1906 * - All planes will go inactive 1907 * - Changing between PSR versions 1908 */ 1909 needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state); 1910 needs_to_disable |= !new_crtc_state->has_psr; 1911 needs_to_disable |= !new_crtc_state->active_planes; 1912 needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled; 1913 1914 if (psr->enabled && needs_to_disable) 1915 intel_psr_disable_locked(intel_dp); 1916 1917 mutex_unlock(&psr->lock); 1918 } 1919 } 1920 1921 static void _intel_psr_post_plane_update(const struct intel_atomic_state *state, 1922 const struct intel_crtc_state *crtc_state) 1923 { 1924 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1925 struct intel_encoder *encoder; 1926 1927 if (!crtc_state->has_psr) 1928 return; 1929 1930 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 1931 crtc_state->uapi.encoder_mask) { 1932 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1933 struct intel_psr *psr = &intel_dp->psr; 1934 1935 mutex_lock(&psr->lock); 1936 1937 if (psr->sink_not_reliable) 1938 goto exit; 1939 1940 drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes); 1941 1942 /* Only enable if there is active planes */ 1943 if (!psr->enabled && crtc_state->active_planes) 1944 intel_psr_enable_locked(intel_dp, crtc_state); 1945 1946 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 1947 if (crtc_state->crc_enabled && psr->enabled) 1948 psr_force_hw_tracking_exit(intel_dp); 1949 1950 exit: 1951 mutex_unlock(&psr->lock); 1952 } 1953 } 1954 1955 void intel_psr_post_plane_update(const struct intel_atomic_state *state) 1956 { 1957 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1958 struct intel_crtc_state *crtc_state; 1959 struct intel_crtc *crtc; 1960 int i; 1961 1962 if (!HAS_PSR(dev_priv)) 1963 return; 1964 1965 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) 1966 _intel_psr_post_plane_update(state, crtc_state); 1967 } 1968 1969 static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp) 1970 { 1971 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1972 1973 /* 1974 * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough. 1975 * As all higher states has bit 4 of PSR2 state set we can just wait for 1976 * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared. 1977 */ 1978 return intel_de_wait_for_clear(dev_priv, 1979 EDP_PSR2_STATUS(intel_dp->psr.transcoder), 1980 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50); 1981 } 1982 1983 static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp) 1984 { 1985 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1986 1987 /* 1988 * From bspec: Panel Self Refresh (BDW+) 1989 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 1990 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 1991 * defensive enough to cover everything. 1992 */ 1993 return intel_de_wait_for_clear(dev_priv, 1994 EDP_PSR_STATUS(intel_dp->psr.transcoder), 1995 EDP_PSR_STATUS_STATE_MASK, 50); 1996 } 1997 1998 /** 1999 * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update 2000 * @new_crtc_state: new CRTC state 2001 * 2002 * This function is expected to be called from pipe_update_start() where it is 2003 * not expected to race with PSR enable or disable. 2004 */ 2005 void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state) 2006 { 2007 struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev); 2008 struct intel_encoder *encoder; 2009 2010 if (!new_crtc_state->has_psr) 2011 return; 2012 2013 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, 2014 new_crtc_state->uapi.encoder_mask) { 2015 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2016 int ret; 2017 2018 lockdep_assert_held(&intel_dp->psr.lock); 2019 2020 if (!intel_dp->psr.enabled) 2021 continue; 2022 2023 if (intel_dp->psr.psr2_enabled) 2024 ret = _psr2_ready_for_pipe_update_locked(intel_dp); 2025 else 2026 ret = _psr1_ready_for_pipe_update_locked(intel_dp); 2027 2028 if (ret) 2029 drm_err(&dev_priv->drm, "PSR wait timed out, atomic update may fail\n"); 2030 } 2031 } 2032 2033 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) 2034 { 2035 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2036 i915_reg_t reg; 2037 u32 mask; 2038 int err; 2039 2040 if (!intel_dp->psr.enabled) 2041 return false; 2042 2043 if (intel_dp->psr.psr2_enabled) { 2044 reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 2045 mask = EDP_PSR2_STATUS_STATE_MASK; 2046 } else { 2047 reg = EDP_PSR_STATUS(intel_dp->psr.transcoder); 2048 mask = EDP_PSR_STATUS_STATE_MASK; 2049 } 2050 2051 mutex_unlock(&intel_dp->psr.lock); 2052 2053 err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); 2054 if (err) 2055 drm_err(&dev_priv->drm, 2056 "Timed out waiting for PSR Idle for re-enable\n"); 2057 2058 /* After the unlocked wait, verify that PSR is still wanted! */ 2059 mutex_lock(&intel_dp->psr.lock); 2060 return err == 0 && intel_dp->psr.enabled; 2061 } 2062 2063 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) 2064 { 2065 struct drm_connector_list_iter conn_iter; 2066 struct drm_modeset_acquire_ctx ctx; 2067 struct drm_atomic_state *state; 2068 struct drm_connector *conn; 2069 int err = 0; 2070 2071 state = drm_atomic_state_alloc(&dev_priv->drm); 2072 if (!state) 2073 return -ENOMEM; 2074 2075 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 2076 state->acquire_ctx = &ctx; 2077 2078 retry: 2079 2080 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 2081 drm_for_each_connector_iter(conn, &conn_iter) { 2082 struct drm_connector_state *conn_state; 2083 struct drm_crtc_state *crtc_state; 2084 2085 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) 2086 continue; 2087 2088 conn_state = drm_atomic_get_connector_state(state, conn); 2089 if (IS_ERR(conn_state)) { 2090 err = PTR_ERR(conn_state); 2091 break; 2092 } 2093 2094 if (!conn_state->crtc) 2095 continue; 2096 2097 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); 2098 if (IS_ERR(crtc_state)) { 2099 err = PTR_ERR(crtc_state); 2100 break; 2101 } 2102 2103 /* Mark mode as changed to trigger a pipe->update() */ 2104 crtc_state->mode_changed = true; 2105 } 2106 drm_connector_list_iter_end(&conn_iter); 2107 2108 if (err == 0) 2109 err = drm_atomic_commit(state); 2110 2111 if (err == -EDEADLK) { 2112 drm_atomic_state_clear(state); 2113 err = drm_modeset_backoff(&ctx); 2114 if (!err) 2115 goto retry; 2116 } 2117 2118 drm_modeset_drop_locks(&ctx); 2119 drm_modeset_acquire_fini(&ctx); 2120 drm_atomic_state_put(state); 2121 2122 return err; 2123 } 2124 2125 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) 2126 { 2127 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2128 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 2129 u32 old_mode; 2130 int ret; 2131 2132 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || 2133 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 2134 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); 2135 return -EINVAL; 2136 } 2137 2138 ret = mutex_lock_interruptible(&intel_dp->psr.lock); 2139 if (ret) 2140 return ret; 2141 2142 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; 2143 intel_dp->psr.debug = val; 2144 2145 /* 2146 * Do it right away if it's already enabled, otherwise it will be done 2147 * when enabling the source. 2148 */ 2149 if (intel_dp->psr.enabled) 2150 psr_irq_control(intel_dp); 2151 2152 mutex_unlock(&intel_dp->psr.lock); 2153 2154 if (old_mode != mode) 2155 ret = intel_psr_fastset_force(dev_priv); 2156 2157 return ret; 2158 } 2159 2160 static void intel_psr_handle_irq(struct intel_dp *intel_dp) 2161 { 2162 struct intel_psr *psr = &intel_dp->psr; 2163 2164 intel_psr_disable_locked(intel_dp); 2165 psr->sink_not_reliable = true; 2166 /* let's make sure that sink is awaken */ 2167 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 2168 } 2169 2170 static void intel_psr_work(struct work_struct *work) 2171 { 2172 struct intel_dp *intel_dp = 2173 container_of(work, typeof(*intel_dp), psr.work); 2174 2175 mutex_lock(&intel_dp->psr.lock); 2176 2177 if (!intel_dp->psr.enabled) 2178 goto unlock; 2179 2180 if (READ_ONCE(intel_dp->psr.irq_aux_error)) 2181 intel_psr_handle_irq(intel_dp); 2182 2183 /* 2184 * We have to make sure PSR is ready for re-enable 2185 * otherwise it keeps disabled until next full enable/disable cycle. 2186 * PSR might take some time to get fully disabled 2187 * and be ready for re-enable. 2188 */ 2189 if (!__psr_wait_for_idle_locked(intel_dp)) 2190 goto unlock; 2191 2192 /* 2193 * The delayed work can race with an invalidate hence we need to 2194 * recheck. Since psr_flush first clears this and then reschedules we 2195 * won't ever miss a flush when bailing out here. 2196 */ 2197 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) 2198 goto unlock; 2199 2200 intel_psr_activate(intel_dp); 2201 unlock: 2202 mutex_unlock(&intel_dp->psr.lock); 2203 } 2204 2205 static void _psr_invalidate_handle(struct intel_dp *intel_dp) 2206 { 2207 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2208 2209 if (intel_dp->psr.psr2_sel_fetch_enabled) { 2210 u32 val; 2211 2212 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) 2213 return; 2214 2215 val = man_trk_ctl_enable_bit_get(dev_priv) | 2216 man_trk_ctl_partial_frame_bit_get(dev_priv) | 2217 man_trk_ctl_continuos_full_frame(dev_priv); 2218 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), val); 2219 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 2220 intel_dp->psr.psr2_sel_fetch_cff_enabled = true; 2221 } else { 2222 intel_psr_exit(intel_dp); 2223 } 2224 } 2225 2226 /** 2227 * intel_psr_invalidate - Invalidate PSR 2228 * @dev_priv: i915 device 2229 * @frontbuffer_bits: frontbuffer plane tracking bits 2230 * @origin: which operation caused the invalidate 2231 * 2232 * Since the hardware frontbuffer tracking has gaps we need to integrate 2233 * with the software frontbuffer tracking. This function gets called every 2234 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 2235 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 2236 * 2237 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 2238 */ 2239 void intel_psr_invalidate(struct drm_i915_private *dev_priv, 2240 unsigned frontbuffer_bits, enum fb_op_origin origin) 2241 { 2242 struct intel_encoder *encoder; 2243 2244 if (origin == ORIGIN_FLIP) 2245 return; 2246 2247 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2248 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 2249 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2250 2251 mutex_lock(&intel_dp->psr.lock); 2252 if (!intel_dp->psr.enabled) { 2253 mutex_unlock(&intel_dp->psr.lock); 2254 continue; 2255 } 2256 2257 pipe_frontbuffer_bits &= 2258 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 2259 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; 2260 2261 if (pipe_frontbuffer_bits) 2262 _psr_invalidate_handle(intel_dp); 2263 2264 mutex_unlock(&intel_dp->psr.lock); 2265 } 2266 } 2267 /* 2268 * When we will be completely rely on PSR2 S/W tracking in future, 2269 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP 2270 * event also therefore tgl_dc3co_flush_locked() require to be changed 2271 * accordingly in future. 2272 */ 2273 static void 2274 tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits, 2275 enum fb_op_origin origin) 2276 { 2277 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled || 2278 !intel_dp->psr.active) 2279 return; 2280 2281 /* 2282 * At every frontbuffer flush flip event modified delay of delayed work, 2283 * when delayed work schedules that means display has been idle. 2284 */ 2285 if (!(frontbuffer_bits & 2286 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) 2287 return; 2288 2289 tgl_psr2_enable_dc3co(intel_dp); 2290 mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work, 2291 intel_dp->psr.dc3co_exit_delay); 2292 } 2293 2294 static void _psr_flush_handle(struct intel_dp *intel_dp) 2295 { 2296 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2297 2298 if (intel_dp->psr.psr2_sel_fetch_enabled) { 2299 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { 2300 /* can we turn CFF off? */ 2301 if (intel_dp->psr.busy_frontbuffer_bits == 0) { 2302 u32 val = man_trk_ctl_enable_bit_get(dev_priv) | 2303 man_trk_ctl_partial_frame_bit_get(dev_priv) | 2304 man_trk_ctl_single_full_frame_bit_get(dev_priv); 2305 2306 /* 2307 * turn continuous full frame off and do a single 2308 * full frame 2309 */ 2310 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 2311 val); 2312 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 2313 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 2314 } 2315 } else { 2316 /* 2317 * continuous full frame is disabled, only a single full 2318 * frame is required 2319 */ 2320 psr_force_hw_tracking_exit(intel_dp); 2321 } 2322 } else { 2323 psr_force_hw_tracking_exit(intel_dp); 2324 2325 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) 2326 schedule_work(&intel_dp->psr.work); 2327 } 2328 } 2329 2330 /** 2331 * intel_psr_flush - Flush PSR 2332 * @dev_priv: i915 device 2333 * @frontbuffer_bits: frontbuffer plane tracking bits 2334 * @origin: which operation caused the flush 2335 * 2336 * Since the hardware frontbuffer tracking has gaps we need to integrate 2337 * with the software frontbuffer tracking. This function gets called every 2338 * time frontbuffer rendering has completed and flushed out to memory. PSR 2339 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 2340 * 2341 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 2342 */ 2343 void intel_psr_flush(struct drm_i915_private *dev_priv, 2344 unsigned frontbuffer_bits, enum fb_op_origin origin) 2345 { 2346 struct intel_encoder *encoder; 2347 2348 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2349 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 2350 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2351 2352 mutex_lock(&intel_dp->psr.lock); 2353 if (!intel_dp->psr.enabled) { 2354 mutex_unlock(&intel_dp->psr.lock); 2355 continue; 2356 } 2357 2358 pipe_frontbuffer_bits &= 2359 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 2360 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; 2361 2362 /* 2363 * If the PSR is paused by an explicit intel_psr_paused() call, 2364 * we have to ensure that the PSR is not activated until 2365 * intel_psr_resume() is called. 2366 */ 2367 if (intel_dp->psr.paused) 2368 goto unlock; 2369 2370 if (origin == ORIGIN_FLIP || 2371 (origin == ORIGIN_CURSOR_UPDATE && 2372 !intel_dp->psr.psr2_sel_fetch_enabled)) { 2373 tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin); 2374 goto unlock; 2375 } 2376 2377 if (pipe_frontbuffer_bits == 0) 2378 goto unlock; 2379 2380 /* By definition flush = invalidate + flush */ 2381 _psr_flush_handle(intel_dp); 2382 unlock: 2383 mutex_unlock(&intel_dp->psr.lock); 2384 } 2385 } 2386 2387 /** 2388 * intel_psr_init - Init basic PSR work and mutex. 2389 * @intel_dp: Intel DP 2390 * 2391 * This function is called after the initializing connector. 2392 * (the initializing of connector treats the handling of connector capabilities) 2393 * And it initializes basic PSR stuff for each DP Encoder. 2394 */ 2395 void intel_psr_init(struct intel_dp *intel_dp) 2396 { 2397 struct intel_connector *connector = intel_dp->attached_connector; 2398 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2399 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2400 2401 if (!HAS_PSR(dev_priv)) 2402 return; 2403 2404 /* 2405 * HSW spec explicitly says PSR is tied to port A. 2406 * BDW+ platforms have a instance of PSR registers per transcoder but 2407 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder 2408 * than eDP one. 2409 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11. 2410 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11. 2411 * But GEN12 supports a instance of PSR registers per transcoder. 2412 */ 2413 if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) { 2414 drm_dbg_kms(&dev_priv->drm, 2415 "PSR condition failed: Port not supported\n"); 2416 return; 2417 } 2418 2419 intel_dp->psr.source_support = true; 2420 2421 /* Set link_standby x link_off defaults */ 2422 if (DISPLAY_VER(dev_priv) < 12) 2423 /* For new platforms up to TGL let's respect VBT back again */ 2424 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link; 2425 2426 INIT_WORK(&intel_dp->psr.work, intel_psr_work); 2427 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); 2428 mutex_init(&intel_dp->psr.lock); 2429 } 2430 2431 static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 2432 u8 *status, u8 *error_status) 2433 { 2434 struct drm_dp_aux *aux = &intel_dp->aux; 2435 int ret; 2436 2437 ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status); 2438 if (ret != 1) 2439 return ret; 2440 2441 ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status); 2442 if (ret != 1) 2443 return ret; 2444 2445 *status = *status & DP_PSR_SINK_STATE_MASK; 2446 2447 return 0; 2448 } 2449 2450 static void psr_alpm_check(struct intel_dp *intel_dp) 2451 { 2452 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2453 struct drm_dp_aux *aux = &intel_dp->aux; 2454 struct intel_psr *psr = &intel_dp->psr; 2455 u8 val; 2456 int r; 2457 2458 if (!psr->psr2_enabled) 2459 return; 2460 2461 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); 2462 if (r != 1) { 2463 drm_err(&dev_priv->drm, "Error reading ALPM status\n"); 2464 return; 2465 } 2466 2467 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) { 2468 intel_psr_disable_locked(intel_dp); 2469 psr->sink_not_reliable = true; 2470 drm_dbg_kms(&dev_priv->drm, 2471 "ALPM lock timeout error, disabling PSR\n"); 2472 2473 /* Clearing error */ 2474 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); 2475 } 2476 } 2477 2478 static void psr_capability_changed_check(struct intel_dp *intel_dp) 2479 { 2480 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2481 struct intel_psr *psr = &intel_dp->psr; 2482 u8 val; 2483 int r; 2484 2485 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 2486 if (r != 1) { 2487 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n"); 2488 return; 2489 } 2490 2491 if (val & DP_PSR_CAPS_CHANGE) { 2492 intel_psr_disable_locked(intel_dp); 2493 psr->sink_not_reliable = true; 2494 drm_dbg_kms(&dev_priv->drm, 2495 "Sink PSR capability changed, disabling PSR\n"); 2496 2497 /* Clearing it */ 2498 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 2499 } 2500 } 2501 2502 void intel_psr_short_pulse(struct intel_dp *intel_dp) 2503 { 2504 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2505 struct intel_psr *psr = &intel_dp->psr; 2506 u8 status, error_status; 2507 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 2508 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 2509 DP_PSR_LINK_CRC_ERROR; 2510 2511 if (!CAN_PSR(intel_dp)) 2512 return; 2513 2514 mutex_lock(&psr->lock); 2515 2516 if (!psr->enabled) 2517 goto exit; 2518 2519 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 2520 drm_err(&dev_priv->drm, 2521 "Error reading PSR status or error status\n"); 2522 goto exit; 2523 } 2524 2525 if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) { 2526 intel_psr_disable_locked(intel_dp); 2527 psr->sink_not_reliable = true; 2528 } 2529 2530 if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status) 2531 drm_dbg_kms(&dev_priv->drm, 2532 "PSR sink internal error, disabling PSR\n"); 2533 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 2534 drm_dbg_kms(&dev_priv->drm, 2535 "PSR RFB storage error, disabling PSR\n"); 2536 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 2537 drm_dbg_kms(&dev_priv->drm, 2538 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 2539 if (error_status & DP_PSR_LINK_CRC_ERROR) 2540 drm_dbg_kms(&dev_priv->drm, 2541 "PSR Link CRC error, disabling PSR\n"); 2542 2543 if (error_status & ~errors) 2544 drm_err(&dev_priv->drm, 2545 "PSR_ERROR_STATUS unhandled errors %x\n", 2546 error_status & ~errors); 2547 /* clear status register */ 2548 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 2549 2550 psr_alpm_check(intel_dp); 2551 psr_capability_changed_check(intel_dp); 2552 2553 exit: 2554 mutex_unlock(&psr->lock); 2555 } 2556 2557 bool intel_psr_enabled(struct intel_dp *intel_dp) 2558 { 2559 bool ret; 2560 2561 if (!CAN_PSR(intel_dp)) 2562 return false; 2563 2564 mutex_lock(&intel_dp->psr.lock); 2565 ret = intel_dp->psr.enabled; 2566 mutex_unlock(&intel_dp->psr.lock); 2567 2568 return ret; 2569 } 2570 2571 /** 2572 * intel_psr_lock - grab PSR lock 2573 * @crtc_state: the crtc state 2574 * 2575 * This is initially meant to be used by around CRTC update, when 2576 * vblank sensitive registers are updated and we need grab the lock 2577 * before it to avoid vblank evasion. 2578 */ 2579 void intel_psr_lock(const struct intel_crtc_state *crtc_state) 2580 { 2581 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2582 struct intel_encoder *encoder; 2583 2584 if (!crtc_state->has_psr) 2585 return; 2586 2587 for_each_intel_encoder_mask_with_psr(&i915->drm, encoder, 2588 crtc_state->uapi.encoder_mask) { 2589 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2590 2591 mutex_lock(&intel_dp->psr.lock); 2592 break; 2593 } 2594 } 2595 2596 /** 2597 * intel_psr_unlock - release PSR lock 2598 * @crtc_state: the crtc state 2599 * 2600 * Release the PSR lock that was held during pipe update. 2601 */ 2602 void intel_psr_unlock(const struct intel_crtc_state *crtc_state) 2603 { 2604 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2605 struct intel_encoder *encoder; 2606 2607 if (!crtc_state->has_psr) 2608 return; 2609 2610 for_each_intel_encoder_mask_with_psr(&i915->drm, encoder, 2611 crtc_state->uapi.encoder_mask) { 2612 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2613 2614 mutex_unlock(&intel_dp->psr.lock); 2615 break; 2616 } 2617 } 2618