1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_damage_helper.h> 26 27 #include "display/intel_dp.h" 28 29 #include "i915_drv.h" 30 #include "i915_reg.h" 31 #include "intel_atomic.h" 32 #include "intel_crtc.h" 33 #include "intel_de.h" 34 #include "intel_display_types.h" 35 #include "intel_dp_aux.h" 36 #include "intel_hdmi.h" 37 #include "intel_psr.h" 38 #include "intel_snps_phy.h" 39 #include "skl_universal_plane.h" 40 41 /** 42 * DOC: Panel Self Refresh (PSR/SRD) 43 * 44 * Since Haswell Display controller supports Panel Self-Refresh on display 45 * panels witch have a remote frame buffer (RFB) implemented according to PSR 46 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 47 * when system is idle but display is on as it eliminates display refresh 48 * request to DDR memory completely as long as the frame buffer for that 49 * display is unchanged. 50 * 51 * Panel Self Refresh must be supported by both Hardware (source) and 52 * Panel (sink). 53 * 54 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 55 * to power down the link and memory controller. For DSI panels the same idea 56 * is called "manual mode". 57 * 58 * The implementation uses the hardware-based PSR support which automatically 59 * enters/exits self-refresh mode. The hardware takes care of sending the 60 * required DP aux message and could even retrain the link (that part isn't 61 * enabled yet though). The hardware also keeps track of any frontbuffer 62 * changes to know when to exit self-refresh mode again. Unfortunately that 63 * part doesn't work too well, hence why the i915 PSR support uses the 64 * software frontbuffer tracking to make sure it doesn't miss a screen 65 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 66 * get called by the frontbuffer tracking code. Note that because of locking 67 * issues the self-refresh re-enable code is done from a work queue, which 68 * must be correctly synchronized/cancelled when shutting down the pipe." 69 * 70 * DC3CO (DC3 clock off) 71 * 72 * On top of PSR2, GEN12 adds a intermediate power savings state that turns 73 * clock off automatically during PSR2 idle state. 74 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep 75 * entry/exit allows the HW to enter a low-power state even when page flipping 76 * periodically (for instance a 30fps video playback scenario). 77 * 78 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), 79 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 80 * frames, if no other flip occurs and the function above is executed, DC3CO is 81 * disabled and PSR2 is configured to enter deep sleep, resetting again in case 82 * of another flip. 83 * Front buffer modifications do not trigger DC3CO activation on purpose as it 84 * would bring a lot of complexity and most of the moderns systems will only 85 * use page flips. 86 */ 87 88 static bool psr_global_enabled(struct intel_dp *intel_dp) 89 { 90 struct intel_connector *connector = intel_dp->attached_connector; 91 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 92 93 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 94 case I915_PSR_DEBUG_DEFAULT: 95 if (i915->params.enable_psr == -1) 96 return connector->panel.vbt.psr.enable; 97 return i915->params.enable_psr; 98 case I915_PSR_DEBUG_DISABLE: 99 return false; 100 default: 101 return true; 102 } 103 } 104 105 static bool psr2_global_enabled(struct intel_dp *intel_dp) 106 { 107 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 108 109 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 110 case I915_PSR_DEBUG_DISABLE: 111 case I915_PSR_DEBUG_FORCE_PSR1: 112 return false; 113 default: 114 if (i915->params.enable_psr == 1) 115 return false; 116 return true; 117 } 118 } 119 120 static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp) 121 { 122 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 123 124 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_ERROR : 125 EDP_PSR_ERROR(intel_dp->psr.transcoder); 126 } 127 128 static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp) 129 { 130 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 131 132 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_POST_EXIT : 133 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder); 134 } 135 136 static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp) 137 { 138 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 139 140 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_PRE_ENTRY : 141 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder); 142 } 143 144 static u32 psr_irq_mask_get(struct intel_dp *intel_dp) 145 { 146 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 147 148 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_MASK : 149 EDP_PSR_MASK(intel_dp->psr.transcoder); 150 } 151 152 static void psr_irq_control(struct intel_dp *intel_dp) 153 { 154 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 155 i915_reg_t imr_reg; 156 u32 mask, val; 157 158 if (DISPLAY_VER(dev_priv) >= 12) 159 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 160 else 161 imr_reg = EDP_PSR_IMR; 162 163 mask = psr_irq_psr_error_bit_get(intel_dp); 164 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) 165 mask |= psr_irq_post_exit_bit_get(intel_dp) | 166 psr_irq_pre_entry_bit_get(intel_dp); 167 168 val = intel_de_read(dev_priv, imr_reg); 169 val &= ~psr_irq_mask_get(intel_dp); 170 val |= ~mask; 171 intel_de_write(dev_priv, imr_reg, val); 172 } 173 174 static void psr_event_print(struct drm_i915_private *i915, 175 u32 val, bool psr2_enabled) 176 { 177 drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val); 178 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 179 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n"); 180 if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) 181 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n"); 182 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 183 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n"); 184 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 185 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n"); 186 if (val & PSR_EVENT_GRAPHICS_RESET) 187 drm_dbg_kms(&i915->drm, "\tGraphics reset\n"); 188 if (val & PSR_EVENT_PCH_INTERRUPT) 189 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n"); 190 if (val & PSR_EVENT_MEMORY_UP) 191 drm_dbg_kms(&i915->drm, "\tMemory up\n"); 192 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 193 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n"); 194 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 195 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n"); 196 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 197 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n"); 198 if (val & PSR_EVENT_REGISTER_UPDATE) 199 drm_dbg_kms(&i915->drm, "\tRegister updated\n"); 200 if (val & PSR_EVENT_HDCP_ENABLE) 201 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n"); 202 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 203 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n"); 204 if (val & PSR_EVENT_VBI_ENABLE) 205 drm_dbg_kms(&i915->drm, "\tVBI enabled\n"); 206 if (val & PSR_EVENT_LPSP_MODE_EXIT) 207 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n"); 208 if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) 209 drm_dbg_kms(&i915->drm, "\tPSR disabled\n"); 210 } 211 212 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) 213 { 214 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 215 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 216 ktime_t time_ns = ktime_get(); 217 i915_reg_t imr_reg; 218 219 if (DISPLAY_VER(dev_priv) >= 12) 220 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 221 else 222 imr_reg = EDP_PSR_IMR; 223 224 if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) { 225 intel_dp->psr.last_entry_attempt = time_ns; 226 drm_dbg_kms(&dev_priv->drm, 227 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 228 transcoder_name(cpu_transcoder)); 229 } 230 231 if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) { 232 intel_dp->psr.last_exit = time_ns; 233 drm_dbg_kms(&dev_priv->drm, 234 "[transcoder %s] PSR exit completed\n", 235 transcoder_name(cpu_transcoder)); 236 237 if (DISPLAY_VER(dev_priv) >= 9) { 238 u32 val = intel_de_read(dev_priv, 239 PSR_EVENT(cpu_transcoder)); 240 bool psr2_enabled = intel_dp->psr.psr2_enabled; 241 242 intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder), 243 val); 244 psr_event_print(dev_priv, val, psr2_enabled); 245 } 246 } 247 248 if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) { 249 u32 val; 250 251 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", 252 transcoder_name(cpu_transcoder)); 253 254 intel_dp->psr.irq_aux_error = true; 255 256 /* 257 * If this interruption is not masked it will keep 258 * interrupting so fast that it prevents the scheduled 259 * work to run. 260 * Also after a PSR error, we don't want to arm PSR 261 * again so we don't care about unmask the interruption 262 * or unset irq_aux_error. 263 */ 264 val = intel_de_read(dev_priv, imr_reg); 265 val |= psr_irq_psr_error_bit_get(intel_dp); 266 intel_de_write(dev_priv, imr_reg, val); 267 268 schedule_work(&intel_dp->psr.work); 269 } 270 } 271 272 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) 273 { 274 u8 alpm_caps = 0; 275 276 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, 277 &alpm_caps) != 1) 278 return false; 279 return alpm_caps & DP_ALPM_CAP; 280 } 281 282 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 283 { 284 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 285 u8 val = 8; /* assume the worst if we can't read the value */ 286 287 if (drm_dp_dpcd_readb(&intel_dp->aux, 288 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 289 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 290 else 291 drm_dbg_kms(&i915->drm, 292 "Unable to get sink synchronization latency, assuming 8 frames\n"); 293 return val; 294 } 295 296 static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) 297 { 298 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 299 ssize_t r; 300 u16 w; 301 u8 y; 302 303 /* If sink don't have specific granularity requirements set legacy ones */ 304 if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { 305 /* As PSR2 HW sends full lines, we do not care about x granularity */ 306 w = 4; 307 y = 4; 308 goto exit; 309 } 310 311 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2); 312 if (r != 2) 313 drm_dbg_kms(&i915->drm, 314 "Unable to read DP_PSR2_SU_X_GRANULARITY\n"); 315 /* 316 * Spec says that if the value read is 0 the default granularity should 317 * be used instead. 318 */ 319 if (r != 2 || w == 0) 320 w = 4; 321 322 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); 323 if (r != 1) { 324 drm_dbg_kms(&i915->drm, 325 "Unable to read DP_PSR2_SU_Y_GRANULARITY\n"); 326 y = 4; 327 } 328 if (y == 0) 329 y = 1; 330 331 exit: 332 intel_dp->psr.su_w_granularity = w; 333 intel_dp->psr.su_y_granularity = y; 334 } 335 336 void intel_psr_init_dpcd(struct intel_dp *intel_dp) 337 { 338 struct drm_i915_private *dev_priv = 339 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 340 341 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, 342 sizeof(intel_dp->psr_dpcd)); 343 344 if (!intel_dp->psr_dpcd[0]) 345 return; 346 drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n", 347 intel_dp->psr_dpcd[0]); 348 349 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { 350 drm_dbg_kms(&dev_priv->drm, 351 "PSR support not currently available for this panel\n"); 352 return; 353 } 354 355 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 356 drm_dbg_kms(&dev_priv->drm, 357 "Panel lacks power state control, PSR cannot be enabled\n"); 358 return; 359 } 360 361 intel_dp->psr.sink_support = true; 362 intel_dp->psr.sink_sync_latency = 363 intel_dp_get_sink_sync_latency(intel_dp); 364 365 if (DISPLAY_VER(dev_priv) >= 9 && 366 (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { 367 bool y_req = intel_dp->psr_dpcd[1] & 368 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 369 bool alpm = intel_dp_get_alpm_status(intel_dp); 370 371 /* 372 * All panels that supports PSR version 03h (PSR2 + 373 * Y-coordinate) can handle Y-coordinates in VSC but we are 374 * only sure that it is going to be used when required by the 375 * panel. This way panel is capable to do selective update 376 * without a aux frame sync. 377 * 378 * To support PSR version 02h and PSR version 03h without 379 * Y-coordinate requirement panels we would need to enable 380 * GTC first. 381 */ 382 intel_dp->psr.sink_psr2_support = y_req && alpm; 383 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n", 384 intel_dp->psr.sink_psr2_support ? "" : "not "); 385 386 if (intel_dp->psr.sink_psr2_support) { 387 intel_dp->psr.colorimetry_support = 388 intel_dp_get_colorimetry_status(intel_dp); 389 intel_dp_get_su_granularity(intel_dp); 390 } 391 } 392 } 393 394 static void intel_psr_enable_sink(struct intel_dp *intel_dp) 395 { 396 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 397 u8 dpcd_val = DP_PSR_ENABLE; 398 399 /* Enable ALPM at sink for psr2 */ 400 if (intel_dp->psr.psr2_enabled) { 401 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 402 DP_ALPM_ENABLE | 403 DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); 404 405 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 406 } else { 407 if (intel_dp->psr.link_standby) 408 dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; 409 410 if (DISPLAY_VER(dev_priv) >= 8) 411 dpcd_val |= DP_PSR_CRC_VERIFICATION; 412 } 413 414 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 415 dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; 416 417 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); 418 419 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 420 } 421 422 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 423 { 424 struct intel_connector *connector = intel_dp->attached_connector; 425 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 426 u32 val = 0; 427 428 if (DISPLAY_VER(dev_priv) >= 11) 429 val |= EDP_PSR_TP4_TIME_0US; 430 431 if (dev_priv->params.psr_safest_params) { 432 val |= EDP_PSR_TP1_TIME_2500us; 433 val |= EDP_PSR_TP2_TP3_TIME_2500us; 434 goto check_tp3_sel; 435 } 436 437 if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0) 438 val |= EDP_PSR_TP1_TIME_0us; 439 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100) 440 val |= EDP_PSR_TP1_TIME_100us; 441 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500) 442 val |= EDP_PSR_TP1_TIME_500us; 443 else 444 val |= EDP_PSR_TP1_TIME_2500us; 445 446 if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) 447 val |= EDP_PSR_TP2_TP3_TIME_0us; 448 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100) 449 val |= EDP_PSR_TP2_TP3_TIME_100us; 450 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500) 451 val |= EDP_PSR_TP2_TP3_TIME_500us; 452 else 453 val |= EDP_PSR_TP2_TP3_TIME_2500us; 454 455 check_tp3_sel: 456 if (intel_dp_source_supports_tps3(dev_priv) && 457 drm_dp_tps3_supported(intel_dp->dpcd)) 458 val |= EDP_PSR_TP1_TP3_SEL; 459 else 460 val |= EDP_PSR_TP1_TP2_SEL; 461 462 return val; 463 } 464 465 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 466 { 467 struct intel_connector *connector = intel_dp->attached_connector; 468 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 469 int idle_frames; 470 471 /* Let's use 6 as the minimum to cover all known cases including the 472 * off-by-one issue that HW has in some cases. 473 */ 474 idle_frames = max(6, connector->panel.vbt.psr.idle_frames); 475 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1); 476 477 if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf)) 478 idle_frames = 0xf; 479 480 return idle_frames; 481 } 482 483 static void hsw_activate_psr1(struct intel_dp *intel_dp) 484 { 485 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 486 u32 max_sleep_time = 0x1f; 487 u32 val = EDP_PSR_ENABLE; 488 489 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT; 490 491 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; 492 if (IS_HASWELL(dev_priv)) 493 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 494 495 if (intel_dp->psr.link_standby) 496 val |= EDP_PSR_LINK_STANDBY; 497 498 val |= intel_psr1_get_tp_time(intel_dp); 499 500 if (DISPLAY_VER(dev_priv) >= 8) 501 val |= EDP_PSR_CRC_ENABLE; 502 503 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) & 504 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK); 505 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val); 506 } 507 508 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 509 { 510 struct intel_connector *connector = intel_dp->attached_connector; 511 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 512 u32 val = 0; 513 514 if (dev_priv->params.psr_safest_params) 515 return EDP_PSR2_TP2_TIME_2500us; 516 517 if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 518 connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 519 val |= EDP_PSR2_TP2_TIME_50us; 520 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 521 val |= EDP_PSR2_TP2_TIME_100us; 522 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 523 val |= EDP_PSR2_TP2_TIME_500us; 524 else 525 val |= EDP_PSR2_TP2_TIME_2500us; 526 527 return val; 528 } 529 530 static void hsw_activate_psr2(struct intel_dp *intel_dp) 531 { 532 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 533 u32 val = EDP_PSR2_ENABLE; 534 535 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT; 536 537 if (DISPLAY_VER(dev_priv) <= 13 && !IS_ALDERLAKE_P(dev_priv)) 538 val |= EDP_SU_TRACK_ENABLE; 539 540 if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12) 541 val |= EDP_Y_COORDINATE_ENABLE; 542 543 val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2)); 544 val |= intel_psr2_get_tp_time(intel_dp); 545 546 /* Wa_22012278275:adl-p */ 547 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { 548 static const u8 map[] = { 549 2, /* 5 lines */ 550 1, /* 6 lines */ 551 0, /* 7 lines */ 552 3, /* 8 lines */ 553 6, /* 9 lines */ 554 5, /* 10 lines */ 555 4, /* 11 lines */ 556 7, /* 12 lines */ 557 }; 558 /* 559 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see 560 * comments bellow for more information 561 */ 562 u32 tmp, lines = 7; 563 564 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 565 566 tmp = map[lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; 567 tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT; 568 val |= tmp; 569 570 tmp = map[lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; 571 tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT; 572 val |= tmp; 573 } else if (DISPLAY_VER(dev_priv) >= 12) { 574 /* 575 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default 576 * values from BSpec. In order to setting an optimal power 577 * consumption, lower than 4k resolution mode needs to decrease 578 * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution 579 * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE. 580 */ 581 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 582 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7); 583 val |= TGL_EDP_PSR2_FAST_WAKE(7); 584 } else if (DISPLAY_VER(dev_priv) >= 9) { 585 val |= EDP_PSR2_IO_BUFFER_WAKE(7); 586 val |= EDP_PSR2_FAST_WAKE(7); 587 } 588 589 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 590 val |= EDP_PSR2_SU_SDP_SCANLINE; 591 592 if (intel_dp->psr.psr2_sel_fetch_enabled) { 593 u32 tmp; 594 595 /* Wa_1408330847 */ 596 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 597 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 598 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 599 DIS_RAM_BYPASS_PSR2_MAN_TRACK); 600 601 tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); 602 drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); 603 } else if (HAS_PSR2_SEL_FETCH(dev_priv)) { 604 intel_de_write(dev_priv, 605 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0); 606 } 607 608 /* 609 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 610 * recommending keep this bit unset while PSR2 is enabled. 611 */ 612 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0); 613 614 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 615 } 616 617 static bool 618 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) 619 { 620 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 621 return trans == TRANSCODER_A || trans == TRANSCODER_B; 622 else if (DISPLAY_VER(dev_priv) >= 12) 623 return trans == TRANSCODER_A; 624 else 625 return trans == TRANSCODER_EDP; 626 } 627 628 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate) 629 { 630 if (!cstate || !cstate->hw.active) 631 return 0; 632 633 return DIV_ROUND_UP(1000 * 1000, 634 drm_mode_vrefresh(&cstate->hw.adjusted_mode)); 635 } 636 637 static void psr2_program_idle_frames(struct intel_dp *intel_dp, 638 u32 idle_frames) 639 { 640 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 641 u32 val; 642 643 idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; 644 val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder)); 645 val &= ~EDP_PSR2_IDLE_FRAME_MASK; 646 val |= idle_frames; 647 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 648 } 649 650 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) 651 { 652 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 653 654 psr2_program_idle_frames(intel_dp, 0); 655 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO); 656 } 657 658 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp) 659 { 660 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 661 662 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 663 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp)); 664 } 665 666 static void tgl_dc3co_disable_work(struct work_struct *work) 667 { 668 struct intel_dp *intel_dp = 669 container_of(work, typeof(*intel_dp), psr.dc3co_work.work); 670 671 mutex_lock(&intel_dp->psr.lock); 672 /* If delayed work is pending, it is not idle */ 673 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) 674 goto unlock; 675 676 tgl_psr2_disable_dc3co(intel_dp); 677 unlock: 678 mutex_unlock(&intel_dp->psr.lock); 679 } 680 681 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) 682 { 683 if (!intel_dp->psr.dc3co_exitline) 684 return; 685 686 cancel_delayed_work(&intel_dp->psr.dc3co_work); 687 /* Before PSR2 exit disallow dc3co*/ 688 tgl_psr2_disable_dc3co(intel_dp); 689 } 690 691 static bool 692 dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp, 693 struct intel_crtc_state *crtc_state) 694 { 695 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 696 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 697 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 698 enum port port = dig_port->base.port; 699 700 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 701 return pipe <= PIPE_B && port <= PORT_B; 702 else 703 return pipe == PIPE_A && port == PORT_A; 704 } 705 706 static void 707 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 708 struct intel_crtc_state *crtc_state) 709 { 710 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; 711 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 712 u32 exit_scanlines; 713 714 /* 715 * FIXME: Due to the changed sequence of activating/deactivating DC3CO, 716 * disable DC3CO until the changed dc3co activating/deactivating sequence 717 * is applied. B.Specs:49196 718 */ 719 return; 720 721 /* 722 * DMC's DC3CO exit mechanism has an issue with Selective Fecth 723 * TODO: when the issue is addressed, this restriction should be removed. 724 */ 725 if (crtc_state->enable_psr2_sel_fetch) 726 return; 727 728 if (!(dev_priv->display.dmc.allowed_dc_mask & DC_STATE_EN_DC3CO)) 729 return; 730 731 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) 732 return; 733 734 /* Wa_16011303918:adl-p */ 735 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 736 return; 737 738 /* 739 * DC3CO Exit time 200us B.Spec 49196 740 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 741 */ 742 exit_scanlines = 743 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; 744 745 if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay)) 746 return; 747 748 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; 749 } 750 751 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, 752 struct intel_crtc_state *crtc_state) 753 { 754 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 755 756 if (!dev_priv->params.enable_psr2_sel_fetch && 757 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 758 drm_dbg_kms(&dev_priv->drm, 759 "PSR2 sel fetch not enabled, disabled by parameter\n"); 760 return false; 761 } 762 763 if (crtc_state->uapi.async_flip) { 764 drm_dbg_kms(&dev_priv->drm, 765 "PSR2 sel fetch not enabled, async flip enabled\n"); 766 return false; 767 } 768 769 /* Wa_14010254185 Wa_14010103792 */ 770 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { 771 drm_dbg_kms(&dev_priv->drm, 772 "PSR2 sel fetch not enabled, missing the implementation of WAs\n"); 773 return false; 774 } 775 776 return crtc_state->enable_psr2_sel_fetch = true; 777 } 778 779 static bool psr2_granularity_check(struct intel_dp *intel_dp, 780 struct intel_crtc_state *crtc_state) 781 { 782 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 783 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 784 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 785 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 786 u16 y_granularity = 0; 787 788 /* PSR2 HW only send full lines so we only need to validate the width */ 789 if (crtc_hdisplay % intel_dp->psr.su_w_granularity) 790 return false; 791 792 if (crtc_vdisplay % intel_dp->psr.su_y_granularity) 793 return false; 794 795 /* HW tracking is only aligned to 4 lines */ 796 if (!crtc_state->enable_psr2_sel_fetch) 797 return intel_dp->psr.su_y_granularity == 4; 798 799 /* 800 * adl_p and mtl platforms have 1 line granularity. 801 * For other platforms with SW tracking we can adjust the y coordinates 802 * to match sink requirement if multiple of 4. 803 */ 804 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 805 y_granularity = intel_dp->psr.su_y_granularity; 806 else if (intel_dp->psr.su_y_granularity <= 2) 807 y_granularity = 4; 808 else if ((intel_dp->psr.su_y_granularity % 4) == 0) 809 y_granularity = intel_dp->psr.su_y_granularity; 810 811 if (y_granularity == 0 || crtc_vdisplay % y_granularity) 812 return false; 813 814 if (crtc_state->dsc.compression_enable && 815 vdsc_cfg->slice_height % y_granularity) 816 return false; 817 818 crtc_state->su_y_granularity = y_granularity; 819 return true; 820 } 821 822 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp, 823 struct intel_crtc_state *crtc_state) 824 { 825 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; 826 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 827 u32 hblank_total, hblank_ns, req_ns; 828 829 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; 830 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); 831 832 /* From spec: ((60 / number of lanes) + 11) * 1000 / symbol clock frequency MHz */ 833 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); 834 835 if ((hblank_ns - req_ns) > 100) 836 return true; 837 838 /* Not supported <13 / Wa_22012279113:adl-p */ 839 if (DISPLAY_VER(dev_priv) <= 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b) 840 return false; 841 842 crtc_state->req_psr2_sdp_prior_scanline = true; 843 return true; 844 } 845 846 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 847 struct intel_crtc_state *crtc_state) 848 { 849 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 850 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 851 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 852 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 853 854 if (!intel_dp->psr.sink_psr2_support) 855 return false; 856 857 /* JSL and EHL only supports eDP 1.3 */ 858 if (IS_JSL_EHL(dev_priv)) { 859 drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n"); 860 return false; 861 } 862 863 /* Wa_16011181250 */ 864 if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) || 865 IS_DG2(dev_priv)) { 866 drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n"); 867 return false; 868 } 869 870 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 871 drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n"); 872 return false; 873 } 874 875 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { 876 drm_dbg_kms(&dev_priv->drm, 877 "PSR2 not supported in transcoder %s\n", 878 transcoder_name(crtc_state->cpu_transcoder)); 879 return false; 880 } 881 882 if (!psr2_global_enabled(intel_dp)) { 883 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); 884 return false; 885 } 886 887 /* 888 * DSC and PSR2 cannot be enabled simultaneously. If a requested 889 * resolution requires DSC to be enabled, priority is given to DSC 890 * over PSR2. 891 */ 892 if (crtc_state->dsc.compression_enable && 893 (DISPLAY_VER(dev_priv) <= 13 && !IS_ALDERLAKE_P(dev_priv))) { 894 drm_dbg_kms(&dev_priv->drm, 895 "PSR2 cannot be enabled since DSC is enabled\n"); 896 return false; 897 } 898 899 if (crtc_state->crc_enabled) { 900 drm_dbg_kms(&dev_priv->drm, 901 "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); 902 return false; 903 } 904 905 if (DISPLAY_VER(dev_priv) >= 12) { 906 psr_max_h = 5120; 907 psr_max_v = 3200; 908 max_bpp = 30; 909 } else if (DISPLAY_VER(dev_priv) >= 10) { 910 psr_max_h = 4096; 911 psr_max_v = 2304; 912 max_bpp = 24; 913 } else if (DISPLAY_VER(dev_priv) == 9) { 914 psr_max_h = 3640; 915 psr_max_v = 2304; 916 max_bpp = 24; 917 } 918 919 if (crtc_state->pipe_bpp > max_bpp) { 920 drm_dbg_kms(&dev_priv->drm, 921 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 922 crtc_state->pipe_bpp, max_bpp); 923 return false; 924 } 925 926 /* Wa_16011303918:adl-p */ 927 if (crtc_state->vrr.enable && 928 IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 929 drm_dbg_kms(&dev_priv->drm, 930 "PSR2 not enabled, not compatible with HW stepping + VRR\n"); 931 return false; 932 } 933 934 if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) { 935 drm_dbg_kms(&dev_priv->drm, 936 "PSR2 not enabled, PSR2 SDP indication do not fit in hblank\n"); 937 return false; 938 } 939 940 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 941 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && 942 !HAS_PSR_HW_TRACKING(dev_priv)) { 943 drm_dbg_kms(&dev_priv->drm, 944 "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); 945 return false; 946 } 947 } 948 949 /* Wa_2209313811 */ 950 if (!crtc_state->enable_psr2_sel_fetch && 951 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { 952 drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n"); 953 goto unsupported; 954 } 955 956 if (!psr2_granularity_check(intel_dp, crtc_state)) { 957 drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n"); 958 goto unsupported; 959 } 960 961 if (!crtc_state->enable_psr2_sel_fetch && 962 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { 963 drm_dbg_kms(&dev_priv->drm, 964 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 965 crtc_hdisplay, crtc_vdisplay, 966 psr_max_h, psr_max_v); 967 goto unsupported; 968 } 969 970 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); 971 return true; 972 973 unsupported: 974 crtc_state->enable_psr2_sel_fetch = false; 975 return false; 976 } 977 978 void intel_psr_compute_config(struct intel_dp *intel_dp, 979 struct intel_crtc_state *crtc_state, 980 struct drm_connector_state *conn_state) 981 { 982 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 983 const struct drm_display_mode *adjusted_mode = 984 &crtc_state->hw.adjusted_mode; 985 int psr_setup_time; 986 987 /* 988 * Current PSR panels don't work reliably with VRR enabled 989 * So if VRR is enabled, do not enable PSR. 990 */ 991 if (crtc_state->vrr.enable) 992 return; 993 994 if (!CAN_PSR(intel_dp)) 995 return; 996 997 if (!psr_global_enabled(intel_dp)) { 998 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); 999 return; 1000 } 1001 1002 if (intel_dp->psr.sink_not_reliable) { 1003 drm_dbg_kms(&dev_priv->drm, 1004 "PSR sink implementation is not reliable\n"); 1005 return; 1006 } 1007 1008 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 1009 drm_dbg_kms(&dev_priv->drm, 1010 "PSR condition failed: Interlaced mode enabled\n"); 1011 return; 1012 } 1013 1014 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); 1015 if (psr_setup_time < 0) { 1016 drm_dbg_kms(&dev_priv->drm, 1017 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 1018 intel_dp->psr_dpcd[1]); 1019 return; 1020 } 1021 1022 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 1023 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 1024 drm_dbg_kms(&dev_priv->drm, 1025 "PSR condition failed: PSR setup time (%d us) too long\n", 1026 psr_setup_time); 1027 return; 1028 } 1029 1030 crtc_state->has_psr = true; 1031 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); 1032 1033 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1034 intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, 1035 &crtc_state->psr_vsc); 1036 } 1037 1038 void intel_psr_get_config(struct intel_encoder *encoder, 1039 struct intel_crtc_state *pipe_config) 1040 { 1041 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1042 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1043 struct intel_dp *intel_dp; 1044 u32 val; 1045 1046 if (!dig_port) 1047 return; 1048 1049 intel_dp = &dig_port->dp; 1050 if (!CAN_PSR(intel_dp)) 1051 return; 1052 1053 mutex_lock(&intel_dp->psr.lock); 1054 if (!intel_dp->psr.enabled) 1055 goto unlock; 1056 1057 /* 1058 * Not possible to read EDP_PSR/PSR2_CTL registers as it is 1059 * enabled/disabled because of frontbuffer tracking and others. 1060 */ 1061 pipe_config->has_psr = true; 1062 pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; 1063 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1064 1065 if (!intel_dp->psr.psr2_enabled) 1066 goto unlock; 1067 1068 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 1069 val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); 1070 if (val & PSR2_MAN_TRK_CTL_ENABLE) 1071 pipe_config->enable_psr2_sel_fetch = true; 1072 } 1073 1074 if (DISPLAY_VER(dev_priv) >= 12) { 1075 val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder)); 1076 val &= EXITLINE_MASK; 1077 pipe_config->dc3co_exitline = val; 1078 } 1079 unlock: 1080 mutex_unlock(&intel_dp->psr.lock); 1081 } 1082 1083 static void intel_psr_activate(struct intel_dp *intel_dp) 1084 { 1085 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1086 enum transcoder transcoder = intel_dp->psr.transcoder; 1087 1088 if (transcoder_has_psr2(dev_priv, transcoder)) 1089 drm_WARN_ON(&dev_priv->drm, 1090 intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE); 1091 1092 drm_WARN_ON(&dev_priv->drm, 1093 intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE); 1094 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active); 1095 lockdep_assert_held(&intel_dp->psr.lock); 1096 1097 /* psr1 and psr2 are mutually exclusive.*/ 1098 if (intel_dp->psr.psr2_enabled) 1099 hsw_activate_psr2(intel_dp); 1100 else 1101 hsw_activate_psr1(intel_dp); 1102 1103 intel_dp->psr.active = true; 1104 } 1105 1106 static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp) 1107 { 1108 switch (intel_dp->psr.pipe) { 1109 case PIPE_A: 1110 return LATENCY_REPORTING_REMOVED_PIPE_A; 1111 case PIPE_B: 1112 return LATENCY_REPORTING_REMOVED_PIPE_B; 1113 case PIPE_C: 1114 return LATENCY_REPORTING_REMOVED_PIPE_C; 1115 default: 1116 MISSING_CASE(intel_dp->psr.pipe); 1117 return 0; 1118 } 1119 } 1120 1121 static void intel_psr_enable_source(struct intel_dp *intel_dp, 1122 const struct intel_crtc_state *crtc_state) 1123 { 1124 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1125 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1126 u32 mask; 1127 1128 /* 1129 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 1130 * mask LPSP to avoid dependency on other drivers that might block 1131 * runtime_pm besides preventing other hw tracking issues now we 1132 * can rely on frontbuffer tracking. 1133 */ 1134 mask = EDP_PSR_DEBUG_MASK_MEMUP | 1135 EDP_PSR_DEBUG_MASK_HPD | 1136 EDP_PSR_DEBUG_MASK_LPSP | 1137 EDP_PSR_DEBUG_MASK_MAX_SLEEP; 1138 1139 if (DISPLAY_VER(dev_priv) < 11) 1140 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 1141 1142 intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder), 1143 mask); 1144 1145 psr_irq_control(intel_dp); 1146 1147 if (intel_dp->psr.dc3co_exitline) { 1148 u32 val; 1149 1150 /* 1151 * TODO: if future platforms supports DC3CO in more than one 1152 * transcoder, EXITLINE will need to be unset when disabling PSR 1153 */ 1154 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder)); 1155 val &= ~EXITLINE_MASK; 1156 val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT; 1157 val |= EXITLINE_ENABLE; 1158 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); 1159 } 1160 1161 if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv)) 1162 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, 1163 intel_dp->psr.psr2_sel_fetch_enabled ? 1164 IGNORE_PSR2_HW_TRACKING : 0); 1165 1166 if (intel_dp->psr.psr2_enabled) { 1167 if (DISPLAY_VER(dev_priv) == 9) 1168 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, 1169 PSR2_VSC_ENABLE_PROG_HEADER | 1170 PSR2_ADD_VERTICAL_LINE_COUNT); 1171 1172 /* 1173 * Wa_16014451276:adlp,mtl[a0,b0] 1174 * All supported adlp panels have 1-based X granularity, this may 1175 * cause issues if non-supported panels are used. 1176 */ 1177 if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1178 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 0, 1179 ADLP_1_BASED_X_GRANULARITY); 1180 else if (IS_ALDERLAKE_P(dev_priv)) 1181 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, 1182 ADLP_1_BASED_X_GRANULARITY); 1183 1184 /* Wa_16011168373:adl-p */ 1185 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1186 intel_de_rmw(dev_priv, 1187 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), 1188 TRANS_SET_CONTEXT_LATENCY_MASK, 1189 TRANS_SET_CONTEXT_LATENCY_VALUE(1)); 1190 1191 /* Wa_16012604467:adlp,mtl[a0,b0] */ 1192 if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1193 intel_de_rmw(dev_priv, 1194 MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0, 1195 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS); 1196 else if (IS_ALDERLAKE_P(dev_priv)) 1197 intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0, 1198 CLKGATE_DIS_MISC_DMASC_GATING_DIS); 1199 1200 /* Wa_16013835468:tgl[b0+], dg1 */ 1201 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) || 1202 IS_DG1(dev_priv)) { 1203 u16 vtotal, vblank; 1204 1205 vtotal = crtc_state->uapi.adjusted_mode.crtc_vtotal - 1206 crtc_state->uapi.adjusted_mode.crtc_vdisplay; 1207 vblank = crtc_state->uapi.adjusted_mode.crtc_vblank_end - 1208 crtc_state->uapi.adjusted_mode.crtc_vblank_start; 1209 if (vblank > vtotal) 1210 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, 1211 wa_16013835468_bit_get(intel_dp)); 1212 } 1213 } 1214 } 1215 1216 static bool psr_interrupt_error_check(struct intel_dp *intel_dp) 1217 { 1218 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1219 u32 val; 1220 1221 /* 1222 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 1223 * will still keep the error set even after the reset done in the 1224 * irq_preinstall and irq_uninstall hooks. 1225 * And enabling in this situation cause the screen to freeze in the 1226 * first time that PSR HW tries to activate so lets keep PSR disabled 1227 * to avoid any rendering problems. 1228 */ 1229 if (DISPLAY_VER(dev_priv) >= 12) 1230 val = intel_de_read(dev_priv, 1231 TRANS_PSR_IIR(intel_dp->psr.transcoder)); 1232 else 1233 val = intel_de_read(dev_priv, EDP_PSR_IIR); 1234 val &= psr_irq_psr_error_bit_get(intel_dp); 1235 if (val) { 1236 intel_dp->psr.sink_not_reliable = true; 1237 drm_dbg_kms(&dev_priv->drm, 1238 "PSR interruption error set, not enabling PSR\n"); 1239 return false; 1240 } 1241 1242 return true; 1243 } 1244 1245 static void intel_psr_enable_locked(struct intel_dp *intel_dp, 1246 const struct intel_crtc_state *crtc_state) 1247 { 1248 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1249 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1250 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 1251 struct intel_encoder *encoder = &dig_port->base; 1252 u32 val; 1253 1254 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); 1255 1256 intel_dp->psr.psr2_enabled = crtc_state->has_psr2; 1257 intel_dp->psr.busy_frontbuffer_bits = 0; 1258 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1259 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; 1260 /* DC5/DC6 requires at least 6 idle frames */ 1261 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 1262 intel_dp->psr.dc3co_exit_delay = val; 1263 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; 1264 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; 1265 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 1266 intel_dp->psr.req_psr2_sdp_prior_scanline = 1267 crtc_state->req_psr2_sdp_prior_scanline; 1268 1269 if (!psr_interrupt_error_check(intel_dp)) 1270 return; 1271 1272 drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", 1273 intel_dp->psr.psr2_enabled ? "2" : "1"); 1274 intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc); 1275 intel_snps_phy_update_psr_power_state(dev_priv, phy, true); 1276 intel_psr_enable_sink(intel_dp); 1277 intel_psr_enable_source(intel_dp, crtc_state); 1278 intel_dp->psr.enabled = true; 1279 intel_dp->psr.paused = false; 1280 1281 intel_psr_activate(intel_dp); 1282 } 1283 1284 static void intel_psr_exit(struct intel_dp *intel_dp) 1285 { 1286 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1287 u32 val; 1288 1289 if (!intel_dp->psr.active) { 1290 if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) { 1291 val = intel_de_read(dev_priv, 1292 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1293 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE); 1294 } 1295 1296 val = intel_de_read(dev_priv, 1297 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1298 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE); 1299 1300 return; 1301 } 1302 1303 if (intel_dp->psr.psr2_enabled) { 1304 tgl_disallow_dc3co_on_psr2_exit(intel_dp); 1305 val = intel_de_read(dev_priv, 1306 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1307 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE)); 1308 val &= ~EDP_PSR2_ENABLE; 1309 intel_de_write(dev_priv, 1310 EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 1311 } else { 1312 val = intel_de_read(dev_priv, 1313 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1314 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE)); 1315 val &= ~EDP_PSR_ENABLE; 1316 intel_de_write(dev_priv, 1317 EDP_PSR_CTL(intel_dp->psr.transcoder), val); 1318 } 1319 intel_dp->psr.active = false; 1320 } 1321 1322 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) 1323 { 1324 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1325 i915_reg_t psr_status; 1326 u32 psr_status_mask; 1327 1328 if (intel_dp->psr.psr2_enabled) { 1329 psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 1330 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 1331 } else { 1332 psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder); 1333 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 1334 } 1335 1336 /* Wait till PSR is idle */ 1337 if (intel_de_wait_for_clear(dev_priv, psr_status, 1338 psr_status_mask, 2000)) 1339 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n"); 1340 } 1341 1342 static void intel_psr_disable_locked(struct intel_dp *intel_dp) 1343 { 1344 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1345 enum phy phy = intel_port_to_phy(dev_priv, 1346 dp_to_dig_port(intel_dp)->base.port); 1347 1348 lockdep_assert_held(&intel_dp->psr.lock); 1349 1350 if (!intel_dp->psr.enabled) 1351 return; 1352 1353 drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", 1354 intel_dp->psr.psr2_enabled ? "2" : "1"); 1355 1356 intel_psr_exit(intel_dp); 1357 intel_psr_wait_exit_locked(intel_dp); 1358 1359 /* Wa_1408330847 */ 1360 if (intel_dp->psr.psr2_sel_fetch_enabled && 1361 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1362 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1363 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0); 1364 1365 if (intel_dp->psr.psr2_enabled) { 1366 /* Wa_16011168373:adl-p */ 1367 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1368 intel_de_rmw(dev_priv, 1369 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), 1370 TRANS_SET_CONTEXT_LATENCY_MASK, 0); 1371 1372 /* Wa_16012604467:adlp,mtl[a0,b0] */ 1373 if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1374 intel_de_rmw(dev_priv, 1375 MTL_CLKGATE_DIS_TRANS(intel_dp->psr.transcoder), 1376 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); 1377 else if (IS_ALDERLAKE_P(dev_priv)) 1378 intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 1379 CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0); 1380 1381 /* Wa_16013835468:tgl[b0+], dg1 */ 1382 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) || 1383 IS_DG1(dev_priv)) 1384 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 1385 wa_16013835468_bit_get(intel_dp), 0); 1386 } 1387 1388 intel_snps_phy_update_psr_power_state(dev_priv, phy, false); 1389 1390 /* Disable PSR on Sink */ 1391 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 1392 1393 if (intel_dp->psr.psr2_enabled) 1394 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); 1395 1396 intel_dp->psr.enabled = false; 1397 intel_dp->psr.psr2_enabled = false; 1398 intel_dp->psr.psr2_sel_fetch_enabled = false; 1399 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 1400 } 1401 1402 /** 1403 * intel_psr_disable - Disable PSR 1404 * @intel_dp: Intel DP 1405 * @old_crtc_state: old CRTC state 1406 * 1407 * This function needs to be called before disabling pipe. 1408 */ 1409 void intel_psr_disable(struct intel_dp *intel_dp, 1410 const struct intel_crtc_state *old_crtc_state) 1411 { 1412 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1413 1414 if (!old_crtc_state->has_psr) 1415 return; 1416 1417 if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp))) 1418 return; 1419 1420 mutex_lock(&intel_dp->psr.lock); 1421 1422 intel_psr_disable_locked(intel_dp); 1423 1424 mutex_unlock(&intel_dp->psr.lock); 1425 cancel_work_sync(&intel_dp->psr.work); 1426 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); 1427 } 1428 1429 /** 1430 * intel_psr_pause - Pause PSR 1431 * @intel_dp: Intel DP 1432 * 1433 * This function need to be called after enabling psr. 1434 */ 1435 void intel_psr_pause(struct intel_dp *intel_dp) 1436 { 1437 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1438 struct intel_psr *psr = &intel_dp->psr; 1439 1440 if (!CAN_PSR(intel_dp)) 1441 return; 1442 1443 mutex_lock(&psr->lock); 1444 1445 if (!psr->enabled) { 1446 mutex_unlock(&psr->lock); 1447 return; 1448 } 1449 1450 /* If we ever hit this, we will need to add refcount to pause/resume */ 1451 drm_WARN_ON(&dev_priv->drm, psr->paused); 1452 1453 intel_psr_exit(intel_dp); 1454 intel_psr_wait_exit_locked(intel_dp); 1455 psr->paused = true; 1456 1457 mutex_unlock(&psr->lock); 1458 1459 cancel_work_sync(&psr->work); 1460 cancel_delayed_work_sync(&psr->dc3co_work); 1461 } 1462 1463 /** 1464 * intel_psr_resume - Resume PSR 1465 * @intel_dp: Intel DP 1466 * 1467 * This function need to be called after pausing psr. 1468 */ 1469 void intel_psr_resume(struct intel_dp *intel_dp) 1470 { 1471 struct intel_psr *psr = &intel_dp->psr; 1472 1473 if (!CAN_PSR(intel_dp)) 1474 return; 1475 1476 mutex_lock(&psr->lock); 1477 1478 if (!psr->paused) 1479 goto unlock; 1480 1481 psr->paused = false; 1482 intel_psr_activate(intel_dp); 1483 1484 unlock: 1485 mutex_unlock(&psr->lock); 1486 } 1487 1488 static u32 man_trk_ctl_enable_bit_get(struct drm_i915_private *dev_priv) 1489 { 1490 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ? 0 : 1491 PSR2_MAN_TRK_CTL_ENABLE; 1492 } 1493 1494 static u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private *dev_priv) 1495 { 1496 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ? 1497 ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME : 1498 PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 1499 } 1500 1501 static u32 man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev_priv) 1502 { 1503 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ? 1504 ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE : 1505 PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; 1506 } 1507 1508 static u32 man_trk_ctl_continuos_full_frame(struct drm_i915_private *dev_priv) 1509 { 1510 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ? 1511 ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME : 1512 PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME; 1513 } 1514 1515 static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) 1516 { 1517 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1518 1519 if (intel_dp->psr.psr2_sel_fetch_enabled) 1520 intel_de_write(dev_priv, 1521 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 1522 man_trk_ctl_enable_bit_get(dev_priv) | 1523 man_trk_ctl_partial_frame_bit_get(dev_priv) | 1524 man_trk_ctl_single_full_frame_bit_get(dev_priv) | 1525 man_trk_ctl_continuos_full_frame(dev_priv)); 1526 1527 /* 1528 * Display WA #0884: skl+ 1529 * This documented WA for bxt can be safely applied 1530 * broadly so we can force HW tracking to exit PSR 1531 * instead of disabling and re-enabling. 1532 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 1533 * but it makes more sense write to the current active 1534 * pipe. 1535 * 1536 * This workaround do not exist for platforms with display 10 or newer 1537 * but testing proved that it works for up display 13, for newer 1538 * than that testing will be needed. 1539 */ 1540 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 1541 } 1542 1543 void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane, 1544 const struct intel_crtc_state *crtc_state) 1545 { 1546 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1547 enum pipe pipe = plane->pipe; 1548 1549 if (!crtc_state->enable_psr2_sel_fetch) 1550 return; 1551 1552 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0); 1553 } 1554 1555 void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, 1556 const struct intel_crtc_state *crtc_state, 1557 const struct intel_plane_state *plane_state, 1558 int color_plane) 1559 { 1560 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1561 enum pipe pipe = plane->pipe; 1562 const struct drm_rect *clip; 1563 u32 val; 1564 int x, y; 1565 1566 if (!crtc_state->enable_psr2_sel_fetch) 1567 return; 1568 1569 if (plane->id == PLANE_CURSOR) { 1570 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 1571 plane_state->ctl); 1572 return; 1573 } 1574 1575 clip = &plane_state->psr2_sel_fetch_area; 1576 1577 val = (clip->y1 + plane_state->uapi.dst.y1) << 16; 1578 val |= plane_state->uapi.dst.x1; 1579 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); 1580 1581 x = plane_state->view.color_plane[color_plane].x; 1582 1583 /* 1584 * From Bspec: UV surface Start Y Position = half of Y plane Y 1585 * start position. 1586 */ 1587 if (!color_plane) 1588 y = plane_state->view.color_plane[color_plane].y + clip->y1; 1589 else 1590 y = plane_state->view.color_plane[color_plane].y + clip->y1 / 2; 1591 1592 val = y << 16 | x; 1593 1594 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), 1595 val); 1596 1597 /* Sizes are 0 based */ 1598 val = (drm_rect_height(clip) - 1) << 16; 1599 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; 1600 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); 1601 1602 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 1603 PLANE_SEL_FETCH_CTL_ENABLE); 1604 } 1605 1606 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) 1607 { 1608 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1609 struct intel_encoder *encoder; 1610 1611 if (!crtc_state->enable_psr2_sel_fetch) 1612 return; 1613 1614 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, 1615 crtc_state->uapi.encoder_mask) { 1616 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1617 1618 lockdep_assert_held(&intel_dp->psr.lock); 1619 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) 1620 return; 1621 break; 1622 } 1623 1624 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder), 1625 crtc_state->psr2_man_track_ctl); 1626 } 1627 1628 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, 1629 struct drm_rect *clip, bool full_update) 1630 { 1631 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1632 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1633 u32 val = man_trk_ctl_enable_bit_get(dev_priv); 1634 1635 /* SF partial frame enable has to be set even on full update */ 1636 val |= man_trk_ctl_partial_frame_bit_get(dev_priv); 1637 1638 if (full_update) { 1639 val |= man_trk_ctl_single_full_frame_bit_get(dev_priv); 1640 val |= man_trk_ctl_continuos_full_frame(dev_priv); 1641 goto exit; 1642 } 1643 1644 if (clip->y1 == -1) 1645 goto exit; 1646 1647 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) { 1648 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1); 1649 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 - 1); 1650 } else { 1651 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4); 1652 1653 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1); 1654 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1); 1655 } 1656 exit: 1657 crtc_state->psr2_man_track_ctl = val; 1658 } 1659 1660 static void clip_area_update(struct drm_rect *overlap_damage_area, 1661 struct drm_rect *damage_area, 1662 struct drm_rect *pipe_src) 1663 { 1664 if (!drm_rect_intersect(damage_area, pipe_src)) 1665 return; 1666 1667 if (overlap_damage_area->y1 == -1) { 1668 overlap_damage_area->y1 = damage_area->y1; 1669 overlap_damage_area->y2 = damage_area->y2; 1670 return; 1671 } 1672 1673 if (damage_area->y1 < overlap_damage_area->y1) 1674 overlap_damage_area->y1 = damage_area->y1; 1675 1676 if (damage_area->y2 > overlap_damage_area->y2) 1677 overlap_damage_area->y2 = damage_area->y2; 1678 } 1679 1680 static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state, 1681 struct drm_rect *pipe_clip) 1682 { 1683 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1684 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1685 u16 y_alignment; 1686 1687 /* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */ 1688 if (crtc_state->dsc.compression_enable && 1689 (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)) 1690 y_alignment = vdsc_cfg->slice_height; 1691 else 1692 y_alignment = crtc_state->su_y_granularity; 1693 1694 pipe_clip->y1 -= pipe_clip->y1 % y_alignment; 1695 if (pipe_clip->y2 % y_alignment) 1696 pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment; 1697 } 1698 1699 /* 1700 * TODO: Not clear how to handle planes with negative position, 1701 * also planes are not updated if they have a negative X 1702 * position so for now doing a full update in this cases 1703 * 1704 * Plane scaling and rotation is not supported by selective fetch and both 1705 * properties can change without a modeset, so need to be check at every 1706 * atomic commit. 1707 */ 1708 static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state) 1709 { 1710 if (plane_state->uapi.dst.y1 < 0 || 1711 plane_state->uapi.dst.x1 < 0 || 1712 plane_state->scaler_id >= 0 || 1713 plane_state->uapi.rotation != DRM_MODE_ROTATE_0) 1714 return false; 1715 1716 return true; 1717 } 1718 1719 /* 1720 * Check for pipe properties that is not supported by selective fetch. 1721 * 1722 * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed 1723 * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch 1724 * enabled and going to the full update path. 1725 */ 1726 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state) 1727 { 1728 if (crtc_state->scaler_state.scaler_id >= 0) 1729 return false; 1730 1731 return true; 1732 } 1733 1734 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 1735 struct intel_crtc *crtc) 1736 { 1737 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1738 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 1739 struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 }; 1740 struct intel_plane_state *new_plane_state, *old_plane_state; 1741 struct intel_plane *plane; 1742 bool full_update = false; 1743 int i, ret; 1744 1745 if (!crtc_state->enable_psr2_sel_fetch) 1746 return 0; 1747 1748 if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) { 1749 full_update = true; 1750 goto skip_sel_fetch_set_loop; 1751 } 1752 1753 /* 1754 * Calculate minimal selective fetch area of each plane and calculate 1755 * the pipe damaged area. 1756 * In the next loop the plane selective fetch area will actually be set 1757 * using whole pipe damaged area. 1758 */ 1759 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1760 new_plane_state, i) { 1761 struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1, 1762 .x2 = INT_MAX }; 1763 1764 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) 1765 continue; 1766 1767 if (!new_plane_state->uapi.visible && 1768 !old_plane_state->uapi.visible) 1769 continue; 1770 1771 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 1772 full_update = true; 1773 break; 1774 } 1775 1776 /* 1777 * If visibility or plane moved, mark the whole plane area as 1778 * damaged as it needs to be complete redraw in the new and old 1779 * position. 1780 */ 1781 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || 1782 !drm_rect_equals(&new_plane_state->uapi.dst, 1783 &old_plane_state->uapi.dst)) { 1784 if (old_plane_state->uapi.visible) { 1785 damaged_area.y1 = old_plane_state->uapi.dst.y1; 1786 damaged_area.y2 = old_plane_state->uapi.dst.y2; 1787 clip_area_update(&pipe_clip, &damaged_area, 1788 &crtc_state->pipe_src); 1789 } 1790 1791 if (new_plane_state->uapi.visible) { 1792 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1793 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1794 clip_area_update(&pipe_clip, &damaged_area, 1795 &crtc_state->pipe_src); 1796 } 1797 continue; 1798 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { 1799 /* If alpha changed mark the whole plane area as damaged */ 1800 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1801 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1802 clip_area_update(&pipe_clip, &damaged_area, 1803 &crtc_state->pipe_src); 1804 continue; 1805 } 1806 1807 src = drm_plane_state_src(&new_plane_state->uapi); 1808 drm_rect_fp_to_int(&src, &src); 1809 1810 if (!drm_atomic_helper_damage_merged(&old_plane_state->uapi, 1811 &new_plane_state->uapi, &damaged_area)) 1812 continue; 1813 1814 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; 1815 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; 1816 damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1; 1817 damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1; 1818 1819 clip_area_update(&pipe_clip, &damaged_area, &crtc_state->pipe_src); 1820 } 1821 1822 /* 1823 * TODO: For now we are just using full update in case 1824 * selective fetch area calculation fails. To optimize this we 1825 * should identify cases where this happens and fix the area 1826 * calculation for those. 1827 */ 1828 if (pipe_clip.y1 == -1) { 1829 drm_info_once(&dev_priv->drm, 1830 "Selective fetch area calculation failed in pipe %c\n", 1831 pipe_name(crtc->pipe)); 1832 full_update = true; 1833 } 1834 1835 if (full_update) 1836 goto skip_sel_fetch_set_loop; 1837 1838 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 1839 if (ret) 1840 return ret; 1841 1842 intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip); 1843 1844 /* 1845 * Now that we have the pipe damaged area check if it intersect with 1846 * every plane, if it does set the plane selective fetch area. 1847 */ 1848 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1849 new_plane_state, i) { 1850 struct drm_rect *sel_fetch_area, inter; 1851 struct intel_plane *linked = new_plane_state->planar_linked_plane; 1852 1853 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || 1854 !new_plane_state->uapi.visible) 1855 continue; 1856 1857 inter = pipe_clip; 1858 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) 1859 continue; 1860 1861 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 1862 full_update = true; 1863 break; 1864 } 1865 1866 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 1867 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; 1868 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; 1869 crtc_state->update_planes |= BIT(plane->id); 1870 1871 /* 1872 * Sel_fetch_area is calculated for UV plane. Use 1873 * same area for Y plane as well. 1874 */ 1875 if (linked) { 1876 struct intel_plane_state *linked_new_plane_state; 1877 struct drm_rect *linked_sel_fetch_area; 1878 1879 linked_new_plane_state = intel_atomic_get_plane_state(state, linked); 1880 if (IS_ERR(linked_new_plane_state)) 1881 return PTR_ERR(linked_new_plane_state); 1882 1883 linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area; 1884 linked_sel_fetch_area->y1 = sel_fetch_area->y1; 1885 linked_sel_fetch_area->y2 = sel_fetch_area->y2; 1886 crtc_state->update_planes |= BIT(linked->id); 1887 } 1888 } 1889 1890 skip_sel_fetch_set_loop: 1891 psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update); 1892 return 0; 1893 } 1894 1895 void intel_psr_pre_plane_update(struct intel_atomic_state *state, 1896 struct intel_crtc *crtc) 1897 { 1898 struct drm_i915_private *i915 = to_i915(state->base.dev); 1899 const struct intel_crtc_state *old_crtc_state = 1900 intel_atomic_get_old_crtc_state(state, crtc); 1901 const struct intel_crtc_state *new_crtc_state = 1902 intel_atomic_get_new_crtc_state(state, crtc); 1903 struct intel_encoder *encoder; 1904 1905 if (!HAS_PSR(i915)) 1906 return; 1907 1908 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 1909 old_crtc_state->uapi.encoder_mask) { 1910 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1911 struct intel_psr *psr = &intel_dp->psr; 1912 bool needs_to_disable = false; 1913 1914 mutex_lock(&psr->lock); 1915 1916 /* 1917 * Reasons to disable: 1918 * - PSR disabled in new state 1919 * - All planes will go inactive 1920 * - Changing between PSR versions 1921 */ 1922 needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state); 1923 needs_to_disable |= !new_crtc_state->has_psr; 1924 needs_to_disable |= !new_crtc_state->active_planes; 1925 needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled; 1926 1927 if (psr->enabled && needs_to_disable) 1928 intel_psr_disable_locked(intel_dp); 1929 1930 mutex_unlock(&psr->lock); 1931 } 1932 } 1933 1934 static void _intel_psr_post_plane_update(const struct intel_atomic_state *state, 1935 const struct intel_crtc_state *crtc_state) 1936 { 1937 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1938 struct intel_encoder *encoder; 1939 1940 if (!crtc_state->has_psr) 1941 return; 1942 1943 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 1944 crtc_state->uapi.encoder_mask) { 1945 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1946 struct intel_psr *psr = &intel_dp->psr; 1947 1948 mutex_lock(&psr->lock); 1949 1950 if (psr->sink_not_reliable) 1951 goto exit; 1952 1953 drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes); 1954 1955 /* Only enable if there is active planes */ 1956 if (!psr->enabled && crtc_state->active_planes) 1957 intel_psr_enable_locked(intel_dp, crtc_state); 1958 1959 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 1960 if (crtc_state->crc_enabled && psr->enabled) 1961 psr_force_hw_tracking_exit(intel_dp); 1962 1963 exit: 1964 mutex_unlock(&psr->lock); 1965 } 1966 } 1967 1968 void intel_psr_post_plane_update(const struct intel_atomic_state *state) 1969 { 1970 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1971 struct intel_crtc_state *crtc_state; 1972 struct intel_crtc *crtc; 1973 int i; 1974 1975 if (!HAS_PSR(dev_priv)) 1976 return; 1977 1978 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) 1979 _intel_psr_post_plane_update(state, crtc_state); 1980 } 1981 1982 static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp) 1983 { 1984 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1985 1986 /* 1987 * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough. 1988 * As all higher states has bit 4 of PSR2 state set we can just wait for 1989 * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared. 1990 */ 1991 return intel_de_wait_for_clear(dev_priv, 1992 EDP_PSR2_STATUS(intel_dp->psr.transcoder), 1993 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50); 1994 } 1995 1996 static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp) 1997 { 1998 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1999 2000 /* 2001 * From bspec: Panel Self Refresh (BDW+) 2002 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 2003 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 2004 * defensive enough to cover everything. 2005 */ 2006 return intel_de_wait_for_clear(dev_priv, 2007 EDP_PSR_STATUS(intel_dp->psr.transcoder), 2008 EDP_PSR_STATUS_STATE_MASK, 50); 2009 } 2010 2011 /** 2012 * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update 2013 * @new_crtc_state: new CRTC state 2014 * 2015 * This function is expected to be called from pipe_update_start() where it is 2016 * not expected to race with PSR enable or disable. 2017 */ 2018 void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state) 2019 { 2020 struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev); 2021 struct intel_encoder *encoder; 2022 2023 if (!new_crtc_state->has_psr) 2024 return; 2025 2026 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, 2027 new_crtc_state->uapi.encoder_mask) { 2028 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2029 int ret; 2030 2031 lockdep_assert_held(&intel_dp->psr.lock); 2032 2033 if (!intel_dp->psr.enabled) 2034 continue; 2035 2036 if (intel_dp->psr.psr2_enabled) 2037 ret = _psr2_ready_for_pipe_update_locked(intel_dp); 2038 else 2039 ret = _psr1_ready_for_pipe_update_locked(intel_dp); 2040 2041 if (ret) 2042 drm_err(&dev_priv->drm, "PSR wait timed out, atomic update may fail\n"); 2043 } 2044 } 2045 2046 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) 2047 { 2048 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2049 i915_reg_t reg; 2050 u32 mask; 2051 int err; 2052 2053 if (!intel_dp->psr.enabled) 2054 return false; 2055 2056 if (intel_dp->psr.psr2_enabled) { 2057 reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 2058 mask = EDP_PSR2_STATUS_STATE_MASK; 2059 } else { 2060 reg = EDP_PSR_STATUS(intel_dp->psr.transcoder); 2061 mask = EDP_PSR_STATUS_STATE_MASK; 2062 } 2063 2064 mutex_unlock(&intel_dp->psr.lock); 2065 2066 err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); 2067 if (err) 2068 drm_err(&dev_priv->drm, 2069 "Timed out waiting for PSR Idle for re-enable\n"); 2070 2071 /* After the unlocked wait, verify that PSR is still wanted! */ 2072 mutex_lock(&intel_dp->psr.lock); 2073 return err == 0 && intel_dp->psr.enabled; 2074 } 2075 2076 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) 2077 { 2078 struct drm_connector_list_iter conn_iter; 2079 struct drm_modeset_acquire_ctx ctx; 2080 struct drm_atomic_state *state; 2081 struct drm_connector *conn; 2082 int err = 0; 2083 2084 state = drm_atomic_state_alloc(&dev_priv->drm); 2085 if (!state) 2086 return -ENOMEM; 2087 2088 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 2089 state->acquire_ctx = &ctx; 2090 2091 retry: 2092 2093 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 2094 drm_for_each_connector_iter(conn, &conn_iter) { 2095 struct drm_connector_state *conn_state; 2096 struct drm_crtc_state *crtc_state; 2097 2098 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) 2099 continue; 2100 2101 conn_state = drm_atomic_get_connector_state(state, conn); 2102 if (IS_ERR(conn_state)) { 2103 err = PTR_ERR(conn_state); 2104 break; 2105 } 2106 2107 if (!conn_state->crtc) 2108 continue; 2109 2110 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); 2111 if (IS_ERR(crtc_state)) { 2112 err = PTR_ERR(crtc_state); 2113 break; 2114 } 2115 2116 /* Mark mode as changed to trigger a pipe->update() */ 2117 crtc_state->mode_changed = true; 2118 } 2119 drm_connector_list_iter_end(&conn_iter); 2120 2121 if (err == 0) 2122 err = drm_atomic_commit(state); 2123 2124 if (err == -EDEADLK) { 2125 drm_atomic_state_clear(state); 2126 err = drm_modeset_backoff(&ctx); 2127 if (!err) 2128 goto retry; 2129 } 2130 2131 drm_modeset_drop_locks(&ctx); 2132 drm_modeset_acquire_fini(&ctx); 2133 drm_atomic_state_put(state); 2134 2135 return err; 2136 } 2137 2138 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) 2139 { 2140 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2141 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 2142 u32 old_mode; 2143 int ret; 2144 2145 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || 2146 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 2147 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); 2148 return -EINVAL; 2149 } 2150 2151 ret = mutex_lock_interruptible(&intel_dp->psr.lock); 2152 if (ret) 2153 return ret; 2154 2155 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; 2156 intel_dp->psr.debug = val; 2157 2158 /* 2159 * Do it right away if it's already enabled, otherwise it will be done 2160 * when enabling the source. 2161 */ 2162 if (intel_dp->psr.enabled) 2163 psr_irq_control(intel_dp); 2164 2165 mutex_unlock(&intel_dp->psr.lock); 2166 2167 if (old_mode != mode) 2168 ret = intel_psr_fastset_force(dev_priv); 2169 2170 return ret; 2171 } 2172 2173 static void intel_psr_handle_irq(struct intel_dp *intel_dp) 2174 { 2175 struct intel_psr *psr = &intel_dp->psr; 2176 2177 intel_psr_disable_locked(intel_dp); 2178 psr->sink_not_reliable = true; 2179 /* let's make sure that sink is awaken */ 2180 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 2181 } 2182 2183 static void intel_psr_work(struct work_struct *work) 2184 { 2185 struct intel_dp *intel_dp = 2186 container_of(work, typeof(*intel_dp), psr.work); 2187 2188 mutex_lock(&intel_dp->psr.lock); 2189 2190 if (!intel_dp->psr.enabled) 2191 goto unlock; 2192 2193 if (READ_ONCE(intel_dp->psr.irq_aux_error)) 2194 intel_psr_handle_irq(intel_dp); 2195 2196 /* 2197 * We have to make sure PSR is ready for re-enable 2198 * otherwise it keeps disabled until next full enable/disable cycle. 2199 * PSR might take some time to get fully disabled 2200 * and be ready for re-enable. 2201 */ 2202 if (!__psr_wait_for_idle_locked(intel_dp)) 2203 goto unlock; 2204 2205 /* 2206 * The delayed work can race with an invalidate hence we need to 2207 * recheck. Since psr_flush first clears this and then reschedules we 2208 * won't ever miss a flush when bailing out here. 2209 */ 2210 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) 2211 goto unlock; 2212 2213 intel_psr_activate(intel_dp); 2214 unlock: 2215 mutex_unlock(&intel_dp->psr.lock); 2216 } 2217 2218 static void _psr_invalidate_handle(struct intel_dp *intel_dp) 2219 { 2220 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2221 2222 if (intel_dp->psr.psr2_sel_fetch_enabled) { 2223 u32 val; 2224 2225 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { 2226 /* Send one update otherwise lag is observed in screen */ 2227 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 2228 return; 2229 } 2230 2231 val = man_trk_ctl_enable_bit_get(dev_priv) | 2232 man_trk_ctl_partial_frame_bit_get(dev_priv) | 2233 man_trk_ctl_continuos_full_frame(dev_priv); 2234 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), val); 2235 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 2236 intel_dp->psr.psr2_sel_fetch_cff_enabled = true; 2237 } else { 2238 intel_psr_exit(intel_dp); 2239 } 2240 } 2241 2242 /** 2243 * intel_psr_invalidate - Invalidate PSR 2244 * @dev_priv: i915 device 2245 * @frontbuffer_bits: frontbuffer plane tracking bits 2246 * @origin: which operation caused the invalidate 2247 * 2248 * Since the hardware frontbuffer tracking has gaps we need to integrate 2249 * with the software frontbuffer tracking. This function gets called every 2250 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 2251 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 2252 * 2253 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 2254 */ 2255 void intel_psr_invalidate(struct drm_i915_private *dev_priv, 2256 unsigned frontbuffer_bits, enum fb_op_origin origin) 2257 { 2258 struct intel_encoder *encoder; 2259 2260 if (origin == ORIGIN_FLIP) 2261 return; 2262 2263 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2264 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 2265 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2266 2267 mutex_lock(&intel_dp->psr.lock); 2268 if (!intel_dp->psr.enabled) { 2269 mutex_unlock(&intel_dp->psr.lock); 2270 continue; 2271 } 2272 2273 pipe_frontbuffer_bits &= 2274 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 2275 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; 2276 2277 if (pipe_frontbuffer_bits) 2278 _psr_invalidate_handle(intel_dp); 2279 2280 mutex_unlock(&intel_dp->psr.lock); 2281 } 2282 } 2283 /* 2284 * When we will be completely rely on PSR2 S/W tracking in future, 2285 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP 2286 * event also therefore tgl_dc3co_flush_locked() require to be changed 2287 * accordingly in future. 2288 */ 2289 static void 2290 tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits, 2291 enum fb_op_origin origin) 2292 { 2293 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled || 2294 !intel_dp->psr.active) 2295 return; 2296 2297 /* 2298 * At every frontbuffer flush flip event modified delay of delayed work, 2299 * when delayed work schedules that means display has been idle. 2300 */ 2301 if (!(frontbuffer_bits & 2302 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) 2303 return; 2304 2305 tgl_psr2_enable_dc3co(intel_dp); 2306 mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work, 2307 intel_dp->psr.dc3co_exit_delay); 2308 } 2309 2310 static void _psr_flush_handle(struct intel_dp *intel_dp) 2311 { 2312 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2313 2314 if (intel_dp->psr.psr2_sel_fetch_enabled) { 2315 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { 2316 /* can we turn CFF off? */ 2317 if (intel_dp->psr.busy_frontbuffer_bits == 0) { 2318 u32 val = man_trk_ctl_enable_bit_get(dev_priv) | 2319 man_trk_ctl_partial_frame_bit_get(dev_priv) | 2320 man_trk_ctl_single_full_frame_bit_get(dev_priv) | 2321 man_trk_ctl_continuos_full_frame(dev_priv); 2322 2323 /* 2324 * Set psr2_sel_fetch_cff_enabled as false to allow selective 2325 * updates. Still keep cff bit enabled as we don't have proper 2326 * SU configuration in case update is sent for any reason after 2327 * sff bit gets cleared by the HW on next vblank. 2328 */ 2329 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 2330 val); 2331 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 2332 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 2333 } 2334 } else { 2335 /* 2336 * continuous full frame is disabled, only a single full 2337 * frame is required 2338 */ 2339 psr_force_hw_tracking_exit(intel_dp); 2340 } 2341 } else { 2342 psr_force_hw_tracking_exit(intel_dp); 2343 2344 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) 2345 schedule_work(&intel_dp->psr.work); 2346 } 2347 } 2348 2349 /** 2350 * intel_psr_flush - Flush PSR 2351 * @dev_priv: i915 device 2352 * @frontbuffer_bits: frontbuffer plane tracking bits 2353 * @origin: which operation caused the flush 2354 * 2355 * Since the hardware frontbuffer tracking has gaps we need to integrate 2356 * with the software frontbuffer tracking. This function gets called every 2357 * time frontbuffer rendering has completed and flushed out to memory. PSR 2358 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 2359 * 2360 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 2361 */ 2362 void intel_psr_flush(struct drm_i915_private *dev_priv, 2363 unsigned frontbuffer_bits, enum fb_op_origin origin) 2364 { 2365 struct intel_encoder *encoder; 2366 2367 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2368 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 2369 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2370 2371 mutex_lock(&intel_dp->psr.lock); 2372 if (!intel_dp->psr.enabled) { 2373 mutex_unlock(&intel_dp->psr.lock); 2374 continue; 2375 } 2376 2377 pipe_frontbuffer_bits &= 2378 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 2379 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; 2380 2381 /* 2382 * If the PSR is paused by an explicit intel_psr_paused() call, 2383 * we have to ensure that the PSR is not activated until 2384 * intel_psr_resume() is called. 2385 */ 2386 if (intel_dp->psr.paused) 2387 goto unlock; 2388 2389 if (origin == ORIGIN_FLIP || 2390 (origin == ORIGIN_CURSOR_UPDATE && 2391 !intel_dp->psr.psr2_sel_fetch_enabled)) { 2392 tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin); 2393 goto unlock; 2394 } 2395 2396 if (pipe_frontbuffer_bits == 0) 2397 goto unlock; 2398 2399 /* By definition flush = invalidate + flush */ 2400 _psr_flush_handle(intel_dp); 2401 unlock: 2402 mutex_unlock(&intel_dp->psr.lock); 2403 } 2404 } 2405 2406 /** 2407 * intel_psr_init - Init basic PSR work and mutex. 2408 * @intel_dp: Intel DP 2409 * 2410 * This function is called after the initializing connector. 2411 * (the initializing of connector treats the handling of connector capabilities) 2412 * And it initializes basic PSR stuff for each DP Encoder. 2413 */ 2414 void intel_psr_init(struct intel_dp *intel_dp) 2415 { 2416 struct intel_connector *connector = intel_dp->attached_connector; 2417 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2418 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2419 2420 if (!HAS_PSR(dev_priv)) 2421 return; 2422 2423 /* 2424 * HSW spec explicitly says PSR is tied to port A. 2425 * BDW+ platforms have a instance of PSR registers per transcoder but 2426 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder 2427 * than eDP one. 2428 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11. 2429 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11. 2430 * But GEN12 supports a instance of PSR registers per transcoder. 2431 */ 2432 if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) { 2433 drm_dbg_kms(&dev_priv->drm, 2434 "PSR condition failed: Port not supported\n"); 2435 return; 2436 } 2437 2438 intel_dp->psr.source_support = true; 2439 2440 /* Set link_standby x link_off defaults */ 2441 if (DISPLAY_VER(dev_priv) < 12) 2442 /* For new platforms up to TGL let's respect VBT back again */ 2443 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link; 2444 2445 INIT_WORK(&intel_dp->psr.work, intel_psr_work); 2446 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); 2447 mutex_init(&intel_dp->psr.lock); 2448 } 2449 2450 static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 2451 u8 *status, u8 *error_status) 2452 { 2453 struct drm_dp_aux *aux = &intel_dp->aux; 2454 int ret; 2455 2456 ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status); 2457 if (ret != 1) 2458 return ret; 2459 2460 ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status); 2461 if (ret != 1) 2462 return ret; 2463 2464 *status = *status & DP_PSR_SINK_STATE_MASK; 2465 2466 return 0; 2467 } 2468 2469 static void psr_alpm_check(struct intel_dp *intel_dp) 2470 { 2471 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2472 struct drm_dp_aux *aux = &intel_dp->aux; 2473 struct intel_psr *psr = &intel_dp->psr; 2474 u8 val; 2475 int r; 2476 2477 if (!psr->psr2_enabled) 2478 return; 2479 2480 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); 2481 if (r != 1) { 2482 drm_err(&dev_priv->drm, "Error reading ALPM status\n"); 2483 return; 2484 } 2485 2486 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) { 2487 intel_psr_disable_locked(intel_dp); 2488 psr->sink_not_reliable = true; 2489 drm_dbg_kms(&dev_priv->drm, 2490 "ALPM lock timeout error, disabling PSR\n"); 2491 2492 /* Clearing error */ 2493 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); 2494 } 2495 } 2496 2497 static void psr_capability_changed_check(struct intel_dp *intel_dp) 2498 { 2499 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2500 struct intel_psr *psr = &intel_dp->psr; 2501 u8 val; 2502 int r; 2503 2504 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 2505 if (r != 1) { 2506 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n"); 2507 return; 2508 } 2509 2510 if (val & DP_PSR_CAPS_CHANGE) { 2511 intel_psr_disable_locked(intel_dp); 2512 psr->sink_not_reliable = true; 2513 drm_dbg_kms(&dev_priv->drm, 2514 "Sink PSR capability changed, disabling PSR\n"); 2515 2516 /* Clearing it */ 2517 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 2518 } 2519 } 2520 2521 void intel_psr_short_pulse(struct intel_dp *intel_dp) 2522 { 2523 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2524 struct intel_psr *psr = &intel_dp->psr; 2525 u8 status, error_status; 2526 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 2527 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 2528 DP_PSR_LINK_CRC_ERROR; 2529 2530 if (!CAN_PSR(intel_dp)) 2531 return; 2532 2533 mutex_lock(&psr->lock); 2534 2535 if (!psr->enabled) 2536 goto exit; 2537 2538 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 2539 drm_err(&dev_priv->drm, 2540 "Error reading PSR status or error status\n"); 2541 goto exit; 2542 } 2543 2544 if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) { 2545 intel_psr_disable_locked(intel_dp); 2546 psr->sink_not_reliable = true; 2547 } 2548 2549 if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status) 2550 drm_dbg_kms(&dev_priv->drm, 2551 "PSR sink internal error, disabling PSR\n"); 2552 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 2553 drm_dbg_kms(&dev_priv->drm, 2554 "PSR RFB storage error, disabling PSR\n"); 2555 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 2556 drm_dbg_kms(&dev_priv->drm, 2557 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 2558 if (error_status & DP_PSR_LINK_CRC_ERROR) 2559 drm_dbg_kms(&dev_priv->drm, 2560 "PSR Link CRC error, disabling PSR\n"); 2561 2562 if (error_status & ~errors) 2563 drm_err(&dev_priv->drm, 2564 "PSR_ERROR_STATUS unhandled errors %x\n", 2565 error_status & ~errors); 2566 /* clear status register */ 2567 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 2568 2569 psr_alpm_check(intel_dp); 2570 psr_capability_changed_check(intel_dp); 2571 2572 exit: 2573 mutex_unlock(&psr->lock); 2574 } 2575 2576 bool intel_psr_enabled(struct intel_dp *intel_dp) 2577 { 2578 bool ret; 2579 2580 if (!CAN_PSR(intel_dp)) 2581 return false; 2582 2583 mutex_lock(&intel_dp->psr.lock); 2584 ret = intel_dp->psr.enabled; 2585 mutex_unlock(&intel_dp->psr.lock); 2586 2587 return ret; 2588 } 2589 2590 /** 2591 * intel_psr_lock - grab PSR lock 2592 * @crtc_state: the crtc state 2593 * 2594 * This is initially meant to be used by around CRTC update, when 2595 * vblank sensitive registers are updated and we need grab the lock 2596 * before it to avoid vblank evasion. 2597 */ 2598 void intel_psr_lock(const struct intel_crtc_state *crtc_state) 2599 { 2600 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2601 struct intel_encoder *encoder; 2602 2603 if (!crtc_state->has_psr) 2604 return; 2605 2606 for_each_intel_encoder_mask_with_psr(&i915->drm, encoder, 2607 crtc_state->uapi.encoder_mask) { 2608 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2609 2610 mutex_lock(&intel_dp->psr.lock); 2611 break; 2612 } 2613 } 2614 2615 /** 2616 * intel_psr_unlock - release PSR lock 2617 * @crtc_state: the crtc state 2618 * 2619 * Release the PSR lock that was held during pipe update. 2620 */ 2621 void intel_psr_unlock(const struct intel_crtc_state *crtc_state) 2622 { 2623 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2624 struct intel_encoder *encoder; 2625 2626 if (!crtc_state->has_psr) 2627 return; 2628 2629 for_each_intel_encoder_mask_with_psr(&i915->drm, encoder, 2630 crtc_state->uapi.encoder_mask) { 2631 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2632 2633 mutex_unlock(&intel_dp->psr.lock); 2634 break; 2635 } 2636 } 2637