1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_damage_helper.h> 26 27 #include "display/intel_dp.h" 28 29 #include "i915_drv.h" 30 #include "intel_atomic.h" 31 #include "intel_de.h" 32 #include "intel_display_types.h" 33 #include "intel_dp_aux.h" 34 #include "intel_hdmi.h" 35 #include "intel_psr.h" 36 #include "intel_snps_phy.h" 37 #include "intel_sprite.h" 38 #include "skl_universal_plane.h" 39 40 /** 41 * DOC: Panel Self Refresh (PSR/SRD) 42 * 43 * Since Haswell Display controller supports Panel Self-Refresh on display 44 * panels witch have a remote frame buffer (RFB) implemented according to PSR 45 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 46 * when system is idle but display is on as it eliminates display refresh 47 * request to DDR memory completely as long as the frame buffer for that 48 * display is unchanged. 49 * 50 * Panel Self Refresh must be supported by both Hardware (source) and 51 * Panel (sink). 52 * 53 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 54 * to power down the link and memory controller. For DSI panels the same idea 55 * is called "manual mode". 56 * 57 * The implementation uses the hardware-based PSR support which automatically 58 * enters/exits self-refresh mode. The hardware takes care of sending the 59 * required DP aux message and could even retrain the link (that part isn't 60 * enabled yet though). The hardware also keeps track of any frontbuffer 61 * changes to know when to exit self-refresh mode again. Unfortunately that 62 * part doesn't work too well, hence why the i915 PSR support uses the 63 * software frontbuffer tracking to make sure it doesn't miss a screen 64 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 65 * get called by the frontbuffer tracking code. Note that because of locking 66 * issues the self-refresh re-enable code is done from a work queue, which 67 * must be correctly synchronized/cancelled when shutting down the pipe." 68 * 69 * DC3CO (DC3 clock off) 70 * 71 * On top of PSR2, GEN12 adds a intermediate power savings state that turns 72 * clock off automatically during PSR2 idle state. 73 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep 74 * entry/exit allows the HW to enter a low-power state even when page flipping 75 * periodically (for instance a 30fps video playback scenario). 76 * 77 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), 78 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 79 * frames, if no other flip occurs and the function above is executed, DC3CO is 80 * disabled and PSR2 is configured to enter deep sleep, resetting again in case 81 * of another flip. 82 * Front buffer modifications do not trigger DC3CO activation on purpose as it 83 * would bring a lot of complexity and most of the moderns systems will only 84 * use page flips. 85 */ 86 87 static bool psr_global_enabled(struct intel_dp *intel_dp) 88 { 89 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 90 91 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 92 case I915_PSR_DEBUG_DEFAULT: 93 return i915->params.enable_psr; 94 case I915_PSR_DEBUG_DISABLE: 95 return false; 96 default: 97 return true; 98 } 99 } 100 101 static bool psr2_global_enabled(struct intel_dp *intel_dp) 102 { 103 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 104 case I915_PSR_DEBUG_DISABLE: 105 case I915_PSR_DEBUG_FORCE_PSR1: 106 return false; 107 default: 108 return true; 109 } 110 } 111 112 static void psr_irq_control(struct intel_dp *intel_dp) 113 { 114 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 115 enum transcoder trans_shift; 116 i915_reg_t imr_reg; 117 u32 mask, val; 118 119 /* 120 * gen12+ has registers relative to transcoder and one per transcoder 121 * using the same bit definition: handle it as TRANSCODER_EDP to force 122 * 0 shift in bit definition 123 */ 124 if (DISPLAY_VER(dev_priv) >= 12) { 125 trans_shift = 0; 126 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 127 } else { 128 trans_shift = intel_dp->psr.transcoder; 129 imr_reg = EDP_PSR_IMR; 130 } 131 132 mask = EDP_PSR_ERROR(trans_shift); 133 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) 134 mask |= EDP_PSR_POST_EXIT(trans_shift) | 135 EDP_PSR_PRE_ENTRY(trans_shift); 136 137 /* Warning: it is masking/setting reserved bits too */ 138 val = intel_de_read(dev_priv, imr_reg); 139 val &= ~EDP_PSR_TRANS_MASK(trans_shift); 140 val |= ~mask; 141 intel_de_write(dev_priv, imr_reg, val); 142 } 143 144 static void psr_event_print(struct drm_i915_private *i915, 145 u32 val, bool psr2_enabled) 146 { 147 drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val); 148 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 149 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n"); 150 if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) 151 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n"); 152 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 153 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n"); 154 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 155 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n"); 156 if (val & PSR_EVENT_GRAPHICS_RESET) 157 drm_dbg_kms(&i915->drm, "\tGraphics reset\n"); 158 if (val & PSR_EVENT_PCH_INTERRUPT) 159 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n"); 160 if (val & PSR_EVENT_MEMORY_UP) 161 drm_dbg_kms(&i915->drm, "\tMemory up\n"); 162 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 163 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n"); 164 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 165 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n"); 166 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 167 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n"); 168 if (val & PSR_EVENT_REGISTER_UPDATE) 169 drm_dbg_kms(&i915->drm, "\tRegister updated\n"); 170 if (val & PSR_EVENT_HDCP_ENABLE) 171 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n"); 172 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 173 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n"); 174 if (val & PSR_EVENT_VBI_ENABLE) 175 drm_dbg_kms(&i915->drm, "\tVBI enabled\n"); 176 if (val & PSR_EVENT_LPSP_MODE_EXIT) 177 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n"); 178 if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) 179 drm_dbg_kms(&i915->drm, "\tPSR disabled\n"); 180 } 181 182 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) 183 { 184 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 185 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 186 ktime_t time_ns = ktime_get(); 187 enum transcoder trans_shift; 188 i915_reg_t imr_reg; 189 190 if (DISPLAY_VER(dev_priv) >= 12) { 191 trans_shift = 0; 192 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 193 } else { 194 trans_shift = intel_dp->psr.transcoder; 195 imr_reg = EDP_PSR_IMR; 196 } 197 198 if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) { 199 intel_dp->psr.last_entry_attempt = time_ns; 200 drm_dbg_kms(&dev_priv->drm, 201 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 202 transcoder_name(cpu_transcoder)); 203 } 204 205 if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) { 206 intel_dp->psr.last_exit = time_ns; 207 drm_dbg_kms(&dev_priv->drm, 208 "[transcoder %s] PSR exit completed\n", 209 transcoder_name(cpu_transcoder)); 210 211 if (DISPLAY_VER(dev_priv) >= 9) { 212 u32 val = intel_de_read(dev_priv, 213 PSR_EVENT(cpu_transcoder)); 214 bool psr2_enabled = intel_dp->psr.psr2_enabled; 215 216 intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder), 217 val); 218 psr_event_print(dev_priv, val, psr2_enabled); 219 } 220 } 221 222 if (psr_iir & EDP_PSR_ERROR(trans_shift)) { 223 u32 val; 224 225 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", 226 transcoder_name(cpu_transcoder)); 227 228 intel_dp->psr.irq_aux_error = true; 229 230 /* 231 * If this interruption is not masked it will keep 232 * interrupting so fast that it prevents the scheduled 233 * work to run. 234 * Also after a PSR error, we don't want to arm PSR 235 * again so we don't care about unmask the interruption 236 * or unset irq_aux_error. 237 */ 238 val = intel_de_read(dev_priv, imr_reg); 239 val |= EDP_PSR_ERROR(trans_shift); 240 intel_de_write(dev_priv, imr_reg, val); 241 242 schedule_work(&intel_dp->psr.work); 243 } 244 } 245 246 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) 247 { 248 u8 alpm_caps = 0; 249 250 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, 251 &alpm_caps) != 1) 252 return false; 253 return alpm_caps & DP_ALPM_CAP; 254 } 255 256 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 257 { 258 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 259 u8 val = 8; /* assume the worst if we can't read the value */ 260 261 if (drm_dp_dpcd_readb(&intel_dp->aux, 262 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 263 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 264 else 265 drm_dbg_kms(&i915->drm, 266 "Unable to get sink synchronization latency, assuming 8 frames\n"); 267 return val; 268 } 269 270 static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) 271 { 272 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 273 ssize_t r; 274 u16 w; 275 u8 y; 276 277 /* If sink don't have specific granularity requirements set legacy ones */ 278 if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { 279 /* As PSR2 HW sends full lines, we do not care about x granularity */ 280 w = 4; 281 y = 4; 282 goto exit; 283 } 284 285 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2); 286 if (r != 2) 287 drm_dbg_kms(&i915->drm, 288 "Unable to read DP_PSR2_SU_X_GRANULARITY\n"); 289 /* 290 * Spec says that if the value read is 0 the default granularity should 291 * be used instead. 292 */ 293 if (r != 2 || w == 0) 294 w = 4; 295 296 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); 297 if (r != 1) { 298 drm_dbg_kms(&i915->drm, 299 "Unable to read DP_PSR2_SU_Y_GRANULARITY\n"); 300 y = 4; 301 } 302 if (y == 0) 303 y = 1; 304 305 exit: 306 intel_dp->psr.su_w_granularity = w; 307 intel_dp->psr.su_y_granularity = y; 308 } 309 310 void intel_psr_init_dpcd(struct intel_dp *intel_dp) 311 { 312 struct drm_i915_private *dev_priv = 313 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 314 315 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, 316 sizeof(intel_dp->psr_dpcd)); 317 318 if (!intel_dp->psr_dpcd[0]) 319 return; 320 drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n", 321 intel_dp->psr_dpcd[0]); 322 323 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { 324 drm_dbg_kms(&dev_priv->drm, 325 "PSR support not currently available for this panel\n"); 326 return; 327 } 328 329 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 330 drm_dbg_kms(&dev_priv->drm, 331 "Panel lacks power state control, PSR cannot be enabled\n"); 332 return; 333 } 334 335 intel_dp->psr.sink_support = true; 336 intel_dp->psr.sink_sync_latency = 337 intel_dp_get_sink_sync_latency(intel_dp); 338 339 if (DISPLAY_VER(dev_priv) >= 9 && 340 (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { 341 bool y_req = intel_dp->psr_dpcd[1] & 342 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 343 bool alpm = intel_dp_get_alpm_status(intel_dp); 344 345 /* 346 * All panels that supports PSR version 03h (PSR2 + 347 * Y-coordinate) can handle Y-coordinates in VSC but we are 348 * only sure that it is going to be used when required by the 349 * panel. This way panel is capable to do selective update 350 * without a aux frame sync. 351 * 352 * To support PSR version 02h and PSR version 03h without 353 * Y-coordinate requirement panels we would need to enable 354 * GTC first. 355 */ 356 intel_dp->psr.sink_psr2_support = y_req && alpm; 357 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n", 358 intel_dp->psr.sink_psr2_support ? "" : "not "); 359 360 if (intel_dp->psr.sink_psr2_support) { 361 intel_dp->psr.colorimetry_support = 362 intel_dp_get_colorimetry_status(intel_dp); 363 intel_dp_get_su_granularity(intel_dp); 364 } 365 } 366 } 367 368 static void intel_psr_enable_sink(struct intel_dp *intel_dp) 369 { 370 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 371 u8 dpcd_val = DP_PSR_ENABLE; 372 373 /* Enable ALPM at sink for psr2 */ 374 if (intel_dp->psr.psr2_enabled) { 375 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 376 DP_ALPM_ENABLE | 377 DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); 378 379 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 380 } else { 381 if (intel_dp->psr.link_standby) 382 dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; 383 384 if (DISPLAY_VER(dev_priv) >= 8) 385 dpcd_val |= DP_PSR_CRC_VERIFICATION; 386 } 387 388 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 389 dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; 390 391 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); 392 393 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 394 } 395 396 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 397 { 398 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 399 u32 val = 0; 400 401 if (DISPLAY_VER(dev_priv) >= 11) 402 val |= EDP_PSR_TP4_TIME_0US; 403 404 if (dev_priv->params.psr_safest_params) { 405 val |= EDP_PSR_TP1_TIME_2500us; 406 val |= EDP_PSR_TP2_TP3_TIME_2500us; 407 goto check_tp3_sel; 408 } 409 410 if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) 411 val |= EDP_PSR_TP1_TIME_0us; 412 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100) 413 val |= EDP_PSR_TP1_TIME_100us; 414 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500) 415 val |= EDP_PSR_TP1_TIME_500us; 416 else 417 val |= EDP_PSR_TP1_TIME_2500us; 418 419 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0) 420 val |= EDP_PSR_TP2_TP3_TIME_0us; 421 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) 422 val |= EDP_PSR_TP2_TP3_TIME_100us; 423 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) 424 val |= EDP_PSR_TP2_TP3_TIME_500us; 425 else 426 val |= EDP_PSR_TP2_TP3_TIME_2500us; 427 428 check_tp3_sel: 429 if (intel_dp_source_supports_tps3(dev_priv) && 430 drm_dp_tps3_supported(intel_dp->dpcd)) 431 val |= EDP_PSR_TP1_TP3_SEL; 432 else 433 val |= EDP_PSR_TP1_TP2_SEL; 434 435 return val; 436 } 437 438 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 439 { 440 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 441 int idle_frames; 442 443 /* Let's use 6 as the minimum to cover all known cases including the 444 * off-by-one issue that HW has in some cases. 445 */ 446 idle_frames = max(6, dev_priv->vbt.psr.idle_frames); 447 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1); 448 449 if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf)) 450 idle_frames = 0xf; 451 452 return idle_frames; 453 } 454 455 static void hsw_activate_psr1(struct intel_dp *intel_dp) 456 { 457 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 458 u32 max_sleep_time = 0x1f; 459 u32 val = EDP_PSR_ENABLE; 460 461 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT; 462 463 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; 464 if (IS_HASWELL(dev_priv)) 465 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 466 467 if (intel_dp->psr.link_standby) 468 val |= EDP_PSR_LINK_STANDBY; 469 470 val |= intel_psr1_get_tp_time(intel_dp); 471 472 if (DISPLAY_VER(dev_priv) >= 8) 473 val |= EDP_PSR_CRC_ENABLE; 474 475 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) & 476 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK); 477 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val); 478 } 479 480 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 481 { 482 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 483 u32 val = 0; 484 485 if (dev_priv->params.psr_safest_params) 486 return EDP_PSR2_TP2_TIME_2500us; 487 488 if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 489 dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 490 val |= EDP_PSR2_TP2_TIME_50us; 491 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 492 val |= EDP_PSR2_TP2_TIME_100us; 493 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 494 val |= EDP_PSR2_TP2_TIME_500us; 495 else 496 val |= EDP_PSR2_TP2_TIME_2500us; 497 498 return val; 499 } 500 501 static void hsw_activate_psr2(struct intel_dp *intel_dp) 502 { 503 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 504 u32 val = EDP_PSR2_ENABLE; 505 506 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT; 507 508 if (!IS_ALDERLAKE_P(dev_priv)) 509 val |= EDP_SU_TRACK_ENABLE; 510 511 if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12) 512 val |= EDP_Y_COORDINATE_ENABLE; 513 514 val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2)); 515 val |= intel_psr2_get_tp_time(intel_dp); 516 517 /* Wa_22012278275:adl-p */ 518 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { 519 static const u8 map[] = { 520 2, /* 5 lines */ 521 1, /* 6 lines */ 522 0, /* 7 lines */ 523 3, /* 8 lines */ 524 6, /* 9 lines */ 525 5, /* 10 lines */ 526 4, /* 11 lines */ 527 7, /* 12 lines */ 528 }; 529 /* 530 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see 531 * comments bellow for more information 532 */ 533 u32 tmp, lines = 7; 534 535 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 536 537 tmp = map[lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; 538 tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT; 539 val |= tmp; 540 541 tmp = map[lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; 542 tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT; 543 val |= tmp; 544 } else if (DISPLAY_VER(dev_priv) >= 12) { 545 /* 546 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default 547 * values from BSpec. In order to setting an optimal power 548 * consumption, lower than 4k resoluition mode needs to decrese 549 * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution 550 * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE. 551 */ 552 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 553 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7); 554 val |= TGL_EDP_PSR2_FAST_WAKE(7); 555 } else if (DISPLAY_VER(dev_priv) >= 9) { 556 val |= EDP_PSR2_IO_BUFFER_WAKE(7); 557 val |= EDP_PSR2_FAST_WAKE(7); 558 } 559 560 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 561 val |= EDP_PSR2_SU_SDP_SCANLINE; 562 563 if (intel_dp->psr.psr2_sel_fetch_enabled) { 564 u32 tmp; 565 566 /* Wa_1408330847 */ 567 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 568 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 569 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 570 DIS_RAM_BYPASS_PSR2_MAN_TRACK); 571 572 tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); 573 drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); 574 } else if (HAS_PSR2_SEL_FETCH(dev_priv)) { 575 intel_de_write(dev_priv, 576 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0); 577 } 578 579 /* 580 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 581 * recommending keep this bit unset while PSR2 is enabled. 582 */ 583 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0); 584 585 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 586 } 587 588 static bool 589 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) 590 { 591 if (DISPLAY_VER(dev_priv) >= 12) 592 return trans == TRANSCODER_A; 593 else 594 return trans == TRANSCODER_EDP; 595 } 596 597 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate) 598 { 599 if (!cstate || !cstate->hw.active) 600 return 0; 601 602 return DIV_ROUND_UP(1000 * 1000, 603 drm_mode_vrefresh(&cstate->hw.adjusted_mode)); 604 } 605 606 static void psr2_program_idle_frames(struct intel_dp *intel_dp, 607 u32 idle_frames) 608 { 609 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 610 u32 val; 611 612 idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; 613 val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder)); 614 val &= ~EDP_PSR2_IDLE_FRAME_MASK; 615 val |= idle_frames; 616 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 617 } 618 619 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) 620 { 621 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 622 623 psr2_program_idle_frames(intel_dp, 0); 624 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO); 625 } 626 627 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp) 628 { 629 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 630 631 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 632 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp)); 633 } 634 635 static void tgl_dc3co_disable_work(struct work_struct *work) 636 { 637 struct intel_dp *intel_dp = 638 container_of(work, typeof(*intel_dp), psr.dc3co_work.work); 639 640 mutex_lock(&intel_dp->psr.lock); 641 /* If delayed work is pending, it is not idle */ 642 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) 643 goto unlock; 644 645 tgl_psr2_disable_dc3co(intel_dp); 646 unlock: 647 mutex_unlock(&intel_dp->psr.lock); 648 } 649 650 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) 651 { 652 if (!intel_dp->psr.dc3co_exitline) 653 return; 654 655 cancel_delayed_work(&intel_dp->psr.dc3co_work); 656 /* Before PSR2 exit disallow dc3co*/ 657 tgl_psr2_disable_dc3co(intel_dp); 658 } 659 660 static bool 661 dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp, 662 struct intel_crtc_state *crtc_state) 663 { 664 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 665 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 666 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 667 enum port port = dig_port->base.port; 668 669 if (IS_ALDERLAKE_P(dev_priv)) 670 return pipe <= PIPE_B && port <= PORT_B; 671 else 672 return pipe == PIPE_A && port == PORT_A; 673 } 674 675 static void 676 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 677 struct intel_crtc_state *crtc_state) 678 { 679 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; 680 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 681 u32 exit_scanlines; 682 683 /* 684 * FIXME: Due to the changed sequence of activating/deactivating DC3CO, 685 * disable DC3CO until the changed dc3co activating/deactivating sequence 686 * is applied. B.Specs:49196 687 */ 688 return; 689 690 /* 691 * DMC's DC3CO exit mechanism has an issue with Selective Fecth 692 * TODO: when the issue is addressed, this restriction should be removed. 693 */ 694 if (crtc_state->enable_psr2_sel_fetch) 695 return; 696 697 if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO)) 698 return; 699 700 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) 701 return; 702 703 /* Wa_16011303918:adl-p */ 704 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 705 return; 706 707 /* 708 * DC3CO Exit time 200us B.Spec 49196 709 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 710 */ 711 exit_scanlines = 712 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; 713 714 if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay)) 715 return; 716 717 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; 718 } 719 720 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, 721 struct intel_crtc_state *crtc_state) 722 { 723 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 724 725 if (!dev_priv->params.enable_psr2_sel_fetch && 726 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 727 drm_dbg_kms(&dev_priv->drm, 728 "PSR2 sel fetch not enabled, disabled by parameter\n"); 729 return false; 730 } 731 732 if (crtc_state->uapi.async_flip) { 733 drm_dbg_kms(&dev_priv->drm, 734 "PSR2 sel fetch not enabled, async flip enabled\n"); 735 return false; 736 } 737 738 /* Wa_14010254185 Wa_14010103792 */ 739 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { 740 drm_dbg_kms(&dev_priv->drm, 741 "PSR2 sel fetch not enabled, missing the implementation of WAs\n"); 742 return false; 743 } 744 745 return crtc_state->enable_psr2_sel_fetch = true; 746 } 747 748 static bool psr2_granularity_check(struct intel_dp *intel_dp, 749 struct intel_crtc_state *crtc_state) 750 { 751 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 752 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 753 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 754 u16 y_granularity = 0; 755 756 /* PSR2 HW only send full lines so we only need to validate the width */ 757 if (crtc_hdisplay % intel_dp->psr.su_w_granularity) 758 return false; 759 760 if (crtc_vdisplay % intel_dp->psr.su_y_granularity) 761 return false; 762 763 /* HW tracking is only aligned to 4 lines */ 764 if (!crtc_state->enable_psr2_sel_fetch) 765 return intel_dp->psr.su_y_granularity == 4; 766 767 /* 768 * adl_p has 1 line granularity. For other platforms with SW tracking we 769 * can adjust the y coordinates to match sink requirement if multiple of 770 * 4. 771 */ 772 if (IS_ALDERLAKE_P(dev_priv)) 773 y_granularity = intel_dp->psr.su_y_granularity; 774 else if (intel_dp->psr.su_y_granularity <= 2) 775 y_granularity = 4; 776 else if ((intel_dp->psr.su_y_granularity % 4) == 0) 777 y_granularity = intel_dp->psr.su_y_granularity; 778 779 if (y_granularity == 0 || crtc_vdisplay % y_granularity) 780 return false; 781 782 crtc_state->su_y_granularity = y_granularity; 783 return true; 784 } 785 786 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp, 787 struct intel_crtc_state *crtc_state) 788 { 789 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; 790 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 791 u32 hblank_total, hblank_ns, req_ns; 792 793 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; 794 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); 795 796 /* From spec: (72 / number of lanes) * 1000 / symbol clock frequency MHz */ 797 req_ns = (72 / crtc_state->lane_count) * 1000 / (crtc_state->port_clock / 1000); 798 799 if ((hblank_ns - req_ns) > 100) 800 return true; 801 802 if (DISPLAY_VER(dev_priv) < 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b) 803 return false; 804 805 crtc_state->req_psr2_sdp_prior_scanline = true; 806 return true; 807 } 808 809 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 810 struct intel_crtc_state *crtc_state) 811 { 812 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 813 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 814 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 815 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 816 817 if (!intel_dp->psr.sink_psr2_support) 818 return false; 819 820 /* JSL and EHL only supports eDP 1.3 */ 821 if (IS_JSL_EHL(dev_priv)) { 822 drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n"); 823 return false; 824 } 825 826 /* Wa_16011181250 */ 827 if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) || 828 IS_DG2(dev_priv)) { 829 drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n"); 830 return false; 831 } 832 833 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 834 drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n"); 835 return false; 836 } 837 838 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { 839 drm_dbg_kms(&dev_priv->drm, 840 "PSR2 not supported in transcoder %s\n", 841 transcoder_name(crtc_state->cpu_transcoder)); 842 return false; 843 } 844 845 if (!psr2_global_enabled(intel_dp)) { 846 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); 847 return false; 848 } 849 850 /* 851 * DSC and PSR2 cannot be enabled simultaneously. If a requested 852 * resolution requires DSC to be enabled, priority is given to DSC 853 * over PSR2. 854 */ 855 if (crtc_state->dsc.compression_enable) { 856 drm_dbg_kms(&dev_priv->drm, 857 "PSR2 cannot be enabled since DSC is enabled\n"); 858 return false; 859 } 860 861 if (crtc_state->crc_enabled) { 862 drm_dbg_kms(&dev_priv->drm, 863 "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); 864 return false; 865 } 866 867 if (DISPLAY_VER(dev_priv) >= 12) { 868 psr_max_h = 5120; 869 psr_max_v = 3200; 870 max_bpp = 30; 871 } else if (DISPLAY_VER(dev_priv) >= 10) { 872 psr_max_h = 4096; 873 psr_max_v = 2304; 874 max_bpp = 24; 875 } else if (DISPLAY_VER(dev_priv) == 9) { 876 psr_max_h = 3640; 877 psr_max_v = 2304; 878 max_bpp = 24; 879 } 880 881 if (crtc_state->pipe_bpp > max_bpp) { 882 drm_dbg_kms(&dev_priv->drm, 883 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 884 crtc_state->pipe_bpp, max_bpp); 885 return false; 886 } 887 888 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 889 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && 890 !HAS_PSR_HW_TRACKING(dev_priv)) { 891 drm_dbg_kms(&dev_priv->drm, 892 "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); 893 return false; 894 } 895 } 896 897 /* Wa_2209313811 */ 898 if (!crtc_state->enable_psr2_sel_fetch && 899 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { 900 drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n"); 901 return false; 902 } 903 904 if (!psr2_granularity_check(intel_dp, crtc_state)) { 905 drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n"); 906 return false; 907 } 908 909 if (!crtc_state->enable_psr2_sel_fetch && 910 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { 911 drm_dbg_kms(&dev_priv->drm, 912 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 913 crtc_hdisplay, crtc_vdisplay, 914 psr_max_h, psr_max_v); 915 return false; 916 } 917 918 if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) { 919 drm_dbg_kms(&dev_priv->drm, 920 "PSR2 not enabled, PSR2 SDP indication do not fit in hblank\n"); 921 return false; 922 } 923 924 /* Wa_16011303918:adl-p */ 925 if (crtc_state->vrr.enable && 926 IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 927 drm_dbg_kms(&dev_priv->drm, 928 "PSR2 not enabled, not compatible with HW stepping + VRR\n"); 929 return false; 930 } 931 932 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); 933 return true; 934 } 935 936 void intel_psr_compute_config(struct intel_dp *intel_dp, 937 struct intel_crtc_state *crtc_state, 938 struct drm_connector_state *conn_state) 939 { 940 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 941 const struct drm_display_mode *adjusted_mode = 942 &crtc_state->hw.adjusted_mode; 943 int psr_setup_time; 944 945 /* 946 * Current PSR panels dont work reliably with VRR enabled 947 * So if VRR is enabled, do not enable PSR. 948 */ 949 if (crtc_state->vrr.enable) 950 return; 951 952 if (!CAN_PSR(intel_dp)) 953 return; 954 955 if (!psr_global_enabled(intel_dp)) { 956 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); 957 return; 958 } 959 960 if (intel_dp->psr.sink_not_reliable) { 961 drm_dbg_kms(&dev_priv->drm, 962 "PSR sink implementation is not reliable\n"); 963 return; 964 } 965 966 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 967 drm_dbg_kms(&dev_priv->drm, 968 "PSR condition failed: Interlaced mode enabled\n"); 969 return; 970 } 971 972 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); 973 if (psr_setup_time < 0) { 974 drm_dbg_kms(&dev_priv->drm, 975 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 976 intel_dp->psr_dpcd[1]); 977 return; 978 } 979 980 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 981 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 982 drm_dbg_kms(&dev_priv->drm, 983 "PSR condition failed: PSR setup time (%d us) too long\n", 984 psr_setup_time); 985 return; 986 } 987 988 crtc_state->has_psr = true; 989 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); 990 991 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 992 intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, 993 &crtc_state->psr_vsc); 994 } 995 996 void intel_psr_get_config(struct intel_encoder *encoder, 997 struct intel_crtc_state *pipe_config) 998 { 999 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1000 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1001 struct intel_dp *intel_dp; 1002 u32 val; 1003 1004 if (!dig_port) 1005 return; 1006 1007 intel_dp = &dig_port->dp; 1008 if (!CAN_PSR(intel_dp)) 1009 return; 1010 1011 mutex_lock(&intel_dp->psr.lock); 1012 if (!intel_dp->psr.enabled) 1013 goto unlock; 1014 1015 /* 1016 * Not possible to read EDP_PSR/PSR2_CTL registers as it is 1017 * enabled/disabled because of frontbuffer tracking and others. 1018 */ 1019 pipe_config->has_psr = true; 1020 pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; 1021 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1022 1023 if (!intel_dp->psr.psr2_enabled) 1024 goto unlock; 1025 1026 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 1027 val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); 1028 if (val & PSR2_MAN_TRK_CTL_ENABLE) 1029 pipe_config->enable_psr2_sel_fetch = true; 1030 } 1031 1032 if (DISPLAY_VER(dev_priv) >= 12) { 1033 val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder)); 1034 val &= EXITLINE_MASK; 1035 pipe_config->dc3co_exitline = val; 1036 } 1037 unlock: 1038 mutex_unlock(&intel_dp->psr.lock); 1039 } 1040 1041 static void intel_psr_activate(struct intel_dp *intel_dp) 1042 { 1043 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1044 enum transcoder transcoder = intel_dp->psr.transcoder; 1045 1046 if (transcoder_has_psr2(dev_priv, transcoder)) 1047 drm_WARN_ON(&dev_priv->drm, 1048 intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE); 1049 1050 drm_WARN_ON(&dev_priv->drm, 1051 intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE); 1052 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active); 1053 lockdep_assert_held(&intel_dp->psr.lock); 1054 1055 /* psr1 and psr2 are mutually exclusive.*/ 1056 if (intel_dp->psr.psr2_enabled) 1057 hsw_activate_psr2(intel_dp); 1058 else 1059 hsw_activate_psr1(intel_dp); 1060 1061 intel_dp->psr.active = true; 1062 } 1063 1064 static void intel_psr_enable_source(struct intel_dp *intel_dp) 1065 { 1066 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1067 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1068 u32 mask; 1069 1070 if (intel_dp->psr.psr2_enabled && DISPLAY_VER(dev_priv) == 9) { 1071 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder); 1072 u32 chicken = intel_de_read(dev_priv, reg); 1073 1074 chicken |= PSR2_VSC_ENABLE_PROG_HEADER | 1075 PSR2_ADD_VERTICAL_LINE_COUNT; 1076 intel_de_write(dev_priv, reg, chicken); 1077 } 1078 1079 /* 1080 * Wa_16014451276:adlp 1081 * All supported adlp panels have 1-based X granularity, this may 1082 * cause issues if non-supported panels are used. 1083 */ 1084 if (IS_ALDERLAKE_P(dev_priv) && 1085 intel_dp->psr.psr2_enabled) 1086 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, 1087 ADLP_1_BASED_X_GRANULARITY); 1088 1089 /* 1090 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 1091 * mask LPSP to avoid dependency on other drivers that might block 1092 * runtime_pm besides preventing other hw tracking issues now we 1093 * can rely on frontbuffer tracking. 1094 */ 1095 mask = EDP_PSR_DEBUG_MASK_MEMUP | 1096 EDP_PSR_DEBUG_MASK_HPD | 1097 EDP_PSR_DEBUG_MASK_LPSP | 1098 EDP_PSR_DEBUG_MASK_MAX_SLEEP; 1099 1100 if (DISPLAY_VER(dev_priv) < 11) 1101 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 1102 1103 intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder), 1104 mask); 1105 1106 psr_irq_control(intel_dp); 1107 1108 if (intel_dp->psr.dc3co_exitline) { 1109 u32 val; 1110 1111 /* 1112 * TODO: if future platforms supports DC3CO in more than one 1113 * transcoder, EXITLINE will need to be unset when disabling PSR 1114 */ 1115 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder)); 1116 val &= ~EXITLINE_MASK; 1117 val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT; 1118 val |= EXITLINE_ENABLE; 1119 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); 1120 } 1121 1122 if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv)) 1123 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, 1124 intel_dp->psr.psr2_sel_fetch_enabled ? 1125 IGNORE_PSR2_HW_TRACKING : 0); 1126 1127 /* Wa_16011168373:adl-p */ 1128 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) && 1129 intel_dp->psr.psr2_enabled) 1130 intel_de_rmw(dev_priv, 1131 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), 1132 TRANS_SET_CONTEXT_LATENCY_MASK, 1133 TRANS_SET_CONTEXT_LATENCY_VALUE(1)); 1134 1135 /* Wa_16012604467:adlp */ 1136 if (IS_ALDERLAKE_P(dev_priv) && intel_dp->psr.psr2_enabled) 1137 intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0, 1138 CLKGATE_DIS_MISC_DMASC_GATING_DIS); 1139 } 1140 1141 static bool psr_interrupt_error_check(struct intel_dp *intel_dp) 1142 { 1143 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1144 u32 val; 1145 1146 /* 1147 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 1148 * will still keep the error set even after the reset done in the 1149 * irq_preinstall and irq_uninstall hooks. 1150 * And enabling in this situation cause the screen to freeze in the 1151 * first time that PSR HW tries to activate so lets keep PSR disabled 1152 * to avoid any rendering problems. 1153 */ 1154 if (DISPLAY_VER(dev_priv) >= 12) { 1155 val = intel_de_read(dev_priv, 1156 TRANS_PSR_IIR(intel_dp->psr.transcoder)); 1157 val &= EDP_PSR_ERROR(0); 1158 } else { 1159 val = intel_de_read(dev_priv, EDP_PSR_IIR); 1160 val &= EDP_PSR_ERROR(intel_dp->psr.transcoder); 1161 } 1162 if (val) { 1163 intel_dp->psr.sink_not_reliable = true; 1164 drm_dbg_kms(&dev_priv->drm, 1165 "PSR interruption error set, not enabling PSR\n"); 1166 return false; 1167 } 1168 1169 return true; 1170 } 1171 1172 static void intel_psr_enable_locked(struct intel_dp *intel_dp, 1173 const struct intel_crtc_state *crtc_state) 1174 { 1175 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1176 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1177 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 1178 struct intel_encoder *encoder = &dig_port->base; 1179 u32 val; 1180 1181 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); 1182 1183 intel_dp->psr.psr2_enabled = crtc_state->has_psr2; 1184 intel_dp->psr.busy_frontbuffer_bits = 0; 1185 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1186 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; 1187 /* DC5/DC6 requires at least 6 idle frames */ 1188 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 1189 intel_dp->psr.dc3co_exit_delay = val; 1190 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; 1191 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; 1192 intel_dp->psr.req_psr2_sdp_prior_scanline = 1193 crtc_state->req_psr2_sdp_prior_scanline; 1194 1195 if (!psr_interrupt_error_check(intel_dp)) 1196 return; 1197 1198 drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", 1199 intel_dp->psr.psr2_enabled ? "2" : "1"); 1200 intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc); 1201 intel_snps_phy_update_psr_power_state(dev_priv, phy, true); 1202 intel_psr_enable_sink(intel_dp); 1203 intel_psr_enable_source(intel_dp); 1204 intel_dp->psr.enabled = true; 1205 intel_dp->psr.paused = false; 1206 1207 intel_psr_activate(intel_dp); 1208 } 1209 1210 static void intel_psr_exit(struct intel_dp *intel_dp) 1211 { 1212 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1213 u32 val; 1214 1215 if (!intel_dp->psr.active) { 1216 if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) { 1217 val = intel_de_read(dev_priv, 1218 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1219 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE); 1220 } 1221 1222 val = intel_de_read(dev_priv, 1223 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1224 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE); 1225 1226 return; 1227 } 1228 1229 if (intel_dp->psr.psr2_enabled) { 1230 tgl_disallow_dc3co_on_psr2_exit(intel_dp); 1231 val = intel_de_read(dev_priv, 1232 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1233 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE)); 1234 val &= ~EDP_PSR2_ENABLE; 1235 intel_de_write(dev_priv, 1236 EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 1237 } else { 1238 val = intel_de_read(dev_priv, 1239 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1240 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE)); 1241 val &= ~EDP_PSR_ENABLE; 1242 intel_de_write(dev_priv, 1243 EDP_PSR_CTL(intel_dp->psr.transcoder), val); 1244 } 1245 intel_dp->psr.active = false; 1246 } 1247 1248 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) 1249 { 1250 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1251 i915_reg_t psr_status; 1252 u32 psr_status_mask; 1253 1254 if (intel_dp->psr.psr2_enabled) { 1255 psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 1256 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 1257 } else { 1258 psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder); 1259 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 1260 } 1261 1262 /* Wait till PSR is idle */ 1263 if (intel_de_wait_for_clear(dev_priv, psr_status, 1264 psr_status_mask, 2000)) 1265 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n"); 1266 } 1267 1268 static void intel_psr_disable_locked(struct intel_dp *intel_dp) 1269 { 1270 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1271 enum phy phy = intel_port_to_phy(dev_priv, 1272 dp_to_dig_port(intel_dp)->base.port); 1273 1274 lockdep_assert_held(&intel_dp->psr.lock); 1275 1276 if (!intel_dp->psr.enabled) 1277 return; 1278 1279 drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", 1280 intel_dp->psr.psr2_enabled ? "2" : "1"); 1281 1282 intel_psr_exit(intel_dp); 1283 intel_psr_wait_exit_locked(intel_dp); 1284 1285 /* Wa_1408330847 */ 1286 if (intel_dp->psr.psr2_sel_fetch_enabled && 1287 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1288 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1289 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0); 1290 1291 /* Wa_16011168373:adl-p */ 1292 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) && 1293 intel_dp->psr.psr2_enabled) 1294 intel_de_rmw(dev_priv, 1295 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), 1296 TRANS_SET_CONTEXT_LATENCY_MASK, 0); 1297 1298 /* Wa_16012604467:adlp */ 1299 if (IS_ALDERLAKE_P(dev_priv) && intel_dp->psr.psr2_enabled) 1300 intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 1301 CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0); 1302 1303 intel_snps_phy_update_psr_power_state(dev_priv, phy, false); 1304 1305 /* Disable PSR on Sink */ 1306 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 1307 1308 if (intel_dp->psr.psr2_enabled) 1309 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); 1310 1311 intel_dp->psr.enabled = false; 1312 } 1313 1314 /** 1315 * intel_psr_disable - Disable PSR 1316 * @intel_dp: Intel DP 1317 * @old_crtc_state: old CRTC state 1318 * 1319 * This function needs to be called before disabling pipe. 1320 */ 1321 void intel_psr_disable(struct intel_dp *intel_dp, 1322 const struct intel_crtc_state *old_crtc_state) 1323 { 1324 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1325 1326 if (!old_crtc_state->has_psr) 1327 return; 1328 1329 if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp))) 1330 return; 1331 1332 mutex_lock(&intel_dp->psr.lock); 1333 1334 intel_psr_disable_locked(intel_dp); 1335 1336 mutex_unlock(&intel_dp->psr.lock); 1337 cancel_work_sync(&intel_dp->psr.work); 1338 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); 1339 } 1340 1341 /** 1342 * intel_psr_pause - Pause PSR 1343 * @intel_dp: Intel DP 1344 * 1345 * This function need to be called after enabling psr. 1346 */ 1347 void intel_psr_pause(struct intel_dp *intel_dp) 1348 { 1349 struct intel_psr *psr = &intel_dp->psr; 1350 1351 if (!CAN_PSR(intel_dp)) 1352 return; 1353 1354 mutex_lock(&psr->lock); 1355 1356 if (!psr->enabled) { 1357 mutex_unlock(&psr->lock); 1358 return; 1359 } 1360 1361 intel_psr_exit(intel_dp); 1362 intel_psr_wait_exit_locked(intel_dp); 1363 psr->paused = true; 1364 1365 mutex_unlock(&psr->lock); 1366 1367 cancel_work_sync(&psr->work); 1368 cancel_delayed_work_sync(&psr->dc3co_work); 1369 } 1370 1371 /** 1372 * intel_psr_resume - Resume PSR 1373 * @intel_dp: Intel DP 1374 * 1375 * This function need to be called after pausing psr. 1376 */ 1377 void intel_psr_resume(struct intel_dp *intel_dp) 1378 { 1379 struct intel_psr *psr = &intel_dp->psr; 1380 1381 if (!CAN_PSR(intel_dp)) 1382 return; 1383 1384 mutex_lock(&psr->lock); 1385 1386 if (!psr->paused) 1387 goto unlock; 1388 1389 psr->paused = false; 1390 intel_psr_activate(intel_dp); 1391 1392 unlock: 1393 mutex_unlock(&psr->lock); 1394 } 1395 1396 static inline u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private *dev_priv) 1397 { 1398 return IS_ALDERLAKE_P(dev_priv) ? 1399 ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME : 1400 PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 1401 } 1402 1403 static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) 1404 { 1405 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1406 1407 if (intel_dp->psr.psr2_sel_fetch_enabled) 1408 intel_de_rmw(dev_priv, 1409 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0, 1410 man_trk_ctl_single_full_frame_bit_get(dev_priv)); 1411 1412 /* 1413 * Display WA #0884: skl+ 1414 * This documented WA for bxt can be safely applied 1415 * broadly so we can force HW tracking to exit PSR 1416 * instead of disabling and re-enabling. 1417 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 1418 * but it makes more sense write to the current active 1419 * pipe. 1420 * 1421 * This workaround do not exist for platforms with display 10 or newer 1422 * but testing proved that it works for up display 13, for newer 1423 * than that testing will be needed. 1424 */ 1425 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 1426 } 1427 1428 void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane, 1429 const struct intel_crtc_state *crtc_state) 1430 { 1431 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1432 enum pipe pipe = plane->pipe; 1433 1434 if (!crtc_state->enable_psr2_sel_fetch) 1435 return; 1436 1437 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0); 1438 } 1439 1440 void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, 1441 const struct intel_crtc_state *crtc_state, 1442 const struct intel_plane_state *plane_state, 1443 int color_plane) 1444 { 1445 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1446 enum pipe pipe = plane->pipe; 1447 const struct drm_rect *clip; 1448 u32 val; 1449 int x, y; 1450 1451 if (!crtc_state->enable_psr2_sel_fetch) 1452 return; 1453 1454 if (plane->id == PLANE_CURSOR) { 1455 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 1456 plane_state->ctl); 1457 return; 1458 } 1459 1460 clip = &plane_state->psr2_sel_fetch_area; 1461 1462 val = (clip->y1 + plane_state->uapi.dst.y1) << 16; 1463 val |= plane_state->uapi.dst.x1; 1464 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); 1465 1466 /* TODO: consider auxiliary surfaces */ 1467 x = plane_state->uapi.src.x1 >> 16; 1468 y = (plane_state->uapi.src.y1 >> 16) + clip->y1; 1469 val = y << 16 | x; 1470 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), 1471 val); 1472 1473 /* Sizes are 0 based */ 1474 val = (drm_rect_height(clip) - 1) << 16; 1475 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; 1476 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); 1477 1478 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 1479 PLANE_SEL_FETCH_CTL_ENABLE); 1480 } 1481 1482 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) 1483 { 1484 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1485 1486 if (!crtc_state->enable_psr2_sel_fetch) 1487 return; 1488 1489 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder), 1490 crtc_state->psr2_man_track_ctl); 1491 } 1492 1493 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, 1494 struct drm_rect *clip, bool full_update) 1495 { 1496 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1497 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1498 u32 val = PSR2_MAN_TRK_CTL_ENABLE; 1499 1500 if (full_update) { 1501 /* 1502 * Not applying Wa_14014971508:adlp as we do not support the 1503 * feature that requires this workaround. 1504 */ 1505 val |= man_trk_ctl_single_full_frame_bit_get(dev_priv); 1506 goto exit; 1507 } 1508 1509 if (clip->y1 == -1) 1510 goto exit; 1511 1512 if (IS_ALDERLAKE_P(dev_priv)) { 1513 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1); 1514 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 - 1); 1515 } else { 1516 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4); 1517 1518 val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; 1519 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1); 1520 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1); 1521 } 1522 exit: 1523 crtc_state->psr2_man_track_ctl = val; 1524 } 1525 1526 static void clip_area_update(struct drm_rect *overlap_damage_area, 1527 struct drm_rect *damage_area) 1528 { 1529 if (overlap_damage_area->y1 == -1) { 1530 overlap_damage_area->y1 = damage_area->y1; 1531 overlap_damage_area->y2 = damage_area->y2; 1532 return; 1533 } 1534 1535 if (damage_area->y1 < overlap_damage_area->y1) 1536 overlap_damage_area->y1 = damage_area->y1; 1537 1538 if (damage_area->y2 > overlap_damage_area->y2) 1539 overlap_damage_area->y2 = damage_area->y2; 1540 } 1541 1542 static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state, 1543 struct drm_rect *pipe_clip) 1544 { 1545 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1546 const u16 y_alignment = crtc_state->su_y_granularity; 1547 1548 pipe_clip->y1 -= pipe_clip->y1 % y_alignment; 1549 if (pipe_clip->y2 % y_alignment) 1550 pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment; 1551 1552 if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable) 1553 drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n"); 1554 } 1555 1556 /* 1557 * TODO: Not clear how to handle planes with negative position, 1558 * also planes are not updated if they have a negative X 1559 * position so for now doing a full update in this cases 1560 * 1561 * TODO: We are missing multi-planar formats handling, until it is 1562 * implemented it will send full frame updates. 1563 * 1564 * Plane scaling and rotation is not supported by selective fetch and both 1565 * properties can change without a modeset, so need to be check at every 1566 * atomic commmit. 1567 */ 1568 static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state) 1569 { 1570 if (plane_state->uapi.dst.y1 < 0 || 1571 plane_state->uapi.dst.x1 < 0 || 1572 plane_state->scaler_id >= 0 || 1573 plane_state->hw.fb->format->num_planes > 1 || 1574 plane_state->uapi.rotation != DRM_MODE_ROTATE_0) 1575 return false; 1576 1577 return true; 1578 } 1579 1580 /* 1581 * Check for pipe properties that is not supported by selective fetch. 1582 * 1583 * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed 1584 * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch 1585 * enabled and going to the full update path. 1586 */ 1587 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state) 1588 { 1589 if (crtc_state->scaler_state.scaler_id >= 0) 1590 return false; 1591 1592 return true; 1593 } 1594 1595 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 1596 struct intel_crtc *crtc) 1597 { 1598 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 1599 struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 }; 1600 struct intel_plane_state *new_plane_state, *old_plane_state; 1601 struct intel_plane *plane; 1602 bool full_update = false; 1603 int i, ret; 1604 1605 if (!crtc_state->enable_psr2_sel_fetch) 1606 return 0; 1607 1608 if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) { 1609 full_update = true; 1610 goto skip_sel_fetch_set_loop; 1611 } 1612 1613 /* 1614 * Calculate minimal selective fetch area of each plane and calculate 1615 * the pipe damaged area. 1616 * In the next loop the plane selective fetch area will actually be set 1617 * using whole pipe damaged area. 1618 */ 1619 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1620 new_plane_state, i) { 1621 struct drm_rect src, damaged_area = { .y1 = -1 }; 1622 struct drm_atomic_helper_damage_iter iter; 1623 struct drm_rect clip; 1624 1625 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) 1626 continue; 1627 1628 if (!new_plane_state->uapi.visible && 1629 !old_plane_state->uapi.visible) 1630 continue; 1631 1632 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 1633 full_update = true; 1634 break; 1635 } 1636 1637 /* 1638 * If visibility or plane moved, mark the whole plane area as 1639 * damaged as it needs to be complete redraw in the new and old 1640 * position. 1641 */ 1642 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || 1643 !drm_rect_equals(&new_plane_state->uapi.dst, 1644 &old_plane_state->uapi.dst)) { 1645 if (old_plane_state->uapi.visible) { 1646 damaged_area.y1 = old_plane_state->uapi.dst.y1; 1647 damaged_area.y2 = old_plane_state->uapi.dst.y2; 1648 clip_area_update(&pipe_clip, &damaged_area); 1649 } 1650 1651 if (new_plane_state->uapi.visible) { 1652 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1653 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1654 clip_area_update(&pipe_clip, &damaged_area); 1655 } 1656 continue; 1657 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { 1658 /* If alpha changed mark the whole plane area as damaged */ 1659 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1660 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1661 clip_area_update(&pipe_clip, &damaged_area); 1662 continue; 1663 } 1664 1665 drm_rect_fp_to_int(&src, &new_plane_state->uapi.src); 1666 1667 drm_atomic_helper_damage_iter_init(&iter, 1668 &old_plane_state->uapi, 1669 &new_plane_state->uapi); 1670 drm_atomic_for_each_plane_damage(&iter, &clip) { 1671 if (drm_rect_intersect(&clip, &src)) 1672 clip_area_update(&damaged_area, &clip); 1673 } 1674 1675 if (damaged_area.y1 == -1) 1676 continue; 1677 1678 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; 1679 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; 1680 clip_area_update(&pipe_clip, &damaged_area); 1681 } 1682 1683 if (full_update) 1684 goto skip_sel_fetch_set_loop; 1685 1686 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 1687 if (ret) 1688 return ret; 1689 1690 intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip); 1691 1692 /* 1693 * Now that we have the pipe damaged area check if it intersect with 1694 * every plane, if it does set the plane selective fetch area. 1695 */ 1696 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1697 new_plane_state, i) { 1698 struct drm_rect *sel_fetch_area, inter; 1699 1700 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || 1701 !new_plane_state->uapi.visible) 1702 continue; 1703 1704 inter = pipe_clip; 1705 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) 1706 continue; 1707 1708 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 1709 full_update = true; 1710 break; 1711 } 1712 1713 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 1714 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; 1715 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; 1716 crtc_state->update_planes |= BIT(plane->id); 1717 } 1718 1719 skip_sel_fetch_set_loop: 1720 psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update); 1721 return 0; 1722 } 1723 1724 static void _intel_psr_pre_plane_update(const struct intel_atomic_state *state, 1725 const struct intel_crtc_state *crtc_state) 1726 { 1727 struct intel_encoder *encoder; 1728 1729 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 1730 crtc_state->uapi.encoder_mask) { 1731 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1732 struct intel_psr *psr = &intel_dp->psr; 1733 bool needs_to_disable = false; 1734 1735 mutex_lock(&psr->lock); 1736 1737 /* 1738 * Reasons to disable: 1739 * - PSR disabled in new state 1740 * - All planes will go inactive 1741 * - Changing between PSR versions 1742 */ 1743 needs_to_disable |= !crtc_state->has_psr; 1744 needs_to_disable |= !crtc_state->active_planes; 1745 needs_to_disable |= crtc_state->has_psr2 != psr->psr2_enabled; 1746 1747 if (psr->enabled && needs_to_disable) 1748 intel_psr_disable_locked(intel_dp); 1749 1750 mutex_unlock(&psr->lock); 1751 } 1752 } 1753 1754 void intel_psr_pre_plane_update(const struct intel_atomic_state *state) 1755 { 1756 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1757 struct intel_crtc_state *crtc_state; 1758 struct intel_crtc *crtc; 1759 int i; 1760 1761 if (!HAS_PSR(dev_priv)) 1762 return; 1763 1764 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) 1765 _intel_psr_pre_plane_update(state, crtc_state); 1766 } 1767 1768 static void _intel_psr_post_plane_update(const struct intel_atomic_state *state, 1769 const struct intel_crtc_state *crtc_state) 1770 { 1771 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1772 struct intel_encoder *encoder; 1773 1774 if (!crtc_state->has_psr) 1775 return; 1776 1777 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 1778 crtc_state->uapi.encoder_mask) { 1779 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1780 struct intel_psr *psr = &intel_dp->psr; 1781 1782 mutex_lock(&psr->lock); 1783 1784 drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes); 1785 1786 /* Only enable if there is active planes */ 1787 if (!psr->enabled && crtc_state->active_planes) 1788 intel_psr_enable_locked(intel_dp, crtc_state); 1789 1790 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 1791 if (crtc_state->crc_enabled && psr->enabled) 1792 psr_force_hw_tracking_exit(intel_dp); 1793 1794 mutex_unlock(&psr->lock); 1795 } 1796 } 1797 1798 void intel_psr_post_plane_update(const struct intel_atomic_state *state) 1799 { 1800 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1801 struct intel_crtc_state *crtc_state; 1802 struct intel_crtc *crtc; 1803 int i; 1804 1805 if (!HAS_PSR(dev_priv)) 1806 return; 1807 1808 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) 1809 _intel_psr_post_plane_update(state, crtc_state); 1810 } 1811 1812 /** 1813 * psr_wait_for_idle - wait for PSR1 to idle 1814 * @intel_dp: Intel DP 1815 * @out_value: PSR status in case of failure 1816 * 1817 * Returns: 0 on success or -ETIMEOUT if PSR status does not idle. 1818 * 1819 */ 1820 static int psr_wait_for_idle(struct intel_dp *intel_dp, u32 *out_value) 1821 { 1822 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1823 1824 /* 1825 * From bspec: Panel Self Refresh (BDW+) 1826 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 1827 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 1828 * defensive enough to cover everything. 1829 */ 1830 return __intel_wait_for_register(&dev_priv->uncore, 1831 EDP_PSR_STATUS(intel_dp->psr.transcoder), 1832 EDP_PSR_STATUS_STATE_MASK, 1833 EDP_PSR_STATUS_STATE_IDLE, 2, 50, 1834 out_value); 1835 } 1836 1837 /** 1838 * intel_psr_wait_for_idle - wait for PSR1 to idle 1839 * @new_crtc_state: new CRTC state 1840 * 1841 * This function is expected to be called from pipe_update_start() where it is 1842 * not expected to race with PSR enable or disable. 1843 */ 1844 void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state) 1845 { 1846 struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev); 1847 struct intel_encoder *encoder; 1848 1849 if (!new_crtc_state->has_psr) 1850 return; 1851 1852 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, 1853 new_crtc_state->uapi.encoder_mask) { 1854 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1855 u32 psr_status; 1856 1857 mutex_lock(&intel_dp->psr.lock); 1858 if (!intel_dp->psr.enabled || intel_dp->psr.psr2_enabled) { 1859 mutex_unlock(&intel_dp->psr.lock); 1860 continue; 1861 } 1862 1863 /* when the PSR1 is enabled */ 1864 if (psr_wait_for_idle(intel_dp, &psr_status)) 1865 drm_err(&dev_priv->drm, 1866 "PSR idle timed out 0x%x, atomic update may fail\n", 1867 psr_status); 1868 mutex_unlock(&intel_dp->psr.lock); 1869 } 1870 } 1871 1872 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) 1873 { 1874 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1875 i915_reg_t reg; 1876 u32 mask; 1877 int err; 1878 1879 if (!intel_dp->psr.enabled) 1880 return false; 1881 1882 if (intel_dp->psr.psr2_enabled) { 1883 reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 1884 mask = EDP_PSR2_STATUS_STATE_MASK; 1885 } else { 1886 reg = EDP_PSR_STATUS(intel_dp->psr.transcoder); 1887 mask = EDP_PSR_STATUS_STATE_MASK; 1888 } 1889 1890 mutex_unlock(&intel_dp->psr.lock); 1891 1892 err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); 1893 if (err) 1894 drm_err(&dev_priv->drm, 1895 "Timed out waiting for PSR Idle for re-enable\n"); 1896 1897 /* After the unlocked wait, verify that PSR is still wanted! */ 1898 mutex_lock(&intel_dp->psr.lock); 1899 return err == 0 && intel_dp->psr.enabled; 1900 } 1901 1902 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) 1903 { 1904 struct drm_connector_list_iter conn_iter; 1905 struct drm_device *dev = &dev_priv->drm; 1906 struct drm_modeset_acquire_ctx ctx; 1907 struct drm_atomic_state *state; 1908 struct drm_connector *conn; 1909 int err = 0; 1910 1911 state = drm_atomic_state_alloc(dev); 1912 if (!state) 1913 return -ENOMEM; 1914 1915 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1916 state->acquire_ctx = &ctx; 1917 1918 retry: 1919 1920 drm_connector_list_iter_begin(dev, &conn_iter); 1921 drm_for_each_connector_iter(conn, &conn_iter) { 1922 struct drm_connector_state *conn_state; 1923 struct drm_crtc_state *crtc_state; 1924 1925 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) 1926 continue; 1927 1928 conn_state = drm_atomic_get_connector_state(state, conn); 1929 if (IS_ERR(conn_state)) { 1930 err = PTR_ERR(conn_state); 1931 break; 1932 } 1933 1934 if (!conn_state->crtc) 1935 continue; 1936 1937 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); 1938 if (IS_ERR(crtc_state)) { 1939 err = PTR_ERR(crtc_state); 1940 break; 1941 } 1942 1943 /* Mark mode as changed to trigger a pipe->update() */ 1944 crtc_state->mode_changed = true; 1945 } 1946 drm_connector_list_iter_end(&conn_iter); 1947 1948 if (err == 0) 1949 err = drm_atomic_commit(state); 1950 1951 if (err == -EDEADLK) { 1952 drm_atomic_state_clear(state); 1953 err = drm_modeset_backoff(&ctx); 1954 if (!err) 1955 goto retry; 1956 } 1957 1958 drm_modeset_drop_locks(&ctx); 1959 drm_modeset_acquire_fini(&ctx); 1960 drm_atomic_state_put(state); 1961 1962 return err; 1963 } 1964 1965 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) 1966 { 1967 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1968 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 1969 u32 old_mode; 1970 int ret; 1971 1972 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || 1973 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 1974 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); 1975 return -EINVAL; 1976 } 1977 1978 ret = mutex_lock_interruptible(&intel_dp->psr.lock); 1979 if (ret) 1980 return ret; 1981 1982 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; 1983 intel_dp->psr.debug = val; 1984 1985 /* 1986 * Do it right away if it's already enabled, otherwise it will be done 1987 * when enabling the source. 1988 */ 1989 if (intel_dp->psr.enabled) 1990 psr_irq_control(intel_dp); 1991 1992 mutex_unlock(&intel_dp->psr.lock); 1993 1994 if (old_mode != mode) 1995 ret = intel_psr_fastset_force(dev_priv); 1996 1997 return ret; 1998 } 1999 2000 static void intel_psr_handle_irq(struct intel_dp *intel_dp) 2001 { 2002 struct intel_psr *psr = &intel_dp->psr; 2003 2004 intel_psr_disable_locked(intel_dp); 2005 psr->sink_not_reliable = true; 2006 /* let's make sure that sink is awaken */ 2007 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 2008 } 2009 2010 static void intel_psr_work(struct work_struct *work) 2011 { 2012 struct intel_dp *intel_dp = 2013 container_of(work, typeof(*intel_dp), psr.work); 2014 2015 mutex_lock(&intel_dp->psr.lock); 2016 2017 if (!intel_dp->psr.enabled) 2018 goto unlock; 2019 2020 if (READ_ONCE(intel_dp->psr.irq_aux_error)) 2021 intel_psr_handle_irq(intel_dp); 2022 2023 /* 2024 * We have to make sure PSR is ready for re-enable 2025 * otherwise it keeps disabled until next full enable/disable cycle. 2026 * PSR might take some time to get fully disabled 2027 * and be ready for re-enable. 2028 */ 2029 if (!__psr_wait_for_idle_locked(intel_dp)) 2030 goto unlock; 2031 2032 /* 2033 * The delayed work can race with an invalidate hence we need to 2034 * recheck. Since psr_flush first clears this and then reschedules we 2035 * won't ever miss a flush when bailing out here. 2036 */ 2037 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) 2038 goto unlock; 2039 2040 intel_psr_activate(intel_dp); 2041 unlock: 2042 mutex_unlock(&intel_dp->psr.lock); 2043 } 2044 2045 /** 2046 * intel_psr_invalidate - Invalidade PSR 2047 * @dev_priv: i915 device 2048 * @frontbuffer_bits: frontbuffer plane tracking bits 2049 * @origin: which operation caused the invalidate 2050 * 2051 * Since the hardware frontbuffer tracking has gaps we need to integrate 2052 * with the software frontbuffer tracking. This function gets called every 2053 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 2054 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 2055 * 2056 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 2057 */ 2058 void intel_psr_invalidate(struct drm_i915_private *dev_priv, 2059 unsigned frontbuffer_bits, enum fb_op_origin origin) 2060 { 2061 struct intel_encoder *encoder; 2062 2063 if (origin == ORIGIN_FLIP) 2064 return; 2065 2066 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2067 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 2068 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2069 2070 mutex_lock(&intel_dp->psr.lock); 2071 if (!intel_dp->psr.enabled) { 2072 mutex_unlock(&intel_dp->psr.lock); 2073 continue; 2074 } 2075 2076 pipe_frontbuffer_bits &= 2077 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 2078 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; 2079 2080 if (pipe_frontbuffer_bits) 2081 intel_psr_exit(intel_dp); 2082 2083 mutex_unlock(&intel_dp->psr.lock); 2084 } 2085 } 2086 /* 2087 * When we will be completely rely on PSR2 S/W tracking in future, 2088 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP 2089 * event also therefore tgl_dc3co_flush_locked() require to be changed 2090 * accordingly in future. 2091 */ 2092 static void 2093 tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits, 2094 enum fb_op_origin origin) 2095 { 2096 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled || 2097 !intel_dp->psr.active) 2098 return; 2099 2100 /* 2101 * At every frontbuffer flush flip event modified delay of delayed work, 2102 * when delayed work schedules that means display has been idle. 2103 */ 2104 if (!(frontbuffer_bits & 2105 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) 2106 return; 2107 2108 tgl_psr2_enable_dc3co(intel_dp); 2109 mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work, 2110 intel_dp->psr.dc3co_exit_delay); 2111 } 2112 2113 /** 2114 * intel_psr_flush - Flush PSR 2115 * @dev_priv: i915 device 2116 * @frontbuffer_bits: frontbuffer plane tracking bits 2117 * @origin: which operation caused the flush 2118 * 2119 * Since the hardware frontbuffer tracking has gaps we need to integrate 2120 * with the software frontbuffer tracking. This function gets called every 2121 * time frontbuffer rendering has completed and flushed out to memory. PSR 2122 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 2123 * 2124 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 2125 */ 2126 void intel_psr_flush(struct drm_i915_private *dev_priv, 2127 unsigned frontbuffer_bits, enum fb_op_origin origin) 2128 { 2129 struct intel_encoder *encoder; 2130 2131 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2132 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 2133 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2134 2135 mutex_lock(&intel_dp->psr.lock); 2136 if (!intel_dp->psr.enabled) { 2137 mutex_unlock(&intel_dp->psr.lock); 2138 continue; 2139 } 2140 2141 pipe_frontbuffer_bits &= 2142 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 2143 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; 2144 2145 /* 2146 * If the PSR is paused by an explicit intel_psr_paused() call, 2147 * we have to ensure that the PSR is not activated until 2148 * intel_psr_resume() is called. 2149 */ 2150 if (intel_dp->psr.paused) { 2151 mutex_unlock(&intel_dp->psr.lock); 2152 continue; 2153 } 2154 2155 if (origin == ORIGIN_FLIP || 2156 (origin == ORIGIN_CURSOR_UPDATE && 2157 !intel_dp->psr.psr2_sel_fetch_enabled)) { 2158 tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin); 2159 mutex_unlock(&intel_dp->psr.lock); 2160 continue; 2161 } 2162 2163 /* By definition flush = invalidate + flush */ 2164 if (pipe_frontbuffer_bits) 2165 psr_force_hw_tracking_exit(intel_dp); 2166 2167 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) 2168 schedule_work(&intel_dp->psr.work); 2169 mutex_unlock(&intel_dp->psr.lock); 2170 } 2171 } 2172 2173 /** 2174 * intel_psr_init - Init basic PSR work and mutex. 2175 * @intel_dp: Intel DP 2176 * 2177 * This function is called after the initializing connector. 2178 * (the initializing of connector treats the handling of connector capabilities) 2179 * And it initializes basic PSR stuff for each DP Encoder. 2180 */ 2181 void intel_psr_init(struct intel_dp *intel_dp) 2182 { 2183 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2184 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2185 2186 if (!HAS_PSR(dev_priv)) 2187 return; 2188 2189 /* 2190 * HSW spec explicitly says PSR is tied to port A. 2191 * BDW+ platforms have a instance of PSR registers per transcoder but 2192 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder 2193 * than eDP one. 2194 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11. 2195 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11. 2196 * But GEN12 supports a instance of PSR registers per transcoder. 2197 */ 2198 if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) { 2199 drm_dbg_kms(&dev_priv->drm, 2200 "PSR condition failed: Port not supported\n"); 2201 return; 2202 } 2203 2204 intel_dp->psr.source_support = true; 2205 2206 if (dev_priv->params.enable_psr == -1) 2207 if (!dev_priv->vbt.psr.enable) 2208 dev_priv->params.enable_psr = 0; 2209 2210 /* Set link_standby x link_off defaults */ 2211 if (DISPLAY_VER(dev_priv) < 12) 2212 /* For new platforms up to TGL let's respect VBT back again */ 2213 intel_dp->psr.link_standby = dev_priv->vbt.psr.full_link; 2214 2215 INIT_WORK(&intel_dp->psr.work, intel_psr_work); 2216 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); 2217 mutex_init(&intel_dp->psr.lock); 2218 } 2219 2220 static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 2221 u8 *status, u8 *error_status) 2222 { 2223 struct drm_dp_aux *aux = &intel_dp->aux; 2224 int ret; 2225 2226 ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status); 2227 if (ret != 1) 2228 return ret; 2229 2230 ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status); 2231 if (ret != 1) 2232 return ret; 2233 2234 *status = *status & DP_PSR_SINK_STATE_MASK; 2235 2236 return 0; 2237 } 2238 2239 static void psr_alpm_check(struct intel_dp *intel_dp) 2240 { 2241 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2242 struct drm_dp_aux *aux = &intel_dp->aux; 2243 struct intel_psr *psr = &intel_dp->psr; 2244 u8 val; 2245 int r; 2246 2247 if (!psr->psr2_enabled) 2248 return; 2249 2250 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); 2251 if (r != 1) { 2252 drm_err(&dev_priv->drm, "Error reading ALPM status\n"); 2253 return; 2254 } 2255 2256 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) { 2257 intel_psr_disable_locked(intel_dp); 2258 psr->sink_not_reliable = true; 2259 drm_dbg_kms(&dev_priv->drm, 2260 "ALPM lock timeout error, disabling PSR\n"); 2261 2262 /* Clearing error */ 2263 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); 2264 } 2265 } 2266 2267 static void psr_capability_changed_check(struct intel_dp *intel_dp) 2268 { 2269 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2270 struct intel_psr *psr = &intel_dp->psr; 2271 u8 val; 2272 int r; 2273 2274 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 2275 if (r != 1) { 2276 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n"); 2277 return; 2278 } 2279 2280 if (val & DP_PSR_CAPS_CHANGE) { 2281 intel_psr_disable_locked(intel_dp); 2282 psr->sink_not_reliable = true; 2283 drm_dbg_kms(&dev_priv->drm, 2284 "Sink PSR capability changed, disabling PSR\n"); 2285 2286 /* Clearing it */ 2287 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 2288 } 2289 } 2290 2291 void intel_psr_short_pulse(struct intel_dp *intel_dp) 2292 { 2293 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2294 struct intel_psr *psr = &intel_dp->psr; 2295 u8 status, error_status; 2296 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 2297 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 2298 DP_PSR_LINK_CRC_ERROR; 2299 2300 if (!CAN_PSR(intel_dp)) 2301 return; 2302 2303 mutex_lock(&psr->lock); 2304 2305 if (!psr->enabled) 2306 goto exit; 2307 2308 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 2309 drm_err(&dev_priv->drm, 2310 "Error reading PSR status or error status\n"); 2311 goto exit; 2312 } 2313 2314 if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) { 2315 intel_psr_disable_locked(intel_dp); 2316 psr->sink_not_reliable = true; 2317 } 2318 2319 if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status) 2320 drm_dbg_kms(&dev_priv->drm, 2321 "PSR sink internal error, disabling PSR\n"); 2322 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 2323 drm_dbg_kms(&dev_priv->drm, 2324 "PSR RFB storage error, disabling PSR\n"); 2325 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 2326 drm_dbg_kms(&dev_priv->drm, 2327 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 2328 if (error_status & DP_PSR_LINK_CRC_ERROR) 2329 drm_dbg_kms(&dev_priv->drm, 2330 "PSR Link CRC error, disabling PSR\n"); 2331 2332 if (error_status & ~errors) 2333 drm_err(&dev_priv->drm, 2334 "PSR_ERROR_STATUS unhandled errors %x\n", 2335 error_status & ~errors); 2336 /* clear status register */ 2337 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 2338 2339 psr_alpm_check(intel_dp); 2340 psr_capability_changed_check(intel_dp); 2341 2342 exit: 2343 mutex_unlock(&psr->lock); 2344 } 2345 2346 bool intel_psr_enabled(struct intel_dp *intel_dp) 2347 { 2348 bool ret; 2349 2350 if (!CAN_PSR(intel_dp)) 2351 return false; 2352 2353 mutex_lock(&intel_dp->psr.lock); 2354 ret = intel_dp->psr.enabled; 2355 mutex_unlock(&intel_dp->psr.lock); 2356 2357 return ret; 2358 } 2359