1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_damage_helper.h> 26 27 #include "i915_drv.h" 28 #include "i915_reg.h" 29 #include "intel_atomic.h" 30 #include "intel_crtc.h" 31 #include "intel_de.h" 32 #include "intel_display_types.h" 33 #include "intel_dp.h" 34 #include "intel_dp_aux.h" 35 #include "intel_hdmi.h" 36 #include "intel_psr.h" 37 #include "intel_snps_phy.h" 38 #include "skl_universal_plane.h" 39 40 /** 41 * DOC: Panel Self Refresh (PSR/SRD) 42 * 43 * Since Haswell Display controller supports Panel Self-Refresh on display 44 * panels witch have a remote frame buffer (RFB) implemented according to PSR 45 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 46 * when system is idle but display is on as it eliminates display refresh 47 * request to DDR memory completely as long as the frame buffer for that 48 * display is unchanged. 49 * 50 * Panel Self Refresh must be supported by both Hardware (source) and 51 * Panel (sink). 52 * 53 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 54 * to power down the link and memory controller. For DSI panels the same idea 55 * is called "manual mode". 56 * 57 * The implementation uses the hardware-based PSR support which automatically 58 * enters/exits self-refresh mode. The hardware takes care of sending the 59 * required DP aux message and could even retrain the link (that part isn't 60 * enabled yet though). The hardware also keeps track of any frontbuffer 61 * changes to know when to exit self-refresh mode again. Unfortunately that 62 * part doesn't work too well, hence why the i915 PSR support uses the 63 * software frontbuffer tracking to make sure it doesn't miss a screen 64 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 65 * get called by the frontbuffer tracking code. Note that because of locking 66 * issues the self-refresh re-enable code is done from a work queue, which 67 * must be correctly synchronized/cancelled when shutting down the pipe." 68 * 69 * DC3CO (DC3 clock off) 70 * 71 * On top of PSR2, GEN12 adds a intermediate power savings state that turns 72 * clock off automatically during PSR2 idle state. 73 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep 74 * entry/exit allows the HW to enter a low-power state even when page flipping 75 * periodically (for instance a 30fps video playback scenario). 76 * 77 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), 78 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 79 * frames, if no other flip occurs and the function above is executed, DC3CO is 80 * disabled and PSR2 is configured to enter deep sleep, resetting again in case 81 * of another flip. 82 * Front buffer modifications do not trigger DC3CO activation on purpose as it 83 * would bring a lot of complexity and most of the moderns systems will only 84 * use page flips. 85 */ 86 87 static bool psr_global_enabled(struct intel_dp *intel_dp) 88 { 89 struct intel_connector *connector = intel_dp->attached_connector; 90 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 91 92 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 93 case I915_PSR_DEBUG_DEFAULT: 94 if (i915->params.enable_psr == -1) 95 return connector->panel.vbt.psr.enable; 96 return i915->params.enable_psr; 97 case I915_PSR_DEBUG_DISABLE: 98 return false; 99 default: 100 return true; 101 } 102 } 103 104 static bool psr2_global_enabled(struct intel_dp *intel_dp) 105 { 106 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 107 108 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 109 case I915_PSR_DEBUG_DISABLE: 110 case I915_PSR_DEBUG_FORCE_PSR1: 111 return false; 112 default: 113 if (i915->params.enable_psr == 1) 114 return false; 115 return true; 116 } 117 } 118 119 static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp) 120 { 121 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 122 123 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_ERROR : 124 EDP_PSR_ERROR(intel_dp->psr.transcoder); 125 } 126 127 static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp) 128 { 129 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 130 131 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_POST_EXIT : 132 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder); 133 } 134 135 static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp) 136 { 137 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 138 139 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_PRE_ENTRY : 140 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder); 141 } 142 143 static u32 psr_irq_mask_get(struct intel_dp *intel_dp) 144 { 145 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 146 147 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_MASK : 148 EDP_PSR_MASK(intel_dp->psr.transcoder); 149 } 150 151 static void psr_irq_control(struct intel_dp *intel_dp) 152 { 153 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 154 i915_reg_t imr_reg; 155 u32 mask, val; 156 157 if (DISPLAY_VER(dev_priv) >= 12) 158 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 159 else 160 imr_reg = EDP_PSR_IMR; 161 162 mask = psr_irq_psr_error_bit_get(intel_dp); 163 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) 164 mask |= psr_irq_post_exit_bit_get(intel_dp) | 165 psr_irq_pre_entry_bit_get(intel_dp); 166 167 val = intel_de_read(dev_priv, imr_reg); 168 val &= ~psr_irq_mask_get(intel_dp); 169 val |= ~mask; 170 intel_de_write(dev_priv, imr_reg, val); 171 } 172 173 static void psr_event_print(struct drm_i915_private *i915, 174 u32 val, bool psr2_enabled) 175 { 176 drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val); 177 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 178 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n"); 179 if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) 180 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n"); 181 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 182 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n"); 183 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 184 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n"); 185 if (val & PSR_EVENT_GRAPHICS_RESET) 186 drm_dbg_kms(&i915->drm, "\tGraphics reset\n"); 187 if (val & PSR_EVENT_PCH_INTERRUPT) 188 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n"); 189 if (val & PSR_EVENT_MEMORY_UP) 190 drm_dbg_kms(&i915->drm, "\tMemory up\n"); 191 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 192 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n"); 193 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 194 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n"); 195 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 196 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n"); 197 if (val & PSR_EVENT_REGISTER_UPDATE) 198 drm_dbg_kms(&i915->drm, "\tRegister updated\n"); 199 if (val & PSR_EVENT_HDCP_ENABLE) 200 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n"); 201 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 202 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n"); 203 if (val & PSR_EVENT_VBI_ENABLE) 204 drm_dbg_kms(&i915->drm, "\tVBI enabled\n"); 205 if (val & PSR_EVENT_LPSP_MODE_EXIT) 206 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n"); 207 if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) 208 drm_dbg_kms(&i915->drm, "\tPSR disabled\n"); 209 } 210 211 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) 212 { 213 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 214 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 215 ktime_t time_ns = ktime_get(); 216 i915_reg_t imr_reg; 217 218 if (DISPLAY_VER(dev_priv) >= 12) 219 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 220 else 221 imr_reg = EDP_PSR_IMR; 222 223 if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) { 224 intel_dp->psr.last_entry_attempt = time_ns; 225 drm_dbg_kms(&dev_priv->drm, 226 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 227 transcoder_name(cpu_transcoder)); 228 } 229 230 if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) { 231 intel_dp->psr.last_exit = time_ns; 232 drm_dbg_kms(&dev_priv->drm, 233 "[transcoder %s] PSR exit completed\n", 234 transcoder_name(cpu_transcoder)); 235 236 if (DISPLAY_VER(dev_priv) >= 9) { 237 u32 val = intel_de_read(dev_priv, 238 PSR_EVENT(cpu_transcoder)); 239 bool psr2_enabled = intel_dp->psr.psr2_enabled; 240 241 intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder), 242 val); 243 psr_event_print(dev_priv, val, psr2_enabled); 244 } 245 } 246 247 if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) { 248 u32 val; 249 250 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", 251 transcoder_name(cpu_transcoder)); 252 253 intel_dp->psr.irq_aux_error = true; 254 255 /* 256 * If this interruption is not masked it will keep 257 * interrupting so fast that it prevents the scheduled 258 * work to run. 259 * Also after a PSR error, we don't want to arm PSR 260 * again so we don't care about unmask the interruption 261 * or unset irq_aux_error. 262 */ 263 val = intel_de_read(dev_priv, imr_reg); 264 val |= psr_irq_psr_error_bit_get(intel_dp); 265 intel_de_write(dev_priv, imr_reg, val); 266 267 schedule_work(&intel_dp->psr.work); 268 } 269 } 270 271 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) 272 { 273 u8 alpm_caps = 0; 274 275 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, 276 &alpm_caps) != 1) 277 return false; 278 return alpm_caps & DP_ALPM_CAP; 279 } 280 281 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 282 { 283 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 284 u8 val = 8; /* assume the worst if we can't read the value */ 285 286 if (drm_dp_dpcd_readb(&intel_dp->aux, 287 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 288 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 289 else 290 drm_dbg_kms(&i915->drm, 291 "Unable to get sink synchronization latency, assuming 8 frames\n"); 292 return val; 293 } 294 295 static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) 296 { 297 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 298 ssize_t r; 299 u16 w; 300 u8 y; 301 302 /* If sink don't have specific granularity requirements set legacy ones */ 303 if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { 304 /* As PSR2 HW sends full lines, we do not care about x granularity */ 305 w = 4; 306 y = 4; 307 goto exit; 308 } 309 310 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2); 311 if (r != 2) 312 drm_dbg_kms(&i915->drm, 313 "Unable to read DP_PSR2_SU_X_GRANULARITY\n"); 314 /* 315 * Spec says that if the value read is 0 the default granularity should 316 * be used instead. 317 */ 318 if (r != 2 || w == 0) 319 w = 4; 320 321 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); 322 if (r != 1) { 323 drm_dbg_kms(&i915->drm, 324 "Unable to read DP_PSR2_SU_Y_GRANULARITY\n"); 325 y = 4; 326 } 327 if (y == 0) 328 y = 1; 329 330 exit: 331 intel_dp->psr.su_w_granularity = w; 332 intel_dp->psr.su_y_granularity = y; 333 } 334 335 void intel_psr_init_dpcd(struct intel_dp *intel_dp) 336 { 337 struct drm_i915_private *dev_priv = 338 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 339 340 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, 341 sizeof(intel_dp->psr_dpcd)); 342 343 if (!intel_dp->psr_dpcd[0]) 344 return; 345 drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n", 346 intel_dp->psr_dpcd[0]); 347 348 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { 349 drm_dbg_kms(&dev_priv->drm, 350 "PSR support not currently available for this panel\n"); 351 return; 352 } 353 354 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 355 drm_dbg_kms(&dev_priv->drm, 356 "Panel lacks power state control, PSR cannot be enabled\n"); 357 return; 358 } 359 360 intel_dp->psr.sink_support = true; 361 intel_dp->psr.sink_sync_latency = 362 intel_dp_get_sink_sync_latency(intel_dp); 363 364 if (DISPLAY_VER(dev_priv) >= 9 && 365 (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { 366 bool y_req = intel_dp->psr_dpcd[1] & 367 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 368 bool alpm = intel_dp_get_alpm_status(intel_dp); 369 370 /* 371 * All panels that supports PSR version 03h (PSR2 + 372 * Y-coordinate) can handle Y-coordinates in VSC but we are 373 * only sure that it is going to be used when required by the 374 * panel. This way panel is capable to do selective update 375 * without a aux frame sync. 376 * 377 * To support PSR version 02h and PSR version 03h without 378 * Y-coordinate requirement panels we would need to enable 379 * GTC first. 380 */ 381 intel_dp->psr.sink_psr2_support = y_req && alpm; 382 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n", 383 intel_dp->psr.sink_psr2_support ? "" : "not "); 384 385 if (intel_dp->psr.sink_psr2_support) { 386 intel_dp->psr.colorimetry_support = 387 intel_dp_get_colorimetry_status(intel_dp); 388 intel_dp_get_su_granularity(intel_dp); 389 } 390 } 391 } 392 393 static void intel_psr_enable_sink(struct intel_dp *intel_dp) 394 { 395 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 396 u8 dpcd_val = DP_PSR_ENABLE; 397 398 /* Enable ALPM at sink for psr2 */ 399 if (intel_dp->psr.psr2_enabled) { 400 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 401 DP_ALPM_ENABLE | 402 DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); 403 404 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 405 } else { 406 if (intel_dp->psr.link_standby) 407 dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; 408 409 if (DISPLAY_VER(dev_priv) >= 8) 410 dpcd_val |= DP_PSR_CRC_VERIFICATION; 411 } 412 413 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 414 dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; 415 416 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); 417 418 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 419 } 420 421 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 422 { 423 struct intel_connector *connector = intel_dp->attached_connector; 424 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 425 u32 val = 0; 426 427 if (DISPLAY_VER(dev_priv) >= 11) 428 val |= EDP_PSR_TP4_TIME_0US; 429 430 if (dev_priv->params.psr_safest_params) { 431 val |= EDP_PSR_TP1_TIME_2500us; 432 val |= EDP_PSR_TP2_TP3_TIME_2500us; 433 goto check_tp3_sel; 434 } 435 436 if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0) 437 val |= EDP_PSR_TP1_TIME_0us; 438 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100) 439 val |= EDP_PSR_TP1_TIME_100us; 440 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500) 441 val |= EDP_PSR_TP1_TIME_500us; 442 else 443 val |= EDP_PSR_TP1_TIME_2500us; 444 445 if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) 446 val |= EDP_PSR_TP2_TP3_TIME_0us; 447 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100) 448 val |= EDP_PSR_TP2_TP3_TIME_100us; 449 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500) 450 val |= EDP_PSR_TP2_TP3_TIME_500us; 451 else 452 val |= EDP_PSR_TP2_TP3_TIME_2500us; 453 454 check_tp3_sel: 455 if (intel_dp_source_supports_tps3(dev_priv) && 456 drm_dp_tps3_supported(intel_dp->dpcd)) 457 val |= EDP_PSR_TP1_TP3_SEL; 458 else 459 val |= EDP_PSR_TP1_TP2_SEL; 460 461 return val; 462 } 463 464 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 465 { 466 struct intel_connector *connector = intel_dp->attached_connector; 467 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 468 int idle_frames; 469 470 /* Let's use 6 as the minimum to cover all known cases including the 471 * off-by-one issue that HW has in some cases. 472 */ 473 idle_frames = max(6, connector->panel.vbt.psr.idle_frames); 474 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1); 475 476 if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf)) 477 idle_frames = 0xf; 478 479 return idle_frames; 480 } 481 482 static void hsw_activate_psr1(struct intel_dp *intel_dp) 483 { 484 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 485 u32 max_sleep_time = 0x1f; 486 u32 val = EDP_PSR_ENABLE; 487 488 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT; 489 490 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; 491 if (IS_HASWELL(dev_priv)) 492 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 493 494 if (intel_dp->psr.link_standby) 495 val |= EDP_PSR_LINK_STANDBY; 496 497 val |= intel_psr1_get_tp_time(intel_dp); 498 499 if (DISPLAY_VER(dev_priv) >= 8) 500 val |= EDP_PSR_CRC_ENABLE; 501 502 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) & 503 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK); 504 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val); 505 } 506 507 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 508 { 509 struct intel_connector *connector = intel_dp->attached_connector; 510 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 511 u32 val = 0; 512 513 if (dev_priv->params.psr_safest_params) 514 return EDP_PSR2_TP2_TIME_2500us; 515 516 if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 517 connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 518 val |= EDP_PSR2_TP2_TIME_50us; 519 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 520 val |= EDP_PSR2_TP2_TIME_100us; 521 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 522 val |= EDP_PSR2_TP2_TIME_500us; 523 else 524 val |= EDP_PSR2_TP2_TIME_2500us; 525 526 return val; 527 } 528 529 static void hsw_activate_psr2(struct intel_dp *intel_dp) 530 { 531 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 532 u32 val = EDP_PSR2_ENABLE; 533 534 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT; 535 536 if (DISPLAY_VER(dev_priv) <= 13 && !IS_ALDERLAKE_P(dev_priv)) 537 val |= EDP_SU_TRACK_ENABLE; 538 539 if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12) 540 val |= EDP_Y_COORDINATE_ENABLE; 541 542 val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2)); 543 val |= intel_psr2_get_tp_time(intel_dp); 544 545 /* Wa_22012278275:adl-p */ 546 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { 547 static const u8 map[] = { 548 2, /* 5 lines */ 549 1, /* 6 lines */ 550 0, /* 7 lines */ 551 3, /* 8 lines */ 552 6, /* 9 lines */ 553 5, /* 10 lines */ 554 4, /* 11 lines */ 555 7, /* 12 lines */ 556 }; 557 /* 558 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see 559 * comments bellow for more information 560 */ 561 u32 tmp, lines = 7; 562 563 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 564 565 tmp = map[lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; 566 tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT; 567 val |= tmp; 568 569 tmp = map[lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; 570 tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT; 571 val |= tmp; 572 } else if (DISPLAY_VER(dev_priv) >= 12) { 573 /* 574 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default 575 * values from BSpec. In order to setting an optimal power 576 * consumption, lower than 4k resolution mode needs to decrease 577 * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution 578 * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE. 579 */ 580 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 581 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7); 582 val |= TGL_EDP_PSR2_FAST_WAKE(7); 583 } else if (DISPLAY_VER(dev_priv) >= 9) { 584 val |= EDP_PSR2_IO_BUFFER_WAKE(7); 585 val |= EDP_PSR2_FAST_WAKE(7); 586 } 587 588 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 589 val |= EDP_PSR2_SU_SDP_SCANLINE; 590 591 if (intel_dp->psr.psr2_sel_fetch_enabled) { 592 u32 tmp; 593 594 /* Wa_1408330847 */ 595 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 596 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 597 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 598 DIS_RAM_BYPASS_PSR2_MAN_TRACK); 599 600 tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); 601 drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); 602 } else if (HAS_PSR2_SEL_FETCH(dev_priv)) { 603 intel_de_write(dev_priv, 604 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0); 605 } 606 607 /* 608 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 609 * recommending keep this bit unset while PSR2 is enabled. 610 */ 611 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0); 612 613 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 614 } 615 616 static bool 617 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) 618 { 619 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 620 return trans == TRANSCODER_A || trans == TRANSCODER_B; 621 else if (DISPLAY_VER(dev_priv) >= 12) 622 return trans == TRANSCODER_A; 623 else 624 return trans == TRANSCODER_EDP; 625 } 626 627 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate) 628 { 629 if (!cstate || !cstate->hw.active) 630 return 0; 631 632 return DIV_ROUND_UP(1000 * 1000, 633 drm_mode_vrefresh(&cstate->hw.adjusted_mode)); 634 } 635 636 static void psr2_program_idle_frames(struct intel_dp *intel_dp, 637 u32 idle_frames) 638 { 639 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 640 u32 val; 641 642 idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; 643 val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder)); 644 val &= ~EDP_PSR2_IDLE_FRAME_MASK; 645 val |= idle_frames; 646 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 647 } 648 649 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) 650 { 651 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 652 653 psr2_program_idle_frames(intel_dp, 0); 654 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO); 655 } 656 657 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp) 658 { 659 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 660 661 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 662 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp)); 663 } 664 665 static void tgl_dc3co_disable_work(struct work_struct *work) 666 { 667 struct intel_dp *intel_dp = 668 container_of(work, typeof(*intel_dp), psr.dc3co_work.work); 669 670 mutex_lock(&intel_dp->psr.lock); 671 /* If delayed work is pending, it is not idle */ 672 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) 673 goto unlock; 674 675 tgl_psr2_disable_dc3co(intel_dp); 676 unlock: 677 mutex_unlock(&intel_dp->psr.lock); 678 } 679 680 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) 681 { 682 if (!intel_dp->psr.dc3co_exitline) 683 return; 684 685 cancel_delayed_work(&intel_dp->psr.dc3co_work); 686 /* Before PSR2 exit disallow dc3co*/ 687 tgl_psr2_disable_dc3co(intel_dp); 688 } 689 690 static bool 691 dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp, 692 struct intel_crtc_state *crtc_state) 693 { 694 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 695 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 696 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 697 enum port port = dig_port->base.port; 698 699 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 700 return pipe <= PIPE_B && port <= PORT_B; 701 else 702 return pipe == PIPE_A && port == PORT_A; 703 } 704 705 static void 706 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 707 struct intel_crtc_state *crtc_state) 708 { 709 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; 710 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 711 u32 exit_scanlines; 712 713 /* 714 * FIXME: Due to the changed sequence of activating/deactivating DC3CO, 715 * disable DC3CO until the changed dc3co activating/deactivating sequence 716 * is applied. B.Specs:49196 717 */ 718 return; 719 720 /* 721 * DMC's DC3CO exit mechanism has an issue with Selective Fecth 722 * TODO: when the issue is addressed, this restriction should be removed. 723 */ 724 if (crtc_state->enable_psr2_sel_fetch) 725 return; 726 727 if (!(dev_priv->display.dmc.allowed_dc_mask & DC_STATE_EN_DC3CO)) 728 return; 729 730 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) 731 return; 732 733 /* Wa_16011303918:adl-p */ 734 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 735 return; 736 737 /* 738 * DC3CO Exit time 200us B.Spec 49196 739 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 740 */ 741 exit_scanlines = 742 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; 743 744 if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay)) 745 return; 746 747 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; 748 } 749 750 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, 751 struct intel_crtc_state *crtc_state) 752 { 753 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 754 755 if (!dev_priv->params.enable_psr2_sel_fetch && 756 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 757 drm_dbg_kms(&dev_priv->drm, 758 "PSR2 sel fetch not enabled, disabled by parameter\n"); 759 return false; 760 } 761 762 if (crtc_state->uapi.async_flip) { 763 drm_dbg_kms(&dev_priv->drm, 764 "PSR2 sel fetch not enabled, async flip enabled\n"); 765 return false; 766 } 767 768 /* Wa_14010254185 Wa_14010103792 */ 769 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { 770 drm_dbg_kms(&dev_priv->drm, 771 "PSR2 sel fetch not enabled, missing the implementation of WAs\n"); 772 return false; 773 } 774 775 return crtc_state->enable_psr2_sel_fetch = true; 776 } 777 778 static bool psr2_granularity_check(struct intel_dp *intel_dp, 779 struct intel_crtc_state *crtc_state) 780 { 781 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 782 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 783 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 784 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 785 u16 y_granularity = 0; 786 787 /* PSR2 HW only send full lines so we only need to validate the width */ 788 if (crtc_hdisplay % intel_dp->psr.su_w_granularity) 789 return false; 790 791 if (crtc_vdisplay % intel_dp->psr.su_y_granularity) 792 return false; 793 794 /* HW tracking is only aligned to 4 lines */ 795 if (!crtc_state->enable_psr2_sel_fetch) 796 return intel_dp->psr.su_y_granularity == 4; 797 798 /* 799 * adl_p and mtl platforms have 1 line granularity. 800 * For other platforms with SW tracking we can adjust the y coordinates 801 * to match sink requirement if multiple of 4. 802 */ 803 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 804 y_granularity = intel_dp->psr.su_y_granularity; 805 else if (intel_dp->psr.su_y_granularity <= 2) 806 y_granularity = 4; 807 else if ((intel_dp->psr.su_y_granularity % 4) == 0) 808 y_granularity = intel_dp->psr.su_y_granularity; 809 810 if (y_granularity == 0 || crtc_vdisplay % y_granularity) 811 return false; 812 813 if (crtc_state->dsc.compression_enable && 814 vdsc_cfg->slice_height % y_granularity) 815 return false; 816 817 crtc_state->su_y_granularity = y_granularity; 818 return true; 819 } 820 821 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp, 822 struct intel_crtc_state *crtc_state) 823 { 824 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; 825 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 826 u32 hblank_total, hblank_ns, req_ns; 827 828 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; 829 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); 830 831 /* From spec: ((60 / number of lanes) + 11) * 1000 / symbol clock frequency MHz */ 832 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); 833 834 if ((hblank_ns - req_ns) > 100) 835 return true; 836 837 /* Not supported <13 / Wa_22012279113:adl-p */ 838 if (DISPLAY_VER(dev_priv) <= 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b) 839 return false; 840 841 crtc_state->req_psr2_sdp_prior_scanline = true; 842 return true; 843 } 844 845 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 846 struct intel_crtc_state *crtc_state) 847 { 848 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 849 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 850 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 851 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 852 853 if (!intel_dp->psr.sink_psr2_support) 854 return false; 855 856 /* JSL and EHL only supports eDP 1.3 */ 857 if (IS_JSL_EHL(dev_priv)) { 858 drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n"); 859 return false; 860 } 861 862 /* Wa_16011181250 */ 863 if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) || 864 IS_DG2(dev_priv)) { 865 drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n"); 866 return false; 867 } 868 869 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 870 drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n"); 871 return false; 872 } 873 874 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { 875 drm_dbg_kms(&dev_priv->drm, 876 "PSR2 not supported in transcoder %s\n", 877 transcoder_name(crtc_state->cpu_transcoder)); 878 return false; 879 } 880 881 if (!psr2_global_enabled(intel_dp)) { 882 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); 883 return false; 884 } 885 886 /* 887 * DSC and PSR2 cannot be enabled simultaneously. If a requested 888 * resolution requires DSC to be enabled, priority is given to DSC 889 * over PSR2. 890 */ 891 if (crtc_state->dsc.compression_enable && 892 (DISPLAY_VER(dev_priv) <= 13 && !IS_ALDERLAKE_P(dev_priv))) { 893 drm_dbg_kms(&dev_priv->drm, 894 "PSR2 cannot be enabled since DSC is enabled\n"); 895 return false; 896 } 897 898 if (crtc_state->crc_enabled) { 899 drm_dbg_kms(&dev_priv->drm, 900 "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); 901 return false; 902 } 903 904 if (DISPLAY_VER(dev_priv) >= 12) { 905 psr_max_h = 5120; 906 psr_max_v = 3200; 907 max_bpp = 30; 908 } else if (DISPLAY_VER(dev_priv) >= 10) { 909 psr_max_h = 4096; 910 psr_max_v = 2304; 911 max_bpp = 24; 912 } else if (DISPLAY_VER(dev_priv) == 9) { 913 psr_max_h = 3640; 914 psr_max_v = 2304; 915 max_bpp = 24; 916 } 917 918 if (crtc_state->pipe_bpp > max_bpp) { 919 drm_dbg_kms(&dev_priv->drm, 920 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 921 crtc_state->pipe_bpp, max_bpp); 922 return false; 923 } 924 925 /* Wa_16011303918:adl-p */ 926 if (crtc_state->vrr.enable && 927 IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 928 drm_dbg_kms(&dev_priv->drm, 929 "PSR2 not enabled, not compatible with HW stepping + VRR\n"); 930 return false; 931 } 932 933 if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) { 934 drm_dbg_kms(&dev_priv->drm, 935 "PSR2 not enabled, PSR2 SDP indication do not fit in hblank\n"); 936 return false; 937 } 938 939 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 940 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && 941 !HAS_PSR_HW_TRACKING(dev_priv)) { 942 drm_dbg_kms(&dev_priv->drm, 943 "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); 944 return false; 945 } 946 } 947 948 /* Wa_2209313811 */ 949 if (!crtc_state->enable_psr2_sel_fetch && 950 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { 951 drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n"); 952 goto unsupported; 953 } 954 955 if (!psr2_granularity_check(intel_dp, crtc_state)) { 956 drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n"); 957 goto unsupported; 958 } 959 960 if (!crtc_state->enable_psr2_sel_fetch && 961 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { 962 drm_dbg_kms(&dev_priv->drm, 963 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 964 crtc_hdisplay, crtc_vdisplay, 965 psr_max_h, psr_max_v); 966 goto unsupported; 967 } 968 969 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); 970 return true; 971 972 unsupported: 973 crtc_state->enable_psr2_sel_fetch = false; 974 return false; 975 } 976 977 void intel_psr_compute_config(struct intel_dp *intel_dp, 978 struct intel_crtc_state *crtc_state, 979 struct drm_connector_state *conn_state) 980 { 981 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 982 const struct drm_display_mode *adjusted_mode = 983 &crtc_state->hw.adjusted_mode; 984 int psr_setup_time; 985 986 /* 987 * Current PSR panels don't work reliably with VRR enabled 988 * So if VRR is enabled, do not enable PSR. 989 */ 990 if (crtc_state->vrr.enable) 991 return; 992 993 if (!CAN_PSR(intel_dp)) 994 return; 995 996 if (!psr_global_enabled(intel_dp)) { 997 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); 998 return; 999 } 1000 1001 if (intel_dp->psr.sink_not_reliable) { 1002 drm_dbg_kms(&dev_priv->drm, 1003 "PSR sink implementation is not reliable\n"); 1004 return; 1005 } 1006 1007 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 1008 drm_dbg_kms(&dev_priv->drm, 1009 "PSR condition failed: Interlaced mode enabled\n"); 1010 return; 1011 } 1012 1013 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); 1014 if (psr_setup_time < 0) { 1015 drm_dbg_kms(&dev_priv->drm, 1016 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 1017 intel_dp->psr_dpcd[1]); 1018 return; 1019 } 1020 1021 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 1022 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 1023 drm_dbg_kms(&dev_priv->drm, 1024 "PSR condition failed: PSR setup time (%d us) too long\n", 1025 psr_setup_time); 1026 return; 1027 } 1028 1029 crtc_state->has_psr = true; 1030 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); 1031 1032 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1033 intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, 1034 &crtc_state->psr_vsc); 1035 } 1036 1037 void intel_psr_get_config(struct intel_encoder *encoder, 1038 struct intel_crtc_state *pipe_config) 1039 { 1040 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1041 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1042 struct intel_dp *intel_dp; 1043 u32 val; 1044 1045 if (!dig_port) 1046 return; 1047 1048 intel_dp = &dig_port->dp; 1049 if (!CAN_PSR(intel_dp)) 1050 return; 1051 1052 mutex_lock(&intel_dp->psr.lock); 1053 if (!intel_dp->psr.enabled) 1054 goto unlock; 1055 1056 /* 1057 * Not possible to read EDP_PSR/PSR2_CTL registers as it is 1058 * enabled/disabled because of frontbuffer tracking and others. 1059 */ 1060 pipe_config->has_psr = true; 1061 pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; 1062 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1063 1064 if (!intel_dp->psr.psr2_enabled) 1065 goto unlock; 1066 1067 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 1068 val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); 1069 if (val & PSR2_MAN_TRK_CTL_ENABLE) 1070 pipe_config->enable_psr2_sel_fetch = true; 1071 } 1072 1073 if (DISPLAY_VER(dev_priv) >= 12) { 1074 val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder)); 1075 val &= EXITLINE_MASK; 1076 pipe_config->dc3co_exitline = val; 1077 } 1078 unlock: 1079 mutex_unlock(&intel_dp->psr.lock); 1080 } 1081 1082 static void intel_psr_activate(struct intel_dp *intel_dp) 1083 { 1084 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1085 enum transcoder transcoder = intel_dp->psr.transcoder; 1086 1087 if (transcoder_has_psr2(dev_priv, transcoder)) 1088 drm_WARN_ON(&dev_priv->drm, 1089 intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE); 1090 1091 drm_WARN_ON(&dev_priv->drm, 1092 intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE); 1093 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active); 1094 lockdep_assert_held(&intel_dp->psr.lock); 1095 1096 /* psr1 and psr2 are mutually exclusive.*/ 1097 if (intel_dp->psr.psr2_enabled) 1098 hsw_activate_psr2(intel_dp); 1099 else 1100 hsw_activate_psr1(intel_dp); 1101 1102 intel_dp->psr.active = true; 1103 } 1104 1105 static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp) 1106 { 1107 switch (intel_dp->psr.pipe) { 1108 case PIPE_A: 1109 return LATENCY_REPORTING_REMOVED_PIPE_A; 1110 case PIPE_B: 1111 return LATENCY_REPORTING_REMOVED_PIPE_B; 1112 case PIPE_C: 1113 return LATENCY_REPORTING_REMOVED_PIPE_C; 1114 case PIPE_D: 1115 return LATENCY_REPORTING_REMOVED_PIPE_D; 1116 default: 1117 MISSING_CASE(intel_dp->psr.pipe); 1118 return 0; 1119 } 1120 } 1121 1122 static void intel_psr_enable_source(struct intel_dp *intel_dp, 1123 const struct intel_crtc_state *crtc_state) 1124 { 1125 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1126 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1127 u32 mask; 1128 1129 /* 1130 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 1131 * mask LPSP to avoid dependency on other drivers that might block 1132 * runtime_pm besides preventing other hw tracking issues now we 1133 * can rely on frontbuffer tracking. 1134 */ 1135 mask = EDP_PSR_DEBUG_MASK_MEMUP | 1136 EDP_PSR_DEBUG_MASK_HPD | 1137 EDP_PSR_DEBUG_MASK_LPSP | 1138 EDP_PSR_DEBUG_MASK_MAX_SLEEP; 1139 1140 if (DISPLAY_VER(dev_priv) < 11) 1141 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 1142 1143 intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder), 1144 mask); 1145 1146 psr_irq_control(intel_dp); 1147 1148 if (intel_dp->psr.dc3co_exitline) { 1149 u32 val; 1150 1151 /* 1152 * TODO: if future platforms supports DC3CO in more than one 1153 * transcoder, EXITLINE will need to be unset when disabling PSR 1154 */ 1155 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder)); 1156 val &= ~EXITLINE_MASK; 1157 val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT; 1158 val |= EXITLINE_ENABLE; 1159 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); 1160 } 1161 1162 if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv)) 1163 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, 1164 intel_dp->psr.psr2_sel_fetch_enabled ? 1165 IGNORE_PSR2_HW_TRACKING : 0); 1166 1167 /* 1168 * Wa_16013835468 1169 * Wa_14015648006 1170 */ 1171 if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) || 1172 IS_DISPLAY_VER(dev_priv, 12, 13)) { 1173 u16 vtotal, vblank; 1174 1175 vtotal = crtc_state->uapi.adjusted_mode.crtc_vtotal - 1176 crtc_state->uapi.adjusted_mode.crtc_vdisplay; 1177 vblank = crtc_state->uapi.adjusted_mode.crtc_vblank_end - 1178 crtc_state->uapi.adjusted_mode.crtc_vblank_start; 1179 if (vblank > vtotal) 1180 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, 1181 wa_16013835468_bit_get(intel_dp)); 1182 } 1183 1184 if (intel_dp->psr.psr2_enabled) { 1185 if (DISPLAY_VER(dev_priv) == 9) 1186 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, 1187 PSR2_VSC_ENABLE_PROG_HEADER | 1188 PSR2_ADD_VERTICAL_LINE_COUNT); 1189 1190 /* 1191 * Wa_16014451276:adlp,mtl[a0,b0] 1192 * All supported adlp panels have 1-based X granularity, this may 1193 * cause issues if non-supported panels are used. 1194 */ 1195 if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1196 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 0, 1197 ADLP_1_BASED_X_GRANULARITY); 1198 else if (IS_ALDERLAKE_P(dev_priv)) 1199 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, 1200 ADLP_1_BASED_X_GRANULARITY); 1201 1202 /* Wa_16011168373:adl-p */ 1203 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1204 intel_de_rmw(dev_priv, 1205 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), 1206 TRANS_SET_CONTEXT_LATENCY_MASK, 1207 TRANS_SET_CONTEXT_LATENCY_VALUE(1)); 1208 1209 /* Wa_16012604467:adlp,mtl[a0,b0] */ 1210 if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1211 intel_de_rmw(dev_priv, 1212 MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0, 1213 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS); 1214 else if (IS_ALDERLAKE_P(dev_priv)) 1215 intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0, 1216 CLKGATE_DIS_MISC_DMASC_GATING_DIS); 1217 } 1218 } 1219 1220 static bool psr_interrupt_error_check(struct intel_dp *intel_dp) 1221 { 1222 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1223 u32 val; 1224 1225 /* 1226 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 1227 * will still keep the error set even after the reset done in the 1228 * irq_preinstall and irq_uninstall hooks. 1229 * And enabling in this situation cause the screen to freeze in the 1230 * first time that PSR HW tries to activate so lets keep PSR disabled 1231 * to avoid any rendering problems. 1232 */ 1233 if (DISPLAY_VER(dev_priv) >= 12) 1234 val = intel_de_read(dev_priv, 1235 TRANS_PSR_IIR(intel_dp->psr.transcoder)); 1236 else 1237 val = intel_de_read(dev_priv, EDP_PSR_IIR); 1238 val &= psr_irq_psr_error_bit_get(intel_dp); 1239 if (val) { 1240 intel_dp->psr.sink_not_reliable = true; 1241 drm_dbg_kms(&dev_priv->drm, 1242 "PSR interruption error set, not enabling PSR\n"); 1243 return false; 1244 } 1245 1246 return true; 1247 } 1248 1249 static void intel_psr_enable_locked(struct intel_dp *intel_dp, 1250 const struct intel_crtc_state *crtc_state) 1251 { 1252 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1253 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1254 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 1255 struct intel_encoder *encoder = &dig_port->base; 1256 u32 val; 1257 1258 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); 1259 1260 intel_dp->psr.psr2_enabled = crtc_state->has_psr2; 1261 intel_dp->psr.busy_frontbuffer_bits = 0; 1262 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1263 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; 1264 /* DC5/DC6 requires at least 6 idle frames */ 1265 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 1266 intel_dp->psr.dc3co_exit_delay = val; 1267 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; 1268 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; 1269 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 1270 intel_dp->psr.req_psr2_sdp_prior_scanline = 1271 crtc_state->req_psr2_sdp_prior_scanline; 1272 1273 if (!psr_interrupt_error_check(intel_dp)) 1274 return; 1275 1276 drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", 1277 intel_dp->psr.psr2_enabled ? "2" : "1"); 1278 intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc); 1279 intel_snps_phy_update_psr_power_state(dev_priv, phy, true); 1280 intel_psr_enable_sink(intel_dp); 1281 intel_psr_enable_source(intel_dp, crtc_state); 1282 intel_dp->psr.enabled = true; 1283 intel_dp->psr.paused = false; 1284 1285 intel_psr_activate(intel_dp); 1286 } 1287 1288 static void intel_psr_exit(struct intel_dp *intel_dp) 1289 { 1290 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1291 u32 val; 1292 1293 if (!intel_dp->psr.active) { 1294 if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) { 1295 val = intel_de_read(dev_priv, 1296 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1297 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE); 1298 } 1299 1300 val = intel_de_read(dev_priv, 1301 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1302 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE); 1303 1304 return; 1305 } 1306 1307 if (intel_dp->psr.psr2_enabled) { 1308 tgl_disallow_dc3co_on_psr2_exit(intel_dp); 1309 val = intel_de_read(dev_priv, 1310 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1311 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE)); 1312 val &= ~EDP_PSR2_ENABLE; 1313 intel_de_write(dev_priv, 1314 EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 1315 } else { 1316 val = intel_de_read(dev_priv, 1317 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1318 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE)); 1319 val &= ~EDP_PSR_ENABLE; 1320 intel_de_write(dev_priv, 1321 EDP_PSR_CTL(intel_dp->psr.transcoder), val); 1322 } 1323 intel_dp->psr.active = false; 1324 } 1325 1326 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) 1327 { 1328 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1329 i915_reg_t psr_status; 1330 u32 psr_status_mask; 1331 1332 if (intel_dp->psr.psr2_enabled) { 1333 psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 1334 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 1335 } else { 1336 psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder); 1337 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 1338 } 1339 1340 /* Wait till PSR is idle */ 1341 if (intel_de_wait_for_clear(dev_priv, psr_status, 1342 psr_status_mask, 2000)) 1343 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n"); 1344 } 1345 1346 static void intel_psr_disable_locked(struct intel_dp *intel_dp) 1347 { 1348 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1349 enum phy phy = intel_port_to_phy(dev_priv, 1350 dp_to_dig_port(intel_dp)->base.port); 1351 1352 lockdep_assert_held(&intel_dp->psr.lock); 1353 1354 if (!intel_dp->psr.enabled) 1355 return; 1356 1357 drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", 1358 intel_dp->psr.psr2_enabled ? "2" : "1"); 1359 1360 intel_psr_exit(intel_dp); 1361 intel_psr_wait_exit_locked(intel_dp); 1362 1363 /* Wa_1408330847 */ 1364 if (intel_dp->psr.psr2_sel_fetch_enabled && 1365 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1366 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1367 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0); 1368 1369 /* 1370 * Wa_16013835468 1371 * Wa_14015648006 1372 */ 1373 if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) || 1374 IS_DISPLAY_VER(dev_priv, 12, 13)) 1375 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 1376 wa_16013835468_bit_get(intel_dp), 0); 1377 1378 if (intel_dp->psr.psr2_enabled) { 1379 /* Wa_16011168373:adl-p */ 1380 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1381 intel_de_rmw(dev_priv, 1382 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), 1383 TRANS_SET_CONTEXT_LATENCY_MASK, 0); 1384 1385 /* Wa_16012604467:adlp,mtl[a0,b0] */ 1386 if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1387 intel_de_rmw(dev_priv, 1388 MTL_CLKGATE_DIS_TRANS(intel_dp->psr.transcoder), 1389 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); 1390 else if (IS_ALDERLAKE_P(dev_priv)) 1391 intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 1392 CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0); 1393 } 1394 1395 intel_snps_phy_update_psr_power_state(dev_priv, phy, false); 1396 1397 /* Disable PSR on Sink */ 1398 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 1399 1400 if (intel_dp->psr.psr2_enabled) 1401 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); 1402 1403 intel_dp->psr.enabled = false; 1404 intel_dp->psr.psr2_enabled = false; 1405 intel_dp->psr.psr2_sel_fetch_enabled = false; 1406 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 1407 } 1408 1409 /** 1410 * intel_psr_disable - Disable PSR 1411 * @intel_dp: Intel DP 1412 * @old_crtc_state: old CRTC state 1413 * 1414 * This function needs to be called before disabling pipe. 1415 */ 1416 void intel_psr_disable(struct intel_dp *intel_dp, 1417 const struct intel_crtc_state *old_crtc_state) 1418 { 1419 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1420 1421 if (!old_crtc_state->has_psr) 1422 return; 1423 1424 if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp))) 1425 return; 1426 1427 mutex_lock(&intel_dp->psr.lock); 1428 1429 intel_psr_disable_locked(intel_dp); 1430 1431 mutex_unlock(&intel_dp->psr.lock); 1432 cancel_work_sync(&intel_dp->psr.work); 1433 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); 1434 } 1435 1436 /** 1437 * intel_psr_pause - Pause PSR 1438 * @intel_dp: Intel DP 1439 * 1440 * This function need to be called after enabling psr. 1441 */ 1442 void intel_psr_pause(struct intel_dp *intel_dp) 1443 { 1444 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1445 struct intel_psr *psr = &intel_dp->psr; 1446 1447 if (!CAN_PSR(intel_dp)) 1448 return; 1449 1450 mutex_lock(&psr->lock); 1451 1452 if (!psr->enabled) { 1453 mutex_unlock(&psr->lock); 1454 return; 1455 } 1456 1457 /* If we ever hit this, we will need to add refcount to pause/resume */ 1458 drm_WARN_ON(&dev_priv->drm, psr->paused); 1459 1460 intel_psr_exit(intel_dp); 1461 intel_psr_wait_exit_locked(intel_dp); 1462 psr->paused = true; 1463 1464 mutex_unlock(&psr->lock); 1465 1466 cancel_work_sync(&psr->work); 1467 cancel_delayed_work_sync(&psr->dc3co_work); 1468 } 1469 1470 /** 1471 * intel_psr_resume - Resume PSR 1472 * @intel_dp: Intel DP 1473 * 1474 * This function need to be called after pausing psr. 1475 */ 1476 void intel_psr_resume(struct intel_dp *intel_dp) 1477 { 1478 struct intel_psr *psr = &intel_dp->psr; 1479 1480 if (!CAN_PSR(intel_dp)) 1481 return; 1482 1483 mutex_lock(&psr->lock); 1484 1485 if (!psr->paused) 1486 goto unlock; 1487 1488 psr->paused = false; 1489 intel_psr_activate(intel_dp); 1490 1491 unlock: 1492 mutex_unlock(&psr->lock); 1493 } 1494 1495 static u32 man_trk_ctl_enable_bit_get(struct drm_i915_private *dev_priv) 1496 { 1497 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ? 0 : 1498 PSR2_MAN_TRK_CTL_ENABLE; 1499 } 1500 1501 static u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private *dev_priv) 1502 { 1503 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ? 1504 ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME : 1505 PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 1506 } 1507 1508 static u32 man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev_priv) 1509 { 1510 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ? 1511 ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE : 1512 PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; 1513 } 1514 1515 static u32 man_trk_ctl_continuos_full_frame(struct drm_i915_private *dev_priv) 1516 { 1517 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ? 1518 ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME : 1519 PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME; 1520 } 1521 1522 static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) 1523 { 1524 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1525 1526 if (intel_dp->psr.psr2_sel_fetch_enabled) 1527 intel_de_write(dev_priv, 1528 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 1529 man_trk_ctl_enable_bit_get(dev_priv) | 1530 man_trk_ctl_partial_frame_bit_get(dev_priv) | 1531 man_trk_ctl_single_full_frame_bit_get(dev_priv) | 1532 man_trk_ctl_continuos_full_frame(dev_priv)); 1533 1534 /* 1535 * Display WA #0884: skl+ 1536 * This documented WA for bxt can be safely applied 1537 * broadly so we can force HW tracking to exit PSR 1538 * instead of disabling and re-enabling. 1539 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 1540 * but it makes more sense write to the current active 1541 * pipe. 1542 * 1543 * This workaround do not exist for platforms with display 10 or newer 1544 * but testing proved that it works for up display 13, for newer 1545 * than that testing will be needed. 1546 */ 1547 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 1548 } 1549 1550 void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane, 1551 const struct intel_crtc_state *crtc_state) 1552 { 1553 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1554 enum pipe pipe = plane->pipe; 1555 1556 if (!crtc_state->enable_psr2_sel_fetch) 1557 return; 1558 1559 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0); 1560 } 1561 1562 void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, 1563 const struct intel_crtc_state *crtc_state, 1564 const struct intel_plane_state *plane_state, 1565 int color_plane) 1566 { 1567 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1568 enum pipe pipe = plane->pipe; 1569 const struct drm_rect *clip; 1570 u32 val; 1571 int x, y; 1572 1573 if (!crtc_state->enable_psr2_sel_fetch) 1574 return; 1575 1576 if (plane->id == PLANE_CURSOR) { 1577 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 1578 plane_state->ctl); 1579 return; 1580 } 1581 1582 clip = &plane_state->psr2_sel_fetch_area; 1583 1584 val = (clip->y1 + plane_state->uapi.dst.y1) << 16; 1585 val |= plane_state->uapi.dst.x1; 1586 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); 1587 1588 x = plane_state->view.color_plane[color_plane].x; 1589 1590 /* 1591 * From Bspec: UV surface Start Y Position = half of Y plane Y 1592 * start position. 1593 */ 1594 if (!color_plane) 1595 y = plane_state->view.color_plane[color_plane].y + clip->y1; 1596 else 1597 y = plane_state->view.color_plane[color_plane].y + clip->y1 / 2; 1598 1599 val = y << 16 | x; 1600 1601 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), 1602 val); 1603 1604 /* Sizes are 0 based */ 1605 val = (drm_rect_height(clip) - 1) << 16; 1606 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; 1607 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); 1608 1609 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 1610 PLANE_SEL_FETCH_CTL_ENABLE); 1611 } 1612 1613 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) 1614 { 1615 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1616 struct intel_encoder *encoder; 1617 1618 if (!crtc_state->enable_psr2_sel_fetch) 1619 return; 1620 1621 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, 1622 crtc_state->uapi.encoder_mask) { 1623 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1624 1625 lockdep_assert_held(&intel_dp->psr.lock); 1626 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) 1627 return; 1628 break; 1629 } 1630 1631 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder), 1632 crtc_state->psr2_man_track_ctl); 1633 } 1634 1635 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, 1636 struct drm_rect *clip, bool full_update) 1637 { 1638 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1639 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1640 u32 val = man_trk_ctl_enable_bit_get(dev_priv); 1641 1642 /* SF partial frame enable has to be set even on full update */ 1643 val |= man_trk_ctl_partial_frame_bit_get(dev_priv); 1644 1645 if (full_update) { 1646 val |= man_trk_ctl_single_full_frame_bit_get(dev_priv); 1647 val |= man_trk_ctl_continuos_full_frame(dev_priv); 1648 goto exit; 1649 } 1650 1651 if (clip->y1 == -1) 1652 goto exit; 1653 1654 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) { 1655 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1); 1656 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 - 1); 1657 } else { 1658 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4); 1659 1660 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1); 1661 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1); 1662 } 1663 exit: 1664 crtc_state->psr2_man_track_ctl = val; 1665 } 1666 1667 static void clip_area_update(struct drm_rect *overlap_damage_area, 1668 struct drm_rect *damage_area, 1669 struct drm_rect *pipe_src) 1670 { 1671 if (!drm_rect_intersect(damage_area, pipe_src)) 1672 return; 1673 1674 if (overlap_damage_area->y1 == -1) { 1675 overlap_damage_area->y1 = damage_area->y1; 1676 overlap_damage_area->y2 = damage_area->y2; 1677 return; 1678 } 1679 1680 if (damage_area->y1 < overlap_damage_area->y1) 1681 overlap_damage_area->y1 = damage_area->y1; 1682 1683 if (damage_area->y2 > overlap_damage_area->y2) 1684 overlap_damage_area->y2 = damage_area->y2; 1685 } 1686 1687 static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state, 1688 struct drm_rect *pipe_clip) 1689 { 1690 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1691 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1692 u16 y_alignment; 1693 1694 /* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */ 1695 if (crtc_state->dsc.compression_enable && 1696 (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)) 1697 y_alignment = vdsc_cfg->slice_height; 1698 else 1699 y_alignment = crtc_state->su_y_granularity; 1700 1701 pipe_clip->y1 -= pipe_clip->y1 % y_alignment; 1702 if (pipe_clip->y2 % y_alignment) 1703 pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment; 1704 } 1705 1706 /* 1707 * TODO: Not clear how to handle planes with negative position, 1708 * also planes are not updated if they have a negative X 1709 * position so for now doing a full update in this cases 1710 * 1711 * Plane scaling and rotation is not supported by selective fetch and both 1712 * properties can change without a modeset, so need to be check at every 1713 * atomic commit. 1714 */ 1715 static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state) 1716 { 1717 if (plane_state->uapi.dst.y1 < 0 || 1718 plane_state->uapi.dst.x1 < 0 || 1719 plane_state->scaler_id >= 0 || 1720 plane_state->uapi.rotation != DRM_MODE_ROTATE_0) 1721 return false; 1722 1723 return true; 1724 } 1725 1726 /* 1727 * Check for pipe properties that is not supported by selective fetch. 1728 * 1729 * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed 1730 * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch 1731 * enabled and going to the full update path. 1732 */ 1733 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state) 1734 { 1735 if (crtc_state->scaler_state.scaler_id >= 0) 1736 return false; 1737 1738 return true; 1739 } 1740 1741 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 1742 struct intel_crtc *crtc) 1743 { 1744 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1745 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 1746 struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 }; 1747 struct intel_plane_state *new_plane_state, *old_plane_state; 1748 struct intel_plane *plane; 1749 bool full_update = false; 1750 int i, ret; 1751 1752 if (!crtc_state->enable_psr2_sel_fetch) 1753 return 0; 1754 1755 if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) { 1756 full_update = true; 1757 goto skip_sel_fetch_set_loop; 1758 } 1759 1760 /* 1761 * Calculate minimal selective fetch area of each plane and calculate 1762 * the pipe damaged area. 1763 * In the next loop the plane selective fetch area will actually be set 1764 * using whole pipe damaged area. 1765 */ 1766 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1767 new_plane_state, i) { 1768 struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1, 1769 .x2 = INT_MAX }; 1770 1771 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) 1772 continue; 1773 1774 if (!new_plane_state->uapi.visible && 1775 !old_plane_state->uapi.visible) 1776 continue; 1777 1778 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 1779 full_update = true; 1780 break; 1781 } 1782 1783 /* 1784 * If visibility or plane moved, mark the whole plane area as 1785 * damaged as it needs to be complete redraw in the new and old 1786 * position. 1787 */ 1788 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || 1789 !drm_rect_equals(&new_plane_state->uapi.dst, 1790 &old_plane_state->uapi.dst)) { 1791 if (old_plane_state->uapi.visible) { 1792 damaged_area.y1 = old_plane_state->uapi.dst.y1; 1793 damaged_area.y2 = old_plane_state->uapi.dst.y2; 1794 clip_area_update(&pipe_clip, &damaged_area, 1795 &crtc_state->pipe_src); 1796 } 1797 1798 if (new_plane_state->uapi.visible) { 1799 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1800 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1801 clip_area_update(&pipe_clip, &damaged_area, 1802 &crtc_state->pipe_src); 1803 } 1804 continue; 1805 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { 1806 /* If alpha changed mark the whole plane area as damaged */ 1807 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1808 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1809 clip_area_update(&pipe_clip, &damaged_area, 1810 &crtc_state->pipe_src); 1811 continue; 1812 } 1813 1814 src = drm_plane_state_src(&new_plane_state->uapi); 1815 drm_rect_fp_to_int(&src, &src); 1816 1817 if (!drm_atomic_helper_damage_merged(&old_plane_state->uapi, 1818 &new_plane_state->uapi, &damaged_area)) 1819 continue; 1820 1821 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; 1822 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; 1823 damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1; 1824 damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1; 1825 1826 clip_area_update(&pipe_clip, &damaged_area, &crtc_state->pipe_src); 1827 } 1828 1829 /* 1830 * TODO: For now we are just using full update in case 1831 * selective fetch area calculation fails. To optimize this we 1832 * should identify cases where this happens and fix the area 1833 * calculation for those. 1834 */ 1835 if (pipe_clip.y1 == -1) { 1836 drm_info_once(&dev_priv->drm, 1837 "Selective fetch area calculation failed in pipe %c\n", 1838 pipe_name(crtc->pipe)); 1839 full_update = true; 1840 } 1841 1842 if (full_update) 1843 goto skip_sel_fetch_set_loop; 1844 1845 /* Wa_14014971492 */ 1846 if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) || 1847 IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) && 1848 crtc_state->splitter.enable) 1849 pipe_clip.y1 = 0; 1850 1851 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 1852 if (ret) 1853 return ret; 1854 1855 intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip); 1856 1857 /* 1858 * Now that we have the pipe damaged area check if it intersect with 1859 * every plane, if it does set the plane selective fetch area. 1860 */ 1861 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1862 new_plane_state, i) { 1863 struct drm_rect *sel_fetch_area, inter; 1864 struct intel_plane *linked = new_plane_state->planar_linked_plane; 1865 1866 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || 1867 !new_plane_state->uapi.visible) 1868 continue; 1869 1870 inter = pipe_clip; 1871 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) 1872 continue; 1873 1874 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 1875 full_update = true; 1876 break; 1877 } 1878 1879 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 1880 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; 1881 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; 1882 crtc_state->update_planes |= BIT(plane->id); 1883 1884 /* 1885 * Sel_fetch_area is calculated for UV plane. Use 1886 * same area for Y plane as well. 1887 */ 1888 if (linked) { 1889 struct intel_plane_state *linked_new_plane_state; 1890 struct drm_rect *linked_sel_fetch_area; 1891 1892 linked_new_plane_state = intel_atomic_get_plane_state(state, linked); 1893 if (IS_ERR(linked_new_plane_state)) 1894 return PTR_ERR(linked_new_plane_state); 1895 1896 linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area; 1897 linked_sel_fetch_area->y1 = sel_fetch_area->y1; 1898 linked_sel_fetch_area->y2 = sel_fetch_area->y2; 1899 crtc_state->update_planes |= BIT(linked->id); 1900 } 1901 } 1902 1903 skip_sel_fetch_set_loop: 1904 psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update); 1905 return 0; 1906 } 1907 1908 void intel_psr_pre_plane_update(struct intel_atomic_state *state, 1909 struct intel_crtc *crtc) 1910 { 1911 struct drm_i915_private *i915 = to_i915(state->base.dev); 1912 const struct intel_crtc_state *old_crtc_state = 1913 intel_atomic_get_old_crtc_state(state, crtc); 1914 const struct intel_crtc_state *new_crtc_state = 1915 intel_atomic_get_new_crtc_state(state, crtc); 1916 struct intel_encoder *encoder; 1917 1918 if (!HAS_PSR(i915)) 1919 return; 1920 1921 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 1922 old_crtc_state->uapi.encoder_mask) { 1923 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1924 struct intel_psr *psr = &intel_dp->psr; 1925 bool needs_to_disable = false; 1926 1927 mutex_lock(&psr->lock); 1928 1929 /* 1930 * Reasons to disable: 1931 * - PSR disabled in new state 1932 * - All planes will go inactive 1933 * - Changing between PSR versions 1934 */ 1935 needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state); 1936 needs_to_disable |= !new_crtc_state->has_psr; 1937 needs_to_disable |= !new_crtc_state->active_planes; 1938 needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled; 1939 1940 if (psr->enabled && needs_to_disable) 1941 intel_psr_disable_locked(intel_dp); 1942 1943 mutex_unlock(&psr->lock); 1944 } 1945 } 1946 1947 static void _intel_psr_post_plane_update(const struct intel_atomic_state *state, 1948 const struct intel_crtc_state *crtc_state) 1949 { 1950 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1951 struct intel_encoder *encoder; 1952 1953 if (!crtc_state->has_psr) 1954 return; 1955 1956 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 1957 crtc_state->uapi.encoder_mask) { 1958 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1959 struct intel_psr *psr = &intel_dp->psr; 1960 1961 mutex_lock(&psr->lock); 1962 1963 if (psr->sink_not_reliable) 1964 goto exit; 1965 1966 drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes); 1967 1968 /* Only enable if there is active planes */ 1969 if (!psr->enabled && crtc_state->active_planes) 1970 intel_psr_enable_locked(intel_dp, crtc_state); 1971 1972 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 1973 if (crtc_state->crc_enabled && psr->enabled) 1974 psr_force_hw_tracking_exit(intel_dp); 1975 1976 exit: 1977 mutex_unlock(&psr->lock); 1978 } 1979 } 1980 1981 void intel_psr_post_plane_update(const struct intel_atomic_state *state) 1982 { 1983 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1984 struct intel_crtc_state *crtc_state; 1985 struct intel_crtc *crtc; 1986 int i; 1987 1988 if (!HAS_PSR(dev_priv)) 1989 return; 1990 1991 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) 1992 _intel_psr_post_plane_update(state, crtc_state); 1993 } 1994 1995 static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp) 1996 { 1997 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1998 1999 /* 2000 * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough. 2001 * As all higher states has bit 4 of PSR2 state set we can just wait for 2002 * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared. 2003 */ 2004 return intel_de_wait_for_clear(dev_priv, 2005 EDP_PSR2_STATUS(intel_dp->psr.transcoder), 2006 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50); 2007 } 2008 2009 static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp) 2010 { 2011 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2012 2013 /* 2014 * From bspec: Panel Self Refresh (BDW+) 2015 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 2016 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 2017 * defensive enough to cover everything. 2018 */ 2019 return intel_de_wait_for_clear(dev_priv, 2020 EDP_PSR_STATUS(intel_dp->psr.transcoder), 2021 EDP_PSR_STATUS_STATE_MASK, 50); 2022 } 2023 2024 /** 2025 * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update 2026 * @new_crtc_state: new CRTC state 2027 * 2028 * This function is expected to be called from pipe_update_start() where it is 2029 * not expected to race with PSR enable or disable. 2030 */ 2031 void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state) 2032 { 2033 struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev); 2034 struct intel_encoder *encoder; 2035 2036 if (!new_crtc_state->has_psr) 2037 return; 2038 2039 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, 2040 new_crtc_state->uapi.encoder_mask) { 2041 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2042 int ret; 2043 2044 lockdep_assert_held(&intel_dp->psr.lock); 2045 2046 if (!intel_dp->psr.enabled) 2047 continue; 2048 2049 if (intel_dp->psr.psr2_enabled) 2050 ret = _psr2_ready_for_pipe_update_locked(intel_dp); 2051 else 2052 ret = _psr1_ready_for_pipe_update_locked(intel_dp); 2053 2054 if (ret) 2055 drm_err(&dev_priv->drm, "PSR wait timed out, atomic update may fail\n"); 2056 } 2057 } 2058 2059 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) 2060 { 2061 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2062 i915_reg_t reg; 2063 u32 mask; 2064 int err; 2065 2066 if (!intel_dp->psr.enabled) 2067 return false; 2068 2069 if (intel_dp->psr.psr2_enabled) { 2070 reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 2071 mask = EDP_PSR2_STATUS_STATE_MASK; 2072 } else { 2073 reg = EDP_PSR_STATUS(intel_dp->psr.transcoder); 2074 mask = EDP_PSR_STATUS_STATE_MASK; 2075 } 2076 2077 mutex_unlock(&intel_dp->psr.lock); 2078 2079 err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); 2080 if (err) 2081 drm_err(&dev_priv->drm, 2082 "Timed out waiting for PSR Idle for re-enable\n"); 2083 2084 /* After the unlocked wait, verify that PSR is still wanted! */ 2085 mutex_lock(&intel_dp->psr.lock); 2086 return err == 0 && intel_dp->psr.enabled; 2087 } 2088 2089 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) 2090 { 2091 struct drm_connector_list_iter conn_iter; 2092 struct drm_modeset_acquire_ctx ctx; 2093 struct drm_atomic_state *state; 2094 struct drm_connector *conn; 2095 int err = 0; 2096 2097 state = drm_atomic_state_alloc(&dev_priv->drm); 2098 if (!state) 2099 return -ENOMEM; 2100 2101 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 2102 state->acquire_ctx = &ctx; 2103 2104 retry: 2105 2106 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 2107 drm_for_each_connector_iter(conn, &conn_iter) { 2108 struct drm_connector_state *conn_state; 2109 struct drm_crtc_state *crtc_state; 2110 2111 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) 2112 continue; 2113 2114 conn_state = drm_atomic_get_connector_state(state, conn); 2115 if (IS_ERR(conn_state)) { 2116 err = PTR_ERR(conn_state); 2117 break; 2118 } 2119 2120 if (!conn_state->crtc) 2121 continue; 2122 2123 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); 2124 if (IS_ERR(crtc_state)) { 2125 err = PTR_ERR(crtc_state); 2126 break; 2127 } 2128 2129 /* Mark mode as changed to trigger a pipe->update() */ 2130 crtc_state->mode_changed = true; 2131 } 2132 drm_connector_list_iter_end(&conn_iter); 2133 2134 if (err == 0) 2135 err = drm_atomic_commit(state); 2136 2137 if (err == -EDEADLK) { 2138 drm_atomic_state_clear(state); 2139 err = drm_modeset_backoff(&ctx); 2140 if (!err) 2141 goto retry; 2142 } 2143 2144 drm_modeset_drop_locks(&ctx); 2145 drm_modeset_acquire_fini(&ctx); 2146 drm_atomic_state_put(state); 2147 2148 return err; 2149 } 2150 2151 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) 2152 { 2153 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2154 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 2155 u32 old_mode; 2156 int ret; 2157 2158 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || 2159 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 2160 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); 2161 return -EINVAL; 2162 } 2163 2164 ret = mutex_lock_interruptible(&intel_dp->psr.lock); 2165 if (ret) 2166 return ret; 2167 2168 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; 2169 intel_dp->psr.debug = val; 2170 2171 /* 2172 * Do it right away if it's already enabled, otherwise it will be done 2173 * when enabling the source. 2174 */ 2175 if (intel_dp->psr.enabled) 2176 psr_irq_control(intel_dp); 2177 2178 mutex_unlock(&intel_dp->psr.lock); 2179 2180 if (old_mode != mode) 2181 ret = intel_psr_fastset_force(dev_priv); 2182 2183 return ret; 2184 } 2185 2186 static void intel_psr_handle_irq(struct intel_dp *intel_dp) 2187 { 2188 struct intel_psr *psr = &intel_dp->psr; 2189 2190 intel_psr_disable_locked(intel_dp); 2191 psr->sink_not_reliable = true; 2192 /* let's make sure that sink is awaken */ 2193 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 2194 } 2195 2196 static void intel_psr_work(struct work_struct *work) 2197 { 2198 struct intel_dp *intel_dp = 2199 container_of(work, typeof(*intel_dp), psr.work); 2200 2201 mutex_lock(&intel_dp->psr.lock); 2202 2203 if (!intel_dp->psr.enabled) 2204 goto unlock; 2205 2206 if (READ_ONCE(intel_dp->psr.irq_aux_error)) 2207 intel_psr_handle_irq(intel_dp); 2208 2209 /* 2210 * We have to make sure PSR is ready for re-enable 2211 * otherwise it keeps disabled until next full enable/disable cycle. 2212 * PSR might take some time to get fully disabled 2213 * and be ready for re-enable. 2214 */ 2215 if (!__psr_wait_for_idle_locked(intel_dp)) 2216 goto unlock; 2217 2218 /* 2219 * The delayed work can race with an invalidate hence we need to 2220 * recheck. Since psr_flush first clears this and then reschedules we 2221 * won't ever miss a flush when bailing out here. 2222 */ 2223 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) 2224 goto unlock; 2225 2226 intel_psr_activate(intel_dp); 2227 unlock: 2228 mutex_unlock(&intel_dp->psr.lock); 2229 } 2230 2231 static void _psr_invalidate_handle(struct intel_dp *intel_dp) 2232 { 2233 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2234 2235 if (intel_dp->psr.psr2_sel_fetch_enabled) { 2236 u32 val; 2237 2238 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { 2239 /* Send one update otherwise lag is observed in screen */ 2240 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 2241 return; 2242 } 2243 2244 val = man_trk_ctl_enable_bit_get(dev_priv) | 2245 man_trk_ctl_partial_frame_bit_get(dev_priv) | 2246 man_trk_ctl_continuos_full_frame(dev_priv); 2247 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), val); 2248 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 2249 intel_dp->psr.psr2_sel_fetch_cff_enabled = true; 2250 } else { 2251 intel_psr_exit(intel_dp); 2252 } 2253 } 2254 2255 /** 2256 * intel_psr_invalidate - Invalidate PSR 2257 * @dev_priv: i915 device 2258 * @frontbuffer_bits: frontbuffer plane tracking bits 2259 * @origin: which operation caused the invalidate 2260 * 2261 * Since the hardware frontbuffer tracking has gaps we need to integrate 2262 * with the software frontbuffer tracking. This function gets called every 2263 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 2264 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 2265 * 2266 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 2267 */ 2268 void intel_psr_invalidate(struct drm_i915_private *dev_priv, 2269 unsigned frontbuffer_bits, enum fb_op_origin origin) 2270 { 2271 struct intel_encoder *encoder; 2272 2273 if (origin == ORIGIN_FLIP) 2274 return; 2275 2276 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2277 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 2278 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2279 2280 mutex_lock(&intel_dp->psr.lock); 2281 if (!intel_dp->psr.enabled) { 2282 mutex_unlock(&intel_dp->psr.lock); 2283 continue; 2284 } 2285 2286 pipe_frontbuffer_bits &= 2287 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 2288 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; 2289 2290 if (pipe_frontbuffer_bits) 2291 _psr_invalidate_handle(intel_dp); 2292 2293 mutex_unlock(&intel_dp->psr.lock); 2294 } 2295 } 2296 /* 2297 * When we will be completely rely on PSR2 S/W tracking in future, 2298 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP 2299 * event also therefore tgl_dc3co_flush_locked() require to be changed 2300 * accordingly in future. 2301 */ 2302 static void 2303 tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits, 2304 enum fb_op_origin origin) 2305 { 2306 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled || 2307 !intel_dp->psr.active) 2308 return; 2309 2310 /* 2311 * At every frontbuffer flush flip event modified delay of delayed work, 2312 * when delayed work schedules that means display has been idle. 2313 */ 2314 if (!(frontbuffer_bits & 2315 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) 2316 return; 2317 2318 tgl_psr2_enable_dc3co(intel_dp); 2319 mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work, 2320 intel_dp->psr.dc3co_exit_delay); 2321 } 2322 2323 static void _psr_flush_handle(struct intel_dp *intel_dp) 2324 { 2325 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2326 2327 if (intel_dp->psr.psr2_sel_fetch_enabled) { 2328 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { 2329 /* can we turn CFF off? */ 2330 if (intel_dp->psr.busy_frontbuffer_bits == 0) { 2331 u32 val = man_trk_ctl_enable_bit_get(dev_priv) | 2332 man_trk_ctl_partial_frame_bit_get(dev_priv) | 2333 man_trk_ctl_single_full_frame_bit_get(dev_priv) | 2334 man_trk_ctl_continuos_full_frame(dev_priv); 2335 2336 /* 2337 * Set psr2_sel_fetch_cff_enabled as false to allow selective 2338 * updates. Still keep cff bit enabled as we don't have proper 2339 * SU configuration in case update is sent for any reason after 2340 * sff bit gets cleared by the HW on next vblank. 2341 */ 2342 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 2343 val); 2344 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 2345 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 2346 } 2347 } else { 2348 /* 2349 * continuous full frame is disabled, only a single full 2350 * frame is required 2351 */ 2352 psr_force_hw_tracking_exit(intel_dp); 2353 } 2354 } else { 2355 psr_force_hw_tracking_exit(intel_dp); 2356 2357 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) 2358 schedule_work(&intel_dp->psr.work); 2359 } 2360 } 2361 2362 /** 2363 * intel_psr_flush - Flush PSR 2364 * @dev_priv: i915 device 2365 * @frontbuffer_bits: frontbuffer plane tracking bits 2366 * @origin: which operation caused the flush 2367 * 2368 * Since the hardware frontbuffer tracking has gaps we need to integrate 2369 * with the software frontbuffer tracking. This function gets called every 2370 * time frontbuffer rendering has completed and flushed out to memory. PSR 2371 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 2372 * 2373 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 2374 */ 2375 void intel_psr_flush(struct drm_i915_private *dev_priv, 2376 unsigned frontbuffer_bits, enum fb_op_origin origin) 2377 { 2378 struct intel_encoder *encoder; 2379 2380 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2381 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 2382 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2383 2384 mutex_lock(&intel_dp->psr.lock); 2385 if (!intel_dp->psr.enabled) { 2386 mutex_unlock(&intel_dp->psr.lock); 2387 continue; 2388 } 2389 2390 pipe_frontbuffer_bits &= 2391 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 2392 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; 2393 2394 /* 2395 * If the PSR is paused by an explicit intel_psr_paused() call, 2396 * we have to ensure that the PSR is not activated until 2397 * intel_psr_resume() is called. 2398 */ 2399 if (intel_dp->psr.paused) 2400 goto unlock; 2401 2402 if (origin == ORIGIN_FLIP || 2403 (origin == ORIGIN_CURSOR_UPDATE && 2404 !intel_dp->psr.psr2_sel_fetch_enabled)) { 2405 tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin); 2406 goto unlock; 2407 } 2408 2409 if (pipe_frontbuffer_bits == 0) 2410 goto unlock; 2411 2412 /* By definition flush = invalidate + flush */ 2413 _psr_flush_handle(intel_dp); 2414 unlock: 2415 mutex_unlock(&intel_dp->psr.lock); 2416 } 2417 } 2418 2419 /** 2420 * intel_psr_init - Init basic PSR work and mutex. 2421 * @intel_dp: Intel DP 2422 * 2423 * This function is called after the initializing connector. 2424 * (the initializing of connector treats the handling of connector capabilities) 2425 * And it initializes basic PSR stuff for each DP Encoder. 2426 */ 2427 void intel_psr_init(struct intel_dp *intel_dp) 2428 { 2429 struct intel_connector *connector = intel_dp->attached_connector; 2430 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2431 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2432 2433 if (!HAS_PSR(dev_priv)) 2434 return; 2435 2436 /* 2437 * HSW spec explicitly says PSR is tied to port A. 2438 * BDW+ platforms have a instance of PSR registers per transcoder but 2439 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder 2440 * than eDP one. 2441 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11. 2442 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11. 2443 * But GEN12 supports a instance of PSR registers per transcoder. 2444 */ 2445 if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) { 2446 drm_dbg_kms(&dev_priv->drm, 2447 "PSR condition failed: Port not supported\n"); 2448 return; 2449 } 2450 2451 intel_dp->psr.source_support = true; 2452 2453 /* Set link_standby x link_off defaults */ 2454 if (DISPLAY_VER(dev_priv) < 12) 2455 /* For new platforms up to TGL let's respect VBT back again */ 2456 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link; 2457 2458 INIT_WORK(&intel_dp->psr.work, intel_psr_work); 2459 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); 2460 mutex_init(&intel_dp->psr.lock); 2461 } 2462 2463 static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 2464 u8 *status, u8 *error_status) 2465 { 2466 struct drm_dp_aux *aux = &intel_dp->aux; 2467 int ret; 2468 2469 ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status); 2470 if (ret != 1) 2471 return ret; 2472 2473 ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status); 2474 if (ret != 1) 2475 return ret; 2476 2477 *status = *status & DP_PSR_SINK_STATE_MASK; 2478 2479 return 0; 2480 } 2481 2482 static void psr_alpm_check(struct intel_dp *intel_dp) 2483 { 2484 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2485 struct drm_dp_aux *aux = &intel_dp->aux; 2486 struct intel_psr *psr = &intel_dp->psr; 2487 u8 val; 2488 int r; 2489 2490 if (!psr->psr2_enabled) 2491 return; 2492 2493 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); 2494 if (r != 1) { 2495 drm_err(&dev_priv->drm, "Error reading ALPM status\n"); 2496 return; 2497 } 2498 2499 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) { 2500 intel_psr_disable_locked(intel_dp); 2501 psr->sink_not_reliable = true; 2502 drm_dbg_kms(&dev_priv->drm, 2503 "ALPM lock timeout error, disabling PSR\n"); 2504 2505 /* Clearing error */ 2506 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); 2507 } 2508 } 2509 2510 static void psr_capability_changed_check(struct intel_dp *intel_dp) 2511 { 2512 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2513 struct intel_psr *psr = &intel_dp->psr; 2514 u8 val; 2515 int r; 2516 2517 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 2518 if (r != 1) { 2519 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n"); 2520 return; 2521 } 2522 2523 if (val & DP_PSR_CAPS_CHANGE) { 2524 intel_psr_disable_locked(intel_dp); 2525 psr->sink_not_reliable = true; 2526 drm_dbg_kms(&dev_priv->drm, 2527 "Sink PSR capability changed, disabling PSR\n"); 2528 2529 /* Clearing it */ 2530 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 2531 } 2532 } 2533 2534 void intel_psr_short_pulse(struct intel_dp *intel_dp) 2535 { 2536 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2537 struct intel_psr *psr = &intel_dp->psr; 2538 u8 status, error_status; 2539 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 2540 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 2541 DP_PSR_LINK_CRC_ERROR; 2542 2543 if (!CAN_PSR(intel_dp)) 2544 return; 2545 2546 mutex_lock(&psr->lock); 2547 2548 if (!psr->enabled) 2549 goto exit; 2550 2551 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 2552 drm_err(&dev_priv->drm, 2553 "Error reading PSR status or error status\n"); 2554 goto exit; 2555 } 2556 2557 if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) { 2558 intel_psr_disable_locked(intel_dp); 2559 psr->sink_not_reliable = true; 2560 } 2561 2562 if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status) 2563 drm_dbg_kms(&dev_priv->drm, 2564 "PSR sink internal error, disabling PSR\n"); 2565 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 2566 drm_dbg_kms(&dev_priv->drm, 2567 "PSR RFB storage error, disabling PSR\n"); 2568 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 2569 drm_dbg_kms(&dev_priv->drm, 2570 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 2571 if (error_status & DP_PSR_LINK_CRC_ERROR) 2572 drm_dbg_kms(&dev_priv->drm, 2573 "PSR Link CRC error, disabling PSR\n"); 2574 2575 if (error_status & ~errors) 2576 drm_err(&dev_priv->drm, 2577 "PSR_ERROR_STATUS unhandled errors %x\n", 2578 error_status & ~errors); 2579 /* clear status register */ 2580 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 2581 2582 psr_alpm_check(intel_dp); 2583 psr_capability_changed_check(intel_dp); 2584 2585 exit: 2586 mutex_unlock(&psr->lock); 2587 } 2588 2589 bool intel_psr_enabled(struct intel_dp *intel_dp) 2590 { 2591 bool ret; 2592 2593 if (!CAN_PSR(intel_dp)) 2594 return false; 2595 2596 mutex_lock(&intel_dp->psr.lock); 2597 ret = intel_dp->psr.enabled; 2598 mutex_unlock(&intel_dp->psr.lock); 2599 2600 return ret; 2601 } 2602 2603 /** 2604 * intel_psr_lock - grab PSR lock 2605 * @crtc_state: the crtc state 2606 * 2607 * This is initially meant to be used by around CRTC update, when 2608 * vblank sensitive registers are updated and we need grab the lock 2609 * before it to avoid vblank evasion. 2610 */ 2611 void intel_psr_lock(const struct intel_crtc_state *crtc_state) 2612 { 2613 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2614 struct intel_encoder *encoder; 2615 2616 if (!crtc_state->has_psr) 2617 return; 2618 2619 for_each_intel_encoder_mask_with_psr(&i915->drm, encoder, 2620 crtc_state->uapi.encoder_mask) { 2621 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2622 2623 mutex_lock(&intel_dp->psr.lock); 2624 break; 2625 } 2626 } 2627 2628 /** 2629 * intel_psr_unlock - release PSR lock 2630 * @crtc_state: the crtc state 2631 * 2632 * Release the PSR lock that was held during pipe update. 2633 */ 2634 void intel_psr_unlock(const struct intel_crtc_state *crtc_state) 2635 { 2636 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2637 struct intel_encoder *encoder; 2638 2639 if (!crtc_state->has_psr) 2640 return; 2641 2642 for_each_intel_encoder_mask_with_psr(&i915->drm, encoder, 2643 crtc_state->uapi.encoder_mask) { 2644 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2645 2646 mutex_unlock(&intel_dp->psr.lock); 2647 break; 2648 } 2649 } 2650