1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <drm/drm_atomic_helper.h> 25 26 #include "display/intel_dp.h" 27 28 #include "i915_drv.h" 29 #include "intel_atomic.h" 30 #include "intel_display_types.h" 31 #include "intel_dp_aux.h" 32 #include "intel_hdmi.h" 33 #include "intel_psr.h" 34 #include "intel_sprite.h" 35 #include "skl_universal_plane.h" 36 37 /** 38 * DOC: Panel Self Refresh (PSR/SRD) 39 * 40 * Since Haswell Display controller supports Panel Self-Refresh on display 41 * panels witch have a remote frame buffer (RFB) implemented according to PSR 42 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 43 * when system is idle but display is on as it eliminates display refresh 44 * request to DDR memory completely as long as the frame buffer for that 45 * display is unchanged. 46 * 47 * Panel Self Refresh must be supported by both Hardware (source) and 48 * Panel (sink). 49 * 50 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 51 * to power down the link and memory controller. For DSI panels the same idea 52 * is called "manual mode". 53 * 54 * The implementation uses the hardware-based PSR support which automatically 55 * enters/exits self-refresh mode. The hardware takes care of sending the 56 * required DP aux message and could even retrain the link (that part isn't 57 * enabled yet though). The hardware also keeps track of any frontbuffer 58 * changes to know when to exit self-refresh mode again. Unfortunately that 59 * part doesn't work too well, hence why the i915 PSR support uses the 60 * software frontbuffer tracking to make sure it doesn't miss a screen 61 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 62 * get called by the frontbuffer tracking code. Note that because of locking 63 * issues the self-refresh re-enable code is done from a work queue, which 64 * must be correctly synchronized/cancelled when shutting down the pipe." 65 * 66 * DC3CO (DC3 clock off) 67 * 68 * On top of PSR2, GEN12 adds a intermediate power savings state that turns 69 * clock off automatically during PSR2 idle state. 70 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep 71 * entry/exit allows the HW to enter a low-power state even when page flipping 72 * periodically (for instance a 30fps video playback scenario). 73 * 74 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), 75 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 76 * frames, if no other flip occurs and the function above is executed, DC3CO is 77 * disabled and PSR2 is configured to enter deep sleep, resetting again in case 78 * of another flip. 79 * Front buffer modifications do not trigger DC3CO activation on purpose as it 80 * would bring a lot of complexity and most of the moderns systems will only 81 * use page flips. 82 */ 83 84 static bool psr_global_enabled(struct intel_dp *intel_dp) 85 { 86 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 87 88 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 89 case I915_PSR_DEBUG_DEFAULT: 90 return i915->params.enable_psr; 91 case I915_PSR_DEBUG_DISABLE: 92 return false; 93 default: 94 return true; 95 } 96 } 97 98 static bool psr2_global_enabled(struct intel_dp *intel_dp) 99 { 100 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 101 case I915_PSR_DEBUG_DISABLE: 102 case I915_PSR_DEBUG_FORCE_PSR1: 103 return false; 104 default: 105 return true; 106 } 107 } 108 109 static void psr_irq_control(struct intel_dp *intel_dp) 110 { 111 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 112 enum transcoder trans_shift; 113 i915_reg_t imr_reg; 114 u32 mask, val; 115 116 /* 117 * gen12+ has registers relative to transcoder and one per transcoder 118 * using the same bit definition: handle it as TRANSCODER_EDP to force 119 * 0 shift in bit definition 120 */ 121 if (INTEL_GEN(dev_priv) >= 12) { 122 trans_shift = 0; 123 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 124 } else { 125 trans_shift = intel_dp->psr.transcoder; 126 imr_reg = EDP_PSR_IMR; 127 } 128 129 mask = EDP_PSR_ERROR(trans_shift); 130 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) 131 mask |= EDP_PSR_POST_EXIT(trans_shift) | 132 EDP_PSR_PRE_ENTRY(trans_shift); 133 134 /* Warning: it is masking/setting reserved bits too */ 135 val = intel_de_read(dev_priv, imr_reg); 136 val &= ~EDP_PSR_TRANS_MASK(trans_shift); 137 val |= ~mask; 138 intel_de_write(dev_priv, imr_reg, val); 139 } 140 141 static void psr_event_print(struct drm_i915_private *i915, 142 u32 val, bool psr2_enabled) 143 { 144 drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val); 145 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 146 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n"); 147 if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) 148 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n"); 149 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 150 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n"); 151 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 152 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n"); 153 if (val & PSR_EVENT_GRAPHICS_RESET) 154 drm_dbg_kms(&i915->drm, "\tGraphics reset\n"); 155 if (val & PSR_EVENT_PCH_INTERRUPT) 156 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n"); 157 if (val & PSR_EVENT_MEMORY_UP) 158 drm_dbg_kms(&i915->drm, "\tMemory up\n"); 159 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 160 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n"); 161 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 162 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n"); 163 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 164 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n"); 165 if (val & PSR_EVENT_REGISTER_UPDATE) 166 drm_dbg_kms(&i915->drm, "\tRegister updated\n"); 167 if (val & PSR_EVENT_HDCP_ENABLE) 168 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n"); 169 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 170 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n"); 171 if (val & PSR_EVENT_VBI_ENABLE) 172 drm_dbg_kms(&i915->drm, "\tVBI enabled\n"); 173 if (val & PSR_EVENT_LPSP_MODE_EXIT) 174 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n"); 175 if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) 176 drm_dbg_kms(&i915->drm, "\tPSR disabled\n"); 177 } 178 179 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) 180 { 181 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 182 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 183 ktime_t time_ns = ktime_get(); 184 enum transcoder trans_shift; 185 i915_reg_t imr_reg; 186 187 if (INTEL_GEN(dev_priv) >= 12) { 188 trans_shift = 0; 189 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 190 } else { 191 trans_shift = intel_dp->psr.transcoder; 192 imr_reg = EDP_PSR_IMR; 193 } 194 195 if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) { 196 intel_dp->psr.last_entry_attempt = time_ns; 197 drm_dbg_kms(&dev_priv->drm, 198 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 199 transcoder_name(cpu_transcoder)); 200 } 201 202 if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) { 203 intel_dp->psr.last_exit = time_ns; 204 drm_dbg_kms(&dev_priv->drm, 205 "[transcoder %s] PSR exit completed\n", 206 transcoder_name(cpu_transcoder)); 207 208 if (INTEL_GEN(dev_priv) >= 9) { 209 u32 val = intel_de_read(dev_priv, 210 PSR_EVENT(cpu_transcoder)); 211 bool psr2_enabled = intel_dp->psr.psr2_enabled; 212 213 intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder), 214 val); 215 psr_event_print(dev_priv, val, psr2_enabled); 216 } 217 } 218 219 if (psr_iir & EDP_PSR_ERROR(trans_shift)) { 220 u32 val; 221 222 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", 223 transcoder_name(cpu_transcoder)); 224 225 intel_dp->psr.irq_aux_error = true; 226 227 /* 228 * If this interruption is not masked it will keep 229 * interrupting so fast that it prevents the scheduled 230 * work to run. 231 * Also after a PSR error, we don't want to arm PSR 232 * again so we don't care about unmask the interruption 233 * or unset irq_aux_error. 234 */ 235 val = intel_de_read(dev_priv, imr_reg); 236 val |= EDP_PSR_ERROR(trans_shift); 237 intel_de_write(dev_priv, imr_reg, val); 238 239 schedule_work(&intel_dp->psr.work); 240 } 241 } 242 243 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) 244 { 245 u8 alpm_caps = 0; 246 247 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, 248 &alpm_caps) != 1) 249 return false; 250 return alpm_caps & DP_ALPM_CAP; 251 } 252 253 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 254 { 255 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 256 u8 val = 8; /* assume the worst if we can't read the value */ 257 258 if (drm_dp_dpcd_readb(&intel_dp->aux, 259 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 260 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 261 else 262 drm_dbg_kms(&i915->drm, 263 "Unable to get sink synchronization latency, assuming 8 frames\n"); 264 return val; 265 } 266 267 static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp) 268 { 269 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 270 u16 val; 271 ssize_t r; 272 273 /* 274 * Returning the default X granularity if granularity not required or 275 * if DPCD read fails 276 */ 277 if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) 278 return 4; 279 280 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &val, 2); 281 if (r != 2) 282 drm_dbg_kms(&i915->drm, 283 "Unable to read DP_PSR2_SU_X_GRANULARITY\n"); 284 285 /* 286 * Spec says that if the value read is 0 the default granularity should 287 * be used instead. 288 */ 289 if (r != 2 || val == 0) 290 val = 4; 291 292 return val; 293 } 294 295 void intel_psr_init_dpcd(struct intel_dp *intel_dp) 296 { 297 struct drm_i915_private *dev_priv = 298 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 299 300 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, 301 sizeof(intel_dp->psr_dpcd)); 302 303 if (!intel_dp->psr_dpcd[0]) 304 return; 305 drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n", 306 intel_dp->psr_dpcd[0]); 307 308 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { 309 drm_dbg_kms(&dev_priv->drm, 310 "PSR support not currently available for this panel\n"); 311 return; 312 } 313 314 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 315 drm_dbg_kms(&dev_priv->drm, 316 "Panel lacks power state control, PSR cannot be enabled\n"); 317 return; 318 } 319 320 intel_dp->psr.sink_support = true; 321 intel_dp->psr.sink_sync_latency = 322 intel_dp_get_sink_sync_latency(intel_dp); 323 324 if (INTEL_GEN(dev_priv) >= 9 && 325 (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { 326 bool y_req = intel_dp->psr_dpcd[1] & 327 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 328 bool alpm = intel_dp_get_alpm_status(intel_dp); 329 330 /* 331 * All panels that supports PSR version 03h (PSR2 + 332 * Y-coordinate) can handle Y-coordinates in VSC but we are 333 * only sure that it is going to be used when required by the 334 * panel. This way panel is capable to do selective update 335 * without a aux frame sync. 336 * 337 * To support PSR version 02h and PSR version 03h without 338 * Y-coordinate requirement panels we would need to enable 339 * GTC first. 340 */ 341 intel_dp->psr.sink_psr2_support = y_req && alpm; 342 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n", 343 intel_dp->psr.sink_psr2_support ? "" : "not "); 344 345 if (intel_dp->psr.sink_psr2_support) { 346 intel_dp->psr.colorimetry_support = 347 intel_dp_get_colorimetry_status(intel_dp); 348 intel_dp->psr.su_x_granularity = 349 intel_dp_get_su_x_granulartiy(intel_dp); 350 } 351 } 352 } 353 354 static void hsw_psr_setup_aux(struct intel_dp *intel_dp) 355 { 356 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 357 u32 aux_clock_divider, aux_ctl; 358 int i; 359 static const u8 aux_msg[] = { 360 [0] = DP_AUX_NATIVE_WRITE << 4, 361 [1] = DP_SET_POWER >> 8, 362 [2] = DP_SET_POWER & 0xff, 363 [3] = 1 - 1, 364 [4] = DP_SET_POWER_D0, 365 }; 366 u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK | 367 EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | 368 EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | 369 EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; 370 371 BUILD_BUG_ON(sizeof(aux_msg) > 20); 372 for (i = 0; i < sizeof(aux_msg); i += 4) 373 intel_de_write(dev_priv, 374 EDP_PSR_AUX_DATA(intel_dp->psr.transcoder, i >> 2), 375 intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); 376 377 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 378 379 /* Start with bits set for DDI_AUX_CTL register */ 380 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), 381 aux_clock_divider); 382 383 /* Select only valid bits for SRD_AUX_CTL */ 384 aux_ctl &= psr_aux_mask; 385 intel_de_write(dev_priv, EDP_PSR_AUX_CTL(intel_dp->psr.transcoder), 386 aux_ctl); 387 } 388 389 static void intel_psr_enable_sink(struct intel_dp *intel_dp) 390 { 391 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 392 u8 dpcd_val = DP_PSR_ENABLE; 393 394 /* Enable ALPM at sink for psr2 */ 395 if (intel_dp->psr.psr2_enabled) { 396 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 397 DP_ALPM_ENABLE | 398 DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); 399 400 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 401 } else { 402 if (intel_dp->psr.link_standby) 403 dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; 404 405 if (INTEL_GEN(dev_priv) >= 8) 406 dpcd_val |= DP_PSR_CRC_VERIFICATION; 407 } 408 409 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); 410 411 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 412 } 413 414 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 415 { 416 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 417 u32 val = 0; 418 419 if (INTEL_GEN(dev_priv) >= 11) 420 val |= EDP_PSR_TP4_TIME_0US; 421 422 if (dev_priv->params.psr_safest_params) { 423 val |= EDP_PSR_TP1_TIME_2500us; 424 val |= EDP_PSR_TP2_TP3_TIME_2500us; 425 goto check_tp3_sel; 426 } 427 428 if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) 429 val |= EDP_PSR_TP1_TIME_0us; 430 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100) 431 val |= EDP_PSR_TP1_TIME_100us; 432 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500) 433 val |= EDP_PSR_TP1_TIME_500us; 434 else 435 val |= EDP_PSR_TP1_TIME_2500us; 436 437 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0) 438 val |= EDP_PSR_TP2_TP3_TIME_0us; 439 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) 440 val |= EDP_PSR_TP2_TP3_TIME_100us; 441 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) 442 val |= EDP_PSR_TP2_TP3_TIME_500us; 443 else 444 val |= EDP_PSR_TP2_TP3_TIME_2500us; 445 446 check_tp3_sel: 447 if (intel_dp_source_supports_hbr2(intel_dp) && 448 drm_dp_tps3_supported(intel_dp->dpcd)) 449 val |= EDP_PSR_TP1_TP3_SEL; 450 else 451 val |= EDP_PSR_TP1_TP2_SEL; 452 453 return val; 454 } 455 456 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 457 { 458 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 459 int idle_frames; 460 461 /* Let's use 6 as the minimum to cover all known cases including the 462 * off-by-one issue that HW has in some cases. 463 */ 464 idle_frames = max(6, dev_priv->vbt.psr.idle_frames); 465 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1); 466 467 if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf)) 468 idle_frames = 0xf; 469 470 return idle_frames; 471 } 472 473 static void hsw_activate_psr1(struct intel_dp *intel_dp) 474 { 475 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 476 u32 max_sleep_time = 0x1f; 477 u32 val = EDP_PSR_ENABLE; 478 479 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT; 480 481 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; 482 if (IS_HASWELL(dev_priv)) 483 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 484 485 if (intel_dp->psr.link_standby) 486 val |= EDP_PSR_LINK_STANDBY; 487 488 val |= intel_psr1_get_tp_time(intel_dp); 489 490 if (INTEL_GEN(dev_priv) >= 8) 491 val |= EDP_PSR_CRC_ENABLE; 492 493 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) & 494 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK); 495 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val); 496 } 497 498 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 499 { 500 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 501 u32 val = 0; 502 503 if (dev_priv->params.psr_safest_params) 504 return EDP_PSR2_TP2_TIME_2500us; 505 506 if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 507 dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 508 val |= EDP_PSR2_TP2_TIME_50us; 509 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 510 val |= EDP_PSR2_TP2_TIME_100us; 511 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 512 val |= EDP_PSR2_TP2_TIME_500us; 513 else 514 val |= EDP_PSR2_TP2_TIME_2500us; 515 516 return val; 517 } 518 519 static void hsw_activate_psr2(struct intel_dp *intel_dp) 520 { 521 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 522 u32 val; 523 524 val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT; 525 526 val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; 527 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 528 val |= EDP_Y_COORDINATE_ENABLE; 529 530 val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1); 531 val |= intel_psr2_get_tp_time(intel_dp); 532 533 if (INTEL_GEN(dev_priv) >= 12) { 534 /* 535 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default 536 * values from BSpec. In order to setting an optimal power 537 * consumption, lower than 4k resoluition mode needs to decrese 538 * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution 539 * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE. 540 */ 541 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 542 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7); 543 val |= TGL_EDP_PSR2_FAST_WAKE(7); 544 } else if (INTEL_GEN(dev_priv) >= 9) { 545 val |= EDP_PSR2_IO_BUFFER_WAKE(7); 546 val |= EDP_PSR2_FAST_WAKE(7); 547 } 548 549 if (intel_dp->psr.psr2_sel_fetch_enabled) { 550 /* WA 1408330847 */ 551 if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) || 552 IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)) 553 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 554 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 555 DIS_RAM_BYPASS_PSR2_MAN_TRACK); 556 557 intel_de_write(dev_priv, 558 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 559 PSR2_MAN_TRK_CTL_ENABLE); 560 } else if (HAS_PSR2_SEL_FETCH(dev_priv)) { 561 intel_de_write(dev_priv, 562 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0); 563 } 564 565 /* 566 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 567 * recommending keep this bit unset while PSR2 is enabled. 568 */ 569 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0); 570 571 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 572 } 573 574 static bool 575 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) 576 { 577 if (INTEL_GEN(dev_priv) < 9) 578 return false; 579 else if (INTEL_GEN(dev_priv) >= 12) 580 return trans == TRANSCODER_A; 581 else 582 return trans == TRANSCODER_EDP; 583 } 584 585 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate) 586 { 587 if (!cstate || !cstate->hw.active) 588 return 0; 589 590 return DIV_ROUND_UP(1000 * 1000, 591 drm_mode_vrefresh(&cstate->hw.adjusted_mode)); 592 } 593 594 static void psr2_program_idle_frames(struct intel_dp *intel_dp, 595 u32 idle_frames) 596 { 597 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 598 u32 val; 599 600 idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; 601 val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder)); 602 val &= ~EDP_PSR2_IDLE_FRAME_MASK; 603 val |= idle_frames; 604 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 605 } 606 607 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) 608 { 609 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 610 611 psr2_program_idle_frames(intel_dp, 0); 612 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO); 613 } 614 615 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp) 616 { 617 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 618 619 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 620 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp)); 621 } 622 623 static void tgl_dc3co_disable_work(struct work_struct *work) 624 { 625 struct intel_dp *intel_dp = 626 container_of(work, typeof(*intel_dp), psr.dc3co_work.work); 627 628 mutex_lock(&intel_dp->psr.lock); 629 /* If delayed work is pending, it is not idle */ 630 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) 631 goto unlock; 632 633 tgl_psr2_disable_dc3co(intel_dp); 634 unlock: 635 mutex_unlock(&intel_dp->psr.lock); 636 } 637 638 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) 639 { 640 if (!intel_dp->psr.dc3co_enabled) 641 return; 642 643 cancel_delayed_work(&intel_dp->psr.dc3co_work); 644 /* Before PSR2 exit disallow dc3co*/ 645 tgl_psr2_disable_dc3co(intel_dp); 646 } 647 648 static void 649 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 650 struct intel_crtc_state *crtc_state) 651 { 652 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; 653 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 654 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 655 u32 exit_scanlines; 656 657 /* 658 * DMC's DC3CO exit mechanism has an issue with Selective Fecth 659 * TODO: when the issue is addressed, this restriction should be removed. 660 */ 661 if (crtc_state->enable_psr2_sel_fetch) 662 return; 663 664 if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)) 665 return; 666 667 /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/ 668 if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A || 669 dig_port->base.port != PORT_A) 670 return; 671 672 /* 673 * DC3CO Exit time 200us B.Spec 49196 674 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 675 */ 676 exit_scanlines = 677 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; 678 679 if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay)) 680 return; 681 682 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; 683 } 684 685 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, 686 struct intel_crtc_state *crtc_state) 687 { 688 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 689 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 690 struct intel_plane_state *plane_state; 691 struct intel_plane *plane; 692 int i; 693 694 if (!dev_priv->params.enable_psr2_sel_fetch && 695 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 696 drm_dbg_kms(&dev_priv->drm, 697 "PSR2 sel fetch not enabled, disabled by parameter\n"); 698 return false; 699 } 700 701 if (crtc_state->uapi.async_flip) { 702 drm_dbg_kms(&dev_priv->drm, 703 "PSR2 sel fetch not enabled, async flip enabled\n"); 704 return false; 705 } 706 707 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 708 if (plane_state->uapi.rotation != DRM_MODE_ROTATE_0) { 709 drm_dbg_kms(&dev_priv->drm, 710 "PSR2 sel fetch not enabled, plane rotated\n"); 711 return false; 712 } 713 } 714 715 return crtc_state->enable_psr2_sel_fetch = true; 716 } 717 718 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 719 struct intel_crtc_state *crtc_state) 720 { 721 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 722 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 723 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 724 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 725 726 if (!intel_dp->psr.sink_psr2_support) 727 return false; 728 729 /* JSL and EHL only supports eDP 1.3 */ 730 if (IS_JSL_EHL(dev_priv)) { 731 drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n"); 732 return false; 733 } 734 735 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { 736 drm_dbg_kms(&dev_priv->drm, 737 "PSR2 not supported in transcoder %s\n", 738 transcoder_name(crtc_state->cpu_transcoder)); 739 return false; 740 } 741 742 if (!psr2_global_enabled(intel_dp)) { 743 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); 744 return false; 745 } 746 747 /* 748 * DSC and PSR2 cannot be enabled simultaneously. If a requested 749 * resolution requires DSC to be enabled, priority is given to DSC 750 * over PSR2. 751 */ 752 if (crtc_state->dsc.compression_enable) { 753 drm_dbg_kms(&dev_priv->drm, 754 "PSR2 cannot be enabled since DSC is enabled\n"); 755 return false; 756 } 757 758 if (crtc_state->crc_enabled) { 759 drm_dbg_kms(&dev_priv->drm, 760 "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); 761 return false; 762 } 763 764 if (INTEL_GEN(dev_priv) >= 12) { 765 psr_max_h = 5120; 766 psr_max_v = 3200; 767 max_bpp = 30; 768 } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { 769 psr_max_h = 4096; 770 psr_max_v = 2304; 771 max_bpp = 24; 772 } else if (IS_GEN(dev_priv, 9)) { 773 psr_max_h = 3640; 774 psr_max_v = 2304; 775 max_bpp = 24; 776 } 777 778 if (crtc_state->pipe_bpp > max_bpp) { 779 drm_dbg_kms(&dev_priv->drm, 780 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 781 crtc_state->pipe_bpp, max_bpp); 782 return false; 783 } 784 785 /* 786 * HW sends SU blocks of size four scan lines, which means the starting 787 * X coordinate and Y granularity requirements will always be met. We 788 * only need to validate the SU block width is a multiple of 789 * x granularity. 790 */ 791 if (crtc_hdisplay % intel_dp->psr.su_x_granularity) { 792 drm_dbg_kms(&dev_priv->drm, 793 "PSR2 not enabled, hdisplay(%d) not multiple of %d\n", 794 crtc_hdisplay, intel_dp->psr.su_x_granularity); 795 return false; 796 } 797 798 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 799 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && 800 !HAS_PSR_HW_TRACKING(dev_priv)) { 801 drm_dbg_kms(&dev_priv->drm, 802 "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); 803 return false; 804 } 805 } 806 807 if (!crtc_state->enable_psr2_sel_fetch && 808 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { 809 drm_dbg_kms(&dev_priv->drm, 810 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 811 crtc_hdisplay, crtc_vdisplay, 812 psr_max_h, psr_max_v); 813 return false; 814 } 815 816 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); 817 return true; 818 } 819 820 void intel_psr_compute_config(struct intel_dp *intel_dp, 821 struct intel_crtc_state *crtc_state) 822 { 823 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 824 const struct drm_display_mode *adjusted_mode = 825 &crtc_state->hw.adjusted_mode; 826 int psr_setup_time; 827 828 /* 829 * Current PSR panels dont work reliably with VRR enabled 830 * So if VRR is enabled, do not enable PSR. 831 */ 832 if (crtc_state->vrr.enable) 833 return; 834 835 if (!CAN_PSR(intel_dp)) 836 return; 837 838 if (!psr_global_enabled(intel_dp)) { 839 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); 840 return; 841 } 842 843 if (intel_dp->psr.sink_not_reliable) { 844 drm_dbg_kms(&dev_priv->drm, 845 "PSR sink implementation is not reliable\n"); 846 return; 847 } 848 849 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 850 drm_dbg_kms(&dev_priv->drm, 851 "PSR condition failed: Interlaced mode enabled\n"); 852 return; 853 } 854 855 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); 856 if (psr_setup_time < 0) { 857 drm_dbg_kms(&dev_priv->drm, 858 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 859 intel_dp->psr_dpcd[1]); 860 return; 861 } 862 863 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 864 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 865 drm_dbg_kms(&dev_priv->drm, 866 "PSR condition failed: PSR setup time (%d us) too long\n", 867 psr_setup_time); 868 return; 869 } 870 871 crtc_state->has_psr = true; 872 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); 873 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 874 } 875 876 static void intel_psr_activate(struct intel_dp *intel_dp) 877 { 878 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 879 enum transcoder transcoder = intel_dp->psr.transcoder; 880 881 if (transcoder_has_psr2(dev_priv, transcoder)) 882 drm_WARN_ON(&dev_priv->drm, 883 intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE); 884 885 drm_WARN_ON(&dev_priv->drm, 886 intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE); 887 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active); 888 lockdep_assert_held(&intel_dp->psr.lock); 889 890 /* psr1 and psr2 are mutually exclusive.*/ 891 if (intel_dp->psr.psr2_enabled) 892 hsw_activate_psr2(intel_dp); 893 else 894 hsw_activate_psr1(intel_dp); 895 896 intel_dp->psr.active = true; 897 } 898 899 static void intel_psr_enable_source(struct intel_dp *intel_dp, 900 const struct intel_crtc_state *crtc_state) 901 { 902 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 903 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 904 u32 mask; 905 906 /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+ 907 * use hardcoded values PSR AUX transactions 908 */ 909 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 910 hsw_psr_setup_aux(intel_dp); 911 912 if (intel_dp->psr.psr2_enabled && (IS_GEN(dev_priv, 9) && 913 !IS_GEMINILAKE(dev_priv))) { 914 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder); 915 u32 chicken = intel_de_read(dev_priv, reg); 916 917 chicken |= PSR2_VSC_ENABLE_PROG_HEADER | 918 PSR2_ADD_VERTICAL_LINE_COUNT; 919 intel_de_write(dev_priv, reg, chicken); 920 } 921 922 /* 923 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 924 * mask LPSP to avoid dependency on other drivers that might block 925 * runtime_pm besides preventing other hw tracking issues now we 926 * can rely on frontbuffer tracking. 927 */ 928 mask = EDP_PSR_DEBUG_MASK_MEMUP | 929 EDP_PSR_DEBUG_MASK_HPD | 930 EDP_PSR_DEBUG_MASK_LPSP | 931 EDP_PSR_DEBUG_MASK_MAX_SLEEP; 932 933 if (INTEL_GEN(dev_priv) < 11) 934 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 935 936 intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder), 937 mask); 938 939 psr_irq_control(intel_dp); 940 941 if (crtc_state->dc3co_exitline) { 942 u32 val; 943 944 /* 945 * TODO: if future platforms supports DC3CO in more than one 946 * transcoder, EXITLINE will need to be unset when disabling PSR 947 */ 948 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder)); 949 val &= ~EXITLINE_MASK; 950 val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT; 951 val |= EXITLINE_ENABLE; 952 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); 953 } 954 955 if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv)) 956 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, 957 intel_dp->psr.psr2_sel_fetch_enabled ? 958 IGNORE_PSR2_HW_TRACKING : 0); 959 } 960 961 static void intel_psr_enable_locked(struct intel_dp *intel_dp, 962 const struct intel_crtc_state *crtc_state, 963 const struct drm_connector_state *conn_state) 964 { 965 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 966 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 967 struct intel_encoder *encoder = &dig_port->base; 968 u32 val; 969 970 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); 971 972 intel_dp->psr.psr2_enabled = crtc_state->has_psr2; 973 intel_dp->psr.busy_frontbuffer_bits = 0; 974 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 975 intel_dp->psr.dc3co_enabled = !!crtc_state->dc3co_exitline; 976 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; 977 /* DC5/DC6 requires at least 6 idle frames */ 978 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 979 intel_dp->psr.dc3co_exit_delay = val; 980 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; 981 982 /* 983 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 984 * will still keep the error set even after the reset done in the 985 * irq_preinstall and irq_uninstall hooks. 986 * And enabling in this situation cause the screen to freeze in the 987 * first time that PSR HW tries to activate so lets keep PSR disabled 988 * to avoid any rendering problems. 989 */ 990 if (INTEL_GEN(dev_priv) >= 12) { 991 val = intel_de_read(dev_priv, 992 TRANS_PSR_IIR(intel_dp->psr.transcoder)); 993 val &= EDP_PSR_ERROR(0); 994 } else { 995 val = intel_de_read(dev_priv, EDP_PSR_IIR); 996 val &= EDP_PSR_ERROR(intel_dp->psr.transcoder); 997 } 998 if (val) { 999 intel_dp->psr.sink_not_reliable = true; 1000 drm_dbg_kms(&dev_priv->drm, 1001 "PSR interruption error set, not enabling PSR\n"); 1002 return; 1003 } 1004 1005 drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", 1006 intel_dp->psr.psr2_enabled ? "2" : "1"); 1007 intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, 1008 &intel_dp->psr.vsc); 1009 intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp->psr.vsc); 1010 intel_psr_enable_sink(intel_dp); 1011 intel_psr_enable_source(intel_dp, crtc_state); 1012 intel_dp->psr.enabled = true; 1013 1014 intel_psr_activate(intel_dp); 1015 } 1016 1017 /** 1018 * intel_psr_enable - Enable PSR 1019 * @intel_dp: Intel DP 1020 * @crtc_state: new CRTC state 1021 * @conn_state: new CONNECTOR state 1022 * 1023 * This function can only be called after the pipe is fully trained and enabled. 1024 */ 1025 void intel_psr_enable(struct intel_dp *intel_dp, 1026 const struct intel_crtc_state *crtc_state, 1027 const struct drm_connector_state *conn_state) 1028 { 1029 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1030 1031 if (!CAN_PSR(intel_dp)) 1032 return; 1033 1034 if (!crtc_state->has_psr) 1035 return; 1036 1037 drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp); 1038 1039 mutex_lock(&intel_dp->psr.lock); 1040 intel_psr_enable_locked(intel_dp, crtc_state, conn_state); 1041 mutex_unlock(&intel_dp->psr.lock); 1042 } 1043 1044 static void intel_psr_exit(struct intel_dp *intel_dp) 1045 { 1046 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1047 u32 val; 1048 1049 if (!intel_dp->psr.active) { 1050 if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) { 1051 val = intel_de_read(dev_priv, 1052 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1053 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE); 1054 } 1055 1056 val = intel_de_read(dev_priv, 1057 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1058 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE); 1059 1060 return; 1061 } 1062 1063 if (intel_dp->psr.psr2_enabled) { 1064 tgl_disallow_dc3co_on_psr2_exit(intel_dp); 1065 val = intel_de_read(dev_priv, 1066 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1067 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE)); 1068 val &= ~EDP_PSR2_ENABLE; 1069 intel_de_write(dev_priv, 1070 EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 1071 } else { 1072 val = intel_de_read(dev_priv, 1073 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1074 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE)); 1075 val &= ~EDP_PSR_ENABLE; 1076 intel_de_write(dev_priv, 1077 EDP_PSR_CTL(intel_dp->psr.transcoder), val); 1078 } 1079 intel_dp->psr.active = false; 1080 } 1081 1082 static void intel_psr_disable_locked(struct intel_dp *intel_dp) 1083 { 1084 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1085 i915_reg_t psr_status; 1086 u32 psr_status_mask; 1087 1088 lockdep_assert_held(&intel_dp->psr.lock); 1089 1090 if (!intel_dp->psr.enabled) 1091 return; 1092 1093 drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", 1094 intel_dp->psr.psr2_enabled ? "2" : "1"); 1095 1096 intel_psr_exit(intel_dp); 1097 1098 if (intel_dp->psr.psr2_enabled) { 1099 psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 1100 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 1101 } else { 1102 psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder); 1103 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 1104 } 1105 1106 /* Wait till PSR is idle */ 1107 if (intel_de_wait_for_clear(dev_priv, psr_status, 1108 psr_status_mask, 2000)) 1109 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n"); 1110 1111 /* WA 1408330847 */ 1112 if (intel_dp->psr.psr2_sel_fetch_enabled && 1113 (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) || 1114 IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))) 1115 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1116 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0); 1117 1118 /* Disable PSR on Sink */ 1119 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 1120 1121 if (intel_dp->psr.psr2_enabled) 1122 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); 1123 1124 intel_dp->psr.enabled = false; 1125 } 1126 1127 /** 1128 * intel_psr_disable - Disable PSR 1129 * @intel_dp: Intel DP 1130 * @old_crtc_state: old CRTC state 1131 * 1132 * This function needs to be called before disabling pipe. 1133 */ 1134 void intel_psr_disable(struct intel_dp *intel_dp, 1135 const struct intel_crtc_state *old_crtc_state) 1136 { 1137 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1138 1139 if (!old_crtc_state->has_psr) 1140 return; 1141 1142 if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp))) 1143 return; 1144 1145 mutex_lock(&intel_dp->psr.lock); 1146 1147 intel_psr_disable_locked(intel_dp); 1148 1149 mutex_unlock(&intel_dp->psr.lock); 1150 cancel_work_sync(&intel_dp->psr.work); 1151 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); 1152 } 1153 1154 static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) 1155 { 1156 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1157 1158 if (IS_TIGERLAKE(dev_priv)) 1159 /* 1160 * Writes to CURSURFLIVE in TGL are causing IOMMU errors and 1161 * visual glitches that are often reproduced when executing 1162 * CPU intensive workloads while a eDP 4K panel is attached. 1163 * 1164 * Manually exiting PSR causes the frontbuffer to be updated 1165 * without glitches and the IOMMU errors are also gone but 1166 * this comes at the cost of less time with PSR active. 1167 * 1168 * So using this workaround until this issue is root caused 1169 * and a better fix is found. 1170 */ 1171 intel_psr_exit(intel_dp); 1172 else if (INTEL_GEN(dev_priv) >= 9) 1173 /* 1174 * Display WA #0884: skl+ 1175 * This documented WA for bxt can be safely applied 1176 * broadly so we can force HW tracking to exit PSR 1177 * instead of disabling and re-enabling. 1178 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 1179 * but it makes more sense write to the current active 1180 * pipe. 1181 */ 1182 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 1183 else 1184 /* 1185 * A write to CURSURFLIVE do not cause HW tracking to exit PSR 1186 * on older gens so doing the manual exit instead. 1187 */ 1188 intel_psr_exit(intel_dp); 1189 } 1190 1191 void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, 1192 const struct intel_crtc_state *crtc_state, 1193 const struct intel_plane_state *plane_state, 1194 int color_plane) 1195 { 1196 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1197 enum pipe pipe = plane->pipe; 1198 const struct drm_rect *clip; 1199 u32 val, offset; 1200 int ret, x, y; 1201 1202 if (!crtc_state->enable_psr2_sel_fetch) 1203 return; 1204 1205 val = plane_state ? plane_state->ctl : 0; 1206 val &= plane->id == PLANE_CURSOR ? val : PLANE_SEL_FETCH_CTL_ENABLE; 1207 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val); 1208 if (!val || plane->id == PLANE_CURSOR) 1209 return; 1210 1211 clip = &plane_state->psr2_sel_fetch_area; 1212 1213 val = (clip->y1 + plane_state->uapi.dst.y1) << 16; 1214 val |= plane_state->uapi.dst.x1; 1215 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); 1216 1217 /* TODO: consider auxiliary surfaces */ 1218 x = plane_state->uapi.src.x1 >> 16; 1219 y = (plane_state->uapi.src.y1 >> 16) + clip->y1; 1220 ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset); 1221 if (ret) 1222 drm_warn_once(&dev_priv->drm, "skl_calc_main_surface_offset() returned %i\n", 1223 ret); 1224 val = y << 16 | x; 1225 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), 1226 val); 1227 1228 /* Sizes are 0 based */ 1229 val = (drm_rect_height(clip) - 1) << 16; 1230 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; 1231 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); 1232 } 1233 1234 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) 1235 { 1236 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1237 1238 if (!HAS_PSR2_SEL_FETCH(dev_priv) || 1239 !crtc_state->enable_psr2_sel_fetch) 1240 return; 1241 1242 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder), 1243 crtc_state->psr2_man_track_ctl); 1244 } 1245 1246 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, 1247 struct drm_rect *clip, bool full_update) 1248 { 1249 u32 val = PSR2_MAN_TRK_CTL_ENABLE; 1250 1251 if (full_update) { 1252 val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 1253 goto exit; 1254 } 1255 1256 if (clip->y1 == -1) 1257 goto exit; 1258 1259 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4); 1260 1261 val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; 1262 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1); 1263 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1); 1264 exit: 1265 crtc_state->psr2_man_track_ctl = val; 1266 } 1267 1268 static void clip_area_update(struct drm_rect *overlap_damage_area, 1269 struct drm_rect *damage_area) 1270 { 1271 if (overlap_damage_area->y1 == -1) { 1272 overlap_damage_area->y1 = damage_area->y1; 1273 overlap_damage_area->y2 = damage_area->y2; 1274 return; 1275 } 1276 1277 if (damage_area->y1 < overlap_damage_area->y1) 1278 overlap_damage_area->y1 = damage_area->y1; 1279 1280 if (damage_area->y2 > overlap_damage_area->y2) 1281 overlap_damage_area->y2 = damage_area->y2; 1282 } 1283 1284 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 1285 struct intel_crtc *crtc) 1286 { 1287 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 1288 struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 }; 1289 struct intel_plane_state *new_plane_state, *old_plane_state; 1290 struct intel_plane *plane; 1291 bool full_update = false; 1292 int i, ret; 1293 1294 if (!crtc_state->enable_psr2_sel_fetch) 1295 return 0; 1296 1297 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 1298 if (ret) 1299 return ret; 1300 1301 /* 1302 * Calculate minimal selective fetch area of each plane and calculate 1303 * the pipe damaged area. 1304 * In the next loop the plane selective fetch area will actually be set 1305 * using whole pipe damaged area. 1306 */ 1307 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1308 new_plane_state, i) { 1309 struct drm_rect src, damaged_area = { .y1 = -1 }; 1310 struct drm_mode_rect *damaged_clips; 1311 u32 num_clips, j; 1312 1313 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) 1314 continue; 1315 1316 if (!new_plane_state->uapi.visible && 1317 !old_plane_state->uapi.visible) 1318 continue; 1319 1320 /* 1321 * TODO: Not clear how to handle planes with negative position, 1322 * also planes are not updated if they have a negative X 1323 * position so for now doing a full update in this cases 1324 */ 1325 if (new_plane_state->uapi.dst.y1 < 0 || 1326 new_plane_state->uapi.dst.x1 < 0) { 1327 full_update = true; 1328 break; 1329 } 1330 1331 num_clips = drm_plane_get_damage_clips_count(&new_plane_state->uapi); 1332 1333 /* 1334 * If visibility or plane moved, mark the whole plane area as 1335 * damaged as it needs to be complete redraw in the new and old 1336 * position. 1337 */ 1338 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || 1339 !drm_rect_equals(&new_plane_state->uapi.dst, 1340 &old_plane_state->uapi.dst)) { 1341 if (old_plane_state->uapi.visible) { 1342 damaged_area.y1 = old_plane_state->uapi.dst.y1; 1343 damaged_area.y2 = old_plane_state->uapi.dst.y2; 1344 clip_area_update(&pipe_clip, &damaged_area); 1345 } 1346 1347 if (new_plane_state->uapi.visible) { 1348 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1349 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1350 clip_area_update(&pipe_clip, &damaged_area); 1351 } 1352 continue; 1353 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha || 1354 (!num_clips && 1355 new_plane_state->uapi.fb != old_plane_state->uapi.fb)) { 1356 /* 1357 * If the plane don't have damaged areas but the 1358 * framebuffer changed or alpha changed, mark the whole 1359 * plane area as damaged. 1360 */ 1361 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1362 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1363 clip_area_update(&pipe_clip, &damaged_area); 1364 continue; 1365 } 1366 1367 drm_rect_fp_to_int(&src, &new_plane_state->uapi.src); 1368 damaged_clips = drm_plane_get_damage_clips(&new_plane_state->uapi); 1369 1370 for (j = 0; j < num_clips; j++) { 1371 struct drm_rect clip; 1372 1373 clip.x1 = damaged_clips[j].x1; 1374 clip.y1 = damaged_clips[j].y1; 1375 clip.x2 = damaged_clips[j].x2; 1376 clip.y2 = damaged_clips[j].y2; 1377 if (drm_rect_intersect(&clip, &src)) 1378 clip_area_update(&damaged_area, &clip); 1379 } 1380 1381 if (damaged_area.y1 == -1) 1382 continue; 1383 1384 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; 1385 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; 1386 clip_area_update(&pipe_clip, &damaged_area); 1387 } 1388 1389 if (full_update) 1390 goto skip_sel_fetch_set_loop; 1391 1392 /* It must be aligned to 4 lines */ 1393 pipe_clip.y1 -= pipe_clip.y1 % 4; 1394 if (pipe_clip.y2 % 4) 1395 pipe_clip.y2 = ((pipe_clip.y2 / 4) + 1) * 4; 1396 1397 /* 1398 * Now that we have the pipe damaged area check if it intersect with 1399 * every plane, if it does set the plane selective fetch area. 1400 */ 1401 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1402 new_plane_state, i) { 1403 struct drm_rect *sel_fetch_area, inter; 1404 1405 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || 1406 !new_plane_state->uapi.visible) 1407 continue; 1408 1409 inter = pipe_clip; 1410 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) 1411 continue; 1412 1413 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 1414 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; 1415 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; 1416 } 1417 1418 skip_sel_fetch_set_loop: 1419 psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update); 1420 return 0; 1421 } 1422 1423 /** 1424 * intel_psr_update - Update PSR state 1425 * @intel_dp: Intel DP 1426 * @crtc_state: new CRTC state 1427 * @conn_state: new CONNECTOR state 1428 * 1429 * This functions will update PSR states, disabling, enabling or switching PSR 1430 * version when executing fastsets. For full modeset, intel_psr_disable() and 1431 * intel_psr_enable() should be called instead. 1432 */ 1433 void intel_psr_update(struct intel_dp *intel_dp, 1434 const struct intel_crtc_state *crtc_state, 1435 const struct drm_connector_state *conn_state) 1436 { 1437 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1438 struct intel_psr *psr = &intel_dp->psr; 1439 bool enable, psr2_enable; 1440 1441 if (!CAN_PSR(intel_dp)) 1442 return; 1443 1444 mutex_lock(&intel_dp->psr.lock); 1445 1446 enable = crtc_state->has_psr; 1447 psr2_enable = crtc_state->has_psr2; 1448 1449 if (enable == psr->enabled && psr2_enable == psr->psr2_enabled && 1450 crtc_state->enable_psr2_sel_fetch == psr->psr2_sel_fetch_enabled) { 1451 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 1452 if (crtc_state->crc_enabled && psr->enabled) 1453 psr_force_hw_tracking_exit(intel_dp); 1454 else if (INTEL_GEN(dev_priv) < 9 && psr->enabled) { 1455 /* 1456 * Activate PSR again after a force exit when enabling 1457 * CRC in older gens 1458 */ 1459 if (!intel_dp->psr.active && 1460 !intel_dp->psr.busy_frontbuffer_bits) 1461 schedule_work(&intel_dp->psr.work); 1462 } 1463 1464 goto unlock; 1465 } 1466 1467 if (psr->enabled) 1468 intel_psr_disable_locked(intel_dp); 1469 1470 if (enable) 1471 intel_psr_enable_locked(intel_dp, crtc_state, conn_state); 1472 1473 unlock: 1474 mutex_unlock(&intel_dp->psr.lock); 1475 } 1476 1477 /** 1478 * psr_wait_for_idle - wait for PSR1 to idle 1479 * @intel_dp: Intel DP 1480 * @out_value: PSR status in case of failure 1481 * 1482 * Returns: 0 on success or -ETIMEOUT if PSR status does not idle. 1483 * 1484 */ 1485 static int psr_wait_for_idle(struct intel_dp *intel_dp, u32 *out_value) 1486 { 1487 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1488 1489 /* 1490 * From bspec: Panel Self Refresh (BDW+) 1491 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 1492 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 1493 * defensive enough to cover everything. 1494 */ 1495 return __intel_wait_for_register(&dev_priv->uncore, 1496 EDP_PSR_STATUS(intel_dp->psr.transcoder), 1497 EDP_PSR_STATUS_STATE_MASK, 1498 EDP_PSR_STATUS_STATE_IDLE, 2, 50, 1499 out_value); 1500 } 1501 1502 /** 1503 * intel_psr_wait_for_idle - wait for PSR1 to idle 1504 * @new_crtc_state: new CRTC state 1505 * 1506 * This function is expected to be called from pipe_update_start() where it is 1507 * not expected to race with PSR enable or disable. 1508 */ 1509 void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state) 1510 { 1511 struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev); 1512 struct intel_encoder *encoder; 1513 1514 if (!new_crtc_state->has_psr) 1515 return; 1516 1517 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, 1518 new_crtc_state->uapi.encoder_mask) { 1519 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1520 u32 psr_status; 1521 1522 mutex_lock(&intel_dp->psr.lock); 1523 if (!intel_dp->psr.enabled || 1524 (intel_dp->psr.enabled && intel_dp->psr.psr2_enabled)) { 1525 mutex_unlock(&intel_dp->psr.lock); 1526 continue; 1527 } 1528 1529 /* when the PSR1 is enabled */ 1530 if (psr_wait_for_idle(intel_dp, &psr_status)) 1531 drm_err(&dev_priv->drm, 1532 "PSR idle timed out 0x%x, atomic update may fail\n", 1533 psr_status); 1534 mutex_unlock(&intel_dp->psr.lock); 1535 } 1536 } 1537 1538 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) 1539 { 1540 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1541 i915_reg_t reg; 1542 u32 mask; 1543 int err; 1544 1545 if (!intel_dp->psr.enabled) 1546 return false; 1547 1548 if (intel_dp->psr.psr2_enabled) { 1549 reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 1550 mask = EDP_PSR2_STATUS_STATE_MASK; 1551 } else { 1552 reg = EDP_PSR_STATUS(intel_dp->psr.transcoder); 1553 mask = EDP_PSR_STATUS_STATE_MASK; 1554 } 1555 1556 mutex_unlock(&intel_dp->psr.lock); 1557 1558 err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); 1559 if (err) 1560 drm_err(&dev_priv->drm, 1561 "Timed out waiting for PSR Idle for re-enable\n"); 1562 1563 /* After the unlocked wait, verify that PSR is still wanted! */ 1564 mutex_lock(&intel_dp->psr.lock); 1565 return err == 0 && intel_dp->psr.enabled; 1566 } 1567 1568 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) 1569 { 1570 struct drm_connector_list_iter conn_iter; 1571 struct drm_device *dev = &dev_priv->drm; 1572 struct drm_modeset_acquire_ctx ctx; 1573 struct drm_atomic_state *state; 1574 struct drm_connector *conn; 1575 int err = 0; 1576 1577 state = drm_atomic_state_alloc(dev); 1578 if (!state) 1579 return -ENOMEM; 1580 1581 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1582 state->acquire_ctx = &ctx; 1583 1584 retry: 1585 1586 drm_connector_list_iter_begin(dev, &conn_iter); 1587 drm_for_each_connector_iter(conn, &conn_iter) { 1588 struct drm_connector_state *conn_state; 1589 struct drm_crtc_state *crtc_state; 1590 1591 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) 1592 continue; 1593 1594 conn_state = drm_atomic_get_connector_state(state, conn); 1595 if (IS_ERR(conn_state)) { 1596 err = PTR_ERR(conn_state); 1597 break; 1598 } 1599 1600 if (!conn_state->crtc) 1601 continue; 1602 1603 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); 1604 if (IS_ERR(crtc_state)) { 1605 err = PTR_ERR(crtc_state); 1606 break; 1607 } 1608 1609 /* Mark mode as changed to trigger a pipe->update() */ 1610 crtc_state->mode_changed = true; 1611 } 1612 drm_connector_list_iter_end(&conn_iter); 1613 1614 if (err == 0) 1615 err = drm_atomic_commit(state); 1616 1617 if (err == -EDEADLK) { 1618 drm_atomic_state_clear(state); 1619 err = drm_modeset_backoff(&ctx); 1620 if (!err) 1621 goto retry; 1622 } 1623 1624 drm_modeset_drop_locks(&ctx); 1625 drm_modeset_acquire_fini(&ctx); 1626 drm_atomic_state_put(state); 1627 1628 return err; 1629 } 1630 1631 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) 1632 { 1633 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1634 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 1635 u32 old_mode; 1636 int ret; 1637 1638 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || 1639 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 1640 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); 1641 return -EINVAL; 1642 } 1643 1644 ret = mutex_lock_interruptible(&intel_dp->psr.lock); 1645 if (ret) 1646 return ret; 1647 1648 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; 1649 intel_dp->psr.debug = val; 1650 1651 /* 1652 * Do it right away if it's already enabled, otherwise it will be done 1653 * when enabling the source. 1654 */ 1655 if (intel_dp->psr.enabled) 1656 psr_irq_control(intel_dp); 1657 1658 mutex_unlock(&intel_dp->psr.lock); 1659 1660 if (old_mode != mode) 1661 ret = intel_psr_fastset_force(dev_priv); 1662 1663 return ret; 1664 } 1665 1666 static void intel_psr_handle_irq(struct intel_dp *intel_dp) 1667 { 1668 struct intel_psr *psr = &intel_dp->psr; 1669 1670 intel_psr_disable_locked(intel_dp); 1671 psr->sink_not_reliable = true; 1672 /* let's make sure that sink is awaken */ 1673 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 1674 } 1675 1676 static void intel_psr_work(struct work_struct *work) 1677 { 1678 struct intel_dp *intel_dp = 1679 container_of(work, typeof(*intel_dp), psr.work); 1680 1681 mutex_lock(&intel_dp->psr.lock); 1682 1683 if (!intel_dp->psr.enabled) 1684 goto unlock; 1685 1686 if (READ_ONCE(intel_dp->psr.irq_aux_error)) 1687 intel_psr_handle_irq(intel_dp); 1688 1689 /* 1690 * We have to make sure PSR is ready for re-enable 1691 * otherwise it keeps disabled until next full enable/disable cycle. 1692 * PSR might take some time to get fully disabled 1693 * and be ready for re-enable. 1694 */ 1695 if (!__psr_wait_for_idle_locked(intel_dp)) 1696 goto unlock; 1697 1698 /* 1699 * The delayed work can race with an invalidate hence we need to 1700 * recheck. Since psr_flush first clears this and then reschedules we 1701 * won't ever miss a flush when bailing out here. 1702 */ 1703 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) 1704 goto unlock; 1705 1706 intel_psr_activate(intel_dp); 1707 unlock: 1708 mutex_unlock(&intel_dp->psr.lock); 1709 } 1710 1711 /** 1712 * intel_psr_invalidate - Invalidade PSR 1713 * @dev_priv: i915 device 1714 * @frontbuffer_bits: frontbuffer plane tracking bits 1715 * @origin: which operation caused the invalidate 1716 * 1717 * Since the hardware frontbuffer tracking has gaps we need to integrate 1718 * with the software frontbuffer tracking. This function gets called every 1719 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 1720 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 1721 * 1722 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 1723 */ 1724 void intel_psr_invalidate(struct drm_i915_private *dev_priv, 1725 unsigned frontbuffer_bits, enum fb_op_origin origin) 1726 { 1727 struct intel_encoder *encoder; 1728 1729 if (origin == ORIGIN_FLIP) 1730 return; 1731 1732 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 1733 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 1734 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1735 1736 mutex_lock(&intel_dp->psr.lock); 1737 if (!intel_dp->psr.enabled) { 1738 mutex_unlock(&intel_dp->psr.lock); 1739 continue; 1740 } 1741 1742 pipe_frontbuffer_bits &= 1743 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 1744 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; 1745 1746 if (pipe_frontbuffer_bits) 1747 intel_psr_exit(intel_dp); 1748 1749 mutex_unlock(&intel_dp->psr.lock); 1750 } 1751 } 1752 /* 1753 * When we will be completely rely on PSR2 S/W tracking in future, 1754 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP 1755 * event also therefore tgl_dc3co_flush() require to be changed 1756 * accordingly in future. 1757 */ 1758 static void 1759 tgl_dc3co_flush(struct intel_dp *intel_dp, unsigned int frontbuffer_bits, 1760 enum fb_op_origin origin) 1761 { 1762 mutex_lock(&intel_dp->psr.lock); 1763 1764 if (!intel_dp->psr.dc3co_enabled) 1765 goto unlock; 1766 1767 if (!intel_dp->psr.psr2_enabled || !intel_dp->psr.active) 1768 goto unlock; 1769 1770 /* 1771 * At every frontbuffer flush flip event modified delay of delayed work, 1772 * when delayed work schedules that means display has been idle. 1773 */ 1774 if (!(frontbuffer_bits & 1775 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) 1776 goto unlock; 1777 1778 tgl_psr2_enable_dc3co(intel_dp); 1779 mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work, 1780 intel_dp->psr.dc3co_exit_delay); 1781 1782 unlock: 1783 mutex_unlock(&intel_dp->psr.lock); 1784 } 1785 1786 /** 1787 * intel_psr_flush - Flush PSR 1788 * @dev_priv: i915 device 1789 * @frontbuffer_bits: frontbuffer plane tracking bits 1790 * @origin: which operation caused the flush 1791 * 1792 * Since the hardware frontbuffer tracking has gaps we need to integrate 1793 * with the software frontbuffer tracking. This function gets called every 1794 * time frontbuffer rendering has completed and flushed out to memory. PSR 1795 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 1796 * 1797 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 1798 */ 1799 void intel_psr_flush(struct drm_i915_private *dev_priv, 1800 unsigned frontbuffer_bits, enum fb_op_origin origin) 1801 { 1802 struct intel_encoder *encoder; 1803 1804 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 1805 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 1806 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1807 1808 if (origin == ORIGIN_FLIP) { 1809 tgl_dc3co_flush(intel_dp, frontbuffer_bits, origin); 1810 continue; 1811 } 1812 1813 mutex_lock(&intel_dp->psr.lock); 1814 if (!intel_dp->psr.enabled) { 1815 mutex_unlock(&intel_dp->psr.lock); 1816 continue; 1817 } 1818 1819 pipe_frontbuffer_bits &= 1820 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 1821 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; 1822 1823 /* By definition flush = invalidate + flush */ 1824 if (pipe_frontbuffer_bits) 1825 psr_force_hw_tracking_exit(intel_dp); 1826 1827 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) 1828 schedule_work(&intel_dp->psr.work); 1829 mutex_unlock(&intel_dp->psr.lock); 1830 } 1831 } 1832 1833 /** 1834 * intel_psr_init - Init basic PSR work and mutex. 1835 * @intel_dp: Intel DP 1836 * 1837 * This function is called after the initializing connector. 1838 * (the initializing of connector treats the handling of connector capabilities) 1839 * And it initializes basic PSR stuff for each DP Encoder. 1840 */ 1841 void intel_psr_init(struct intel_dp *intel_dp) 1842 { 1843 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1844 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1845 1846 if (!HAS_PSR(dev_priv)) 1847 return; 1848 1849 /* 1850 * HSW spec explicitly says PSR is tied to port A. 1851 * BDW+ platforms have a instance of PSR registers per transcoder but 1852 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder 1853 * than eDP one. 1854 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11. 1855 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11. 1856 * But GEN12 supports a instance of PSR registers per transcoder. 1857 */ 1858 if (INTEL_GEN(dev_priv) < 12 && dig_port->base.port != PORT_A) { 1859 drm_dbg_kms(&dev_priv->drm, 1860 "PSR condition failed: Port not supported\n"); 1861 return; 1862 } 1863 1864 intel_dp->psr.source_support = true; 1865 1866 if (IS_HASWELL(dev_priv)) 1867 /* 1868 * HSW don't have PSR registers on the same space as transcoder 1869 * so set this to a value that when subtract to the register 1870 * in transcoder space results in the right offset for HSW 1871 */ 1872 dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE; 1873 1874 if (dev_priv->params.enable_psr == -1) 1875 if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable) 1876 dev_priv->params.enable_psr = 0; 1877 1878 /* Set link_standby x link_off defaults */ 1879 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 1880 /* HSW and BDW require workarounds that we don't implement. */ 1881 intel_dp->psr.link_standby = false; 1882 else if (INTEL_GEN(dev_priv) < 12) 1883 /* For new platforms up to TGL let's respect VBT back again */ 1884 intel_dp->psr.link_standby = dev_priv->vbt.psr.full_link; 1885 1886 INIT_WORK(&intel_dp->psr.work, intel_psr_work); 1887 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); 1888 mutex_init(&intel_dp->psr.lock); 1889 } 1890 1891 static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 1892 u8 *status, u8 *error_status) 1893 { 1894 struct drm_dp_aux *aux = &intel_dp->aux; 1895 int ret; 1896 1897 ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status); 1898 if (ret != 1) 1899 return ret; 1900 1901 ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status); 1902 if (ret != 1) 1903 return ret; 1904 1905 *status = *status & DP_PSR_SINK_STATE_MASK; 1906 1907 return 0; 1908 } 1909 1910 static void psr_alpm_check(struct intel_dp *intel_dp) 1911 { 1912 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1913 struct drm_dp_aux *aux = &intel_dp->aux; 1914 struct intel_psr *psr = &intel_dp->psr; 1915 u8 val; 1916 int r; 1917 1918 if (!psr->psr2_enabled) 1919 return; 1920 1921 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); 1922 if (r != 1) { 1923 drm_err(&dev_priv->drm, "Error reading ALPM status\n"); 1924 return; 1925 } 1926 1927 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) { 1928 intel_psr_disable_locked(intel_dp); 1929 psr->sink_not_reliable = true; 1930 drm_dbg_kms(&dev_priv->drm, 1931 "ALPM lock timeout error, disabling PSR\n"); 1932 1933 /* Clearing error */ 1934 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); 1935 } 1936 } 1937 1938 static void psr_capability_changed_check(struct intel_dp *intel_dp) 1939 { 1940 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1941 struct intel_psr *psr = &intel_dp->psr; 1942 u8 val; 1943 int r; 1944 1945 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 1946 if (r != 1) { 1947 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n"); 1948 return; 1949 } 1950 1951 if (val & DP_PSR_CAPS_CHANGE) { 1952 intel_psr_disable_locked(intel_dp); 1953 psr->sink_not_reliable = true; 1954 drm_dbg_kms(&dev_priv->drm, 1955 "Sink PSR capability changed, disabling PSR\n"); 1956 1957 /* Clearing it */ 1958 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 1959 } 1960 } 1961 1962 void intel_psr_short_pulse(struct intel_dp *intel_dp) 1963 { 1964 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1965 struct intel_psr *psr = &intel_dp->psr; 1966 u8 status, error_status; 1967 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 1968 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 1969 DP_PSR_LINK_CRC_ERROR; 1970 1971 if (!CAN_PSR(intel_dp)) 1972 return; 1973 1974 mutex_lock(&psr->lock); 1975 1976 if (!psr->enabled) 1977 goto exit; 1978 1979 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 1980 drm_err(&dev_priv->drm, 1981 "Error reading PSR status or error status\n"); 1982 goto exit; 1983 } 1984 1985 if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) { 1986 intel_psr_disable_locked(intel_dp); 1987 psr->sink_not_reliable = true; 1988 } 1989 1990 if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status) 1991 drm_dbg_kms(&dev_priv->drm, 1992 "PSR sink internal error, disabling PSR\n"); 1993 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 1994 drm_dbg_kms(&dev_priv->drm, 1995 "PSR RFB storage error, disabling PSR\n"); 1996 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 1997 drm_dbg_kms(&dev_priv->drm, 1998 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 1999 if (error_status & DP_PSR_LINK_CRC_ERROR) 2000 drm_dbg_kms(&dev_priv->drm, 2001 "PSR Link CRC error, disabling PSR\n"); 2002 2003 if (error_status & ~errors) 2004 drm_err(&dev_priv->drm, 2005 "PSR_ERROR_STATUS unhandled errors %x\n", 2006 error_status & ~errors); 2007 /* clear status register */ 2008 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 2009 2010 psr_alpm_check(intel_dp); 2011 psr_capability_changed_check(intel_dp); 2012 2013 exit: 2014 mutex_unlock(&psr->lock); 2015 } 2016 2017 bool intel_psr_enabled(struct intel_dp *intel_dp) 2018 { 2019 bool ret; 2020 2021 if (!CAN_PSR(intel_dp)) 2022 return false; 2023 2024 mutex_lock(&intel_dp->psr.lock); 2025 ret = intel_dp->psr.enabled; 2026 mutex_unlock(&intel_dp->psr.lock); 2027 2028 return ret; 2029 } 2030