1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <drm/drm_atomic_helper.h> 25 26 #include "display/intel_dp.h" 27 28 #include "i915_drv.h" 29 #include "intel_atomic.h" 30 #include "intel_display_types.h" 31 #include "intel_psr.h" 32 #include "intel_sprite.h" 33 #include "intel_hdmi.h" 34 35 /** 36 * DOC: Panel Self Refresh (PSR/SRD) 37 * 38 * Since Haswell Display controller supports Panel Self-Refresh on display 39 * panels witch have a remote frame buffer (RFB) implemented according to PSR 40 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 41 * when system is idle but display is on as it eliminates display refresh 42 * request to DDR memory completely as long as the frame buffer for that 43 * display is unchanged. 44 * 45 * Panel Self Refresh must be supported by both Hardware (source) and 46 * Panel (sink). 47 * 48 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 49 * to power down the link and memory controller. For DSI panels the same idea 50 * is called "manual mode". 51 * 52 * The implementation uses the hardware-based PSR support which automatically 53 * enters/exits self-refresh mode. The hardware takes care of sending the 54 * required DP aux message and could even retrain the link (that part isn't 55 * enabled yet though). The hardware also keeps track of any frontbuffer 56 * changes to know when to exit self-refresh mode again. Unfortunately that 57 * part doesn't work too well, hence why the i915 PSR support uses the 58 * software frontbuffer tracking to make sure it doesn't miss a screen 59 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 60 * get called by the frontbuffer tracking code. Note that because of locking 61 * issues the self-refresh re-enable code is done from a work queue, which 62 * must be correctly synchronized/cancelled when shutting down the pipe." 63 * 64 * DC3CO (DC3 clock off) 65 * 66 * On top of PSR2, GEN12 adds a intermediate power savings state that turns 67 * clock off automatically during PSR2 idle state. 68 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep 69 * entry/exit allows the HW to enter a low-power state even when page flipping 70 * periodically (for instance a 30fps video playback scenario). 71 * 72 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), 73 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 74 * frames, if no other flip occurs and the function above is executed, DC3CO is 75 * disabled and PSR2 is configured to enter deep sleep, resetting again in case 76 * of another flip. 77 * Front buffer modifications do not trigger DC3CO activation on purpose as it 78 * would bring a lot of complexity and most of the moderns systems will only 79 * use page flips. 80 */ 81 82 static bool psr_global_enabled(struct drm_i915_private *i915) 83 { 84 switch (i915->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 85 case I915_PSR_DEBUG_DEFAULT: 86 return i915->params.enable_psr; 87 case I915_PSR_DEBUG_DISABLE: 88 return false; 89 default: 90 return true; 91 } 92 } 93 94 static bool psr2_global_enabled(struct drm_i915_private *dev_priv) 95 { 96 switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 97 case I915_PSR_DEBUG_DISABLE: 98 case I915_PSR_DEBUG_FORCE_PSR1: 99 return false; 100 default: 101 return true; 102 } 103 } 104 105 static void psr_irq_control(struct drm_i915_private *dev_priv) 106 { 107 enum transcoder trans_shift; 108 u32 mask, val; 109 i915_reg_t imr_reg; 110 111 /* 112 * gen12+ has registers relative to transcoder and one per transcoder 113 * using the same bit definition: handle it as TRANSCODER_EDP to force 114 * 0 shift in bit definition 115 */ 116 if (INTEL_GEN(dev_priv) >= 12) { 117 trans_shift = 0; 118 imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder); 119 } else { 120 trans_shift = dev_priv->psr.transcoder; 121 imr_reg = EDP_PSR_IMR; 122 } 123 124 mask = EDP_PSR_ERROR(trans_shift); 125 if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ) 126 mask |= EDP_PSR_POST_EXIT(trans_shift) | 127 EDP_PSR_PRE_ENTRY(trans_shift); 128 129 /* Warning: it is masking/setting reserved bits too */ 130 val = intel_de_read(dev_priv, imr_reg); 131 val &= ~EDP_PSR_TRANS_MASK(trans_shift); 132 val |= ~mask; 133 intel_de_write(dev_priv, imr_reg, val); 134 } 135 136 static void psr_event_print(struct drm_i915_private *i915, 137 u32 val, bool psr2_enabled) 138 { 139 drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val); 140 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 141 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n"); 142 if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) 143 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n"); 144 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 145 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n"); 146 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 147 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n"); 148 if (val & PSR_EVENT_GRAPHICS_RESET) 149 drm_dbg_kms(&i915->drm, "\tGraphics reset\n"); 150 if (val & PSR_EVENT_PCH_INTERRUPT) 151 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n"); 152 if (val & PSR_EVENT_MEMORY_UP) 153 drm_dbg_kms(&i915->drm, "\tMemory up\n"); 154 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 155 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n"); 156 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 157 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n"); 158 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 159 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n"); 160 if (val & PSR_EVENT_REGISTER_UPDATE) 161 drm_dbg_kms(&i915->drm, "\tRegister updated\n"); 162 if (val & PSR_EVENT_HDCP_ENABLE) 163 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n"); 164 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 165 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n"); 166 if (val & PSR_EVENT_VBI_ENABLE) 167 drm_dbg_kms(&i915->drm, "\tVBI enabled\n"); 168 if (val & PSR_EVENT_LPSP_MODE_EXIT) 169 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n"); 170 if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) 171 drm_dbg_kms(&i915->drm, "\tPSR disabled\n"); 172 } 173 174 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) 175 { 176 enum transcoder cpu_transcoder = dev_priv->psr.transcoder; 177 enum transcoder trans_shift; 178 i915_reg_t imr_reg; 179 ktime_t time_ns = ktime_get(); 180 181 if (INTEL_GEN(dev_priv) >= 12) { 182 trans_shift = 0; 183 imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder); 184 } else { 185 trans_shift = dev_priv->psr.transcoder; 186 imr_reg = EDP_PSR_IMR; 187 } 188 189 if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) { 190 dev_priv->psr.last_entry_attempt = time_ns; 191 drm_dbg_kms(&dev_priv->drm, 192 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 193 transcoder_name(cpu_transcoder)); 194 } 195 196 if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) { 197 dev_priv->psr.last_exit = time_ns; 198 drm_dbg_kms(&dev_priv->drm, 199 "[transcoder %s] PSR exit completed\n", 200 transcoder_name(cpu_transcoder)); 201 202 if (INTEL_GEN(dev_priv) >= 9) { 203 u32 val = intel_de_read(dev_priv, 204 PSR_EVENT(cpu_transcoder)); 205 bool psr2_enabled = dev_priv->psr.psr2_enabled; 206 207 intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder), 208 val); 209 psr_event_print(dev_priv, val, psr2_enabled); 210 } 211 } 212 213 if (psr_iir & EDP_PSR_ERROR(trans_shift)) { 214 u32 val; 215 216 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", 217 transcoder_name(cpu_transcoder)); 218 219 dev_priv->psr.irq_aux_error = true; 220 221 /* 222 * If this interruption is not masked it will keep 223 * interrupting so fast that it prevents the scheduled 224 * work to run. 225 * Also after a PSR error, we don't want to arm PSR 226 * again so we don't care about unmask the interruption 227 * or unset irq_aux_error. 228 */ 229 val = intel_de_read(dev_priv, imr_reg); 230 val |= EDP_PSR_ERROR(trans_shift); 231 intel_de_write(dev_priv, imr_reg, val); 232 233 schedule_work(&dev_priv->psr.work); 234 } 235 } 236 237 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) 238 { 239 u8 alpm_caps = 0; 240 241 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, 242 &alpm_caps) != 1) 243 return false; 244 return alpm_caps & DP_ALPM_CAP; 245 } 246 247 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 248 { 249 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 250 u8 val = 8; /* assume the worst if we can't read the value */ 251 252 if (drm_dp_dpcd_readb(&intel_dp->aux, 253 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 254 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 255 else 256 drm_dbg_kms(&i915->drm, 257 "Unable to get sink synchronization latency, assuming 8 frames\n"); 258 return val; 259 } 260 261 static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp) 262 { 263 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 264 u16 val; 265 ssize_t r; 266 267 /* 268 * Returning the default X granularity if granularity not required or 269 * if DPCD read fails 270 */ 271 if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) 272 return 4; 273 274 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &val, 2); 275 if (r != 2) 276 drm_dbg_kms(&i915->drm, 277 "Unable to read DP_PSR2_SU_X_GRANULARITY\n"); 278 279 /* 280 * Spec says that if the value read is 0 the default granularity should 281 * be used instead. 282 */ 283 if (r != 2 || val == 0) 284 val = 4; 285 286 return val; 287 } 288 289 void intel_psr_init_dpcd(struct intel_dp *intel_dp) 290 { 291 struct drm_i915_private *dev_priv = 292 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 293 294 if (dev_priv->psr.dp) { 295 drm_warn(&dev_priv->drm, 296 "More than one eDP panel found, PSR support should be extended\n"); 297 return; 298 } 299 300 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, 301 sizeof(intel_dp->psr_dpcd)); 302 303 if (!intel_dp->psr_dpcd[0]) 304 return; 305 drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n", 306 intel_dp->psr_dpcd[0]); 307 308 if (drm_dp_has_quirk(&intel_dp->desc, 0, DP_DPCD_QUIRK_NO_PSR)) { 309 drm_dbg_kms(&dev_priv->drm, 310 "PSR support not currently available for this panel\n"); 311 return; 312 } 313 314 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 315 drm_dbg_kms(&dev_priv->drm, 316 "Panel lacks power state control, PSR cannot be enabled\n"); 317 return; 318 } 319 320 dev_priv->psr.sink_support = true; 321 dev_priv->psr.sink_sync_latency = 322 intel_dp_get_sink_sync_latency(intel_dp); 323 324 dev_priv->psr.dp = intel_dp; 325 326 if (INTEL_GEN(dev_priv) >= 9 && 327 (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { 328 bool y_req = intel_dp->psr_dpcd[1] & 329 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 330 bool alpm = intel_dp_get_alpm_status(intel_dp); 331 332 /* 333 * All panels that supports PSR version 03h (PSR2 + 334 * Y-coordinate) can handle Y-coordinates in VSC but we are 335 * only sure that it is going to be used when required by the 336 * panel. This way panel is capable to do selective update 337 * without a aux frame sync. 338 * 339 * To support PSR version 02h and PSR version 03h without 340 * Y-coordinate requirement panels we would need to enable 341 * GTC first. 342 */ 343 dev_priv->psr.sink_psr2_support = y_req && alpm; 344 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n", 345 dev_priv->psr.sink_psr2_support ? "" : "not "); 346 347 if (dev_priv->psr.sink_psr2_support) { 348 dev_priv->psr.colorimetry_support = 349 intel_dp_get_colorimetry_status(intel_dp); 350 dev_priv->psr.su_x_granularity = 351 intel_dp_get_su_x_granulartiy(intel_dp); 352 } 353 } 354 } 355 356 static void hsw_psr_setup_aux(struct intel_dp *intel_dp) 357 { 358 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 359 u32 aux_clock_divider, aux_ctl; 360 int i; 361 static const u8 aux_msg[] = { 362 [0] = DP_AUX_NATIVE_WRITE << 4, 363 [1] = DP_SET_POWER >> 8, 364 [2] = DP_SET_POWER & 0xff, 365 [3] = 1 - 1, 366 [4] = DP_SET_POWER_D0, 367 }; 368 u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK | 369 EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | 370 EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | 371 EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; 372 373 BUILD_BUG_ON(sizeof(aux_msg) > 20); 374 for (i = 0; i < sizeof(aux_msg); i += 4) 375 intel_de_write(dev_priv, 376 EDP_PSR_AUX_DATA(dev_priv->psr.transcoder, i >> 2), 377 intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); 378 379 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 380 381 /* Start with bits set for DDI_AUX_CTL register */ 382 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), 383 aux_clock_divider); 384 385 /* Select only valid bits for SRD_AUX_CTL */ 386 aux_ctl &= psr_aux_mask; 387 intel_de_write(dev_priv, EDP_PSR_AUX_CTL(dev_priv->psr.transcoder), 388 aux_ctl); 389 } 390 391 static void intel_psr_enable_sink(struct intel_dp *intel_dp) 392 { 393 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 394 u8 dpcd_val = DP_PSR_ENABLE; 395 396 /* Enable ALPM at sink for psr2 */ 397 if (dev_priv->psr.psr2_enabled) { 398 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 399 DP_ALPM_ENABLE | 400 DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); 401 402 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 403 } else { 404 if (dev_priv->psr.link_standby) 405 dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; 406 407 if (INTEL_GEN(dev_priv) >= 8) 408 dpcd_val |= DP_PSR_CRC_VERIFICATION; 409 } 410 411 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); 412 413 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 414 } 415 416 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 417 { 418 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 419 u32 val = 0; 420 421 if (INTEL_GEN(dev_priv) >= 11) 422 val |= EDP_PSR_TP4_TIME_0US; 423 424 if (dev_priv->params.psr_safest_params) { 425 val |= EDP_PSR_TP1_TIME_2500us; 426 val |= EDP_PSR_TP2_TP3_TIME_2500us; 427 goto check_tp3_sel; 428 } 429 430 if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) 431 val |= EDP_PSR_TP1_TIME_0us; 432 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100) 433 val |= EDP_PSR_TP1_TIME_100us; 434 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500) 435 val |= EDP_PSR_TP1_TIME_500us; 436 else 437 val |= EDP_PSR_TP1_TIME_2500us; 438 439 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0) 440 val |= EDP_PSR_TP2_TP3_TIME_0us; 441 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) 442 val |= EDP_PSR_TP2_TP3_TIME_100us; 443 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) 444 val |= EDP_PSR_TP2_TP3_TIME_500us; 445 else 446 val |= EDP_PSR_TP2_TP3_TIME_2500us; 447 448 check_tp3_sel: 449 if (intel_dp_source_supports_hbr2(intel_dp) && 450 drm_dp_tps3_supported(intel_dp->dpcd)) 451 val |= EDP_PSR_TP1_TP3_SEL; 452 else 453 val |= EDP_PSR_TP1_TP2_SEL; 454 455 return val; 456 } 457 458 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 459 { 460 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 461 int idle_frames; 462 463 /* Let's use 6 as the minimum to cover all known cases including the 464 * off-by-one issue that HW has in some cases. 465 */ 466 idle_frames = max(6, dev_priv->vbt.psr.idle_frames); 467 idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); 468 469 if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf)) 470 idle_frames = 0xf; 471 472 return idle_frames; 473 } 474 475 static void hsw_activate_psr1(struct intel_dp *intel_dp) 476 { 477 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 478 u32 max_sleep_time = 0x1f; 479 u32 val = EDP_PSR_ENABLE; 480 481 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT; 482 483 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; 484 if (IS_HASWELL(dev_priv)) 485 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 486 487 if (dev_priv->psr.link_standby) 488 val |= EDP_PSR_LINK_STANDBY; 489 490 val |= intel_psr1_get_tp_time(intel_dp); 491 492 if (INTEL_GEN(dev_priv) >= 8) 493 val |= EDP_PSR_CRC_ENABLE; 494 495 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) & 496 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK); 497 intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), val); 498 } 499 500 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 501 { 502 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 503 u32 val = 0; 504 505 if (dev_priv->params.psr_safest_params) 506 return EDP_PSR2_TP2_TIME_2500us; 507 508 if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 509 dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 510 val |= EDP_PSR2_TP2_TIME_50us; 511 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 512 val |= EDP_PSR2_TP2_TIME_100us; 513 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 514 val |= EDP_PSR2_TP2_TIME_500us; 515 else 516 val |= EDP_PSR2_TP2_TIME_2500us; 517 518 return val; 519 } 520 521 static void hsw_activate_psr2(struct intel_dp *intel_dp) 522 { 523 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 524 u32 val; 525 526 val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT; 527 528 val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; 529 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 530 val |= EDP_Y_COORDINATE_ENABLE; 531 532 val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); 533 val |= intel_psr2_get_tp_time(intel_dp); 534 535 if (INTEL_GEN(dev_priv) >= 12) { 536 /* 537 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default 538 * values from BSpec. In order to setting an optimal power 539 * consumption, lower than 4k resoluition mode needs to decrese 540 * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution 541 * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE. 542 */ 543 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 544 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7); 545 val |= TGL_EDP_PSR2_FAST_WAKE(7); 546 } else if (INTEL_GEN(dev_priv) >= 9) { 547 val |= EDP_PSR2_IO_BUFFER_WAKE(7); 548 val |= EDP_PSR2_FAST_WAKE(7); 549 } 550 551 if (dev_priv->psr.psr2_sel_fetch_enabled) { 552 /* WA 1408330847 */ 553 if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) || 554 IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)) 555 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 556 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 557 DIS_RAM_BYPASS_PSR2_MAN_TRACK); 558 559 intel_de_write(dev_priv, 560 PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), 561 PSR2_MAN_TRK_CTL_ENABLE); 562 } else if (HAS_PSR2_SEL_FETCH(dev_priv)) { 563 intel_de_write(dev_priv, 564 PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), 0); 565 } 566 567 /* 568 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 569 * recommending keep this bit unset while PSR2 is enabled. 570 */ 571 intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), 0); 572 573 intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder), val); 574 } 575 576 static bool 577 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) 578 { 579 if (INTEL_GEN(dev_priv) < 9) 580 return false; 581 else if (INTEL_GEN(dev_priv) >= 12) 582 return trans == TRANSCODER_A; 583 else 584 return trans == TRANSCODER_EDP; 585 } 586 587 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate) 588 { 589 if (!cstate || !cstate->hw.active) 590 return 0; 591 592 return DIV_ROUND_UP(1000 * 1000, 593 drm_mode_vrefresh(&cstate->hw.adjusted_mode)); 594 } 595 596 static void psr2_program_idle_frames(struct drm_i915_private *dev_priv, 597 u32 idle_frames) 598 { 599 u32 val; 600 601 idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; 602 val = intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)); 603 val &= ~EDP_PSR2_IDLE_FRAME_MASK; 604 val |= idle_frames; 605 intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder), val); 606 } 607 608 static void tgl_psr2_enable_dc3co(struct drm_i915_private *dev_priv) 609 { 610 psr2_program_idle_frames(dev_priv, 0); 611 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO); 612 } 613 614 static void tgl_psr2_disable_dc3co(struct drm_i915_private *dev_priv) 615 { 616 struct intel_dp *intel_dp = dev_priv->psr.dp; 617 618 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 619 psr2_program_idle_frames(dev_priv, psr_compute_idle_frames(intel_dp)); 620 } 621 622 static void tgl_dc3co_disable_work(struct work_struct *work) 623 { 624 struct drm_i915_private *dev_priv = 625 container_of(work, typeof(*dev_priv), psr.dc3co_work.work); 626 627 mutex_lock(&dev_priv->psr.lock); 628 /* If delayed work is pending, it is not idle */ 629 if (delayed_work_pending(&dev_priv->psr.dc3co_work)) 630 goto unlock; 631 632 tgl_psr2_disable_dc3co(dev_priv); 633 unlock: 634 mutex_unlock(&dev_priv->psr.lock); 635 } 636 637 static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv) 638 { 639 if (!dev_priv->psr.dc3co_enabled) 640 return; 641 642 cancel_delayed_work(&dev_priv->psr.dc3co_work); 643 /* Before PSR2 exit disallow dc3co*/ 644 tgl_psr2_disable_dc3co(dev_priv); 645 } 646 647 static void 648 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 649 struct intel_crtc_state *crtc_state) 650 { 651 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; 652 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 653 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 654 u32 exit_scanlines; 655 656 if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)) 657 return; 658 659 /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/ 660 if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A || 661 dig_port->base.port != PORT_A) 662 return; 663 664 /* 665 * DC3CO Exit time 200us B.Spec 49196 666 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 667 */ 668 exit_scanlines = 669 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; 670 671 if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay)) 672 return; 673 674 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; 675 } 676 677 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, 678 struct intel_crtc_state *crtc_state) 679 { 680 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 681 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 682 struct intel_plane_state *plane_state; 683 struct intel_plane *plane; 684 int i; 685 686 if (!dev_priv->params.enable_psr2_sel_fetch) { 687 drm_dbg_kms(&dev_priv->drm, 688 "PSR2 sel fetch not enabled, disabled by parameter\n"); 689 return false; 690 } 691 692 if (crtc_state->uapi.async_flip) { 693 drm_dbg_kms(&dev_priv->drm, 694 "PSR2 sel fetch not enabled, async flip enabled\n"); 695 return false; 696 } 697 698 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 699 if (plane_state->uapi.rotation != DRM_MODE_ROTATE_0) { 700 drm_dbg_kms(&dev_priv->drm, 701 "PSR2 sel fetch not enabled, plane rotated\n"); 702 return false; 703 } 704 } 705 706 return crtc_state->enable_psr2_sel_fetch = true; 707 } 708 709 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 710 struct intel_crtc_state *crtc_state) 711 { 712 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 713 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 714 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 715 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 716 717 if (!dev_priv->psr.sink_psr2_support) 718 return false; 719 720 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { 721 drm_dbg_kms(&dev_priv->drm, 722 "PSR2 not supported in transcoder %s\n", 723 transcoder_name(crtc_state->cpu_transcoder)); 724 return false; 725 } 726 727 if (!psr2_global_enabled(dev_priv)) { 728 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); 729 return false; 730 } 731 732 /* 733 * DSC and PSR2 cannot be enabled simultaneously. If a requested 734 * resolution requires DSC to be enabled, priority is given to DSC 735 * over PSR2. 736 */ 737 if (crtc_state->dsc.compression_enable) { 738 drm_dbg_kms(&dev_priv->drm, 739 "PSR2 cannot be enabled since DSC is enabled\n"); 740 return false; 741 } 742 743 if (crtc_state->crc_enabled) { 744 drm_dbg_kms(&dev_priv->drm, 745 "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); 746 return false; 747 } 748 749 if (INTEL_GEN(dev_priv) >= 12) { 750 psr_max_h = 5120; 751 psr_max_v = 3200; 752 max_bpp = 30; 753 } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { 754 psr_max_h = 4096; 755 psr_max_v = 2304; 756 max_bpp = 24; 757 } else if (IS_GEN(dev_priv, 9)) { 758 psr_max_h = 3640; 759 psr_max_v = 2304; 760 max_bpp = 24; 761 } 762 763 if (crtc_state->pipe_bpp > max_bpp) { 764 drm_dbg_kms(&dev_priv->drm, 765 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 766 crtc_state->pipe_bpp, max_bpp); 767 return false; 768 } 769 770 /* 771 * HW sends SU blocks of size four scan lines, which means the starting 772 * X coordinate and Y granularity requirements will always be met. We 773 * only need to validate the SU block width is a multiple of 774 * x granularity. 775 */ 776 if (crtc_hdisplay % dev_priv->psr.su_x_granularity) { 777 drm_dbg_kms(&dev_priv->drm, 778 "PSR2 not enabled, hdisplay(%d) not multiple of %d\n", 779 crtc_hdisplay, dev_priv->psr.su_x_granularity); 780 return false; 781 } 782 783 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 784 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && 785 !HAS_PSR_HW_TRACKING(dev_priv)) { 786 drm_dbg_kms(&dev_priv->drm, 787 "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); 788 return false; 789 } 790 } 791 792 if (!crtc_state->enable_psr2_sel_fetch && 793 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { 794 drm_dbg_kms(&dev_priv->drm, 795 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 796 crtc_hdisplay, crtc_vdisplay, 797 psr_max_h, psr_max_v); 798 return false; 799 } 800 801 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); 802 return true; 803 } 804 805 void intel_psr_compute_config(struct intel_dp *intel_dp, 806 struct intel_crtc_state *crtc_state) 807 { 808 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 809 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 810 const struct drm_display_mode *adjusted_mode = 811 &crtc_state->hw.adjusted_mode; 812 int psr_setup_time; 813 814 if (!CAN_PSR(dev_priv)) 815 return; 816 817 if (intel_dp != dev_priv->psr.dp) 818 return; 819 820 if (!psr_global_enabled(dev_priv)) { 821 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); 822 return; 823 } 824 825 /* 826 * HSW spec explicitly says PSR is tied to port A. 827 * BDW+ platforms have a instance of PSR registers per transcoder but 828 * for now it only supports one instance of PSR, so lets keep it 829 * hardcoded to PORT_A 830 */ 831 if (dig_port->base.port != PORT_A) { 832 drm_dbg_kms(&dev_priv->drm, 833 "PSR condition failed: Port not supported\n"); 834 return; 835 } 836 837 if (dev_priv->psr.sink_not_reliable) { 838 drm_dbg_kms(&dev_priv->drm, 839 "PSR sink implementation is not reliable\n"); 840 return; 841 } 842 843 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 844 drm_dbg_kms(&dev_priv->drm, 845 "PSR condition failed: Interlaced mode enabled\n"); 846 return; 847 } 848 849 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); 850 if (psr_setup_time < 0) { 851 drm_dbg_kms(&dev_priv->drm, 852 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 853 intel_dp->psr_dpcd[1]); 854 return; 855 } 856 857 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 858 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 859 drm_dbg_kms(&dev_priv->drm, 860 "PSR condition failed: PSR setup time (%d us) too long\n", 861 psr_setup_time); 862 return; 863 } 864 865 crtc_state->has_psr = true; 866 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); 867 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 868 } 869 870 static void intel_psr_activate(struct intel_dp *intel_dp) 871 { 872 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 873 874 if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) 875 drm_WARN_ON(&dev_priv->drm, 876 intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE); 877 878 drm_WARN_ON(&dev_priv->drm, 879 intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE); 880 drm_WARN_ON(&dev_priv->drm, dev_priv->psr.active); 881 lockdep_assert_held(&dev_priv->psr.lock); 882 883 /* psr1 and psr2 are mutually exclusive.*/ 884 if (dev_priv->psr.psr2_enabled) 885 hsw_activate_psr2(intel_dp); 886 else 887 hsw_activate_psr1(intel_dp); 888 889 dev_priv->psr.active = true; 890 } 891 892 static void intel_psr_enable_source(struct intel_dp *intel_dp, 893 const struct intel_crtc_state *crtc_state) 894 { 895 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 896 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 897 u32 mask; 898 899 /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+ 900 * use hardcoded values PSR AUX transactions 901 */ 902 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 903 hsw_psr_setup_aux(intel_dp); 904 905 if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) && 906 !IS_GEMINILAKE(dev_priv))) { 907 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder); 908 u32 chicken = intel_de_read(dev_priv, reg); 909 910 chicken |= PSR2_VSC_ENABLE_PROG_HEADER | 911 PSR2_ADD_VERTICAL_LINE_COUNT; 912 intel_de_write(dev_priv, reg, chicken); 913 } 914 915 /* 916 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 917 * mask LPSP to avoid dependency on other drivers that might block 918 * runtime_pm besides preventing other hw tracking issues now we 919 * can rely on frontbuffer tracking. 920 */ 921 mask = EDP_PSR_DEBUG_MASK_MEMUP | 922 EDP_PSR_DEBUG_MASK_HPD | 923 EDP_PSR_DEBUG_MASK_LPSP | 924 EDP_PSR_DEBUG_MASK_MAX_SLEEP; 925 926 if (INTEL_GEN(dev_priv) < 11) 927 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 928 929 intel_de_write(dev_priv, EDP_PSR_DEBUG(dev_priv->psr.transcoder), 930 mask); 931 932 psr_irq_control(dev_priv); 933 934 if (crtc_state->dc3co_exitline) { 935 u32 val; 936 937 /* 938 * TODO: if future platforms supports DC3CO in more than one 939 * transcoder, EXITLINE will need to be unset when disabling PSR 940 */ 941 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder)); 942 val &= ~EXITLINE_MASK; 943 val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT; 944 val |= EXITLINE_ENABLE; 945 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); 946 } 947 948 if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv)) 949 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, 950 dev_priv->psr.psr2_sel_fetch_enabled ? 951 IGNORE_PSR2_HW_TRACKING : 0); 952 } 953 954 static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, 955 const struct intel_crtc_state *crtc_state, 956 const struct drm_connector_state *conn_state) 957 { 958 struct intel_dp *intel_dp = dev_priv->psr.dp; 959 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 960 struct intel_encoder *encoder = &dig_port->base; 961 u32 val; 962 963 drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled); 964 965 dev_priv->psr.psr2_enabled = crtc_state->has_psr2; 966 dev_priv->psr.busy_frontbuffer_bits = 0; 967 dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 968 dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline; 969 dev_priv->psr.transcoder = crtc_state->cpu_transcoder; 970 /* DC5/DC6 requires at least 6 idle frames */ 971 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 972 dev_priv->psr.dc3co_exit_delay = val; 973 dev_priv->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; 974 975 /* 976 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 977 * will still keep the error set even after the reset done in the 978 * irq_preinstall and irq_uninstall hooks. 979 * And enabling in this situation cause the screen to freeze in the 980 * first time that PSR HW tries to activate so lets keep PSR disabled 981 * to avoid any rendering problems. 982 */ 983 if (INTEL_GEN(dev_priv) >= 12) { 984 val = intel_de_read(dev_priv, 985 TRANS_PSR_IIR(dev_priv->psr.transcoder)); 986 val &= EDP_PSR_ERROR(0); 987 } else { 988 val = intel_de_read(dev_priv, EDP_PSR_IIR); 989 val &= EDP_PSR_ERROR(dev_priv->psr.transcoder); 990 } 991 if (val) { 992 dev_priv->psr.sink_not_reliable = true; 993 drm_dbg_kms(&dev_priv->drm, 994 "PSR interruption error set, not enabling PSR\n"); 995 return; 996 } 997 998 drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", 999 dev_priv->psr.psr2_enabled ? "2" : "1"); 1000 intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, 1001 &dev_priv->psr.vsc); 1002 intel_write_dp_vsc_sdp(encoder, crtc_state, &dev_priv->psr.vsc); 1003 intel_psr_enable_sink(intel_dp); 1004 intel_psr_enable_source(intel_dp, crtc_state); 1005 dev_priv->psr.enabled = true; 1006 1007 intel_psr_activate(intel_dp); 1008 } 1009 1010 /** 1011 * intel_psr_enable - Enable PSR 1012 * @intel_dp: Intel DP 1013 * @crtc_state: new CRTC state 1014 * @conn_state: new CONNECTOR state 1015 * 1016 * This function can only be called after the pipe is fully trained and enabled. 1017 */ 1018 void intel_psr_enable(struct intel_dp *intel_dp, 1019 const struct intel_crtc_state *crtc_state, 1020 const struct drm_connector_state *conn_state) 1021 { 1022 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1023 1024 if (!CAN_PSR(dev_priv) || dev_priv->psr.dp != intel_dp) 1025 return; 1026 1027 if (!crtc_state->has_psr) 1028 return; 1029 1030 drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp); 1031 1032 mutex_lock(&dev_priv->psr.lock); 1033 intel_psr_enable_locked(dev_priv, crtc_state, conn_state); 1034 mutex_unlock(&dev_priv->psr.lock); 1035 } 1036 1037 static void intel_psr_exit(struct drm_i915_private *dev_priv) 1038 { 1039 u32 val; 1040 1041 if (!dev_priv->psr.active) { 1042 if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) { 1043 val = intel_de_read(dev_priv, 1044 EDP_PSR2_CTL(dev_priv->psr.transcoder)); 1045 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE); 1046 } 1047 1048 val = intel_de_read(dev_priv, 1049 EDP_PSR_CTL(dev_priv->psr.transcoder)); 1050 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE); 1051 1052 return; 1053 } 1054 1055 if (dev_priv->psr.psr2_enabled) { 1056 tgl_disallow_dc3co_on_psr2_exit(dev_priv); 1057 val = intel_de_read(dev_priv, 1058 EDP_PSR2_CTL(dev_priv->psr.transcoder)); 1059 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE)); 1060 val &= ~EDP_PSR2_ENABLE; 1061 intel_de_write(dev_priv, 1062 EDP_PSR2_CTL(dev_priv->psr.transcoder), val); 1063 } else { 1064 val = intel_de_read(dev_priv, 1065 EDP_PSR_CTL(dev_priv->psr.transcoder)); 1066 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE)); 1067 val &= ~EDP_PSR_ENABLE; 1068 intel_de_write(dev_priv, 1069 EDP_PSR_CTL(dev_priv->psr.transcoder), val); 1070 } 1071 dev_priv->psr.active = false; 1072 } 1073 1074 static void intel_psr_disable_locked(struct intel_dp *intel_dp) 1075 { 1076 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1077 i915_reg_t psr_status; 1078 u32 psr_status_mask; 1079 1080 lockdep_assert_held(&dev_priv->psr.lock); 1081 1082 if (!dev_priv->psr.enabled) 1083 return; 1084 1085 drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", 1086 dev_priv->psr.psr2_enabled ? "2" : "1"); 1087 1088 intel_psr_exit(dev_priv); 1089 1090 if (dev_priv->psr.psr2_enabled) { 1091 psr_status = EDP_PSR2_STATUS(dev_priv->psr.transcoder); 1092 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 1093 } else { 1094 psr_status = EDP_PSR_STATUS(dev_priv->psr.transcoder); 1095 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 1096 } 1097 1098 /* Wait till PSR is idle */ 1099 if (intel_de_wait_for_clear(dev_priv, psr_status, 1100 psr_status_mask, 2000)) 1101 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n"); 1102 1103 /* WA 1408330847 */ 1104 if (dev_priv->psr.psr2_sel_fetch_enabled && 1105 (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) || 1106 IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))) 1107 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1108 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0); 1109 1110 /* Disable PSR on Sink */ 1111 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 1112 1113 if (dev_priv->psr.psr2_enabled) 1114 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); 1115 1116 dev_priv->psr.enabled = false; 1117 } 1118 1119 /** 1120 * intel_psr_disable - Disable PSR 1121 * @intel_dp: Intel DP 1122 * @old_crtc_state: old CRTC state 1123 * 1124 * This function needs to be called before disabling pipe. 1125 */ 1126 void intel_psr_disable(struct intel_dp *intel_dp, 1127 const struct intel_crtc_state *old_crtc_state) 1128 { 1129 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1130 1131 if (!old_crtc_state->has_psr) 1132 return; 1133 1134 if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(dev_priv))) 1135 return; 1136 1137 mutex_lock(&dev_priv->psr.lock); 1138 1139 intel_psr_disable_locked(intel_dp); 1140 1141 mutex_unlock(&dev_priv->psr.lock); 1142 cancel_work_sync(&dev_priv->psr.work); 1143 cancel_delayed_work_sync(&dev_priv->psr.dc3co_work); 1144 } 1145 1146 static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv) 1147 { 1148 if (IS_TIGERLAKE(dev_priv)) 1149 /* 1150 * Writes to CURSURFLIVE in TGL are causing IOMMU errors and 1151 * visual glitches that are often reproduced when executing 1152 * CPU intensive workloads while a eDP 4K panel is attached. 1153 * 1154 * Manually exiting PSR causes the frontbuffer to be updated 1155 * without glitches and the IOMMU errors are also gone but 1156 * this comes at the cost of less time with PSR active. 1157 * 1158 * So using this workaround until this issue is root caused 1159 * and a better fix is found. 1160 */ 1161 intel_psr_exit(dev_priv); 1162 else if (INTEL_GEN(dev_priv) >= 9) 1163 /* 1164 * Display WA #0884: skl+ 1165 * This documented WA for bxt can be safely applied 1166 * broadly so we can force HW tracking to exit PSR 1167 * instead of disabling and re-enabling. 1168 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 1169 * but it makes more sense write to the current active 1170 * pipe. 1171 */ 1172 intel_de_write(dev_priv, CURSURFLIVE(dev_priv->psr.pipe), 0); 1173 else 1174 /* 1175 * A write to CURSURFLIVE do not cause HW tracking to exit PSR 1176 * on older gens so doing the manual exit instead. 1177 */ 1178 intel_psr_exit(dev_priv); 1179 } 1180 1181 void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, 1182 const struct intel_crtc_state *crtc_state, 1183 const struct intel_plane_state *plane_state, 1184 int color_plane) 1185 { 1186 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1187 enum pipe pipe = plane->pipe; 1188 const struct drm_rect *clip; 1189 u32 val, offset; 1190 int ret, x, y; 1191 1192 if (!crtc_state->enable_psr2_sel_fetch) 1193 return; 1194 1195 val = plane_state ? plane_state->ctl : 0; 1196 val &= plane->id == PLANE_CURSOR ? val : PLANE_SEL_FETCH_CTL_ENABLE; 1197 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val); 1198 if (!val || plane->id == PLANE_CURSOR) 1199 return; 1200 1201 clip = &plane_state->psr2_sel_fetch_area; 1202 1203 val = (clip->y1 + plane_state->uapi.dst.y1) << 16; 1204 val |= plane_state->uapi.dst.x1; 1205 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); 1206 1207 /* TODO: consider auxiliary surfaces */ 1208 x = plane_state->uapi.src.x1 >> 16; 1209 y = (plane_state->uapi.src.y1 >> 16) + clip->y1; 1210 ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset); 1211 if (ret) 1212 drm_warn_once(&dev_priv->drm, "skl_calc_main_surface_offset() returned %i\n", 1213 ret); 1214 val = y << 16 | x; 1215 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), 1216 val); 1217 1218 /* Sizes are 0 based */ 1219 val = (drm_rect_height(clip) - 1) << 16; 1220 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; 1221 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); 1222 } 1223 1224 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) 1225 { 1226 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1227 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1228 struct i915_psr *psr = &dev_priv->psr; 1229 1230 if (!HAS_PSR2_SEL_FETCH(dev_priv) || 1231 !crtc_state->enable_psr2_sel_fetch) 1232 return; 1233 1234 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(psr->transcoder), 1235 crtc_state->psr2_man_track_ctl); 1236 } 1237 1238 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, 1239 struct drm_rect *clip, bool full_update) 1240 { 1241 u32 val = PSR2_MAN_TRK_CTL_ENABLE; 1242 1243 if (full_update) { 1244 val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 1245 goto exit; 1246 } 1247 1248 if (clip->y1 == -1) 1249 goto exit; 1250 1251 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4); 1252 1253 val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; 1254 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1); 1255 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1); 1256 exit: 1257 crtc_state->psr2_man_track_ctl = val; 1258 } 1259 1260 static void clip_area_update(struct drm_rect *overlap_damage_area, 1261 struct drm_rect *damage_area) 1262 { 1263 if (overlap_damage_area->y1 == -1) { 1264 overlap_damage_area->y1 = damage_area->y1; 1265 overlap_damage_area->y2 = damage_area->y2; 1266 return; 1267 } 1268 1269 if (damage_area->y1 < overlap_damage_area->y1) 1270 overlap_damage_area->y1 = damage_area->y1; 1271 1272 if (damage_area->y2 > overlap_damage_area->y2) 1273 overlap_damage_area->y2 = damage_area->y2; 1274 } 1275 1276 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 1277 struct intel_crtc *crtc) 1278 { 1279 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 1280 struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 }; 1281 struct intel_plane_state *new_plane_state, *old_plane_state; 1282 struct intel_plane *plane; 1283 bool full_update = false; 1284 int i, ret; 1285 1286 if (!crtc_state->enable_psr2_sel_fetch) 1287 return 0; 1288 1289 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 1290 if (ret) 1291 return ret; 1292 1293 /* 1294 * Calculate minimal selective fetch area of each plane and calculate 1295 * the pipe damaged area. 1296 * In the next loop the plane selective fetch area will actually be set 1297 * using whole pipe damaged area. 1298 */ 1299 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1300 new_plane_state, i) { 1301 struct drm_rect src, damaged_area = { .y1 = -1 }; 1302 struct drm_mode_rect *damaged_clips; 1303 u32 num_clips, j; 1304 1305 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) 1306 continue; 1307 1308 if (!new_plane_state->uapi.visible && 1309 !old_plane_state->uapi.visible) 1310 continue; 1311 1312 /* 1313 * TODO: Not clear how to handle planes with negative position, 1314 * also planes are not updated if they have a negative X 1315 * position so for now doing a full update in this cases 1316 */ 1317 if (new_plane_state->uapi.dst.y1 < 0 || 1318 new_plane_state->uapi.dst.x1 < 0) { 1319 full_update = true; 1320 break; 1321 } 1322 1323 num_clips = drm_plane_get_damage_clips_count(&new_plane_state->uapi); 1324 1325 /* 1326 * If visibility or plane moved, mark the whole plane area as 1327 * damaged as it needs to be complete redraw in the new and old 1328 * position. 1329 */ 1330 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || 1331 !drm_rect_equals(&new_plane_state->uapi.dst, 1332 &old_plane_state->uapi.dst)) { 1333 if (old_plane_state->uapi.visible) { 1334 damaged_area.y1 = old_plane_state->uapi.dst.y1; 1335 damaged_area.y2 = old_plane_state->uapi.dst.y2; 1336 clip_area_update(&pipe_clip, &damaged_area); 1337 } 1338 1339 if (new_plane_state->uapi.visible) { 1340 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1341 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1342 clip_area_update(&pipe_clip, &damaged_area); 1343 } 1344 continue; 1345 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha || 1346 (!num_clips && 1347 new_plane_state->uapi.fb != old_plane_state->uapi.fb)) { 1348 /* 1349 * If the plane don't have damaged areas but the 1350 * framebuffer changed or alpha changed, mark the whole 1351 * plane area as damaged. 1352 */ 1353 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1354 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1355 clip_area_update(&pipe_clip, &damaged_area); 1356 continue; 1357 } 1358 1359 drm_rect_fp_to_int(&src, &new_plane_state->uapi.src); 1360 damaged_clips = drm_plane_get_damage_clips(&new_plane_state->uapi); 1361 1362 for (j = 0; j < num_clips; j++) { 1363 struct drm_rect clip; 1364 1365 clip.x1 = damaged_clips[j].x1; 1366 clip.y1 = damaged_clips[j].y1; 1367 clip.x2 = damaged_clips[j].x2; 1368 clip.y2 = damaged_clips[j].y2; 1369 if (drm_rect_intersect(&clip, &src)) 1370 clip_area_update(&damaged_area, &clip); 1371 } 1372 1373 if (damaged_area.y1 == -1) 1374 continue; 1375 1376 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; 1377 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; 1378 clip_area_update(&pipe_clip, &damaged_area); 1379 } 1380 1381 if (full_update) 1382 goto skip_sel_fetch_set_loop; 1383 1384 /* It must be aligned to 4 lines */ 1385 pipe_clip.y1 -= pipe_clip.y1 % 4; 1386 if (pipe_clip.y2 % 4) 1387 pipe_clip.y2 = ((pipe_clip.y2 / 4) + 1) * 4; 1388 1389 /* 1390 * Now that we have the pipe damaged area check if it intersect with 1391 * every plane, if it does set the plane selective fetch area. 1392 */ 1393 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1394 new_plane_state, i) { 1395 struct drm_rect *sel_fetch_area, inter; 1396 1397 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || 1398 !new_plane_state->uapi.visible) 1399 continue; 1400 1401 inter = pipe_clip; 1402 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) 1403 continue; 1404 1405 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 1406 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; 1407 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; 1408 } 1409 1410 skip_sel_fetch_set_loop: 1411 psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update); 1412 return 0; 1413 } 1414 1415 /** 1416 * intel_psr_update - Update PSR state 1417 * @intel_dp: Intel DP 1418 * @crtc_state: new CRTC state 1419 * @conn_state: new CONNECTOR state 1420 * 1421 * This functions will update PSR states, disabling, enabling or switching PSR 1422 * version when executing fastsets. For full modeset, intel_psr_disable() and 1423 * intel_psr_enable() should be called instead. 1424 */ 1425 void intel_psr_update(struct intel_dp *intel_dp, 1426 const struct intel_crtc_state *crtc_state, 1427 const struct drm_connector_state *conn_state) 1428 { 1429 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1430 struct i915_psr *psr = &dev_priv->psr; 1431 bool enable, psr2_enable; 1432 1433 if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp) 1434 return; 1435 1436 mutex_lock(&dev_priv->psr.lock); 1437 1438 enable = crtc_state->has_psr; 1439 psr2_enable = crtc_state->has_psr2; 1440 1441 if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) { 1442 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 1443 if (crtc_state->crc_enabled && psr->enabled) 1444 psr_force_hw_tracking_exit(dev_priv); 1445 else if (INTEL_GEN(dev_priv) < 9 && psr->enabled) { 1446 /* 1447 * Activate PSR again after a force exit when enabling 1448 * CRC in older gens 1449 */ 1450 if (!dev_priv->psr.active && 1451 !dev_priv->psr.busy_frontbuffer_bits) 1452 schedule_work(&dev_priv->psr.work); 1453 } 1454 1455 goto unlock; 1456 } 1457 1458 if (psr->enabled) 1459 intel_psr_disable_locked(intel_dp); 1460 1461 if (enable) 1462 intel_psr_enable_locked(dev_priv, crtc_state, conn_state); 1463 1464 unlock: 1465 mutex_unlock(&dev_priv->psr.lock); 1466 } 1467 1468 /** 1469 * intel_psr_wait_for_idle - wait for PSR1 to idle 1470 * @new_crtc_state: new CRTC state 1471 * @out_value: PSR status in case of failure 1472 * 1473 * This function is expected to be called from pipe_update_start() where it is 1474 * not expected to race with PSR enable or disable. 1475 * 1476 * Returns: 0 on success or -ETIMEOUT if PSR status does not idle. 1477 */ 1478 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state, 1479 u32 *out_value) 1480 { 1481 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1482 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1483 1484 if (!dev_priv->psr.enabled || !new_crtc_state->has_psr) 1485 return 0; 1486 1487 /* FIXME: Update this for PSR2 if we need to wait for idle */ 1488 if (READ_ONCE(dev_priv->psr.psr2_enabled)) 1489 return 0; 1490 1491 /* 1492 * From bspec: Panel Self Refresh (BDW+) 1493 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 1494 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 1495 * defensive enough to cover everything. 1496 */ 1497 1498 return __intel_wait_for_register(&dev_priv->uncore, 1499 EDP_PSR_STATUS(dev_priv->psr.transcoder), 1500 EDP_PSR_STATUS_STATE_MASK, 1501 EDP_PSR_STATUS_STATE_IDLE, 2, 50, 1502 out_value); 1503 } 1504 1505 static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv) 1506 { 1507 i915_reg_t reg; 1508 u32 mask; 1509 int err; 1510 1511 if (!dev_priv->psr.enabled) 1512 return false; 1513 1514 if (dev_priv->psr.psr2_enabled) { 1515 reg = EDP_PSR2_STATUS(dev_priv->psr.transcoder); 1516 mask = EDP_PSR2_STATUS_STATE_MASK; 1517 } else { 1518 reg = EDP_PSR_STATUS(dev_priv->psr.transcoder); 1519 mask = EDP_PSR_STATUS_STATE_MASK; 1520 } 1521 1522 mutex_unlock(&dev_priv->psr.lock); 1523 1524 err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); 1525 if (err) 1526 drm_err(&dev_priv->drm, 1527 "Timed out waiting for PSR Idle for re-enable\n"); 1528 1529 /* After the unlocked wait, verify that PSR is still wanted! */ 1530 mutex_lock(&dev_priv->psr.lock); 1531 return err == 0 && dev_priv->psr.enabled; 1532 } 1533 1534 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) 1535 { 1536 struct drm_connector_list_iter conn_iter; 1537 struct drm_device *dev = &dev_priv->drm; 1538 struct drm_modeset_acquire_ctx ctx; 1539 struct drm_atomic_state *state; 1540 struct drm_connector *conn; 1541 int err = 0; 1542 1543 state = drm_atomic_state_alloc(dev); 1544 if (!state) 1545 return -ENOMEM; 1546 1547 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1548 state->acquire_ctx = &ctx; 1549 1550 retry: 1551 1552 drm_connector_list_iter_begin(dev, &conn_iter); 1553 drm_for_each_connector_iter(conn, &conn_iter) { 1554 struct drm_connector_state *conn_state; 1555 struct drm_crtc_state *crtc_state; 1556 1557 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) 1558 continue; 1559 1560 conn_state = drm_atomic_get_connector_state(state, conn); 1561 if (IS_ERR(conn_state)) { 1562 err = PTR_ERR(conn_state); 1563 break; 1564 } 1565 1566 if (!conn_state->crtc) 1567 continue; 1568 1569 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); 1570 if (IS_ERR(crtc_state)) { 1571 err = PTR_ERR(crtc_state); 1572 break; 1573 } 1574 1575 /* Mark mode as changed to trigger a pipe->update() */ 1576 crtc_state->mode_changed = true; 1577 } 1578 drm_connector_list_iter_end(&conn_iter); 1579 1580 if (err == 0) 1581 err = drm_atomic_commit(state); 1582 1583 if (err == -EDEADLK) { 1584 drm_atomic_state_clear(state); 1585 err = drm_modeset_backoff(&ctx); 1586 if (!err) 1587 goto retry; 1588 } 1589 1590 drm_modeset_drop_locks(&ctx); 1591 drm_modeset_acquire_fini(&ctx); 1592 drm_atomic_state_put(state); 1593 1594 return err; 1595 } 1596 1597 int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val) 1598 { 1599 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 1600 u32 old_mode; 1601 int ret; 1602 1603 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || 1604 mode > I915_PSR_DEBUG_FORCE_PSR1) { 1605 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); 1606 return -EINVAL; 1607 } 1608 1609 ret = mutex_lock_interruptible(&dev_priv->psr.lock); 1610 if (ret) 1611 return ret; 1612 1613 old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK; 1614 dev_priv->psr.debug = val; 1615 1616 /* 1617 * Do it right away if it's already enabled, otherwise it will be done 1618 * when enabling the source. 1619 */ 1620 if (dev_priv->psr.enabled) 1621 psr_irq_control(dev_priv); 1622 1623 mutex_unlock(&dev_priv->psr.lock); 1624 1625 if (old_mode != mode) 1626 ret = intel_psr_fastset_force(dev_priv); 1627 1628 return ret; 1629 } 1630 1631 static void intel_psr_handle_irq(struct drm_i915_private *dev_priv) 1632 { 1633 struct i915_psr *psr = &dev_priv->psr; 1634 1635 intel_psr_disable_locked(psr->dp); 1636 psr->sink_not_reliable = true; 1637 /* let's make sure that sink is awaken */ 1638 drm_dp_dpcd_writeb(&psr->dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 1639 } 1640 1641 static void intel_psr_work(struct work_struct *work) 1642 { 1643 struct drm_i915_private *dev_priv = 1644 container_of(work, typeof(*dev_priv), psr.work); 1645 1646 mutex_lock(&dev_priv->psr.lock); 1647 1648 if (!dev_priv->psr.enabled) 1649 goto unlock; 1650 1651 if (READ_ONCE(dev_priv->psr.irq_aux_error)) 1652 intel_psr_handle_irq(dev_priv); 1653 1654 /* 1655 * We have to make sure PSR is ready for re-enable 1656 * otherwise it keeps disabled until next full enable/disable cycle. 1657 * PSR might take some time to get fully disabled 1658 * and be ready for re-enable. 1659 */ 1660 if (!__psr_wait_for_idle_locked(dev_priv)) 1661 goto unlock; 1662 1663 /* 1664 * The delayed work can race with an invalidate hence we need to 1665 * recheck. Since psr_flush first clears this and then reschedules we 1666 * won't ever miss a flush when bailing out here. 1667 */ 1668 if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active) 1669 goto unlock; 1670 1671 intel_psr_activate(dev_priv->psr.dp); 1672 unlock: 1673 mutex_unlock(&dev_priv->psr.lock); 1674 } 1675 1676 /** 1677 * intel_psr_invalidate - Invalidade PSR 1678 * @dev_priv: i915 device 1679 * @frontbuffer_bits: frontbuffer plane tracking bits 1680 * @origin: which operation caused the invalidate 1681 * 1682 * Since the hardware frontbuffer tracking has gaps we need to integrate 1683 * with the software frontbuffer tracking. This function gets called every 1684 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 1685 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 1686 * 1687 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 1688 */ 1689 void intel_psr_invalidate(struct drm_i915_private *dev_priv, 1690 unsigned frontbuffer_bits, enum fb_op_origin origin) 1691 { 1692 if (!CAN_PSR(dev_priv)) 1693 return; 1694 1695 if (origin == ORIGIN_FLIP) 1696 return; 1697 1698 mutex_lock(&dev_priv->psr.lock); 1699 if (!dev_priv->psr.enabled) { 1700 mutex_unlock(&dev_priv->psr.lock); 1701 return; 1702 } 1703 1704 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe); 1705 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; 1706 1707 if (frontbuffer_bits) 1708 intel_psr_exit(dev_priv); 1709 1710 mutex_unlock(&dev_priv->psr.lock); 1711 } 1712 1713 /* 1714 * When we will be completely rely on PSR2 S/W tracking in future, 1715 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP 1716 * event also therefore tgl_dc3co_flush() require to be changed 1717 * accordingly in future. 1718 */ 1719 static void 1720 tgl_dc3co_flush(struct drm_i915_private *dev_priv, 1721 unsigned int frontbuffer_bits, enum fb_op_origin origin) 1722 { 1723 mutex_lock(&dev_priv->psr.lock); 1724 1725 if (!dev_priv->psr.dc3co_enabled) 1726 goto unlock; 1727 1728 if (!dev_priv->psr.psr2_enabled || !dev_priv->psr.active) 1729 goto unlock; 1730 1731 /* 1732 * At every frontbuffer flush flip event modified delay of delayed work, 1733 * when delayed work schedules that means display has been idle. 1734 */ 1735 if (!(frontbuffer_bits & 1736 INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe))) 1737 goto unlock; 1738 1739 tgl_psr2_enable_dc3co(dev_priv); 1740 mod_delayed_work(system_wq, &dev_priv->psr.dc3co_work, 1741 dev_priv->psr.dc3co_exit_delay); 1742 1743 unlock: 1744 mutex_unlock(&dev_priv->psr.lock); 1745 } 1746 1747 /** 1748 * intel_psr_flush - Flush PSR 1749 * @dev_priv: i915 device 1750 * @frontbuffer_bits: frontbuffer plane tracking bits 1751 * @origin: which operation caused the flush 1752 * 1753 * Since the hardware frontbuffer tracking has gaps we need to integrate 1754 * with the software frontbuffer tracking. This function gets called every 1755 * time frontbuffer rendering has completed and flushed out to memory. PSR 1756 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 1757 * 1758 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 1759 */ 1760 void intel_psr_flush(struct drm_i915_private *dev_priv, 1761 unsigned frontbuffer_bits, enum fb_op_origin origin) 1762 { 1763 if (!CAN_PSR(dev_priv)) 1764 return; 1765 1766 if (origin == ORIGIN_FLIP) { 1767 tgl_dc3co_flush(dev_priv, frontbuffer_bits, origin); 1768 return; 1769 } 1770 1771 mutex_lock(&dev_priv->psr.lock); 1772 if (!dev_priv->psr.enabled) { 1773 mutex_unlock(&dev_priv->psr.lock); 1774 return; 1775 } 1776 1777 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe); 1778 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; 1779 1780 /* By definition flush = invalidate + flush */ 1781 if (frontbuffer_bits) 1782 psr_force_hw_tracking_exit(dev_priv); 1783 1784 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) 1785 schedule_work(&dev_priv->psr.work); 1786 mutex_unlock(&dev_priv->psr.lock); 1787 } 1788 1789 /** 1790 * intel_psr_init - Init basic PSR work and mutex. 1791 * @dev_priv: i915 device private 1792 * 1793 * This function is called only once at driver load to initialize basic 1794 * PSR stuff. 1795 */ 1796 void intel_psr_init(struct drm_i915_private *dev_priv) 1797 { 1798 if (!HAS_PSR(dev_priv)) 1799 return; 1800 1801 if (!dev_priv->psr.sink_support) 1802 return; 1803 1804 if (IS_HASWELL(dev_priv)) 1805 /* 1806 * HSW don't have PSR registers on the same space as transcoder 1807 * so set this to a value that when subtract to the register 1808 * in transcoder space results in the right offset for HSW 1809 */ 1810 dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE; 1811 1812 if (dev_priv->params.enable_psr == -1) 1813 if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable) 1814 dev_priv->params.enable_psr = 0; 1815 1816 /* Set link_standby x link_off defaults */ 1817 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 1818 /* HSW and BDW require workarounds that we don't implement. */ 1819 dev_priv->psr.link_standby = false; 1820 else if (INTEL_GEN(dev_priv) < 12) 1821 /* For new platforms up to TGL let's respect VBT back again */ 1822 dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; 1823 1824 INIT_WORK(&dev_priv->psr.work, intel_psr_work); 1825 INIT_DELAYED_WORK(&dev_priv->psr.dc3co_work, tgl_dc3co_disable_work); 1826 mutex_init(&dev_priv->psr.lock); 1827 } 1828 1829 static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 1830 u8 *status, u8 *error_status) 1831 { 1832 struct drm_dp_aux *aux = &intel_dp->aux; 1833 int ret; 1834 1835 ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status); 1836 if (ret != 1) 1837 return ret; 1838 1839 ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status); 1840 if (ret != 1) 1841 return ret; 1842 1843 *status = *status & DP_PSR_SINK_STATE_MASK; 1844 1845 return 0; 1846 } 1847 1848 static void psr_alpm_check(struct intel_dp *intel_dp) 1849 { 1850 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1851 struct drm_dp_aux *aux = &intel_dp->aux; 1852 struct i915_psr *psr = &dev_priv->psr; 1853 u8 val; 1854 int r; 1855 1856 if (!psr->psr2_enabled) 1857 return; 1858 1859 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); 1860 if (r != 1) { 1861 drm_err(&dev_priv->drm, "Error reading ALPM status\n"); 1862 return; 1863 } 1864 1865 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) { 1866 intel_psr_disable_locked(intel_dp); 1867 psr->sink_not_reliable = true; 1868 drm_dbg_kms(&dev_priv->drm, 1869 "ALPM lock timeout error, disabling PSR\n"); 1870 1871 /* Clearing error */ 1872 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); 1873 } 1874 } 1875 1876 static void psr_capability_changed_check(struct intel_dp *intel_dp) 1877 { 1878 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1879 struct i915_psr *psr = &dev_priv->psr; 1880 u8 val; 1881 int r; 1882 1883 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 1884 if (r != 1) { 1885 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n"); 1886 return; 1887 } 1888 1889 if (val & DP_PSR_CAPS_CHANGE) { 1890 intel_psr_disable_locked(intel_dp); 1891 psr->sink_not_reliable = true; 1892 drm_dbg_kms(&dev_priv->drm, 1893 "Sink PSR capability changed, disabling PSR\n"); 1894 1895 /* Clearing it */ 1896 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 1897 } 1898 } 1899 1900 void intel_psr_short_pulse(struct intel_dp *intel_dp) 1901 { 1902 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1903 struct i915_psr *psr = &dev_priv->psr; 1904 u8 status, error_status; 1905 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 1906 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 1907 DP_PSR_LINK_CRC_ERROR; 1908 1909 if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp)) 1910 return; 1911 1912 mutex_lock(&psr->lock); 1913 1914 if (!psr->enabled || psr->dp != intel_dp) 1915 goto exit; 1916 1917 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 1918 drm_err(&dev_priv->drm, 1919 "Error reading PSR status or error status\n"); 1920 goto exit; 1921 } 1922 1923 if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) { 1924 intel_psr_disable_locked(intel_dp); 1925 psr->sink_not_reliable = true; 1926 } 1927 1928 if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status) 1929 drm_dbg_kms(&dev_priv->drm, 1930 "PSR sink internal error, disabling PSR\n"); 1931 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 1932 drm_dbg_kms(&dev_priv->drm, 1933 "PSR RFB storage error, disabling PSR\n"); 1934 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 1935 drm_dbg_kms(&dev_priv->drm, 1936 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 1937 if (error_status & DP_PSR_LINK_CRC_ERROR) 1938 drm_dbg_kms(&dev_priv->drm, 1939 "PSR Link CRC error, disabling PSR\n"); 1940 1941 if (error_status & ~errors) 1942 drm_err(&dev_priv->drm, 1943 "PSR_ERROR_STATUS unhandled errors %x\n", 1944 error_status & ~errors); 1945 /* clear status register */ 1946 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 1947 1948 psr_alpm_check(intel_dp); 1949 psr_capability_changed_check(intel_dp); 1950 1951 exit: 1952 mutex_unlock(&psr->lock); 1953 } 1954 1955 bool intel_psr_enabled(struct intel_dp *intel_dp) 1956 { 1957 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1958 bool ret; 1959 1960 if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp)) 1961 return false; 1962 1963 mutex_lock(&dev_priv->psr.lock); 1964 ret = (dev_priv->psr.dp == intel_dp && dev_priv->psr.enabled); 1965 mutex_unlock(&dev_priv->psr.lock); 1966 1967 return ret; 1968 } 1969