1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_damage_helper.h> 26 27 #include "display/intel_dp.h" 28 29 #include "i915_drv.h" 30 #include "intel_atomic.h" 31 #include "intel_crtc.h" 32 #include "intel_de.h" 33 #include "intel_display_types.h" 34 #include "intel_dp_aux.h" 35 #include "intel_hdmi.h" 36 #include "intel_psr.h" 37 #include "intel_snps_phy.h" 38 #include "skl_universal_plane.h" 39 40 /** 41 * DOC: Panel Self Refresh (PSR/SRD) 42 * 43 * Since Haswell Display controller supports Panel Self-Refresh on display 44 * panels witch have a remote frame buffer (RFB) implemented according to PSR 45 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 46 * when system is idle but display is on as it eliminates display refresh 47 * request to DDR memory completely as long as the frame buffer for that 48 * display is unchanged. 49 * 50 * Panel Self Refresh must be supported by both Hardware (source) and 51 * Panel (sink). 52 * 53 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 54 * to power down the link and memory controller. For DSI panels the same idea 55 * is called "manual mode". 56 * 57 * The implementation uses the hardware-based PSR support which automatically 58 * enters/exits self-refresh mode. The hardware takes care of sending the 59 * required DP aux message and could even retrain the link (that part isn't 60 * enabled yet though). The hardware also keeps track of any frontbuffer 61 * changes to know when to exit self-refresh mode again. Unfortunately that 62 * part doesn't work too well, hence why the i915 PSR support uses the 63 * software frontbuffer tracking to make sure it doesn't miss a screen 64 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 65 * get called by the frontbuffer tracking code. Note that because of locking 66 * issues the self-refresh re-enable code is done from a work queue, which 67 * must be correctly synchronized/cancelled when shutting down the pipe." 68 * 69 * DC3CO (DC3 clock off) 70 * 71 * On top of PSR2, GEN12 adds a intermediate power savings state that turns 72 * clock off automatically during PSR2 idle state. 73 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep 74 * entry/exit allows the HW to enter a low-power state even when page flipping 75 * periodically (for instance a 30fps video playback scenario). 76 * 77 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), 78 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 79 * frames, if no other flip occurs and the function above is executed, DC3CO is 80 * disabled and PSR2 is configured to enter deep sleep, resetting again in case 81 * of another flip. 82 * Front buffer modifications do not trigger DC3CO activation on purpose as it 83 * would bring a lot of complexity and most of the moderns systems will only 84 * use page flips. 85 */ 86 87 static bool psr_global_enabled(struct intel_dp *intel_dp) 88 { 89 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 90 91 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 92 case I915_PSR_DEBUG_DEFAULT: 93 return i915->params.enable_psr; 94 case I915_PSR_DEBUG_DISABLE: 95 return false; 96 default: 97 return true; 98 } 99 } 100 101 static bool psr2_global_enabled(struct intel_dp *intel_dp) 102 { 103 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 104 case I915_PSR_DEBUG_DISABLE: 105 case I915_PSR_DEBUG_FORCE_PSR1: 106 return false; 107 default: 108 return true; 109 } 110 } 111 112 static void psr_irq_control(struct intel_dp *intel_dp) 113 { 114 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 115 enum transcoder trans_shift; 116 i915_reg_t imr_reg; 117 u32 mask, val; 118 119 /* 120 * gen12+ has registers relative to transcoder and one per transcoder 121 * using the same bit definition: handle it as TRANSCODER_EDP to force 122 * 0 shift in bit definition 123 */ 124 if (DISPLAY_VER(dev_priv) >= 12) { 125 trans_shift = 0; 126 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 127 } else { 128 trans_shift = intel_dp->psr.transcoder; 129 imr_reg = EDP_PSR_IMR; 130 } 131 132 mask = EDP_PSR_ERROR(trans_shift); 133 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) 134 mask |= EDP_PSR_POST_EXIT(trans_shift) | 135 EDP_PSR_PRE_ENTRY(trans_shift); 136 137 /* Warning: it is masking/setting reserved bits too */ 138 val = intel_de_read(dev_priv, imr_reg); 139 val &= ~EDP_PSR_TRANS_MASK(trans_shift); 140 val |= ~mask; 141 intel_de_write(dev_priv, imr_reg, val); 142 } 143 144 static void psr_event_print(struct drm_i915_private *i915, 145 u32 val, bool psr2_enabled) 146 { 147 drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val); 148 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 149 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n"); 150 if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) 151 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n"); 152 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 153 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n"); 154 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 155 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n"); 156 if (val & PSR_EVENT_GRAPHICS_RESET) 157 drm_dbg_kms(&i915->drm, "\tGraphics reset\n"); 158 if (val & PSR_EVENT_PCH_INTERRUPT) 159 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n"); 160 if (val & PSR_EVENT_MEMORY_UP) 161 drm_dbg_kms(&i915->drm, "\tMemory up\n"); 162 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 163 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n"); 164 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 165 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n"); 166 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 167 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n"); 168 if (val & PSR_EVENT_REGISTER_UPDATE) 169 drm_dbg_kms(&i915->drm, "\tRegister updated\n"); 170 if (val & PSR_EVENT_HDCP_ENABLE) 171 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n"); 172 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 173 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n"); 174 if (val & PSR_EVENT_VBI_ENABLE) 175 drm_dbg_kms(&i915->drm, "\tVBI enabled\n"); 176 if (val & PSR_EVENT_LPSP_MODE_EXIT) 177 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n"); 178 if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) 179 drm_dbg_kms(&i915->drm, "\tPSR disabled\n"); 180 } 181 182 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) 183 { 184 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 185 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 186 ktime_t time_ns = ktime_get(); 187 enum transcoder trans_shift; 188 i915_reg_t imr_reg; 189 190 if (DISPLAY_VER(dev_priv) >= 12) { 191 trans_shift = 0; 192 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 193 } else { 194 trans_shift = intel_dp->psr.transcoder; 195 imr_reg = EDP_PSR_IMR; 196 } 197 198 if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) { 199 intel_dp->psr.last_entry_attempt = time_ns; 200 drm_dbg_kms(&dev_priv->drm, 201 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 202 transcoder_name(cpu_transcoder)); 203 } 204 205 if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) { 206 intel_dp->psr.last_exit = time_ns; 207 drm_dbg_kms(&dev_priv->drm, 208 "[transcoder %s] PSR exit completed\n", 209 transcoder_name(cpu_transcoder)); 210 211 if (DISPLAY_VER(dev_priv) >= 9) { 212 u32 val = intel_de_read(dev_priv, 213 PSR_EVENT(cpu_transcoder)); 214 bool psr2_enabled = intel_dp->psr.psr2_enabled; 215 216 intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder), 217 val); 218 psr_event_print(dev_priv, val, psr2_enabled); 219 } 220 } 221 222 if (psr_iir & EDP_PSR_ERROR(trans_shift)) { 223 u32 val; 224 225 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", 226 transcoder_name(cpu_transcoder)); 227 228 intel_dp->psr.irq_aux_error = true; 229 230 /* 231 * If this interruption is not masked it will keep 232 * interrupting so fast that it prevents the scheduled 233 * work to run. 234 * Also after a PSR error, we don't want to arm PSR 235 * again so we don't care about unmask the interruption 236 * or unset irq_aux_error. 237 */ 238 val = intel_de_read(dev_priv, imr_reg); 239 val |= EDP_PSR_ERROR(trans_shift); 240 intel_de_write(dev_priv, imr_reg, val); 241 242 schedule_work(&intel_dp->psr.work); 243 } 244 } 245 246 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) 247 { 248 u8 alpm_caps = 0; 249 250 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, 251 &alpm_caps) != 1) 252 return false; 253 return alpm_caps & DP_ALPM_CAP; 254 } 255 256 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 257 { 258 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 259 u8 val = 8; /* assume the worst if we can't read the value */ 260 261 if (drm_dp_dpcd_readb(&intel_dp->aux, 262 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 263 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 264 else 265 drm_dbg_kms(&i915->drm, 266 "Unable to get sink synchronization latency, assuming 8 frames\n"); 267 return val; 268 } 269 270 static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) 271 { 272 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 273 ssize_t r; 274 u16 w; 275 u8 y; 276 277 /* If sink don't have specific granularity requirements set legacy ones */ 278 if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { 279 /* As PSR2 HW sends full lines, we do not care about x granularity */ 280 w = 4; 281 y = 4; 282 goto exit; 283 } 284 285 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2); 286 if (r != 2) 287 drm_dbg_kms(&i915->drm, 288 "Unable to read DP_PSR2_SU_X_GRANULARITY\n"); 289 /* 290 * Spec says that if the value read is 0 the default granularity should 291 * be used instead. 292 */ 293 if (r != 2 || w == 0) 294 w = 4; 295 296 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); 297 if (r != 1) { 298 drm_dbg_kms(&i915->drm, 299 "Unable to read DP_PSR2_SU_Y_GRANULARITY\n"); 300 y = 4; 301 } 302 if (y == 0) 303 y = 1; 304 305 exit: 306 intel_dp->psr.su_w_granularity = w; 307 intel_dp->psr.su_y_granularity = y; 308 } 309 310 void intel_psr_init_dpcd(struct intel_dp *intel_dp) 311 { 312 struct drm_i915_private *dev_priv = 313 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 314 315 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, 316 sizeof(intel_dp->psr_dpcd)); 317 318 if (!intel_dp->psr_dpcd[0]) 319 return; 320 drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n", 321 intel_dp->psr_dpcd[0]); 322 323 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { 324 drm_dbg_kms(&dev_priv->drm, 325 "PSR support not currently available for this panel\n"); 326 return; 327 } 328 329 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 330 drm_dbg_kms(&dev_priv->drm, 331 "Panel lacks power state control, PSR cannot be enabled\n"); 332 return; 333 } 334 335 intel_dp->psr.sink_support = true; 336 intel_dp->psr.sink_sync_latency = 337 intel_dp_get_sink_sync_latency(intel_dp); 338 339 if (DISPLAY_VER(dev_priv) >= 9 && 340 (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { 341 bool y_req = intel_dp->psr_dpcd[1] & 342 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 343 bool alpm = intel_dp_get_alpm_status(intel_dp); 344 345 /* 346 * All panels that supports PSR version 03h (PSR2 + 347 * Y-coordinate) can handle Y-coordinates in VSC but we are 348 * only sure that it is going to be used when required by the 349 * panel. This way panel is capable to do selective update 350 * without a aux frame sync. 351 * 352 * To support PSR version 02h and PSR version 03h without 353 * Y-coordinate requirement panels we would need to enable 354 * GTC first. 355 */ 356 intel_dp->psr.sink_psr2_support = y_req && alpm; 357 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n", 358 intel_dp->psr.sink_psr2_support ? "" : "not "); 359 360 if (intel_dp->psr.sink_psr2_support) { 361 intel_dp->psr.colorimetry_support = 362 intel_dp_get_colorimetry_status(intel_dp); 363 intel_dp_get_su_granularity(intel_dp); 364 } 365 } 366 } 367 368 static void intel_psr_enable_sink(struct intel_dp *intel_dp) 369 { 370 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 371 u8 dpcd_val = DP_PSR_ENABLE; 372 373 /* Enable ALPM at sink for psr2 */ 374 if (intel_dp->psr.psr2_enabled) { 375 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 376 DP_ALPM_ENABLE | 377 DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); 378 379 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 380 } else { 381 if (intel_dp->psr.link_standby) 382 dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; 383 384 if (DISPLAY_VER(dev_priv) >= 8) 385 dpcd_val |= DP_PSR_CRC_VERIFICATION; 386 } 387 388 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 389 dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; 390 391 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); 392 393 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 394 } 395 396 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 397 { 398 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 399 u32 val = 0; 400 401 if (DISPLAY_VER(dev_priv) >= 11) 402 val |= EDP_PSR_TP4_TIME_0US; 403 404 if (dev_priv->params.psr_safest_params) { 405 val |= EDP_PSR_TP1_TIME_2500us; 406 val |= EDP_PSR_TP2_TP3_TIME_2500us; 407 goto check_tp3_sel; 408 } 409 410 if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) 411 val |= EDP_PSR_TP1_TIME_0us; 412 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100) 413 val |= EDP_PSR_TP1_TIME_100us; 414 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500) 415 val |= EDP_PSR_TP1_TIME_500us; 416 else 417 val |= EDP_PSR_TP1_TIME_2500us; 418 419 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0) 420 val |= EDP_PSR_TP2_TP3_TIME_0us; 421 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) 422 val |= EDP_PSR_TP2_TP3_TIME_100us; 423 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) 424 val |= EDP_PSR_TP2_TP3_TIME_500us; 425 else 426 val |= EDP_PSR_TP2_TP3_TIME_2500us; 427 428 check_tp3_sel: 429 if (intel_dp_source_supports_tps3(dev_priv) && 430 drm_dp_tps3_supported(intel_dp->dpcd)) 431 val |= EDP_PSR_TP1_TP3_SEL; 432 else 433 val |= EDP_PSR_TP1_TP2_SEL; 434 435 return val; 436 } 437 438 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 439 { 440 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 441 int idle_frames; 442 443 /* Let's use 6 as the minimum to cover all known cases including the 444 * off-by-one issue that HW has in some cases. 445 */ 446 idle_frames = max(6, dev_priv->vbt.psr.idle_frames); 447 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1); 448 449 if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf)) 450 idle_frames = 0xf; 451 452 return idle_frames; 453 } 454 455 static void hsw_activate_psr1(struct intel_dp *intel_dp) 456 { 457 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 458 u32 max_sleep_time = 0x1f; 459 u32 val = EDP_PSR_ENABLE; 460 461 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT; 462 463 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; 464 if (IS_HASWELL(dev_priv)) 465 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 466 467 if (intel_dp->psr.link_standby) 468 val |= EDP_PSR_LINK_STANDBY; 469 470 val |= intel_psr1_get_tp_time(intel_dp); 471 472 if (DISPLAY_VER(dev_priv) >= 8) 473 val |= EDP_PSR_CRC_ENABLE; 474 475 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) & 476 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK); 477 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val); 478 } 479 480 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 481 { 482 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 483 u32 val = 0; 484 485 if (dev_priv->params.psr_safest_params) 486 return EDP_PSR2_TP2_TIME_2500us; 487 488 if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 489 dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 490 val |= EDP_PSR2_TP2_TIME_50us; 491 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 492 val |= EDP_PSR2_TP2_TIME_100us; 493 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 494 val |= EDP_PSR2_TP2_TIME_500us; 495 else 496 val |= EDP_PSR2_TP2_TIME_2500us; 497 498 return val; 499 } 500 501 static void hsw_activate_psr2(struct intel_dp *intel_dp) 502 { 503 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 504 u32 val = EDP_PSR2_ENABLE; 505 506 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT; 507 508 if (!IS_ALDERLAKE_P(dev_priv)) 509 val |= EDP_SU_TRACK_ENABLE; 510 511 if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12) 512 val |= EDP_Y_COORDINATE_ENABLE; 513 514 val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2)); 515 val |= intel_psr2_get_tp_time(intel_dp); 516 517 /* Wa_22012278275:adl-p */ 518 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { 519 static const u8 map[] = { 520 2, /* 5 lines */ 521 1, /* 6 lines */ 522 0, /* 7 lines */ 523 3, /* 8 lines */ 524 6, /* 9 lines */ 525 5, /* 10 lines */ 526 4, /* 11 lines */ 527 7, /* 12 lines */ 528 }; 529 /* 530 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see 531 * comments bellow for more information 532 */ 533 u32 tmp, lines = 7; 534 535 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 536 537 tmp = map[lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; 538 tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT; 539 val |= tmp; 540 541 tmp = map[lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; 542 tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT; 543 val |= tmp; 544 } else if (DISPLAY_VER(dev_priv) >= 12) { 545 /* 546 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default 547 * values from BSpec. In order to setting an optimal power 548 * consumption, lower than 4k resoluition mode needs to decrese 549 * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution 550 * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE. 551 */ 552 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 553 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7); 554 val |= TGL_EDP_PSR2_FAST_WAKE(7); 555 } else if (DISPLAY_VER(dev_priv) >= 9) { 556 val |= EDP_PSR2_IO_BUFFER_WAKE(7); 557 val |= EDP_PSR2_FAST_WAKE(7); 558 } 559 560 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 561 val |= EDP_PSR2_SU_SDP_SCANLINE; 562 563 if (intel_dp->psr.psr2_sel_fetch_enabled) { 564 u32 tmp; 565 566 /* Wa_1408330847 */ 567 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 568 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 569 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 570 DIS_RAM_BYPASS_PSR2_MAN_TRACK); 571 572 tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); 573 drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); 574 } else if (HAS_PSR2_SEL_FETCH(dev_priv)) { 575 intel_de_write(dev_priv, 576 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0); 577 } 578 579 /* 580 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 581 * recommending keep this bit unset while PSR2 is enabled. 582 */ 583 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0); 584 585 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 586 } 587 588 static bool 589 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) 590 { 591 if (IS_ALDERLAKE_P(dev_priv)) 592 return trans == TRANSCODER_A || trans == TRANSCODER_B; 593 else if (DISPLAY_VER(dev_priv) >= 12) 594 return trans == TRANSCODER_A; 595 else 596 return trans == TRANSCODER_EDP; 597 } 598 599 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate) 600 { 601 if (!cstate || !cstate->hw.active) 602 return 0; 603 604 return DIV_ROUND_UP(1000 * 1000, 605 drm_mode_vrefresh(&cstate->hw.adjusted_mode)); 606 } 607 608 static void psr2_program_idle_frames(struct intel_dp *intel_dp, 609 u32 idle_frames) 610 { 611 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 612 u32 val; 613 614 idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; 615 val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder)); 616 val &= ~EDP_PSR2_IDLE_FRAME_MASK; 617 val |= idle_frames; 618 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 619 } 620 621 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) 622 { 623 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 624 625 psr2_program_idle_frames(intel_dp, 0); 626 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO); 627 } 628 629 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp) 630 { 631 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 632 633 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 634 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp)); 635 } 636 637 static void tgl_dc3co_disable_work(struct work_struct *work) 638 { 639 struct intel_dp *intel_dp = 640 container_of(work, typeof(*intel_dp), psr.dc3co_work.work); 641 642 mutex_lock(&intel_dp->psr.lock); 643 /* If delayed work is pending, it is not idle */ 644 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) 645 goto unlock; 646 647 tgl_psr2_disable_dc3co(intel_dp); 648 unlock: 649 mutex_unlock(&intel_dp->psr.lock); 650 } 651 652 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) 653 { 654 if (!intel_dp->psr.dc3co_exitline) 655 return; 656 657 cancel_delayed_work(&intel_dp->psr.dc3co_work); 658 /* Before PSR2 exit disallow dc3co*/ 659 tgl_psr2_disable_dc3co(intel_dp); 660 } 661 662 static bool 663 dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp, 664 struct intel_crtc_state *crtc_state) 665 { 666 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 667 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 668 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 669 enum port port = dig_port->base.port; 670 671 if (IS_ALDERLAKE_P(dev_priv)) 672 return pipe <= PIPE_B && port <= PORT_B; 673 else 674 return pipe == PIPE_A && port == PORT_A; 675 } 676 677 static void 678 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 679 struct intel_crtc_state *crtc_state) 680 { 681 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; 682 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 683 u32 exit_scanlines; 684 685 /* 686 * FIXME: Due to the changed sequence of activating/deactivating DC3CO, 687 * disable DC3CO until the changed dc3co activating/deactivating sequence 688 * is applied. B.Specs:49196 689 */ 690 return; 691 692 /* 693 * DMC's DC3CO exit mechanism has an issue with Selective Fecth 694 * TODO: when the issue is addressed, this restriction should be removed. 695 */ 696 if (crtc_state->enable_psr2_sel_fetch) 697 return; 698 699 if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO)) 700 return; 701 702 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) 703 return; 704 705 /* Wa_16011303918:adl-p */ 706 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 707 return; 708 709 /* 710 * DC3CO Exit time 200us B.Spec 49196 711 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 712 */ 713 exit_scanlines = 714 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; 715 716 if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay)) 717 return; 718 719 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; 720 } 721 722 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, 723 struct intel_crtc_state *crtc_state) 724 { 725 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 726 727 if (!dev_priv->params.enable_psr2_sel_fetch && 728 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 729 drm_dbg_kms(&dev_priv->drm, 730 "PSR2 sel fetch not enabled, disabled by parameter\n"); 731 return false; 732 } 733 734 if (crtc_state->uapi.async_flip) { 735 drm_dbg_kms(&dev_priv->drm, 736 "PSR2 sel fetch not enabled, async flip enabled\n"); 737 return false; 738 } 739 740 /* Wa_14010254185 Wa_14010103792 */ 741 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { 742 drm_dbg_kms(&dev_priv->drm, 743 "PSR2 sel fetch not enabled, missing the implementation of WAs\n"); 744 return false; 745 } 746 747 return crtc_state->enable_psr2_sel_fetch = true; 748 } 749 750 static bool psr2_granularity_check(struct intel_dp *intel_dp, 751 struct intel_crtc_state *crtc_state) 752 { 753 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 754 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 755 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 756 u16 y_granularity = 0; 757 758 /* PSR2 HW only send full lines so we only need to validate the width */ 759 if (crtc_hdisplay % intel_dp->psr.su_w_granularity) 760 return false; 761 762 if (crtc_vdisplay % intel_dp->psr.su_y_granularity) 763 return false; 764 765 /* HW tracking is only aligned to 4 lines */ 766 if (!crtc_state->enable_psr2_sel_fetch) 767 return intel_dp->psr.su_y_granularity == 4; 768 769 /* 770 * adl_p has 1 line granularity. For other platforms with SW tracking we 771 * can adjust the y coordinates to match sink requirement if multiple of 772 * 4. 773 */ 774 if (IS_ALDERLAKE_P(dev_priv)) 775 y_granularity = intel_dp->psr.su_y_granularity; 776 else if (intel_dp->psr.su_y_granularity <= 2) 777 y_granularity = 4; 778 else if ((intel_dp->psr.su_y_granularity % 4) == 0) 779 y_granularity = intel_dp->psr.su_y_granularity; 780 781 if (y_granularity == 0 || crtc_vdisplay % y_granularity) 782 return false; 783 784 crtc_state->su_y_granularity = y_granularity; 785 return true; 786 } 787 788 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp, 789 struct intel_crtc_state *crtc_state) 790 { 791 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; 792 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 793 u32 hblank_total, hblank_ns, req_ns; 794 795 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; 796 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); 797 798 /* From spec: (72 / number of lanes) * 1000 / symbol clock frequency MHz */ 799 req_ns = (72 / crtc_state->lane_count) * 1000 / (crtc_state->port_clock / 1000); 800 801 if ((hblank_ns - req_ns) > 100) 802 return true; 803 804 if (DISPLAY_VER(dev_priv) < 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b) 805 return false; 806 807 crtc_state->req_psr2_sdp_prior_scanline = true; 808 return true; 809 } 810 811 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 812 struct intel_crtc_state *crtc_state) 813 { 814 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 815 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 816 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 817 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 818 819 if (!intel_dp->psr.sink_psr2_support) 820 return false; 821 822 /* JSL and EHL only supports eDP 1.3 */ 823 if (IS_JSL_EHL(dev_priv)) { 824 drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n"); 825 return false; 826 } 827 828 /* Wa_16011181250 */ 829 if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) || 830 IS_DG2(dev_priv)) { 831 drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n"); 832 return false; 833 } 834 835 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 836 drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n"); 837 return false; 838 } 839 840 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { 841 drm_dbg_kms(&dev_priv->drm, 842 "PSR2 not supported in transcoder %s\n", 843 transcoder_name(crtc_state->cpu_transcoder)); 844 return false; 845 } 846 847 if (!psr2_global_enabled(intel_dp)) { 848 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); 849 return false; 850 } 851 852 /* 853 * DSC and PSR2 cannot be enabled simultaneously. If a requested 854 * resolution requires DSC to be enabled, priority is given to DSC 855 * over PSR2. 856 */ 857 if (crtc_state->dsc.compression_enable) { 858 drm_dbg_kms(&dev_priv->drm, 859 "PSR2 cannot be enabled since DSC is enabled\n"); 860 return false; 861 } 862 863 if (crtc_state->crc_enabled) { 864 drm_dbg_kms(&dev_priv->drm, 865 "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); 866 return false; 867 } 868 869 if (DISPLAY_VER(dev_priv) >= 12) { 870 psr_max_h = 5120; 871 psr_max_v = 3200; 872 max_bpp = 30; 873 } else if (DISPLAY_VER(dev_priv) >= 10) { 874 psr_max_h = 4096; 875 psr_max_v = 2304; 876 max_bpp = 24; 877 } else if (DISPLAY_VER(dev_priv) == 9) { 878 psr_max_h = 3640; 879 psr_max_v = 2304; 880 max_bpp = 24; 881 } 882 883 if (crtc_state->pipe_bpp > max_bpp) { 884 drm_dbg_kms(&dev_priv->drm, 885 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 886 crtc_state->pipe_bpp, max_bpp); 887 return false; 888 } 889 890 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 891 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && 892 !HAS_PSR_HW_TRACKING(dev_priv)) { 893 drm_dbg_kms(&dev_priv->drm, 894 "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); 895 return false; 896 } 897 } 898 899 /* Wa_2209313811 */ 900 if (!crtc_state->enable_psr2_sel_fetch && 901 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { 902 drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n"); 903 return false; 904 } 905 906 if (!psr2_granularity_check(intel_dp, crtc_state)) { 907 drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n"); 908 return false; 909 } 910 911 if (!crtc_state->enable_psr2_sel_fetch && 912 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { 913 drm_dbg_kms(&dev_priv->drm, 914 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 915 crtc_hdisplay, crtc_vdisplay, 916 psr_max_h, psr_max_v); 917 return false; 918 } 919 920 if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) { 921 drm_dbg_kms(&dev_priv->drm, 922 "PSR2 not enabled, PSR2 SDP indication do not fit in hblank\n"); 923 return false; 924 } 925 926 /* Wa_16011303918:adl-p */ 927 if (crtc_state->vrr.enable && 928 IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 929 drm_dbg_kms(&dev_priv->drm, 930 "PSR2 not enabled, not compatible with HW stepping + VRR\n"); 931 return false; 932 } 933 934 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); 935 return true; 936 } 937 938 void intel_psr_compute_config(struct intel_dp *intel_dp, 939 struct intel_crtc_state *crtc_state, 940 struct drm_connector_state *conn_state) 941 { 942 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 943 const struct drm_display_mode *adjusted_mode = 944 &crtc_state->hw.adjusted_mode; 945 int psr_setup_time; 946 947 /* 948 * Current PSR panels dont work reliably with VRR enabled 949 * So if VRR is enabled, do not enable PSR. 950 */ 951 if (crtc_state->vrr.enable) 952 return; 953 954 if (!CAN_PSR(intel_dp)) 955 return; 956 957 if (!psr_global_enabled(intel_dp)) { 958 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); 959 return; 960 } 961 962 if (intel_dp->psr.sink_not_reliable) { 963 drm_dbg_kms(&dev_priv->drm, 964 "PSR sink implementation is not reliable\n"); 965 return; 966 } 967 968 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 969 drm_dbg_kms(&dev_priv->drm, 970 "PSR condition failed: Interlaced mode enabled\n"); 971 return; 972 } 973 974 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); 975 if (psr_setup_time < 0) { 976 drm_dbg_kms(&dev_priv->drm, 977 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 978 intel_dp->psr_dpcd[1]); 979 return; 980 } 981 982 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 983 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 984 drm_dbg_kms(&dev_priv->drm, 985 "PSR condition failed: PSR setup time (%d us) too long\n", 986 psr_setup_time); 987 return; 988 } 989 990 crtc_state->has_psr = true; 991 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); 992 993 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 994 intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, 995 &crtc_state->psr_vsc); 996 } 997 998 void intel_psr_get_config(struct intel_encoder *encoder, 999 struct intel_crtc_state *pipe_config) 1000 { 1001 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1002 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1003 struct intel_dp *intel_dp; 1004 u32 val; 1005 1006 if (!dig_port) 1007 return; 1008 1009 intel_dp = &dig_port->dp; 1010 if (!CAN_PSR(intel_dp)) 1011 return; 1012 1013 mutex_lock(&intel_dp->psr.lock); 1014 if (!intel_dp->psr.enabled) 1015 goto unlock; 1016 1017 /* 1018 * Not possible to read EDP_PSR/PSR2_CTL registers as it is 1019 * enabled/disabled because of frontbuffer tracking and others. 1020 */ 1021 pipe_config->has_psr = true; 1022 pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; 1023 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1024 1025 if (!intel_dp->psr.psr2_enabled) 1026 goto unlock; 1027 1028 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 1029 val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); 1030 if (val & PSR2_MAN_TRK_CTL_ENABLE) 1031 pipe_config->enable_psr2_sel_fetch = true; 1032 } 1033 1034 if (DISPLAY_VER(dev_priv) >= 12) { 1035 val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder)); 1036 val &= EXITLINE_MASK; 1037 pipe_config->dc3co_exitline = val; 1038 } 1039 unlock: 1040 mutex_unlock(&intel_dp->psr.lock); 1041 } 1042 1043 static void intel_psr_activate(struct intel_dp *intel_dp) 1044 { 1045 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1046 enum transcoder transcoder = intel_dp->psr.transcoder; 1047 1048 if (transcoder_has_psr2(dev_priv, transcoder)) 1049 drm_WARN_ON(&dev_priv->drm, 1050 intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE); 1051 1052 drm_WARN_ON(&dev_priv->drm, 1053 intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE); 1054 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active); 1055 lockdep_assert_held(&intel_dp->psr.lock); 1056 1057 /* psr1 and psr2 are mutually exclusive.*/ 1058 if (intel_dp->psr.psr2_enabled) 1059 hsw_activate_psr2(intel_dp); 1060 else 1061 hsw_activate_psr1(intel_dp); 1062 1063 intel_dp->psr.active = true; 1064 } 1065 1066 static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp) 1067 { 1068 switch (intel_dp->psr.pipe) { 1069 case PIPE_A: 1070 return LATENCY_REPORTING_REMOVED_PIPE_A; 1071 case PIPE_B: 1072 return LATENCY_REPORTING_REMOVED_PIPE_B; 1073 case PIPE_C: 1074 return LATENCY_REPORTING_REMOVED_PIPE_C; 1075 default: 1076 MISSING_CASE(intel_dp->psr.pipe); 1077 return 0; 1078 } 1079 } 1080 1081 static void intel_psr_enable_source(struct intel_dp *intel_dp, 1082 const struct intel_crtc_state *crtc_state) 1083 { 1084 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1085 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1086 u32 mask; 1087 1088 /* 1089 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 1090 * mask LPSP to avoid dependency on other drivers that might block 1091 * runtime_pm besides preventing other hw tracking issues now we 1092 * can rely on frontbuffer tracking. 1093 */ 1094 mask = EDP_PSR_DEBUG_MASK_MEMUP | 1095 EDP_PSR_DEBUG_MASK_HPD | 1096 EDP_PSR_DEBUG_MASK_LPSP | 1097 EDP_PSR_DEBUG_MASK_MAX_SLEEP; 1098 1099 if (DISPLAY_VER(dev_priv) < 11) 1100 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 1101 1102 intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder), 1103 mask); 1104 1105 psr_irq_control(intel_dp); 1106 1107 if (intel_dp->psr.dc3co_exitline) { 1108 u32 val; 1109 1110 /* 1111 * TODO: if future platforms supports DC3CO in more than one 1112 * transcoder, EXITLINE will need to be unset when disabling PSR 1113 */ 1114 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder)); 1115 val &= ~EXITLINE_MASK; 1116 val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT; 1117 val |= EXITLINE_ENABLE; 1118 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); 1119 } 1120 1121 if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv)) 1122 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, 1123 intel_dp->psr.psr2_sel_fetch_enabled ? 1124 IGNORE_PSR2_HW_TRACKING : 0); 1125 1126 if (intel_dp->psr.psr2_enabled) { 1127 if (DISPLAY_VER(dev_priv) == 9) 1128 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, 1129 PSR2_VSC_ENABLE_PROG_HEADER | 1130 PSR2_ADD_VERTICAL_LINE_COUNT); 1131 1132 /* 1133 * Wa_16014451276:adlp 1134 * All supported adlp panels have 1-based X granularity, this may 1135 * cause issues if non-supported panels are used. 1136 */ 1137 if (IS_ALDERLAKE_P(dev_priv)) 1138 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, 1139 ADLP_1_BASED_X_GRANULARITY); 1140 1141 /* Wa_16011168373:adl-p */ 1142 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1143 intel_de_rmw(dev_priv, 1144 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), 1145 TRANS_SET_CONTEXT_LATENCY_MASK, 1146 TRANS_SET_CONTEXT_LATENCY_VALUE(1)); 1147 1148 /* Wa_16012604467:adlp */ 1149 if (IS_ALDERLAKE_P(dev_priv)) 1150 intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0, 1151 CLKGATE_DIS_MISC_DMASC_GATING_DIS); 1152 1153 /* Wa_16013835468:tgl[b0+], dg1 */ 1154 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) || 1155 IS_DG1(dev_priv)) { 1156 u16 vtotal, vblank; 1157 1158 vtotal = crtc_state->uapi.adjusted_mode.crtc_vtotal - 1159 crtc_state->uapi.adjusted_mode.crtc_vdisplay; 1160 vblank = crtc_state->uapi.adjusted_mode.crtc_vblank_end - 1161 crtc_state->uapi.adjusted_mode.crtc_vblank_start; 1162 if (vblank > vtotal) 1163 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, 1164 wa_16013835468_bit_get(intel_dp)); 1165 } 1166 } 1167 } 1168 1169 static bool psr_interrupt_error_check(struct intel_dp *intel_dp) 1170 { 1171 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1172 u32 val; 1173 1174 /* 1175 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 1176 * will still keep the error set even after the reset done in the 1177 * irq_preinstall and irq_uninstall hooks. 1178 * And enabling in this situation cause the screen to freeze in the 1179 * first time that PSR HW tries to activate so lets keep PSR disabled 1180 * to avoid any rendering problems. 1181 */ 1182 if (DISPLAY_VER(dev_priv) >= 12) { 1183 val = intel_de_read(dev_priv, 1184 TRANS_PSR_IIR(intel_dp->psr.transcoder)); 1185 val &= EDP_PSR_ERROR(0); 1186 } else { 1187 val = intel_de_read(dev_priv, EDP_PSR_IIR); 1188 val &= EDP_PSR_ERROR(intel_dp->psr.transcoder); 1189 } 1190 if (val) { 1191 intel_dp->psr.sink_not_reliable = true; 1192 drm_dbg_kms(&dev_priv->drm, 1193 "PSR interruption error set, not enabling PSR\n"); 1194 return false; 1195 } 1196 1197 return true; 1198 } 1199 1200 static void intel_psr_enable_locked(struct intel_dp *intel_dp, 1201 const struct intel_crtc_state *crtc_state) 1202 { 1203 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1204 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1205 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 1206 struct intel_encoder *encoder = &dig_port->base; 1207 u32 val; 1208 1209 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); 1210 1211 intel_dp->psr.psr2_enabled = crtc_state->has_psr2; 1212 intel_dp->psr.busy_frontbuffer_bits = 0; 1213 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1214 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; 1215 /* DC5/DC6 requires at least 6 idle frames */ 1216 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 1217 intel_dp->psr.dc3co_exit_delay = val; 1218 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; 1219 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; 1220 intel_dp->psr.req_psr2_sdp_prior_scanline = 1221 crtc_state->req_psr2_sdp_prior_scanline; 1222 1223 if (!psr_interrupt_error_check(intel_dp)) 1224 return; 1225 1226 drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", 1227 intel_dp->psr.psr2_enabled ? "2" : "1"); 1228 intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc); 1229 intel_snps_phy_update_psr_power_state(dev_priv, phy, true); 1230 intel_psr_enable_sink(intel_dp); 1231 intel_psr_enable_source(intel_dp, crtc_state); 1232 intel_dp->psr.enabled = true; 1233 intel_dp->psr.paused = false; 1234 1235 intel_psr_activate(intel_dp); 1236 } 1237 1238 static void intel_psr_exit(struct intel_dp *intel_dp) 1239 { 1240 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1241 u32 val; 1242 1243 if (!intel_dp->psr.active) { 1244 if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) { 1245 val = intel_de_read(dev_priv, 1246 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1247 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE); 1248 } 1249 1250 val = intel_de_read(dev_priv, 1251 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1252 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE); 1253 1254 return; 1255 } 1256 1257 if (intel_dp->psr.psr2_enabled) { 1258 tgl_disallow_dc3co_on_psr2_exit(intel_dp); 1259 val = intel_de_read(dev_priv, 1260 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1261 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE)); 1262 val &= ~EDP_PSR2_ENABLE; 1263 intel_de_write(dev_priv, 1264 EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 1265 } else { 1266 val = intel_de_read(dev_priv, 1267 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1268 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE)); 1269 val &= ~EDP_PSR_ENABLE; 1270 intel_de_write(dev_priv, 1271 EDP_PSR_CTL(intel_dp->psr.transcoder), val); 1272 } 1273 intel_dp->psr.active = false; 1274 } 1275 1276 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) 1277 { 1278 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1279 i915_reg_t psr_status; 1280 u32 psr_status_mask; 1281 1282 if (intel_dp->psr.psr2_enabled) { 1283 psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 1284 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 1285 } else { 1286 psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder); 1287 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 1288 } 1289 1290 /* Wait till PSR is idle */ 1291 if (intel_de_wait_for_clear(dev_priv, psr_status, 1292 psr_status_mask, 2000)) 1293 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n"); 1294 } 1295 1296 static void intel_psr_disable_locked(struct intel_dp *intel_dp) 1297 { 1298 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1299 enum phy phy = intel_port_to_phy(dev_priv, 1300 dp_to_dig_port(intel_dp)->base.port); 1301 1302 lockdep_assert_held(&intel_dp->psr.lock); 1303 1304 if (!intel_dp->psr.enabled) 1305 return; 1306 1307 drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", 1308 intel_dp->psr.psr2_enabled ? "2" : "1"); 1309 1310 intel_psr_exit(intel_dp); 1311 intel_psr_wait_exit_locked(intel_dp); 1312 1313 /* Wa_1408330847 */ 1314 if (intel_dp->psr.psr2_sel_fetch_enabled && 1315 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1316 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1317 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0); 1318 1319 if (intel_dp->psr.psr2_enabled) { 1320 /* Wa_16011168373:adl-p */ 1321 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1322 intel_de_rmw(dev_priv, 1323 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), 1324 TRANS_SET_CONTEXT_LATENCY_MASK, 0); 1325 1326 /* Wa_16012604467:adlp */ 1327 if (IS_ALDERLAKE_P(dev_priv)) 1328 intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 1329 CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0); 1330 1331 /* Wa_16013835468:tgl[b0+], dg1 */ 1332 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) || 1333 IS_DG1(dev_priv)) 1334 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 1335 wa_16013835468_bit_get(intel_dp), 0); 1336 } 1337 1338 intel_snps_phy_update_psr_power_state(dev_priv, phy, false); 1339 1340 /* Disable PSR on Sink */ 1341 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 1342 1343 if (intel_dp->psr.psr2_enabled) 1344 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); 1345 1346 intel_dp->psr.enabled = false; 1347 } 1348 1349 /** 1350 * intel_psr_disable - Disable PSR 1351 * @intel_dp: Intel DP 1352 * @old_crtc_state: old CRTC state 1353 * 1354 * This function needs to be called before disabling pipe. 1355 */ 1356 void intel_psr_disable(struct intel_dp *intel_dp, 1357 const struct intel_crtc_state *old_crtc_state) 1358 { 1359 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1360 1361 if (!old_crtc_state->has_psr) 1362 return; 1363 1364 if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp))) 1365 return; 1366 1367 mutex_lock(&intel_dp->psr.lock); 1368 1369 intel_psr_disable_locked(intel_dp); 1370 1371 mutex_unlock(&intel_dp->psr.lock); 1372 cancel_work_sync(&intel_dp->psr.work); 1373 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); 1374 } 1375 1376 /** 1377 * intel_psr_pause - Pause PSR 1378 * @intel_dp: Intel DP 1379 * 1380 * This function need to be called after enabling psr. 1381 */ 1382 void intel_psr_pause(struct intel_dp *intel_dp) 1383 { 1384 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1385 struct intel_psr *psr = &intel_dp->psr; 1386 1387 if (!CAN_PSR(intel_dp)) 1388 return; 1389 1390 mutex_lock(&psr->lock); 1391 1392 if (!psr->enabled) { 1393 mutex_unlock(&psr->lock); 1394 return; 1395 } 1396 1397 /* If we ever hit this, we will need to add refcount to pause/resume */ 1398 drm_WARN_ON(&dev_priv->drm, psr->paused); 1399 1400 intel_psr_exit(intel_dp); 1401 intel_psr_wait_exit_locked(intel_dp); 1402 psr->paused = true; 1403 1404 mutex_unlock(&psr->lock); 1405 1406 cancel_work_sync(&psr->work); 1407 cancel_delayed_work_sync(&psr->dc3co_work); 1408 } 1409 1410 /** 1411 * intel_psr_resume - Resume PSR 1412 * @intel_dp: Intel DP 1413 * 1414 * This function need to be called after pausing psr. 1415 */ 1416 void intel_psr_resume(struct intel_dp *intel_dp) 1417 { 1418 struct intel_psr *psr = &intel_dp->psr; 1419 1420 if (!CAN_PSR(intel_dp)) 1421 return; 1422 1423 mutex_lock(&psr->lock); 1424 1425 if (!psr->paused) 1426 goto unlock; 1427 1428 psr->paused = false; 1429 intel_psr_activate(intel_dp); 1430 1431 unlock: 1432 mutex_unlock(&psr->lock); 1433 } 1434 1435 static inline u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private *dev_priv) 1436 { 1437 return IS_ALDERLAKE_P(dev_priv) ? 1438 ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME : 1439 PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 1440 } 1441 1442 static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) 1443 { 1444 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1445 1446 if (intel_dp->psr.psr2_sel_fetch_enabled) 1447 intel_de_rmw(dev_priv, 1448 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0, 1449 man_trk_ctl_single_full_frame_bit_get(dev_priv)); 1450 1451 /* 1452 * Display WA #0884: skl+ 1453 * This documented WA for bxt can be safely applied 1454 * broadly so we can force HW tracking to exit PSR 1455 * instead of disabling and re-enabling. 1456 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 1457 * but it makes more sense write to the current active 1458 * pipe. 1459 * 1460 * This workaround do not exist for platforms with display 10 or newer 1461 * but testing proved that it works for up display 13, for newer 1462 * than that testing will be needed. 1463 */ 1464 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 1465 } 1466 1467 void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane, 1468 const struct intel_crtc_state *crtc_state) 1469 { 1470 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1471 enum pipe pipe = plane->pipe; 1472 1473 if (!crtc_state->enable_psr2_sel_fetch) 1474 return; 1475 1476 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0); 1477 } 1478 1479 void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, 1480 const struct intel_crtc_state *crtc_state, 1481 const struct intel_plane_state *plane_state, 1482 int color_plane) 1483 { 1484 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1485 enum pipe pipe = plane->pipe; 1486 const struct drm_rect *clip; 1487 u32 val; 1488 int x, y; 1489 1490 if (!crtc_state->enable_psr2_sel_fetch) 1491 return; 1492 1493 if (plane->id == PLANE_CURSOR) { 1494 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 1495 plane_state->ctl); 1496 return; 1497 } 1498 1499 clip = &plane_state->psr2_sel_fetch_area; 1500 1501 val = (clip->y1 + plane_state->uapi.dst.y1) << 16; 1502 val |= plane_state->uapi.dst.x1; 1503 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); 1504 1505 x = plane_state->view.color_plane[color_plane].x; 1506 1507 /* 1508 * From Bspec: UV surface Start Y Position = half of Y plane Y 1509 * start position. 1510 */ 1511 if (!color_plane) 1512 y = plane_state->view.color_plane[color_plane].y + clip->y1; 1513 else 1514 y = plane_state->view.color_plane[color_plane].y + clip->y1 / 2; 1515 1516 val = y << 16 | x; 1517 1518 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), 1519 val); 1520 1521 /* Sizes are 0 based */ 1522 val = (drm_rect_height(clip) - 1) << 16; 1523 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; 1524 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); 1525 1526 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 1527 PLANE_SEL_FETCH_CTL_ENABLE); 1528 } 1529 1530 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) 1531 { 1532 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1533 1534 if (!crtc_state->enable_psr2_sel_fetch) 1535 return; 1536 1537 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder), 1538 crtc_state->psr2_man_track_ctl); 1539 } 1540 1541 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, 1542 struct drm_rect *clip, bool full_update) 1543 { 1544 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1545 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1546 u32 val = PSR2_MAN_TRK_CTL_ENABLE; 1547 1548 if (full_update) { 1549 /* 1550 * Not applying Wa_14014971508:adlp as we do not support the 1551 * feature that requires this workaround. 1552 */ 1553 val |= man_trk_ctl_single_full_frame_bit_get(dev_priv); 1554 goto exit; 1555 } 1556 1557 if (clip->y1 == -1) 1558 goto exit; 1559 1560 if (IS_ALDERLAKE_P(dev_priv)) { 1561 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1); 1562 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 - 1); 1563 } else { 1564 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4); 1565 1566 val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; 1567 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1); 1568 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1); 1569 } 1570 exit: 1571 crtc_state->psr2_man_track_ctl = val; 1572 } 1573 1574 static void clip_area_update(struct drm_rect *overlap_damage_area, 1575 struct drm_rect *damage_area) 1576 { 1577 if (overlap_damage_area->y1 == -1) { 1578 overlap_damage_area->y1 = damage_area->y1; 1579 overlap_damage_area->y2 = damage_area->y2; 1580 return; 1581 } 1582 1583 if (damage_area->y1 < overlap_damage_area->y1) 1584 overlap_damage_area->y1 = damage_area->y1; 1585 1586 if (damage_area->y2 > overlap_damage_area->y2) 1587 overlap_damage_area->y2 = damage_area->y2; 1588 } 1589 1590 static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state, 1591 struct drm_rect *pipe_clip) 1592 { 1593 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1594 const u16 y_alignment = crtc_state->su_y_granularity; 1595 1596 pipe_clip->y1 -= pipe_clip->y1 % y_alignment; 1597 if (pipe_clip->y2 % y_alignment) 1598 pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment; 1599 1600 if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable) 1601 drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n"); 1602 } 1603 1604 /* 1605 * TODO: Not clear how to handle planes with negative position, 1606 * also planes are not updated if they have a negative X 1607 * position so for now doing a full update in this cases 1608 * 1609 * Plane scaling and rotation is not supported by selective fetch and both 1610 * properties can change without a modeset, so need to be check at every 1611 * atomic commmit. 1612 */ 1613 static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state) 1614 { 1615 if (plane_state->uapi.dst.y1 < 0 || 1616 plane_state->uapi.dst.x1 < 0 || 1617 plane_state->scaler_id >= 0 || 1618 plane_state->uapi.rotation != DRM_MODE_ROTATE_0) 1619 return false; 1620 1621 return true; 1622 } 1623 1624 /* 1625 * Check for pipe properties that is not supported by selective fetch. 1626 * 1627 * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed 1628 * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch 1629 * enabled and going to the full update path. 1630 */ 1631 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state) 1632 { 1633 if (crtc_state->scaler_state.scaler_id >= 0) 1634 return false; 1635 1636 return true; 1637 } 1638 1639 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 1640 struct intel_crtc *crtc) 1641 { 1642 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 1643 struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 }; 1644 struct intel_plane_state *new_plane_state, *old_plane_state; 1645 struct intel_plane *plane; 1646 bool full_update = false; 1647 int i, ret; 1648 1649 if (!crtc_state->enable_psr2_sel_fetch) 1650 return 0; 1651 1652 if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) { 1653 full_update = true; 1654 goto skip_sel_fetch_set_loop; 1655 } 1656 1657 /* 1658 * Calculate minimal selective fetch area of each plane and calculate 1659 * the pipe damaged area. 1660 * In the next loop the plane selective fetch area will actually be set 1661 * using whole pipe damaged area. 1662 */ 1663 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1664 new_plane_state, i) { 1665 struct drm_rect src, damaged_area = { .y1 = -1 }; 1666 struct drm_atomic_helper_damage_iter iter; 1667 struct drm_rect clip; 1668 1669 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) 1670 continue; 1671 1672 if (!new_plane_state->uapi.visible && 1673 !old_plane_state->uapi.visible) 1674 continue; 1675 1676 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 1677 full_update = true; 1678 break; 1679 } 1680 1681 /* 1682 * If visibility or plane moved, mark the whole plane area as 1683 * damaged as it needs to be complete redraw in the new and old 1684 * position. 1685 */ 1686 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || 1687 !drm_rect_equals(&new_plane_state->uapi.dst, 1688 &old_plane_state->uapi.dst)) { 1689 if (old_plane_state->uapi.visible) { 1690 damaged_area.y1 = old_plane_state->uapi.dst.y1; 1691 damaged_area.y2 = old_plane_state->uapi.dst.y2; 1692 clip_area_update(&pipe_clip, &damaged_area); 1693 } 1694 1695 if (new_plane_state->uapi.visible) { 1696 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1697 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1698 clip_area_update(&pipe_clip, &damaged_area); 1699 } 1700 continue; 1701 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { 1702 /* If alpha changed mark the whole plane area as damaged */ 1703 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1704 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1705 clip_area_update(&pipe_clip, &damaged_area); 1706 continue; 1707 } 1708 1709 drm_rect_fp_to_int(&src, &new_plane_state->uapi.src); 1710 1711 drm_atomic_helper_damage_iter_init(&iter, 1712 &old_plane_state->uapi, 1713 &new_plane_state->uapi); 1714 drm_atomic_for_each_plane_damage(&iter, &clip) { 1715 if (drm_rect_intersect(&clip, &src)) 1716 clip_area_update(&damaged_area, &clip); 1717 } 1718 1719 if (damaged_area.y1 == -1) 1720 continue; 1721 1722 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; 1723 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; 1724 clip_area_update(&pipe_clip, &damaged_area); 1725 } 1726 1727 if (full_update) 1728 goto skip_sel_fetch_set_loop; 1729 1730 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 1731 if (ret) 1732 return ret; 1733 1734 intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip); 1735 1736 /* 1737 * Now that we have the pipe damaged area check if it intersect with 1738 * every plane, if it does set the plane selective fetch area. 1739 */ 1740 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1741 new_plane_state, i) { 1742 struct drm_rect *sel_fetch_area, inter; 1743 struct intel_plane *linked = new_plane_state->planar_linked_plane; 1744 1745 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || 1746 !new_plane_state->uapi.visible) 1747 continue; 1748 1749 inter = pipe_clip; 1750 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) 1751 continue; 1752 1753 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 1754 full_update = true; 1755 break; 1756 } 1757 1758 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 1759 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; 1760 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; 1761 crtc_state->update_planes |= BIT(plane->id); 1762 1763 /* 1764 * Sel_fetch_area is calculated for UV plane. Use 1765 * same area for Y plane as well. 1766 */ 1767 if (linked) { 1768 struct intel_plane_state *linked_new_plane_state; 1769 struct drm_rect *linked_sel_fetch_area; 1770 1771 linked_new_plane_state = intel_atomic_get_plane_state(state, linked); 1772 if (IS_ERR(linked_new_plane_state)) 1773 return PTR_ERR(linked_new_plane_state); 1774 1775 linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area; 1776 linked_sel_fetch_area->y1 = sel_fetch_area->y1; 1777 linked_sel_fetch_area->y2 = sel_fetch_area->y2; 1778 crtc_state->update_planes |= BIT(linked->id); 1779 } 1780 } 1781 1782 skip_sel_fetch_set_loop: 1783 psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update); 1784 return 0; 1785 } 1786 1787 void intel_psr_pre_plane_update(struct intel_atomic_state *state, 1788 struct intel_crtc *crtc) 1789 { 1790 struct drm_i915_private *i915 = to_i915(state->base.dev); 1791 const struct intel_crtc_state *crtc_state = 1792 intel_atomic_get_new_crtc_state(state, crtc); 1793 struct intel_encoder *encoder; 1794 1795 if (!HAS_PSR(i915)) 1796 return; 1797 1798 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 1799 crtc_state->uapi.encoder_mask) { 1800 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1801 struct intel_psr *psr = &intel_dp->psr; 1802 bool needs_to_disable = false; 1803 1804 mutex_lock(&psr->lock); 1805 1806 /* 1807 * Reasons to disable: 1808 * - PSR disabled in new state 1809 * - All planes will go inactive 1810 * - Changing between PSR versions 1811 */ 1812 needs_to_disable |= intel_crtc_needs_modeset(crtc_state); 1813 needs_to_disable |= !crtc_state->has_psr; 1814 needs_to_disable |= !crtc_state->active_planes; 1815 needs_to_disable |= crtc_state->has_psr2 != psr->psr2_enabled; 1816 1817 if (psr->enabled && needs_to_disable) 1818 intel_psr_disable_locked(intel_dp); 1819 1820 mutex_unlock(&psr->lock); 1821 } 1822 } 1823 1824 static void _intel_psr_post_plane_update(const struct intel_atomic_state *state, 1825 const struct intel_crtc_state *crtc_state) 1826 { 1827 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1828 struct intel_encoder *encoder; 1829 1830 if (!crtc_state->has_psr) 1831 return; 1832 1833 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 1834 crtc_state->uapi.encoder_mask) { 1835 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1836 struct intel_psr *psr = &intel_dp->psr; 1837 1838 mutex_lock(&psr->lock); 1839 1840 if (psr->sink_not_reliable) 1841 goto exit; 1842 1843 drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes); 1844 1845 /* Only enable if there is active planes */ 1846 if (!psr->enabled && crtc_state->active_planes) 1847 intel_psr_enable_locked(intel_dp, crtc_state); 1848 1849 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 1850 if (crtc_state->crc_enabled && psr->enabled) 1851 psr_force_hw_tracking_exit(intel_dp); 1852 1853 exit: 1854 mutex_unlock(&psr->lock); 1855 } 1856 } 1857 1858 void intel_psr_post_plane_update(const struct intel_atomic_state *state) 1859 { 1860 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1861 struct intel_crtc_state *crtc_state; 1862 struct intel_crtc *crtc; 1863 int i; 1864 1865 if (!HAS_PSR(dev_priv)) 1866 return; 1867 1868 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) 1869 _intel_psr_post_plane_update(state, crtc_state); 1870 } 1871 1872 static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp) 1873 { 1874 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1875 1876 /* 1877 * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough. 1878 * As all higher states has bit 4 of PSR2 state set we can just wait for 1879 * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared. 1880 */ 1881 return intel_de_wait_for_clear(dev_priv, 1882 EDP_PSR2_STATUS(intel_dp->psr.transcoder), 1883 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50); 1884 } 1885 1886 static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp) 1887 { 1888 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1889 1890 /* 1891 * From bspec: Panel Self Refresh (BDW+) 1892 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 1893 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 1894 * defensive enough to cover everything. 1895 */ 1896 return intel_de_wait_for_clear(dev_priv, 1897 EDP_PSR_STATUS(intel_dp->psr.transcoder), 1898 EDP_PSR_STATUS_STATE_MASK, 50); 1899 } 1900 1901 /** 1902 * intel_psr_wait_for_idle - wait for PSR be ready for a pipe update 1903 * @new_crtc_state: new CRTC state 1904 * 1905 * This function is expected to be called from pipe_update_start() where it is 1906 * not expected to race with PSR enable or disable. 1907 */ 1908 void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state) 1909 { 1910 struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev); 1911 struct intel_encoder *encoder; 1912 1913 if (!new_crtc_state->has_psr) 1914 return; 1915 1916 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, 1917 new_crtc_state->uapi.encoder_mask) { 1918 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1919 int ret; 1920 1921 mutex_lock(&intel_dp->psr.lock); 1922 1923 if (!intel_dp->psr.enabled) { 1924 mutex_unlock(&intel_dp->psr.lock); 1925 continue; 1926 } 1927 1928 if (intel_dp->psr.psr2_enabled) 1929 ret = _psr2_ready_for_pipe_update_locked(intel_dp); 1930 else 1931 ret = _psr1_ready_for_pipe_update_locked(intel_dp); 1932 1933 if (ret) 1934 drm_err(&dev_priv->drm, "PSR wait timed out, atomic update may fail\n"); 1935 1936 mutex_unlock(&intel_dp->psr.lock); 1937 } 1938 } 1939 1940 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) 1941 { 1942 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1943 i915_reg_t reg; 1944 u32 mask; 1945 int err; 1946 1947 if (!intel_dp->psr.enabled) 1948 return false; 1949 1950 if (intel_dp->psr.psr2_enabled) { 1951 reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 1952 mask = EDP_PSR2_STATUS_STATE_MASK; 1953 } else { 1954 reg = EDP_PSR_STATUS(intel_dp->psr.transcoder); 1955 mask = EDP_PSR_STATUS_STATE_MASK; 1956 } 1957 1958 mutex_unlock(&intel_dp->psr.lock); 1959 1960 err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); 1961 if (err) 1962 drm_err(&dev_priv->drm, 1963 "Timed out waiting for PSR Idle for re-enable\n"); 1964 1965 /* After the unlocked wait, verify that PSR is still wanted! */ 1966 mutex_lock(&intel_dp->psr.lock); 1967 return err == 0 && intel_dp->psr.enabled; 1968 } 1969 1970 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) 1971 { 1972 struct drm_connector_list_iter conn_iter; 1973 struct drm_device *dev = &dev_priv->drm; 1974 struct drm_modeset_acquire_ctx ctx; 1975 struct drm_atomic_state *state; 1976 struct drm_connector *conn; 1977 int err = 0; 1978 1979 state = drm_atomic_state_alloc(dev); 1980 if (!state) 1981 return -ENOMEM; 1982 1983 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1984 state->acquire_ctx = &ctx; 1985 1986 retry: 1987 1988 drm_connector_list_iter_begin(dev, &conn_iter); 1989 drm_for_each_connector_iter(conn, &conn_iter) { 1990 struct drm_connector_state *conn_state; 1991 struct drm_crtc_state *crtc_state; 1992 1993 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) 1994 continue; 1995 1996 conn_state = drm_atomic_get_connector_state(state, conn); 1997 if (IS_ERR(conn_state)) { 1998 err = PTR_ERR(conn_state); 1999 break; 2000 } 2001 2002 if (!conn_state->crtc) 2003 continue; 2004 2005 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); 2006 if (IS_ERR(crtc_state)) { 2007 err = PTR_ERR(crtc_state); 2008 break; 2009 } 2010 2011 /* Mark mode as changed to trigger a pipe->update() */ 2012 crtc_state->mode_changed = true; 2013 } 2014 drm_connector_list_iter_end(&conn_iter); 2015 2016 if (err == 0) 2017 err = drm_atomic_commit(state); 2018 2019 if (err == -EDEADLK) { 2020 drm_atomic_state_clear(state); 2021 err = drm_modeset_backoff(&ctx); 2022 if (!err) 2023 goto retry; 2024 } 2025 2026 drm_modeset_drop_locks(&ctx); 2027 drm_modeset_acquire_fini(&ctx); 2028 drm_atomic_state_put(state); 2029 2030 return err; 2031 } 2032 2033 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) 2034 { 2035 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2036 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 2037 u32 old_mode; 2038 int ret; 2039 2040 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || 2041 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 2042 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); 2043 return -EINVAL; 2044 } 2045 2046 ret = mutex_lock_interruptible(&intel_dp->psr.lock); 2047 if (ret) 2048 return ret; 2049 2050 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; 2051 intel_dp->psr.debug = val; 2052 2053 /* 2054 * Do it right away if it's already enabled, otherwise it will be done 2055 * when enabling the source. 2056 */ 2057 if (intel_dp->psr.enabled) 2058 psr_irq_control(intel_dp); 2059 2060 mutex_unlock(&intel_dp->psr.lock); 2061 2062 if (old_mode != mode) 2063 ret = intel_psr_fastset_force(dev_priv); 2064 2065 return ret; 2066 } 2067 2068 static void intel_psr_handle_irq(struct intel_dp *intel_dp) 2069 { 2070 struct intel_psr *psr = &intel_dp->psr; 2071 2072 intel_psr_disable_locked(intel_dp); 2073 psr->sink_not_reliable = true; 2074 /* let's make sure that sink is awaken */ 2075 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 2076 } 2077 2078 static void intel_psr_work(struct work_struct *work) 2079 { 2080 struct intel_dp *intel_dp = 2081 container_of(work, typeof(*intel_dp), psr.work); 2082 2083 mutex_lock(&intel_dp->psr.lock); 2084 2085 if (!intel_dp->psr.enabled) 2086 goto unlock; 2087 2088 if (READ_ONCE(intel_dp->psr.irq_aux_error)) 2089 intel_psr_handle_irq(intel_dp); 2090 2091 /* 2092 * We have to make sure PSR is ready for re-enable 2093 * otherwise it keeps disabled until next full enable/disable cycle. 2094 * PSR might take some time to get fully disabled 2095 * and be ready for re-enable. 2096 */ 2097 if (!__psr_wait_for_idle_locked(intel_dp)) 2098 goto unlock; 2099 2100 /* 2101 * The delayed work can race with an invalidate hence we need to 2102 * recheck. Since psr_flush first clears this and then reschedules we 2103 * won't ever miss a flush when bailing out here. 2104 */ 2105 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) 2106 goto unlock; 2107 2108 intel_psr_activate(intel_dp); 2109 unlock: 2110 mutex_unlock(&intel_dp->psr.lock); 2111 } 2112 2113 /** 2114 * intel_psr_invalidate - Invalidade PSR 2115 * @dev_priv: i915 device 2116 * @frontbuffer_bits: frontbuffer plane tracking bits 2117 * @origin: which operation caused the invalidate 2118 * 2119 * Since the hardware frontbuffer tracking has gaps we need to integrate 2120 * with the software frontbuffer tracking. This function gets called every 2121 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 2122 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 2123 * 2124 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 2125 */ 2126 void intel_psr_invalidate(struct drm_i915_private *dev_priv, 2127 unsigned frontbuffer_bits, enum fb_op_origin origin) 2128 { 2129 struct intel_encoder *encoder; 2130 2131 if (origin == ORIGIN_FLIP) 2132 return; 2133 2134 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2135 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 2136 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2137 2138 mutex_lock(&intel_dp->psr.lock); 2139 if (!intel_dp->psr.enabled) { 2140 mutex_unlock(&intel_dp->psr.lock); 2141 continue; 2142 } 2143 2144 pipe_frontbuffer_bits &= 2145 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 2146 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; 2147 2148 if (pipe_frontbuffer_bits) 2149 intel_psr_exit(intel_dp); 2150 2151 mutex_unlock(&intel_dp->psr.lock); 2152 } 2153 } 2154 /* 2155 * When we will be completely rely on PSR2 S/W tracking in future, 2156 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP 2157 * event also therefore tgl_dc3co_flush_locked() require to be changed 2158 * accordingly in future. 2159 */ 2160 static void 2161 tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits, 2162 enum fb_op_origin origin) 2163 { 2164 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled || 2165 !intel_dp->psr.active) 2166 return; 2167 2168 /* 2169 * At every frontbuffer flush flip event modified delay of delayed work, 2170 * when delayed work schedules that means display has been idle. 2171 */ 2172 if (!(frontbuffer_bits & 2173 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) 2174 return; 2175 2176 tgl_psr2_enable_dc3co(intel_dp); 2177 mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work, 2178 intel_dp->psr.dc3co_exit_delay); 2179 } 2180 2181 /** 2182 * intel_psr_flush - Flush PSR 2183 * @dev_priv: i915 device 2184 * @frontbuffer_bits: frontbuffer plane tracking bits 2185 * @origin: which operation caused the flush 2186 * 2187 * Since the hardware frontbuffer tracking has gaps we need to integrate 2188 * with the software frontbuffer tracking. This function gets called every 2189 * time frontbuffer rendering has completed and flushed out to memory. PSR 2190 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 2191 * 2192 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 2193 */ 2194 void intel_psr_flush(struct drm_i915_private *dev_priv, 2195 unsigned frontbuffer_bits, enum fb_op_origin origin) 2196 { 2197 struct intel_encoder *encoder; 2198 2199 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2200 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 2201 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2202 2203 mutex_lock(&intel_dp->psr.lock); 2204 if (!intel_dp->psr.enabled) { 2205 mutex_unlock(&intel_dp->psr.lock); 2206 continue; 2207 } 2208 2209 pipe_frontbuffer_bits &= 2210 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 2211 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; 2212 2213 /* 2214 * If the PSR is paused by an explicit intel_psr_paused() call, 2215 * we have to ensure that the PSR is not activated until 2216 * intel_psr_resume() is called. 2217 */ 2218 if (intel_dp->psr.paused) { 2219 mutex_unlock(&intel_dp->psr.lock); 2220 continue; 2221 } 2222 2223 if (origin == ORIGIN_FLIP || 2224 (origin == ORIGIN_CURSOR_UPDATE && 2225 !intel_dp->psr.psr2_sel_fetch_enabled)) { 2226 tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin); 2227 mutex_unlock(&intel_dp->psr.lock); 2228 continue; 2229 } 2230 2231 /* By definition flush = invalidate + flush */ 2232 if (pipe_frontbuffer_bits) 2233 psr_force_hw_tracking_exit(intel_dp); 2234 2235 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) 2236 schedule_work(&intel_dp->psr.work); 2237 mutex_unlock(&intel_dp->psr.lock); 2238 } 2239 } 2240 2241 /** 2242 * intel_psr_init - Init basic PSR work and mutex. 2243 * @intel_dp: Intel DP 2244 * 2245 * This function is called after the initializing connector. 2246 * (the initializing of connector treats the handling of connector capabilities) 2247 * And it initializes basic PSR stuff for each DP Encoder. 2248 */ 2249 void intel_psr_init(struct intel_dp *intel_dp) 2250 { 2251 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2252 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2253 2254 if (!HAS_PSR(dev_priv)) 2255 return; 2256 2257 /* 2258 * HSW spec explicitly says PSR is tied to port A. 2259 * BDW+ platforms have a instance of PSR registers per transcoder but 2260 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder 2261 * than eDP one. 2262 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11. 2263 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11. 2264 * But GEN12 supports a instance of PSR registers per transcoder. 2265 */ 2266 if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) { 2267 drm_dbg_kms(&dev_priv->drm, 2268 "PSR condition failed: Port not supported\n"); 2269 return; 2270 } 2271 2272 intel_dp->psr.source_support = true; 2273 2274 if (dev_priv->params.enable_psr == -1) 2275 if (!dev_priv->vbt.psr.enable) 2276 dev_priv->params.enable_psr = 0; 2277 2278 /* Set link_standby x link_off defaults */ 2279 if (DISPLAY_VER(dev_priv) < 12) 2280 /* For new platforms up to TGL let's respect VBT back again */ 2281 intel_dp->psr.link_standby = dev_priv->vbt.psr.full_link; 2282 2283 INIT_WORK(&intel_dp->psr.work, intel_psr_work); 2284 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); 2285 mutex_init(&intel_dp->psr.lock); 2286 } 2287 2288 static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 2289 u8 *status, u8 *error_status) 2290 { 2291 struct drm_dp_aux *aux = &intel_dp->aux; 2292 int ret; 2293 2294 ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status); 2295 if (ret != 1) 2296 return ret; 2297 2298 ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status); 2299 if (ret != 1) 2300 return ret; 2301 2302 *status = *status & DP_PSR_SINK_STATE_MASK; 2303 2304 return 0; 2305 } 2306 2307 static void psr_alpm_check(struct intel_dp *intel_dp) 2308 { 2309 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2310 struct drm_dp_aux *aux = &intel_dp->aux; 2311 struct intel_psr *psr = &intel_dp->psr; 2312 u8 val; 2313 int r; 2314 2315 if (!psr->psr2_enabled) 2316 return; 2317 2318 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); 2319 if (r != 1) { 2320 drm_err(&dev_priv->drm, "Error reading ALPM status\n"); 2321 return; 2322 } 2323 2324 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) { 2325 intel_psr_disable_locked(intel_dp); 2326 psr->sink_not_reliable = true; 2327 drm_dbg_kms(&dev_priv->drm, 2328 "ALPM lock timeout error, disabling PSR\n"); 2329 2330 /* Clearing error */ 2331 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); 2332 } 2333 } 2334 2335 static void psr_capability_changed_check(struct intel_dp *intel_dp) 2336 { 2337 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2338 struct intel_psr *psr = &intel_dp->psr; 2339 u8 val; 2340 int r; 2341 2342 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 2343 if (r != 1) { 2344 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n"); 2345 return; 2346 } 2347 2348 if (val & DP_PSR_CAPS_CHANGE) { 2349 intel_psr_disable_locked(intel_dp); 2350 psr->sink_not_reliable = true; 2351 drm_dbg_kms(&dev_priv->drm, 2352 "Sink PSR capability changed, disabling PSR\n"); 2353 2354 /* Clearing it */ 2355 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 2356 } 2357 } 2358 2359 void intel_psr_short_pulse(struct intel_dp *intel_dp) 2360 { 2361 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2362 struct intel_psr *psr = &intel_dp->psr; 2363 u8 status, error_status; 2364 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 2365 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 2366 DP_PSR_LINK_CRC_ERROR; 2367 2368 if (!CAN_PSR(intel_dp)) 2369 return; 2370 2371 mutex_lock(&psr->lock); 2372 2373 if (!psr->enabled) 2374 goto exit; 2375 2376 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 2377 drm_err(&dev_priv->drm, 2378 "Error reading PSR status or error status\n"); 2379 goto exit; 2380 } 2381 2382 if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) { 2383 intel_psr_disable_locked(intel_dp); 2384 psr->sink_not_reliable = true; 2385 } 2386 2387 if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status) 2388 drm_dbg_kms(&dev_priv->drm, 2389 "PSR sink internal error, disabling PSR\n"); 2390 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 2391 drm_dbg_kms(&dev_priv->drm, 2392 "PSR RFB storage error, disabling PSR\n"); 2393 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 2394 drm_dbg_kms(&dev_priv->drm, 2395 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 2396 if (error_status & DP_PSR_LINK_CRC_ERROR) 2397 drm_dbg_kms(&dev_priv->drm, 2398 "PSR Link CRC error, disabling PSR\n"); 2399 2400 if (error_status & ~errors) 2401 drm_err(&dev_priv->drm, 2402 "PSR_ERROR_STATUS unhandled errors %x\n", 2403 error_status & ~errors); 2404 /* clear status register */ 2405 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 2406 2407 psr_alpm_check(intel_dp); 2408 psr_capability_changed_check(intel_dp); 2409 2410 exit: 2411 mutex_unlock(&psr->lock); 2412 } 2413 2414 bool intel_psr_enabled(struct intel_dp *intel_dp) 2415 { 2416 bool ret; 2417 2418 if (!CAN_PSR(intel_dp)) 2419 return false; 2420 2421 mutex_lock(&intel_dp->psr.lock); 2422 ret = intel_dp->psr.enabled; 2423 mutex_unlock(&intel_dp->psr.lock); 2424 2425 return ret; 2426 } 2427