1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_damage_helper.h> 26 27 #include "display/intel_dp.h" 28 29 #include "i915_drv.h" 30 #include "i915_reg.h" 31 #include "intel_atomic.h" 32 #include "intel_crtc.h" 33 #include "intel_de.h" 34 #include "intel_display_types.h" 35 #include "intel_dp_aux.h" 36 #include "intel_hdmi.h" 37 #include "intel_psr.h" 38 #include "intel_snps_phy.h" 39 #include "skl_universal_plane.h" 40 41 /** 42 * DOC: Panel Self Refresh (PSR/SRD) 43 * 44 * Since Haswell Display controller supports Panel Self-Refresh on display 45 * panels witch have a remote frame buffer (RFB) implemented according to PSR 46 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 47 * when system is idle but display is on as it eliminates display refresh 48 * request to DDR memory completely as long as the frame buffer for that 49 * display is unchanged. 50 * 51 * Panel Self Refresh must be supported by both Hardware (source) and 52 * Panel (sink). 53 * 54 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 55 * to power down the link and memory controller. For DSI panels the same idea 56 * is called "manual mode". 57 * 58 * The implementation uses the hardware-based PSR support which automatically 59 * enters/exits self-refresh mode. The hardware takes care of sending the 60 * required DP aux message and could even retrain the link (that part isn't 61 * enabled yet though). The hardware also keeps track of any frontbuffer 62 * changes to know when to exit self-refresh mode again. Unfortunately that 63 * part doesn't work too well, hence why the i915 PSR support uses the 64 * software frontbuffer tracking to make sure it doesn't miss a screen 65 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 66 * get called by the frontbuffer tracking code. Note that because of locking 67 * issues the self-refresh re-enable code is done from a work queue, which 68 * must be correctly synchronized/cancelled when shutting down the pipe." 69 * 70 * DC3CO (DC3 clock off) 71 * 72 * On top of PSR2, GEN12 adds a intermediate power savings state that turns 73 * clock off automatically during PSR2 idle state. 74 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep 75 * entry/exit allows the HW to enter a low-power state even when page flipping 76 * periodically (for instance a 30fps video playback scenario). 77 * 78 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), 79 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 80 * frames, if no other flip occurs and the function above is executed, DC3CO is 81 * disabled and PSR2 is configured to enter deep sleep, resetting again in case 82 * of another flip. 83 * Front buffer modifications do not trigger DC3CO activation on purpose as it 84 * would bring a lot of complexity and most of the moderns systems will only 85 * use page flips. 86 */ 87 88 static bool psr_global_enabled(struct intel_dp *intel_dp) 89 { 90 struct intel_connector *connector = intel_dp->attached_connector; 91 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 92 93 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 94 case I915_PSR_DEBUG_DEFAULT: 95 if (i915->params.enable_psr == -1) 96 return connector->panel.vbt.psr.enable; 97 return i915->params.enable_psr; 98 case I915_PSR_DEBUG_DISABLE: 99 return false; 100 default: 101 return true; 102 } 103 } 104 105 static bool psr2_global_enabled(struct intel_dp *intel_dp) 106 { 107 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 108 109 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 110 case I915_PSR_DEBUG_DISABLE: 111 case I915_PSR_DEBUG_FORCE_PSR1: 112 return false; 113 default: 114 if (i915->params.enable_psr == 1) 115 return false; 116 return true; 117 } 118 } 119 120 static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp) 121 { 122 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 123 124 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_ERROR : 125 EDP_PSR_ERROR(intel_dp->psr.transcoder); 126 } 127 128 static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp) 129 { 130 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 131 132 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_POST_EXIT : 133 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder); 134 } 135 136 static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp) 137 { 138 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 139 140 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_PRE_ENTRY : 141 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder); 142 } 143 144 static u32 psr_irq_mask_get(struct intel_dp *intel_dp) 145 { 146 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 147 148 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_MASK : 149 EDP_PSR_MASK(intel_dp->psr.transcoder); 150 } 151 152 static void psr_irq_control(struct intel_dp *intel_dp) 153 { 154 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 155 i915_reg_t imr_reg; 156 u32 mask, val; 157 158 if (DISPLAY_VER(dev_priv) >= 12) 159 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 160 else 161 imr_reg = EDP_PSR_IMR; 162 163 mask = psr_irq_psr_error_bit_get(intel_dp); 164 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) 165 mask |= psr_irq_post_exit_bit_get(intel_dp) | 166 psr_irq_pre_entry_bit_get(intel_dp); 167 168 val = intel_de_read(dev_priv, imr_reg); 169 val &= ~psr_irq_mask_get(intel_dp); 170 val |= ~mask; 171 intel_de_write(dev_priv, imr_reg, val); 172 } 173 174 static void psr_event_print(struct drm_i915_private *i915, 175 u32 val, bool psr2_enabled) 176 { 177 drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val); 178 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 179 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n"); 180 if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) 181 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n"); 182 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 183 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n"); 184 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 185 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n"); 186 if (val & PSR_EVENT_GRAPHICS_RESET) 187 drm_dbg_kms(&i915->drm, "\tGraphics reset\n"); 188 if (val & PSR_EVENT_PCH_INTERRUPT) 189 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n"); 190 if (val & PSR_EVENT_MEMORY_UP) 191 drm_dbg_kms(&i915->drm, "\tMemory up\n"); 192 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 193 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n"); 194 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 195 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n"); 196 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 197 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n"); 198 if (val & PSR_EVENT_REGISTER_UPDATE) 199 drm_dbg_kms(&i915->drm, "\tRegister updated\n"); 200 if (val & PSR_EVENT_HDCP_ENABLE) 201 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n"); 202 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 203 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n"); 204 if (val & PSR_EVENT_VBI_ENABLE) 205 drm_dbg_kms(&i915->drm, "\tVBI enabled\n"); 206 if (val & PSR_EVENT_LPSP_MODE_EXIT) 207 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n"); 208 if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) 209 drm_dbg_kms(&i915->drm, "\tPSR disabled\n"); 210 } 211 212 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) 213 { 214 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 215 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 216 ktime_t time_ns = ktime_get(); 217 i915_reg_t imr_reg; 218 219 if (DISPLAY_VER(dev_priv) >= 12) 220 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 221 else 222 imr_reg = EDP_PSR_IMR; 223 224 if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) { 225 intel_dp->psr.last_entry_attempt = time_ns; 226 drm_dbg_kms(&dev_priv->drm, 227 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 228 transcoder_name(cpu_transcoder)); 229 } 230 231 if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) { 232 intel_dp->psr.last_exit = time_ns; 233 drm_dbg_kms(&dev_priv->drm, 234 "[transcoder %s] PSR exit completed\n", 235 transcoder_name(cpu_transcoder)); 236 237 if (DISPLAY_VER(dev_priv) >= 9) { 238 u32 val = intel_de_read(dev_priv, 239 PSR_EVENT(cpu_transcoder)); 240 bool psr2_enabled = intel_dp->psr.psr2_enabled; 241 242 intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder), 243 val); 244 psr_event_print(dev_priv, val, psr2_enabled); 245 } 246 } 247 248 if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) { 249 u32 val; 250 251 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", 252 transcoder_name(cpu_transcoder)); 253 254 intel_dp->psr.irq_aux_error = true; 255 256 /* 257 * If this interruption is not masked it will keep 258 * interrupting so fast that it prevents the scheduled 259 * work to run. 260 * Also after a PSR error, we don't want to arm PSR 261 * again so we don't care about unmask the interruption 262 * or unset irq_aux_error. 263 */ 264 val = intel_de_read(dev_priv, imr_reg); 265 val |= psr_irq_psr_error_bit_get(intel_dp); 266 intel_de_write(dev_priv, imr_reg, val); 267 268 schedule_work(&intel_dp->psr.work); 269 } 270 } 271 272 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) 273 { 274 u8 alpm_caps = 0; 275 276 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, 277 &alpm_caps) != 1) 278 return false; 279 return alpm_caps & DP_ALPM_CAP; 280 } 281 282 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 283 { 284 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 285 u8 val = 8; /* assume the worst if we can't read the value */ 286 287 if (drm_dp_dpcd_readb(&intel_dp->aux, 288 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 289 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 290 else 291 drm_dbg_kms(&i915->drm, 292 "Unable to get sink synchronization latency, assuming 8 frames\n"); 293 return val; 294 } 295 296 static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) 297 { 298 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 299 ssize_t r; 300 u16 w; 301 u8 y; 302 303 /* If sink don't have specific granularity requirements set legacy ones */ 304 if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { 305 /* As PSR2 HW sends full lines, we do not care about x granularity */ 306 w = 4; 307 y = 4; 308 goto exit; 309 } 310 311 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2); 312 if (r != 2) 313 drm_dbg_kms(&i915->drm, 314 "Unable to read DP_PSR2_SU_X_GRANULARITY\n"); 315 /* 316 * Spec says that if the value read is 0 the default granularity should 317 * be used instead. 318 */ 319 if (r != 2 || w == 0) 320 w = 4; 321 322 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); 323 if (r != 1) { 324 drm_dbg_kms(&i915->drm, 325 "Unable to read DP_PSR2_SU_Y_GRANULARITY\n"); 326 y = 4; 327 } 328 if (y == 0) 329 y = 1; 330 331 exit: 332 intel_dp->psr.su_w_granularity = w; 333 intel_dp->psr.su_y_granularity = y; 334 } 335 336 void intel_psr_init_dpcd(struct intel_dp *intel_dp) 337 { 338 struct drm_i915_private *dev_priv = 339 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 340 341 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, 342 sizeof(intel_dp->psr_dpcd)); 343 344 if (!intel_dp->psr_dpcd[0]) 345 return; 346 drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n", 347 intel_dp->psr_dpcd[0]); 348 349 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { 350 drm_dbg_kms(&dev_priv->drm, 351 "PSR support not currently available for this panel\n"); 352 return; 353 } 354 355 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 356 drm_dbg_kms(&dev_priv->drm, 357 "Panel lacks power state control, PSR cannot be enabled\n"); 358 return; 359 } 360 361 intel_dp->psr.sink_support = true; 362 intel_dp->psr.sink_sync_latency = 363 intel_dp_get_sink_sync_latency(intel_dp); 364 365 if (DISPLAY_VER(dev_priv) >= 9 && 366 (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { 367 bool y_req = intel_dp->psr_dpcd[1] & 368 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 369 bool alpm = intel_dp_get_alpm_status(intel_dp); 370 371 /* 372 * All panels that supports PSR version 03h (PSR2 + 373 * Y-coordinate) can handle Y-coordinates in VSC but we are 374 * only sure that it is going to be used when required by the 375 * panel. This way panel is capable to do selective update 376 * without a aux frame sync. 377 * 378 * To support PSR version 02h and PSR version 03h without 379 * Y-coordinate requirement panels we would need to enable 380 * GTC first. 381 */ 382 intel_dp->psr.sink_psr2_support = y_req && alpm; 383 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n", 384 intel_dp->psr.sink_psr2_support ? "" : "not "); 385 386 if (intel_dp->psr.sink_psr2_support) { 387 intel_dp->psr.colorimetry_support = 388 intel_dp_get_colorimetry_status(intel_dp); 389 intel_dp_get_su_granularity(intel_dp); 390 } 391 } 392 } 393 394 static void intel_psr_enable_sink(struct intel_dp *intel_dp) 395 { 396 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 397 u8 dpcd_val = DP_PSR_ENABLE; 398 399 /* Enable ALPM at sink for psr2 */ 400 if (intel_dp->psr.psr2_enabled) { 401 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 402 DP_ALPM_ENABLE | 403 DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); 404 405 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 406 } else { 407 if (intel_dp->psr.link_standby) 408 dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; 409 410 if (DISPLAY_VER(dev_priv) >= 8) 411 dpcd_val |= DP_PSR_CRC_VERIFICATION; 412 } 413 414 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 415 dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; 416 417 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); 418 419 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 420 } 421 422 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 423 { 424 struct intel_connector *connector = intel_dp->attached_connector; 425 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 426 u32 val = 0; 427 428 if (DISPLAY_VER(dev_priv) >= 11) 429 val |= EDP_PSR_TP4_TIME_0US; 430 431 if (dev_priv->params.psr_safest_params) { 432 val |= EDP_PSR_TP1_TIME_2500us; 433 val |= EDP_PSR_TP2_TP3_TIME_2500us; 434 goto check_tp3_sel; 435 } 436 437 if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0) 438 val |= EDP_PSR_TP1_TIME_0us; 439 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100) 440 val |= EDP_PSR_TP1_TIME_100us; 441 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500) 442 val |= EDP_PSR_TP1_TIME_500us; 443 else 444 val |= EDP_PSR_TP1_TIME_2500us; 445 446 if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) 447 val |= EDP_PSR_TP2_TP3_TIME_0us; 448 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100) 449 val |= EDP_PSR_TP2_TP3_TIME_100us; 450 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500) 451 val |= EDP_PSR_TP2_TP3_TIME_500us; 452 else 453 val |= EDP_PSR_TP2_TP3_TIME_2500us; 454 455 check_tp3_sel: 456 if (intel_dp_source_supports_tps3(dev_priv) && 457 drm_dp_tps3_supported(intel_dp->dpcd)) 458 val |= EDP_PSR_TP1_TP3_SEL; 459 else 460 val |= EDP_PSR_TP1_TP2_SEL; 461 462 return val; 463 } 464 465 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 466 { 467 struct intel_connector *connector = intel_dp->attached_connector; 468 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 469 int idle_frames; 470 471 /* Let's use 6 as the minimum to cover all known cases including the 472 * off-by-one issue that HW has in some cases. 473 */ 474 idle_frames = max(6, connector->panel.vbt.psr.idle_frames); 475 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1); 476 477 if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf)) 478 idle_frames = 0xf; 479 480 return idle_frames; 481 } 482 483 static void hsw_activate_psr1(struct intel_dp *intel_dp) 484 { 485 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 486 u32 max_sleep_time = 0x1f; 487 u32 val = EDP_PSR_ENABLE; 488 489 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT; 490 491 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; 492 if (IS_HASWELL(dev_priv)) 493 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 494 495 if (intel_dp->psr.link_standby) 496 val |= EDP_PSR_LINK_STANDBY; 497 498 val |= intel_psr1_get_tp_time(intel_dp); 499 500 if (DISPLAY_VER(dev_priv) >= 8) 501 val |= EDP_PSR_CRC_ENABLE; 502 503 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) & 504 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK); 505 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val); 506 } 507 508 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 509 { 510 struct intel_connector *connector = intel_dp->attached_connector; 511 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 512 u32 val = 0; 513 514 if (dev_priv->params.psr_safest_params) 515 return EDP_PSR2_TP2_TIME_2500us; 516 517 if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 518 connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 519 val |= EDP_PSR2_TP2_TIME_50us; 520 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 521 val |= EDP_PSR2_TP2_TIME_100us; 522 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 523 val |= EDP_PSR2_TP2_TIME_500us; 524 else 525 val |= EDP_PSR2_TP2_TIME_2500us; 526 527 return val; 528 } 529 530 static void hsw_activate_psr2(struct intel_dp *intel_dp) 531 { 532 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 533 u32 val = EDP_PSR2_ENABLE; 534 535 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT; 536 537 if (DISPLAY_VER(dev_priv) <= 13 && !IS_ALDERLAKE_P(dev_priv)) 538 val |= EDP_SU_TRACK_ENABLE; 539 540 if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12) 541 val |= EDP_Y_COORDINATE_ENABLE; 542 543 val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2)); 544 val |= intel_psr2_get_tp_time(intel_dp); 545 546 /* Wa_22012278275:adl-p */ 547 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { 548 static const u8 map[] = { 549 2, /* 5 lines */ 550 1, /* 6 lines */ 551 0, /* 7 lines */ 552 3, /* 8 lines */ 553 6, /* 9 lines */ 554 5, /* 10 lines */ 555 4, /* 11 lines */ 556 7, /* 12 lines */ 557 }; 558 /* 559 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see 560 * comments bellow for more information 561 */ 562 u32 tmp, lines = 7; 563 564 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 565 566 tmp = map[lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; 567 tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT; 568 val |= tmp; 569 570 tmp = map[lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; 571 tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT; 572 val |= tmp; 573 } else if (DISPLAY_VER(dev_priv) >= 12) { 574 /* 575 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default 576 * values from BSpec. In order to setting an optimal power 577 * consumption, lower than 4k resolution mode needs to decrease 578 * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution 579 * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE. 580 */ 581 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 582 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7); 583 val |= TGL_EDP_PSR2_FAST_WAKE(7); 584 } else if (DISPLAY_VER(dev_priv) >= 9) { 585 val |= EDP_PSR2_IO_BUFFER_WAKE(7); 586 val |= EDP_PSR2_FAST_WAKE(7); 587 } 588 589 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 590 val |= EDP_PSR2_SU_SDP_SCANLINE; 591 592 if (intel_dp->psr.psr2_sel_fetch_enabled) { 593 u32 tmp; 594 595 /* Wa_1408330847 */ 596 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 597 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 598 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 599 DIS_RAM_BYPASS_PSR2_MAN_TRACK); 600 601 tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); 602 drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); 603 } else if (HAS_PSR2_SEL_FETCH(dev_priv)) { 604 intel_de_write(dev_priv, 605 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0); 606 } 607 608 /* 609 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 610 * recommending keep this bit unset while PSR2 is enabled. 611 */ 612 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0); 613 614 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 615 } 616 617 static bool 618 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) 619 { 620 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 621 return trans == TRANSCODER_A || trans == TRANSCODER_B; 622 else if (DISPLAY_VER(dev_priv) >= 12) 623 return trans == TRANSCODER_A; 624 else 625 return trans == TRANSCODER_EDP; 626 } 627 628 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate) 629 { 630 if (!cstate || !cstate->hw.active) 631 return 0; 632 633 return DIV_ROUND_UP(1000 * 1000, 634 drm_mode_vrefresh(&cstate->hw.adjusted_mode)); 635 } 636 637 static void psr2_program_idle_frames(struct intel_dp *intel_dp, 638 u32 idle_frames) 639 { 640 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 641 u32 val; 642 643 idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; 644 val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder)); 645 val &= ~EDP_PSR2_IDLE_FRAME_MASK; 646 val |= idle_frames; 647 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 648 } 649 650 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) 651 { 652 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 653 654 psr2_program_idle_frames(intel_dp, 0); 655 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO); 656 } 657 658 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp) 659 { 660 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 661 662 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 663 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp)); 664 } 665 666 static void tgl_dc3co_disable_work(struct work_struct *work) 667 { 668 struct intel_dp *intel_dp = 669 container_of(work, typeof(*intel_dp), psr.dc3co_work.work); 670 671 mutex_lock(&intel_dp->psr.lock); 672 /* If delayed work is pending, it is not idle */ 673 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) 674 goto unlock; 675 676 tgl_psr2_disable_dc3co(intel_dp); 677 unlock: 678 mutex_unlock(&intel_dp->psr.lock); 679 } 680 681 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) 682 { 683 if (!intel_dp->psr.dc3co_exitline) 684 return; 685 686 cancel_delayed_work(&intel_dp->psr.dc3co_work); 687 /* Before PSR2 exit disallow dc3co*/ 688 tgl_psr2_disable_dc3co(intel_dp); 689 } 690 691 static bool 692 dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp, 693 struct intel_crtc_state *crtc_state) 694 { 695 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 696 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 697 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 698 enum port port = dig_port->base.port; 699 700 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 701 return pipe <= PIPE_B && port <= PORT_B; 702 else 703 return pipe == PIPE_A && port == PORT_A; 704 } 705 706 static void 707 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 708 struct intel_crtc_state *crtc_state) 709 { 710 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; 711 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 712 u32 exit_scanlines; 713 714 /* 715 * FIXME: Due to the changed sequence of activating/deactivating DC3CO, 716 * disable DC3CO until the changed dc3co activating/deactivating sequence 717 * is applied. B.Specs:49196 718 */ 719 return; 720 721 /* 722 * DMC's DC3CO exit mechanism has an issue with Selective Fecth 723 * TODO: when the issue is addressed, this restriction should be removed. 724 */ 725 if (crtc_state->enable_psr2_sel_fetch) 726 return; 727 728 if (!(dev_priv->display.dmc.allowed_dc_mask & DC_STATE_EN_DC3CO)) 729 return; 730 731 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) 732 return; 733 734 /* Wa_16011303918:adl-p */ 735 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 736 return; 737 738 /* 739 * DC3CO Exit time 200us B.Spec 49196 740 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 741 */ 742 exit_scanlines = 743 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; 744 745 if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay)) 746 return; 747 748 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; 749 } 750 751 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, 752 struct intel_crtc_state *crtc_state) 753 { 754 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 755 756 if (!dev_priv->params.enable_psr2_sel_fetch && 757 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 758 drm_dbg_kms(&dev_priv->drm, 759 "PSR2 sel fetch not enabled, disabled by parameter\n"); 760 return false; 761 } 762 763 if (crtc_state->uapi.async_flip) { 764 drm_dbg_kms(&dev_priv->drm, 765 "PSR2 sel fetch not enabled, async flip enabled\n"); 766 return false; 767 } 768 769 /* Wa_14010254185 Wa_14010103792 */ 770 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { 771 drm_dbg_kms(&dev_priv->drm, 772 "PSR2 sel fetch not enabled, missing the implementation of WAs\n"); 773 return false; 774 } 775 776 return crtc_state->enable_psr2_sel_fetch = true; 777 } 778 779 static bool psr2_granularity_check(struct intel_dp *intel_dp, 780 struct intel_crtc_state *crtc_state) 781 { 782 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 783 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 784 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 785 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 786 u16 y_granularity = 0; 787 788 /* PSR2 HW only send full lines so we only need to validate the width */ 789 if (crtc_hdisplay % intel_dp->psr.su_w_granularity) 790 return false; 791 792 if (crtc_vdisplay % intel_dp->psr.su_y_granularity) 793 return false; 794 795 /* HW tracking is only aligned to 4 lines */ 796 if (!crtc_state->enable_psr2_sel_fetch) 797 return intel_dp->psr.su_y_granularity == 4; 798 799 /* 800 * adl_p and display 14+ platforms has 1 line granularity. 801 * For other platforms with SW tracking we can adjust the y coordinates 802 * to match sink requirement if multiple of 4. 803 */ 804 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 805 y_granularity = intel_dp->psr.su_y_granularity; 806 else if (intel_dp->psr.su_y_granularity <= 2) 807 y_granularity = 4; 808 else if ((intel_dp->psr.su_y_granularity % 4) == 0) 809 y_granularity = intel_dp->psr.su_y_granularity; 810 811 if (y_granularity == 0 || crtc_vdisplay % y_granularity) 812 return false; 813 814 if (crtc_state->dsc.compression_enable && 815 vdsc_cfg->slice_height % y_granularity) 816 return false; 817 818 crtc_state->su_y_granularity = y_granularity; 819 return true; 820 } 821 822 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp, 823 struct intel_crtc_state *crtc_state) 824 { 825 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; 826 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 827 u32 hblank_total, hblank_ns, req_ns; 828 829 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; 830 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); 831 832 /* From spec: ((60 / number of lanes) + 11) * 1000 / symbol clock frequency MHz */ 833 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); 834 835 if ((hblank_ns - req_ns) > 100) 836 return true; 837 838 /* Not supported <13 / Wa_22012279113:adl-p */ 839 if (DISPLAY_VER(dev_priv) <= 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b) 840 return false; 841 842 crtc_state->req_psr2_sdp_prior_scanline = true; 843 return true; 844 } 845 846 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 847 struct intel_crtc_state *crtc_state) 848 { 849 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 850 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 851 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 852 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 853 854 if (!intel_dp->psr.sink_psr2_support) 855 return false; 856 857 /* JSL and EHL only supports eDP 1.3 */ 858 if (IS_JSL_EHL(dev_priv)) { 859 drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n"); 860 return false; 861 } 862 863 /* Wa_16011181250 */ 864 if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) || 865 IS_DG2(dev_priv)) { 866 drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n"); 867 return false; 868 } 869 870 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 871 drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n"); 872 return false; 873 } 874 875 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { 876 drm_dbg_kms(&dev_priv->drm, 877 "PSR2 not supported in transcoder %s\n", 878 transcoder_name(crtc_state->cpu_transcoder)); 879 return false; 880 } 881 882 if (!psr2_global_enabled(intel_dp)) { 883 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); 884 return false; 885 } 886 887 /* 888 * DSC and PSR2 cannot be enabled simultaneously. If a requested 889 * resolution requires DSC to be enabled, priority is given to DSC 890 * over PSR2. 891 */ 892 if (crtc_state->dsc.compression_enable && 893 (DISPLAY_VER(dev_priv) <= 13 && !IS_ALDERLAKE_P(dev_priv))) { 894 drm_dbg_kms(&dev_priv->drm, 895 "PSR2 cannot be enabled since DSC is enabled\n"); 896 return false; 897 } 898 899 if (crtc_state->crc_enabled) { 900 drm_dbg_kms(&dev_priv->drm, 901 "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); 902 return false; 903 } 904 905 if (DISPLAY_VER(dev_priv) >= 12) { 906 psr_max_h = 5120; 907 psr_max_v = 3200; 908 max_bpp = 30; 909 } else if (DISPLAY_VER(dev_priv) >= 10) { 910 psr_max_h = 4096; 911 psr_max_v = 2304; 912 max_bpp = 24; 913 } else if (DISPLAY_VER(dev_priv) == 9) { 914 psr_max_h = 3640; 915 psr_max_v = 2304; 916 max_bpp = 24; 917 } 918 919 if (crtc_state->pipe_bpp > max_bpp) { 920 drm_dbg_kms(&dev_priv->drm, 921 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 922 crtc_state->pipe_bpp, max_bpp); 923 return false; 924 } 925 926 /* Wa_16011303918:adl-p */ 927 if (crtc_state->vrr.enable && 928 IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 929 drm_dbg_kms(&dev_priv->drm, 930 "PSR2 not enabled, not compatible with HW stepping + VRR\n"); 931 return false; 932 } 933 934 if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) { 935 drm_dbg_kms(&dev_priv->drm, 936 "PSR2 not enabled, PSR2 SDP indication do not fit in hblank\n"); 937 return false; 938 } 939 940 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 941 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && 942 !HAS_PSR_HW_TRACKING(dev_priv)) { 943 drm_dbg_kms(&dev_priv->drm, 944 "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); 945 return false; 946 } 947 } 948 949 /* Wa_2209313811 */ 950 if (!crtc_state->enable_psr2_sel_fetch && 951 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { 952 drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n"); 953 goto unsupported; 954 } 955 956 if (!psr2_granularity_check(intel_dp, crtc_state)) { 957 drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n"); 958 goto unsupported; 959 } 960 961 if (!crtc_state->enable_psr2_sel_fetch && 962 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { 963 drm_dbg_kms(&dev_priv->drm, 964 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 965 crtc_hdisplay, crtc_vdisplay, 966 psr_max_h, psr_max_v); 967 goto unsupported; 968 } 969 970 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); 971 return true; 972 973 unsupported: 974 crtc_state->enable_psr2_sel_fetch = false; 975 return false; 976 } 977 978 void intel_psr_compute_config(struct intel_dp *intel_dp, 979 struct intel_crtc_state *crtc_state, 980 struct drm_connector_state *conn_state) 981 { 982 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 983 const struct drm_display_mode *adjusted_mode = 984 &crtc_state->hw.adjusted_mode; 985 int psr_setup_time; 986 987 /* 988 * Current PSR panels don't work reliably with VRR enabled 989 * So if VRR is enabled, do not enable PSR. 990 */ 991 if (crtc_state->vrr.enable) 992 return; 993 994 if (!CAN_PSR(intel_dp)) 995 return; 996 997 if (!psr_global_enabled(intel_dp)) { 998 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); 999 return; 1000 } 1001 1002 if (intel_dp->psr.sink_not_reliable) { 1003 drm_dbg_kms(&dev_priv->drm, 1004 "PSR sink implementation is not reliable\n"); 1005 return; 1006 } 1007 1008 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 1009 drm_dbg_kms(&dev_priv->drm, 1010 "PSR condition failed: Interlaced mode enabled\n"); 1011 return; 1012 } 1013 1014 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); 1015 if (psr_setup_time < 0) { 1016 drm_dbg_kms(&dev_priv->drm, 1017 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 1018 intel_dp->psr_dpcd[1]); 1019 return; 1020 } 1021 1022 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 1023 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 1024 drm_dbg_kms(&dev_priv->drm, 1025 "PSR condition failed: PSR setup time (%d us) too long\n", 1026 psr_setup_time); 1027 return; 1028 } 1029 1030 crtc_state->has_psr = true; 1031 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); 1032 1033 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1034 intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, 1035 &crtc_state->psr_vsc); 1036 } 1037 1038 void intel_psr_get_config(struct intel_encoder *encoder, 1039 struct intel_crtc_state *pipe_config) 1040 { 1041 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1042 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1043 struct intel_dp *intel_dp; 1044 u32 val; 1045 1046 if (!dig_port) 1047 return; 1048 1049 intel_dp = &dig_port->dp; 1050 if (!CAN_PSR(intel_dp)) 1051 return; 1052 1053 mutex_lock(&intel_dp->psr.lock); 1054 if (!intel_dp->psr.enabled) 1055 goto unlock; 1056 1057 /* 1058 * Not possible to read EDP_PSR/PSR2_CTL registers as it is 1059 * enabled/disabled because of frontbuffer tracking and others. 1060 */ 1061 pipe_config->has_psr = true; 1062 pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; 1063 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1064 1065 if (!intel_dp->psr.psr2_enabled) 1066 goto unlock; 1067 1068 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 1069 val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); 1070 if (val & PSR2_MAN_TRK_CTL_ENABLE) 1071 pipe_config->enable_psr2_sel_fetch = true; 1072 } 1073 1074 if (DISPLAY_VER(dev_priv) >= 12) { 1075 val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder)); 1076 val &= EXITLINE_MASK; 1077 pipe_config->dc3co_exitline = val; 1078 } 1079 unlock: 1080 mutex_unlock(&intel_dp->psr.lock); 1081 } 1082 1083 static void intel_psr_activate(struct intel_dp *intel_dp) 1084 { 1085 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1086 enum transcoder transcoder = intel_dp->psr.transcoder; 1087 1088 if (transcoder_has_psr2(dev_priv, transcoder)) 1089 drm_WARN_ON(&dev_priv->drm, 1090 intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE); 1091 1092 drm_WARN_ON(&dev_priv->drm, 1093 intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE); 1094 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active); 1095 lockdep_assert_held(&intel_dp->psr.lock); 1096 1097 /* psr1 and psr2 are mutually exclusive.*/ 1098 if (intel_dp->psr.psr2_enabled) 1099 hsw_activate_psr2(intel_dp); 1100 else 1101 hsw_activate_psr1(intel_dp); 1102 1103 intel_dp->psr.active = true; 1104 } 1105 1106 static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp) 1107 { 1108 switch (intel_dp->psr.pipe) { 1109 case PIPE_A: 1110 return LATENCY_REPORTING_REMOVED_PIPE_A; 1111 case PIPE_B: 1112 return LATENCY_REPORTING_REMOVED_PIPE_B; 1113 case PIPE_C: 1114 return LATENCY_REPORTING_REMOVED_PIPE_C; 1115 default: 1116 MISSING_CASE(intel_dp->psr.pipe); 1117 return 0; 1118 } 1119 } 1120 1121 static void intel_psr_enable_source(struct intel_dp *intel_dp, 1122 const struct intel_crtc_state *crtc_state) 1123 { 1124 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1125 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1126 u32 mask; 1127 1128 /* 1129 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 1130 * mask LPSP to avoid dependency on other drivers that might block 1131 * runtime_pm besides preventing other hw tracking issues now we 1132 * can rely on frontbuffer tracking. 1133 */ 1134 mask = EDP_PSR_DEBUG_MASK_MEMUP | 1135 EDP_PSR_DEBUG_MASK_HPD | 1136 EDP_PSR_DEBUG_MASK_LPSP | 1137 EDP_PSR_DEBUG_MASK_MAX_SLEEP; 1138 1139 if (DISPLAY_VER(dev_priv) < 11) 1140 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 1141 1142 intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder), 1143 mask); 1144 1145 psr_irq_control(intel_dp); 1146 1147 if (intel_dp->psr.dc3co_exitline) { 1148 u32 val; 1149 1150 /* 1151 * TODO: if future platforms supports DC3CO in more than one 1152 * transcoder, EXITLINE will need to be unset when disabling PSR 1153 */ 1154 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder)); 1155 val &= ~EXITLINE_MASK; 1156 val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT; 1157 val |= EXITLINE_ENABLE; 1158 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); 1159 } 1160 1161 if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv)) 1162 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, 1163 intel_dp->psr.psr2_sel_fetch_enabled ? 1164 IGNORE_PSR2_HW_TRACKING : 0); 1165 1166 if (intel_dp->psr.psr2_enabled) { 1167 if (DISPLAY_VER(dev_priv) == 9) 1168 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, 1169 PSR2_VSC_ENABLE_PROG_HEADER | 1170 PSR2_ADD_VERTICAL_LINE_COUNT); 1171 1172 /* 1173 * Wa_16014451276:adlp 1174 * All supported adlp panels have 1-based X granularity, this may 1175 * cause issues if non-supported panels are used. 1176 */ 1177 if (IS_ALDERLAKE_P(dev_priv)) 1178 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, 1179 ADLP_1_BASED_X_GRANULARITY); 1180 1181 /* Wa_16011168373:adl-p */ 1182 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1183 intel_de_rmw(dev_priv, 1184 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), 1185 TRANS_SET_CONTEXT_LATENCY_MASK, 1186 TRANS_SET_CONTEXT_LATENCY_VALUE(1)); 1187 1188 /* Wa_16012604467:adlp */ 1189 if (IS_ALDERLAKE_P(dev_priv)) 1190 intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0, 1191 CLKGATE_DIS_MISC_DMASC_GATING_DIS); 1192 1193 /* Wa_16013835468:tgl[b0+], dg1 */ 1194 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) || 1195 IS_DG1(dev_priv)) { 1196 u16 vtotal, vblank; 1197 1198 vtotal = crtc_state->uapi.adjusted_mode.crtc_vtotal - 1199 crtc_state->uapi.adjusted_mode.crtc_vdisplay; 1200 vblank = crtc_state->uapi.adjusted_mode.crtc_vblank_end - 1201 crtc_state->uapi.adjusted_mode.crtc_vblank_start; 1202 if (vblank > vtotal) 1203 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, 1204 wa_16013835468_bit_get(intel_dp)); 1205 } 1206 } 1207 } 1208 1209 static bool psr_interrupt_error_check(struct intel_dp *intel_dp) 1210 { 1211 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1212 u32 val; 1213 1214 /* 1215 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 1216 * will still keep the error set even after the reset done in the 1217 * irq_preinstall and irq_uninstall hooks. 1218 * And enabling in this situation cause the screen to freeze in the 1219 * first time that PSR HW tries to activate so lets keep PSR disabled 1220 * to avoid any rendering problems. 1221 */ 1222 if (DISPLAY_VER(dev_priv) >= 12) 1223 val = intel_de_read(dev_priv, 1224 TRANS_PSR_IIR(intel_dp->psr.transcoder)); 1225 else 1226 val = intel_de_read(dev_priv, EDP_PSR_IIR); 1227 val &= psr_irq_psr_error_bit_get(intel_dp); 1228 if (val) { 1229 intel_dp->psr.sink_not_reliable = true; 1230 drm_dbg_kms(&dev_priv->drm, 1231 "PSR interruption error set, not enabling PSR\n"); 1232 return false; 1233 } 1234 1235 return true; 1236 } 1237 1238 static void intel_psr_enable_locked(struct intel_dp *intel_dp, 1239 const struct intel_crtc_state *crtc_state) 1240 { 1241 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1242 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1243 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 1244 struct intel_encoder *encoder = &dig_port->base; 1245 u32 val; 1246 1247 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); 1248 1249 intel_dp->psr.psr2_enabled = crtc_state->has_psr2; 1250 intel_dp->psr.busy_frontbuffer_bits = 0; 1251 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1252 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; 1253 /* DC5/DC6 requires at least 6 idle frames */ 1254 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 1255 intel_dp->psr.dc3co_exit_delay = val; 1256 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; 1257 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; 1258 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 1259 intel_dp->psr.req_psr2_sdp_prior_scanline = 1260 crtc_state->req_psr2_sdp_prior_scanline; 1261 1262 if (!psr_interrupt_error_check(intel_dp)) 1263 return; 1264 1265 drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", 1266 intel_dp->psr.psr2_enabled ? "2" : "1"); 1267 intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc); 1268 intel_snps_phy_update_psr_power_state(dev_priv, phy, true); 1269 intel_psr_enable_sink(intel_dp); 1270 intel_psr_enable_source(intel_dp, crtc_state); 1271 intel_dp->psr.enabled = true; 1272 intel_dp->psr.paused = false; 1273 1274 intel_psr_activate(intel_dp); 1275 } 1276 1277 static void intel_psr_exit(struct intel_dp *intel_dp) 1278 { 1279 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1280 u32 val; 1281 1282 if (!intel_dp->psr.active) { 1283 if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) { 1284 val = intel_de_read(dev_priv, 1285 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1286 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE); 1287 } 1288 1289 val = intel_de_read(dev_priv, 1290 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1291 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE); 1292 1293 return; 1294 } 1295 1296 if (intel_dp->psr.psr2_enabled) { 1297 tgl_disallow_dc3co_on_psr2_exit(intel_dp); 1298 val = intel_de_read(dev_priv, 1299 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1300 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE)); 1301 val &= ~EDP_PSR2_ENABLE; 1302 intel_de_write(dev_priv, 1303 EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 1304 } else { 1305 val = intel_de_read(dev_priv, 1306 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1307 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE)); 1308 val &= ~EDP_PSR_ENABLE; 1309 intel_de_write(dev_priv, 1310 EDP_PSR_CTL(intel_dp->psr.transcoder), val); 1311 } 1312 intel_dp->psr.active = false; 1313 } 1314 1315 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) 1316 { 1317 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1318 i915_reg_t psr_status; 1319 u32 psr_status_mask; 1320 1321 if (intel_dp->psr.psr2_enabled) { 1322 psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 1323 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 1324 } else { 1325 psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder); 1326 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 1327 } 1328 1329 /* Wait till PSR is idle */ 1330 if (intel_de_wait_for_clear(dev_priv, psr_status, 1331 psr_status_mask, 2000)) 1332 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n"); 1333 } 1334 1335 static void intel_psr_disable_locked(struct intel_dp *intel_dp) 1336 { 1337 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1338 enum phy phy = intel_port_to_phy(dev_priv, 1339 dp_to_dig_port(intel_dp)->base.port); 1340 1341 lockdep_assert_held(&intel_dp->psr.lock); 1342 1343 if (!intel_dp->psr.enabled) 1344 return; 1345 1346 drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", 1347 intel_dp->psr.psr2_enabled ? "2" : "1"); 1348 1349 intel_psr_exit(intel_dp); 1350 intel_psr_wait_exit_locked(intel_dp); 1351 1352 /* Wa_1408330847 */ 1353 if (intel_dp->psr.psr2_sel_fetch_enabled && 1354 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1355 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1356 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0); 1357 1358 if (intel_dp->psr.psr2_enabled) { 1359 /* Wa_16011168373:adl-p */ 1360 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1361 intel_de_rmw(dev_priv, 1362 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), 1363 TRANS_SET_CONTEXT_LATENCY_MASK, 0); 1364 1365 /* Wa_16012604467:adlp */ 1366 if (IS_ALDERLAKE_P(dev_priv)) 1367 intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 1368 CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0); 1369 1370 /* Wa_16013835468:tgl[b0+], dg1 */ 1371 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) || 1372 IS_DG1(dev_priv)) 1373 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 1374 wa_16013835468_bit_get(intel_dp), 0); 1375 } 1376 1377 intel_snps_phy_update_psr_power_state(dev_priv, phy, false); 1378 1379 /* Disable PSR on Sink */ 1380 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 1381 1382 if (intel_dp->psr.psr2_enabled) 1383 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); 1384 1385 intel_dp->psr.enabled = false; 1386 intel_dp->psr.psr2_enabled = false; 1387 intel_dp->psr.psr2_sel_fetch_enabled = false; 1388 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 1389 } 1390 1391 /** 1392 * intel_psr_disable - Disable PSR 1393 * @intel_dp: Intel DP 1394 * @old_crtc_state: old CRTC state 1395 * 1396 * This function needs to be called before disabling pipe. 1397 */ 1398 void intel_psr_disable(struct intel_dp *intel_dp, 1399 const struct intel_crtc_state *old_crtc_state) 1400 { 1401 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1402 1403 if (!old_crtc_state->has_psr) 1404 return; 1405 1406 if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp))) 1407 return; 1408 1409 mutex_lock(&intel_dp->psr.lock); 1410 1411 intel_psr_disable_locked(intel_dp); 1412 1413 mutex_unlock(&intel_dp->psr.lock); 1414 cancel_work_sync(&intel_dp->psr.work); 1415 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); 1416 } 1417 1418 /** 1419 * intel_psr_pause - Pause PSR 1420 * @intel_dp: Intel DP 1421 * 1422 * This function need to be called after enabling psr. 1423 */ 1424 void intel_psr_pause(struct intel_dp *intel_dp) 1425 { 1426 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1427 struct intel_psr *psr = &intel_dp->psr; 1428 1429 if (!CAN_PSR(intel_dp)) 1430 return; 1431 1432 mutex_lock(&psr->lock); 1433 1434 if (!psr->enabled) { 1435 mutex_unlock(&psr->lock); 1436 return; 1437 } 1438 1439 /* If we ever hit this, we will need to add refcount to pause/resume */ 1440 drm_WARN_ON(&dev_priv->drm, psr->paused); 1441 1442 intel_psr_exit(intel_dp); 1443 intel_psr_wait_exit_locked(intel_dp); 1444 psr->paused = true; 1445 1446 mutex_unlock(&psr->lock); 1447 1448 cancel_work_sync(&psr->work); 1449 cancel_delayed_work_sync(&psr->dc3co_work); 1450 } 1451 1452 /** 1453 * intel_psr_resume - Resume PSR 1454 * @intel_dp: Intel DP 1455 * 1456 * This function need to be called after pausing psr. 1457 */ 1458 void intel_psr_resume(struct intel_dp *intel_dp) 1459 { 1460 struct intel_psr *psr = &intel_dp->psr; 1461 1462 if (!CAN_PSR(intel_dp)) 1463 return; 1464 1465 mutex_lock(&psr->lock); 1466 1467 if (!psr->paused) 1468 goto unlock; 1469 1470 psr->paused = false; 1471 intel_psr_activate(intel_dp); 1472 1473 unlock: 1474 mutex_unlock(&psr->lock); 1475 } 1476 1477 static u32 man_trk_ctl_enable_bit_get(struct drm_i915_private *dev_priv) 1478 { 1479 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ? 0 : 1480 PSR2_MAN_TRK_CTL_ENABLE; 1481 } 1482 1483 static u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private *dev_priv) 1484 { 1485 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ? 1486 ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME : 1487 PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 1488 } 1489 1490 static u32 man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev_priv) 1491 { 1492 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ? 1493 ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE : 1494 PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; 1495 } 1496 1497 static u32 man_trk_ctl_continuos_full_frame(struct drm_i915_private *dev_priv) 1498 { 1499 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ? 1500 ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME : 1501 PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME; 1502 } 1503 1504 static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) 1505 { 1506 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1507 1508 if (intel_dp->psr.psr2_sel_fetch_enabled) 1509 intel_de_write(dev_priv, 1510 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 1511 man_trk_ctl_enable_bit_get(dev_priv) | 1512 man_trk_ctl_partial_frame_bit_get(dev_priv) | 1513 man_trk_ctl_single_full_frame_bit_get(dev_priv)); 1514 1515 /* 1516 * Display WA #0884: skl+ 1517 * This documented WA for bxt can be safely applied 1518 * broadly so we can force HW tracking to exit PSR 1519 * instead of disabling and re-enabling. 1520 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 1521 * but it makes more sense write to the current active 1522 * pipe. 1523 * 1524 * This workaround do not exist for platforms with display 10 or newer 1525 * but testing proved that it works for up display 13, for newer 1526 * than that testing will be needed. 1527 */ 1528 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 1529 } 1530 1531 void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane, 1532 const struct intel_crtc_state *crtc_state) 1533 { 1534 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1535 enum pipe pipe = plane->pipe; 1536 1537 if (!crtc_state->enable_psr2_sel_fetch) 1538 return; 1539 1540 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0); 1541 } 1542 1543 void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, 1544 const struct intel_crtc_state *crtc_state, 1545 const struct intel_plane_state *plane_state, 1546 int color_plane) 1547 { 1548 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1549 enum pipe pipe = plane->pipe; 1550 const struct drm_rect *clip; 1551 u32 val; 1552 int x, y; 1553 1554 if (!crtc_state->enable_psr2_sel_fetch) 1555 return; 1556 1557 if (plane->id == PLANE_CURSOR) { 1558 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 1559 plane_state->ctl); 1560 return; 1561 } 1562 1563 clip = &plane_state->psr2_sel_fetch_area; 1564 1565 val = (clip->y1 + plane_state->uapi.dst.y1) << 16; 1566 val |= plane_state->uapi.dst.x1; 1567 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); 1568 1569 x = plane_state->view.color_plane[color_plane].x; 1570 1571 /* 1572 * From Bspec: UV surface Start Y Position = half of Y plane Y 1573 * start position. 1574 */ 1575 if (!color_plane) 1576 y = plane_state->view.color_plane[color_plane].y + clip->y1; 1577 else 1578 y = plane_state->view.color_plane[color_plane].y + clip->y1 / 2; 1579 1580 val = y << 16 | x; 1581 1582 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), 1583 val); 1584 1585 /* Sizes are 0 based */ 1586 val = (drm_rect_height(clip) - 1) << 16; 1587 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; 1588 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); 1589 1590 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 1591 PLANE_SEL_FETCH_CTL_ENABLE); 1592 } 1593 1594 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) 1595 { 1596 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1597 struct intel_encoder *encoder; 1598 1599 if (!crtc_state->enable_psr2_sel_fetch) 1600 return; 1601 1602 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, 1603 crtc_state->uapi.encoder_mask) { 1604 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1605 1606 lockdep_assert_held(&intel_dp->psr.lock); 1607 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) 1608 return; 1609 break; 1610 } 1611 1612 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder), 1613 crtc_state->psr2_man_track_ctl); 1614 } 1615 1616 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, 1617 struct drm_rect *clip, bool full_update) 1618 { 1619 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1620 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1621 u32 val = man_trk_ctl_enable_bit_get(dev_priv); 1622 1623 /* SF partial frame enable has to be set even on full update */ 1624 val |= man_trk_ctl_partial_frame_bit_get(dev_priv); 1625 1626 if (full_update) { 1627 /* 1628 * Not applying Wa_14014971508:adlp as we do not support the 1629 * feature that requires this workaround. 1630 */ 1631 val |= man_trk_ctl_single_full_frame_bit_get(dev_priv); 1632 goto exit; 1633 } 1634 1635 if (clip->y1 == -1) 1636 goto exit; 1637 1638 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) { 1639 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1); 1640 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 - 1); 1641 } else { 1642 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4); 1643 1644 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1); 1645 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1); 1646 } 1647 exit: 1648 crtc_state->psr2_man_track_ctl = val; 1649 } 1650 1651 static void clip_area_update(struct drm_rect *overlap_damage_area, 1652 struct drm_rect *damage_area, 1653 struct drm_rect *pipe_src) 1654 { 1655 if (!drm_rect_intersect(damage_area, pipe_src)) 1656 return; 1657 1658 if (overlap_damage_area->y1 == -1) { 1659 overlap_damage_area->y1 = damage_area->y1; 1660 overlap_damage_area->y2 = damage_area->y2; 1661 return; 1662 } 1663 1664 if (damage_area->y1 < overlap_damage_area->y1) 1665 overlap_damage_area->y1 = damage_area->y1; 1666 1667 if (damage_area->y2 > overlap_damage_area->y2) 1668 overlap_damage_area->y2 = damage_area->y2; 1669 } 1670 1671 static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state, 1672 struct drm_rect *pipe_clip) 1673 { 1674 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1675 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1676 u16 y_alignment; 1677 1678 /* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */ 1679 if (crtc_state->dsc.compression_enable && 1680 (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)) 1681 y_alignment = vdsc_cfg->slice_height; 1682 else 1683 y_alignment = crtc_state->su_y_granularity; 1684 1685 pipe_clip->y1 -= pipe_clip->y1 % y_alignment; 1686 if (pipe_clip->y2 % y_alignment) 1687 pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment; 1688 } 1689 1690 /* 1691 * TODO: Not clear how to handle planes with negative position, 1692 * also planes are not updated if they have a negative X 1693 * position so for now doing a full update in this cases 1694 * 1695 * Plane scaling and rotation is not supported by selective fetch and both 1696 * properties can change without a modeset, so need to be check at every 1697 * atomic commit. 1698 */ 1699 static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state) 1700 { 1701 if (plane_state->uapi.dst.y1 < 0 || 1702 plane_state->uapi.dst.x1 < 0 || 1703 plane_state->scaler_id >= 0 || 1704 plane_state->uapi.rotation != DRM_MODE_ROTATE_0) 1705 return false; 1706 1707 return true; 1708 } 1709 1710 /* 1711 * Check for pipe properties that is not supported by selective fetch. 1712 * 1713 * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed 1714 * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch 1715 * enabled and going to the full update path. 1716 */ 1717 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state) 1718 { 1719 if (crtc_state->scaler_state.scaler_id >= 0) 1720 return false; 1721 1722 return true; 1723 } 1724 1725 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 1726 struct intel_crtc *crtc) 1727 { 1728 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1729 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 1730 struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 }; 1731 struct intel_plane_state *new_plane_state, *old_plane_state; 1732 struct intel_plane *plane; 1733 bool full_update = false; 1734 int i, ret; 1735 1736 if (!crtc_state->enable_psr2_sel_fetch) 1737 return 0; 1738 1739 if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) { 1740 full_update = true; 1741 goto skip_sel_fetch_set_loop; 1742 } 1743 1744 /* 1745 * Calculate minimal selective fetch area of each plane and calculate 1746 * the pipe damaged area. 1747 * In the next loop the plane selective fetch area will actually be set 1748 * using whole pipe damaged area. 1749 */ 1750 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1751 new_plane_state, i) { 1752 struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1, 1753 .x2 = INT_MAX }; 1754 1755 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) 1756 continue; 1757 1758 if (!new_plane_state->uapi.visible && 1759 !old_plane_state->uapi.visible) 1760 continue; 1761 1762 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 1763 full_update = true; 1764 break; 1765 } 1766 1767 /* 1768 * If visibility or plane moved, mark the whole plane area as 1769 * damaged as it needs to be complete redraw in the new and old 1770 * position. 1771 */ 1772 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || 1773 !drm_rect_equals(&new_plane_state->uapi.dst, 1774 &old_plane_state->uapi.dst)) { 1775 if (old_plane_state->uapi.visible) { 1776 damaged_area.y1 = old_plane_state->uapi.dst.y1; 1777 damaged_area.y2 = old_plane_state->uapi.dst.y2; 1778 clip_area_update(&pipe_clip, &damaged_area, 1779 &crtc_state->pipe_src); 1780 } 1781 1782 if (new_plane_state->uapi.visible) { 1783 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1784 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1785 clip_area_update(&pipe_clip, &damaged_area, 1786 &crtc_state->pipe_src); 1787 } 1788 continue; 1789 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { 1790 /* If alpha changed mark the whole plane area as damaged */ 1791 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1792 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1793 clip_area_update(&pipe_clip, &damaged_area, 1794 &crtc_state->pipe_src); 1795 continue; 1796 } 1797 1798 src = drm_plane_state_src(&new_plane_state->uapi); 1799 drm_rect_fp_to_int(&src, &src); 1800 1801 if (!drm_atomic_helper_damage_merged(&old_plane_state->uapi, 1802 &new_plane_state->uapi, &damaged_area)) 1803 continue; 1804 1805 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; 1806 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; 1807 damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1; 1808 damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1; 1809 1810 clip_area_update(&pipe_clip, &damaged_area, &crtc_state->pipe_src); 1811 } 1812 1813 /* 1814 * TODO: For now we are just using full update in case 1815 * selective fetch area calculation fails. To optimize this we 1816 * should identify cases where this happens and fix the area 1817 * calculation for those. 1818 */ 1819 if (pipe_clip.y1 == -1) { 1820 drm_info_once(&dev_priv->drm, 1821 "Selective fetch area calculation failed in pipe %c\n", 1822 pipe_name(crtc->pipe)); 1823 full_update = true; 1824 } 1825 1826 if (full_update) 1827 goto skip_sel_fetch_set_loop; 1828 1829 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 1830 if (ret) 1831 return ret; 1832 1833 intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip); 1834 1835 /* 1836 * Now that we have the pipe damaged area check if it intersect with 1837 * every plane, if it does set the plane selective fetch area. 1838 */ 1839 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1840 new_plane_state, i) { 1841 struct drm_rect *sel_fetch_area, inter; 1842 struct intel_plane *linked = new_plane_state->planar_linked_plane; 1843 1844 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || 1845 !new_plane_state->uapi.visible) 1846 continue; 1847 1848 inter = pipe_clip; 1849 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) 1850 continue; 1851 1852 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 1853 full_update = true; 1854 break; 1855 } 1856 1857 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 1858 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; 1859 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; 1860 crtc_state->update_planes |= BIT(plane->id); 1861 1862 /* 1863 * Sel_fetch_area is calculated for UV plane. Use 1864 * same area for Y plane as well. 1865 */ 1866 if (linked) { 1867 struct intel_plane_state *linked_new_plane_state; 1868 struct drm_rect *linked_sel_fetch_area; 1869 1870 linked_new_plane_state = intel_atomic_get_plane_state(state, linked); 1871 if (IS_ERR(linked_new_plane_state)) 1872 return PTR_ERR(linked_new_plane_state); 1873 1874 linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area; 1875 linked_sel_fetch_area->y1 = sel_fetch_area->y1; 1876 linked_sel_fetch_area->y2 = sel_fetch_area->y2; 1877 crtc_state->update_planes |= BIT(linked->id); 1878 } 1879 } 1880 1881 skip_sel_fetch_set_loop: 1882 psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update); 1883 return 0; 1884 } 1885 1886 void intel_psr_pre_plane_update(struct intel_atomic_state *state, 1887 struct intel_crtc *crtc) 1888 { 1889 struct drm_i915_private *i915 = to_i915(state->base.dev); 1890 const struct intel_crtc_state *old_crtc_state = 1891 intel_atomic_get_old_crtc_state(state, crtc); 1892 const struct intel_crtc_state *new_crtc_state = 1893 intel_atomic_get_new_crtc_state(state, crtc); 1894 struct intel_encoder *encoder; 1895 1896 if (!HAS_PSR(i915)) 1897 return; 1898 1899 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 1900 old_crtc_state->uapi.encoder_mask) { 1901 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1902 struct intel_psr *psr = &intel_dp->psr; 1903 bool needs_to_disable = false; 1904 1905 mutex_lock(&psr->lock); 1906 1907 /* 1908 * Reasons to disable: 1909 * - PSR disabled in new state 1910 * - All planes will go inactive 1911 * - Changing between PSR versions 1912 */ 1913 needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state); 1914 needs_to_disable |= !new_crtc_state->has_psr; 1915 needs_to_disable |= !new_crtc_state->active_planes; 1916 needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled; 1917 1918 if (psr->enabled && needs_to_disable) 1919 intel_psr_disable_locked(intel_dp); 1920 1921 mutex_unlock(&psr->lock); 1922 } 1923 } 1924 1925 static void _intel_psr_post_plane_update(const struct intel_atomic_state *state, 1926 const struct intel_crtc_state *crtc_state) 1927 { 1928 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1929 struct intel_encoder *encoder; 1930 1931 if (!crtc_state->has_psr) 1932 return; 1933 1934 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 1935 crtc_state->uapi.encoder_mask) { 1936 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1937 struct intel_psr *psr = &intel_dp->psr; 1938 1939 mutex_lock(&psr->lock); 1940 1941 if (psr->sink_not_reliable) 1942 goto exit; 1943 1944 drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes); 1945 1946 /* Only enable if there is active planes */ 1947 if (!psr->enabled && crtc_state->active_planes) 1948 intel_psr_enable_locked(intel_dp, crtc_state); 1949 1950 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 1951 if (crtc_state->crc_enabled && psr->enabled) 1952 psr_force_hw_tracking_exit(intel_dp); 1953 1954 exit: 1955 mutex_unlock(&psr->lock); 1956 } 1957 } 1958 1959 void intel_psr_post_plane_update(const struct intel_atomic_state *state) 1960 { 1961 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1962 struct intel_crtc_state *crtc_state; 1963 struct intel_crtc *crtc; 1964 int i; 1965 1966 if (!HAS_PSR(dev_priv)) 1967 return; 1968 1969 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) 1970 _intel_psr_post_plane_update(state, crtc_state); 1971 } 1972 1973 static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp) 1974 { 1975 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1976 1977 /* 1978 * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough. 1979 * As all higher states has bit 4 of PSR2 state set we can just wait for 1980 * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared. 1981 */ 1982 return intel_de_wait_for_clear(dev_priv, 1983 EDP_PSR2_STATUS(intel_dp->psr.transcoder), 1984 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50); 1985 } 1986 1987 static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp) 1988 { 1989 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1990 1991 /* 1992 * From bspec: Panel Self Refresh (BDW+) 1993 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 1994 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 1995 * defensive enough to cover everything. 1996 */ 1997 return intel_de_wait_for_clear(dev_priv, 1998 EDP_PSR_STATUS(intel_dp->psr.transcoder), 1999 EDP_PSR_STATUS_STATE_MASK, 50); 2000 } 2001 2002 /** 2003 * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update 2004 * @new_crtc_state: new CRTC state 2005 * 2006 * This function is expected to be called from pipe_update_start() where it is 2007 * not expected to race with PSR enable or disable. 2008 */ 2009 void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state) 2010 { 2011 struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev); 2012 struct intel_encoder *encoder; 2013 2014 if (!new_crtc_state->has_psr) 2015 return; 2016 2017 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, 2018 new_crtc_state->uapi.encoder_mask) { 2019 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2020 int ret; 2021 2022 lockdep_assert_held(&intel_dp->psr.lock); 2023 2024 if (!intel_dp->psr.enabled) 2025 continue; 2026 2027 if (intel_dp->psr.psr2_enabled) 2028 ret = _psr2_ready_for_pipe_update_locked(intel_dp); 2029 else 2030 ret = _psr1_ready_for_pipe_update_locked(intel_dp); 2031 2032 if (ret) 2033 drm_err(&dev_priv->drm, "PSR wait timed out, atomic update may fail\n"); 2034 } 2035 } 2036 2037 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) 2038 { 2039 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2040 i915_reg_t reg; 2041 u32 mask; 2042 int err; 2043 2044 if (!intel_dp->psr.enabled) 2045 return false; 2046 2047 if (intel_dp->psr.psr2_enabled) { 2048 reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 2049 mask = EDP_PSR2_STATUS_STATE_MASK; 2050 } else { 2051 reg = EDP_PSR_STATUS(intel_dp->psr.transcoder); 2052 mask = EDP_PSR_STATUS_STATE_MASK; 2053 } 2054 2055 mutex_unlock(&intel_dp->psr.lock); 2056 2057 err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); 2058 if (err) 2059 drm_err(&dev_priv->drm, 2060 "Timed out waiting for PSR Idle for re-enable\n"); 2061 2062 /* After the unlocked wait, verify that PSR is still wanted! */ 2063 mutex_lock(&intel_dp->psr.lock); 2064 return err == 0 && intel_dp->psr.enabled; 2065 } 2066 2067 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) 2068 { 2069 struct drm_connector_list_iter conn_iter; 2070 struct drm_modeset_acquire_ctx ctx; 2071 struct drm_atomic_state *state; 2072 struct drm_connector *conn; 2073 int err = 0; 2074 2075 state = drm_atomic_state_alloc(&dev_priv->drm); 2076 if (!state) 2077 return -ENOMEM; 2078 2079 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 2080 state->acquire_ctx = &ctx; 2081 2082 retry: 2083 2084 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 2085 drm_for_each_connector_iter(conn, &conn_iter) { 2086 struct drm_connector_state *conn_state; 2087 struct drm_crtc_state *crtc_state; 2088 2089 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) 2090 continue; 2091 2092 conn_state = drm_atomic_get_connector_state(state, conn); 2093 if (IS_ERR(conn_state)) { 2094 err = PTR_ERR(conn_state); 2095 break; 2096 } 2097 2098 if (!conn_state->crtc) 2099 continue; 2100 2101 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); 2102 if (IS_ERR(crtc_state)) { 2103 err = PTR_ERR(crtc_state); 2104 break; 2105 } 2106 2107 /* Mark mode as changed to trigger a pipe->update() */ 2108 crtc_state->mode_changed = true; 2109 } 2110 drm_connector_list_iter_end(&conn_iter); 2111 2112 if (err == 0) 2113 err = drm_atomic_commit(state); 2114 2115 if (err == -EDEADLK) { 2116 drm_atomic_state_clear(state); 2117 err = drm_modeset_backoff(&ctx); 2118 if (!err) 2119 goto retry; 2120 } 2121 2122 drm_modeset_drop_locks(&ctx); 2123 drm_modeset_acquire_fini(&ctx); 2124 drm_atomic_state_put(state); 2125 2126 return err; 2127 } 2128 2129 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) 2130 { 2131 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2132 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 2133 u32 old_mode; 2134 int ret; 2135 2136 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || 2137 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 2138 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); 2139 return -EINVAL; 2140 } 2141 2142 ret = mutex_lock_interruptible(&intel_dp->psr.lock); 2143 if (ret) 2144 return ret; 2145 2146 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; 2147 intel_dp->psr.debug = val; 2148 2149 /* 2150 * Do it right away if it's already enabled, otherwise it will be done 2151 * when enabling the source. 2152 */ 2153 if (intel_dp->psr.enabled) 2154 psr_irq_control(intel_dp); 2155 2156 mutex_unlock(&intel_dp->psr.lock); 2157 2158 if (old_mode != mode) 2159 ret = intel_psr_fastset_force(dev_priv); 2160 2161 return ret; 2162 } 2163 2164 static void intel_psr_handle_irq(struct intel_dp *intel_dp) 2165 { 2166 struct intel_psr *psr = &intel_dp->psr; 2167 2168 intel_psr_disable_locked(intel_dp); 2169 psr->sink_not_reliable = true; 2170 /* let's make sure that sink is awaken */ 2171 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 2172 } 2173 2174 static void intel_psr_work(struct work_struct *work) 2175 { 2176 struct intel_dp *intel_dp = 2177 container_of(work, typeof(*intel_dp), psr.work); 2178 2179 mutex_lock(&intel_dp->psr.lock); 2180 2181 if (!intel_dp->psr.enabled) 2182 goto unlock; 2183 2184 if (READ_ONCE(intel_dp->psr.irq_aux_error)) 2185 intel_psr_handle_irq(intel_dp); 2186 2187 /* 2188 * We have to make sure PSR is ready for re-enable 2189 * otherwise it keeps disabled until next full enable/disable cycle. 2190 * PSR might take some time to get fully disabled 2191 * and be ready for re-enable. 2192 */ 2193 if (!__psr_wait_for_idle_locked(intel_dp)) 2194 goto unlock; 2195 2196 /* 2197 * The delayed work can race with an invalidate hence we need to 2198 * recheck. Since psr_flush first clears this and then reschedules we 2199 * won't ever miss a flush when bailing out here. 2200 */ 2201 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) 2202 goto unlock; 2203 2204 intel_psr_activate(intel_dp); 2205 unlock: 2206 mutex_unlock(&intel_dp->psr.lock); 2207 } 2208 2209 static void _psr_invalidate_handle(struct intel_dp *intel_dp) 2210 { 2211 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2212 2213 if (intel_dp->psr.psr2_sel_fetch_enabled) { 2214 u32 val; 2215 2216 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { 2217 /* Send one update otherwise lag is observed in screen */ 2218 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 2219 return; 2220 } 2221 2222 val = man_trk_ctl_enable_bit_get(dev_priv) | 2223 man_trk_ctl_partial_frame_bit_get(dev_priv) | 2224 man_trk_ctl_continuos_full_frame(dev_priv); 2225 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), val); 2226 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 2227 intel_dp->psr.psr2_sel_fetch_cff_enabled = true; 2228 } else { 2229 intel_psr_exit(intel_dp); 2230 } 2231 } 2232 2233 /** 2234 * intel_psr_invalidate - Invalidate PSR 2235 * @dev_priv: i915 device 2236 * @frontbuffer_bits: frontbuffer plane tracking bits 2237 * @origin: which operation caused the invalidate 2238 * 2239 * Since the hardware frontbuffer tracking has gaps we need to integrate 2240 * with the software frontbuffer tracking. This function gets called every 2241 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 2242 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 2243 * 2244 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 2245 */ 2246 void intel_psr_invalidate(struct drm_i915_private *dev_priv, 2247 unsigned frontbuffer_bits, enum fb_op_origin origin) 2248 { 2249 struct intel_encoder *encoder; 2250 2251 if (origin == ORIGIN_FLIP) 2252 return; 2253 2254 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2255 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 2256 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2257 2258 mutex_lock(&intel_dp->psr.lock); 2259 if (!intel_dp->psr.enabled) { 2260 mutex_unlock(&intel_dp->psr.lock); 2261 continue; 2262 } 2263 2264 pipe_frontbuffer_bits &= 2265 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 2266 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; 2267 2268 if (pipe_frontbuffer_bits) 2269 _psr_invalidate_handle(intel_dp); 2270 2271 mutex_unlock(&intel_dp->psr.lock); 2272 } 2273 } 2274 /* 2275 * When we will be completely rely on PSR2 S/W tracking in future, 2276 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP 2277 * event also therefore tgl_dc3co_flush_locked() require to be changed 2278 * accordingly in future. 2279 */ 2280 static void 2281 tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits, 2282 enum fb_op_origin origin) 2283 { 2284 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled || 2285 !intel_dp->psr.active) 2286 return; 2287 2288 /* 2289 * At every frontbuffer flush flip event modified delay of delayed work, 2290 * when delayed work schedules that means display has been idle. 2291 */ 2292 if (!(frontbuffer_bits & 2293 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) 2294 return; 2295 2296 tgl_psr2_enable_dc3co(intel_dp); 2297 mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work, 2298 intel_dp->psr.dc3co_exit_delay); 2299 } 2300 2301 static void _psr_flush_handle(struct intel_dp *intel_dp) 2302 { 2303 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2304 2305 if (intel_dp->psr.psr2_sel_fetch_enabled) { 2306 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { 2307 /* can we turn CFF off? */ 2308 if (intel_dp->psr.busy_frontbuffer_bits == 0) { 2309 u32 val = man_trk_ctl_enable_bit_get(dev_priv) | 2310 man_trk_ctl_partial_frame_bit_get(dev_priv) | 2311 man_trk_ctl_single_full_frame_bit_get(dev_priv); 2312 2313 /* 2314 * turn continuous full frame off and do a single 2315 * full frame 2316 */ 2317 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 2318 val); 2319 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 2320 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 2321 } 2322 } else { 2323 /* 2324 * continuous full frame is disabled, only a single full 2325 * frame is required 2326 */ 2327 psr_force_hw_tracking_exit(intel_dp); 2328 } 2329 } else { 2330 psr_force_hw_tracking_exit(intel_dp); 2331 2332 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) 2333 schedule_work(&intel_dp->psr.work); 2334 } 2335 } 2336 2337 /** 2338 * intel_psr_flush - Flush PSR 2339 * @dev_priv: i915 device 2340 * @frontbuffer_bits: frontbuffer plane tracking bits 2341 * @origin: which operation caused the flush 2342 * 2343 * Since the hardware frontbuffer tracking has gaps we need to integrate 2344 * with the software frontbuffer tracking. This function gets called every 2345 * time frontbuffer rendering has completed and flushed out to memory. PSR 2346 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 2347 * 2348 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 2349 */ 2350 void intel_psr_flush(struct drm_i915_private *dev_priv, 2351 unsigned frontbuffer_bits, enum fb_op_origin origin) 2352 { 2353 struct intel_encoder *encoder; 2354 2355 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2356 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 2357 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2358 2359 mutex_lock(&intel_dp->psr.lock); 2360 if (!intel_dp->psr.enabled) { 2361 mutex_unlock(&intel_dp->psr.lock); 2362 continue; 2363 } 2364 2365 pipe_frontbuffer_bits &= 2366 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 2367 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; 2368 2369 /* 2370 * If the PSR is paused by an explicit intel_psr_paused() call, 2371 * we have to ensure that the PSR is not activated until 2372 * intel_psr_resume() is called. 2373 */ 2374 if (intel_dp->psr.paused) 2375 goto unlock; 2376 2377 if (origin == ORIGIN_FLIP || 2378 (origin == ORIGIN_CURSOR_UPDATE && 2379 !intel_dp->psr.psr2_sel_fetch_enabled)) { 2380 tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin); 2381 goto unlock; 2382 } 2383 2384 if (pipe_frontbuffer_bits == 0) 2385 goto unlock; 2386 2387 /* By definition flush = invalidate + flush */ 2388 _psr_flush_handle(intel_dp); 2389 unlock: 2390 mutex_unlock(&intel_dp->psr.lock); 2391 } 2392 } 2393 2394 /** 2395 * intel_psr_init - Init basic PSR work and mutex. 2396 * @intel_dp: Intel DP 2397 * 2398 * This function is called after the initializing connector. 2399 * (the initializing of connector treats the handling of connector capabilities) 2400 * And it initializes basic PSR stuff for each DP Encoder. 2401 */ 2402 void intel_psr_init(struct intel_dp *intel_dp) 2403 { 2404 struct intel_connector *connector = intel_dp->attached_connector; 2405 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2406 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2407 2408 if (!HAS_PSR(dev_priv)) 2409 return; 2410 2411 /* 2412 * HSW spec explicitly says PSR is tied to port A. 2413 * BDW+ platforms have a instance of PSR registers per transcoder but 2414 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder 2415 * than eDP one. 2416 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11. 2417 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11. 2418 * But GEN12 supports a instance of PSR registers per transcoder. 2419 */ 2420 if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) { 2421 drm_dbg_kms(&dev_priv->drm, 2422 "PSR condition failed: Port not supported\n"); 2423 return; 2424 } 2425 2426 intel_dp->psr.source_support = true; 2427 2428 /* Set link_standby x link_off defaults */ 2429 if (DISPLAY_VER(dev_priv) < 12) 2430 /* For new platforms up to TGL let's respect VBT back again */ 2431 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link; 2432 2433 INIT_WORK(&intel_dp->psr.work, intel_psr_work); 2434 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); 2435 mutex_init(&intel_dp->psr.lock); 2436 } 2437 2438 static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 2439 u8 *status, u8 *error_status) 2440 { 2441 struct drm_dp_aux *aux = &intel_dp->aux; 2442 int ret; 2443 2444 ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status); 2445 if (ret != 1) 2446 return ret; 2447 2448 ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status); 2449 if (ret != 1) 2450 return ret; 2451 2452 *status = *status & DP_PSR_SINK_STATE_MASK; 2453 2454 return 0; 2455 } 2456 2457 static void psr_alpm_check(struct intel_dp *intel_dp) 2458 { 2459 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2460 struct drm_dp_aux *aux = &intel_dp->aux; 2461 struct intel_psr *psr = &intel_dp->psr; 2462 u8 val; 2463 int r; 2464 2465 if (!psr->psr2_enabled) 2466 return; 2467 2468 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); 2469 if (r != 1) { 2470 drm_err(&dev_priv->drm, "Error reading ALPM status\n"); 2471 return; 2472 } 2473 2474 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) { 2475 intel_psr_disable_locked(intel_dp); 2476 psr->sink_not_reliable = true; 2477 drm_dbg_kms(&dev_priv->drm, 2478 "ALPM lock timeout error, disabling PSR\n"); 2479 2480 /* Clearing error */ 2481 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); 2482 } 2483 } 2484 2485 static void psr_capability_changed_check(struct intel_dp *intel_dp) 2486 { 2487 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2488 struct intel_psr *psr = &intel_dp->psr; 2489 u8 val; 2490 int r; 2491 2492 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 2493 if (r != 1) { 2494 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n"); 2495 return; 2496 } 2497 2498 if (val & DP_PSR_CAPS_CHANGE) { 2499 intel_psr_disable_locked(intel_dp); 2500 psr->sink_not_reliable = true; 2501 drm_dbg_kms(&dev_priv->drm, 2502 "Sink PSR capability changed, disabling PSR\n"); 2503 2504 /* Clearing it */ 2505 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 2506 } 2507 } 2508 2509 void intel_psr_short_pulse(struct intel_dp *intel_dp) 2510 { 2511 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2512 struct intel_psr *psr = &intel_dp->psr; 2513 u8 status, error_status; 2514 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 2515 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 2516 DP_PSR_LINK_CRC_ERROR; 2517 2518 if (!CAN_PSR(intel_dp)) 2519 return; 2520 2521 mutex_lock(&psr->lock); 2522 2523 if (!psr->enabled) 2524 goto exit; 2525 2526 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 2527 drm_err(&dev_priv->drm, 2528 "Error reading PSR status or error status\n"); 2529 goto exit; 2530 } 2531 2532 if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) { 2533 intel_psr_disable_locked(intel_dp); 2534 psr->sink_not_reliable = true; 2535 } 2536 2537 if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status) 2538 drm_dbg_kms(&dev_priv->drm, 2539 "PSR sink internal error, disabling PSR\n"); 2540 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 2541 drm_dbg_kms(&dev_priv->drm, 2542 "PSR RFB storage error, disabling PSR\n"); 2543 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 2544 drm_dbg_kms(&dev_priv->drm, 2545 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 2546 if (error_status & DP_PSR_LINK_CRC_ERROR) 2547 drm_dbg_kms(&dev_priv->drm, 2548 "PSR Link CRC error, disabling PSR\n"); 2549 2550 if (error_status & ~errors) 2551 drm_err(&dev_priv->drm, 2552 "PSR_ERROR_STATUS unhandled errors %x\n", 2553 error_status & ~errors); 2554 /* clear status register */ 2555 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 2556 2557 psr_alpm_check(intel_dp); 2558 psr_capability_changed_check(intel_dp); 2559 2560 exit: 2561 mutex_unlock(&psr->lock); 2562 } 2563 2564 bool intel_psr_enabled(struct intel_dp *intel_dp) 2565 { 2566 bool ret; 2567 2568 if (!CAN_PSR(intel_dp)) 2569 return false; 2570 2571 mutex_lock(&intel_dp->psr.lock); 2572 ret = intel_dp->psr.enabled; 2573 mutex_unlock(&intel_dp->psr.lock); 2574 2575 return ret; 2576 } 2577 2578 /** 2579 * intel_psr_lock - grab PSR lock 2580 * @crtc_state: the crtc state 2581 * 2582 * This is initially meant to be used by around CRTC update, when 2583 * vblank sensitive registers are updated and we need grab the lock 2584 * before it to avoid vblank evasion. 2585 */ 2586 void intel_psr_lock(const struct intel_crtc_state *crtc_state) 2587 { 2588 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2589 struct intel_encoder *encoder; 2590 2591 if (!crtc_state->has_psr) 2592 return; 2593 2594 for_each_intel_encoder_mask_with_psr(&i915->drm, encoder, 2595 crtc_state->uapi.encoder_mask) { 2596 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2597 2598 mutex_lock(&intel_dp->psr.lock); 2599 break; 2600 } 2601 } 2602 2603 /** 2604 * intel_psr_unlock - release PSR lock 2605 * @crtc_state: the crtc state 2606 * 2607 * Release the PSR lock that was held during pipe update. 2608 */ 2609 void intel_psr_unlock(const struct intel_crtc_state *crtc_state) 2610 { 2611 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2612 struct intel_encoder *encoder; 2613 2614 if (!crtc_state->has_psr) 2615 return; 2616 2617 for_each_intel_encoder_mask_with_psr(&i915->drm, encoder, 2618 crtc_state->uapi.encoder_mask) { 2619 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2620 2621 mutex_unlock(&intel_dp->psr.lock); 2622 break; 2623 } 2624 } 2625