1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <drm/drm_atomic_helper.h> 25 26 #include "display/intel_dp.h" 27 28 #include "i915_drv.h" 29 #include "intel_atomic.h" 30 #include "intel_display_types.h" 31 #include "intel_dp_aux.h" 32 #include "intel_hdmi.h" 33 #include "intel_psr.h" 34 #include "intel_sprite.h" 35 36 /** 37 * DOC: Panel Self Refresh (PSR/SRD) 38 * 39 * Since Haswell Display controller supports Panel Self-Refresh on display 40 * panels witch have a remote frame buffer (RFB) implemented according to PSR 41 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 42 * when system is idle but display is on as it eliminates display refresh 43 * request to DDR memory completely as long as the frame buffer for that 44 * display is unchanged. 45 * 46 * Panel Self Refresh must be supported by both Hardware (source) and 47 * Panel (sink). 48 * 49 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 50 * to power down the link and memory controller. For DSI panels the same idea 51 * is called "manual mode". 52 * 53 * The implementation uses the hardware-based PSR support which automatically 54 * enters/exits self-refresh mode. The hardware takes care of sending the 55 * required DP aux message and could even retrain the link (that part isn't 56 * enabled yet though). The hardware also keeps track of any frontbuffer 57 * changes to know when to exit self-refresh mode again. Unfortunately that 58 * part doesn't work too well, hence why the i915 PSR support uses the 59 * software frontbuffer tracking to make sure it doesn't miss a screen 60 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 61 * get called by the frontbuffer tracking code. Note that because of locking 62 * issues the self-refresh re-enable code is done from a work queue, which 63 * must be correctly synchronized/cancelled when shutting down the pipe." 64 * 65 * DC3CO (DC3 clock off) 66 * 67 * On top of PSR2, GEN12 adds a intermediate power savings state that turns 68 * clock off automatically during PSR2 idle state. 69 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep 70 * entry/exit allows the HW to enter a low-power state even when page flipping 71 * periodically (for instance a 30fps video playback scenario). 72 * 73 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), 74 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 75 * frames, if no other flip occurs and the function above is executed, DC3CO is 76 * disabled and PSR2 is configured to enter deep sleep, resetting again in case 77 * of another flip. 78 * Front buffer modifications do not trigger DC3CO activation on purpose as it 79 * would bring a lot of complexity and most of the moderns systems will only 80 * use page flips. 81 */ 82 83 static bool psr_global_enabled(struct drm_i915_private *i915) 84 { 85 switch (i915->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 86 case I915_PSR_DEBUG_DEFAULT: 87 return i915->params.enable_psr; 88 case I915_PSR_DEBUG_DISABLE: 89 return false; 90 default: 91 return true; 92 } 93 } 94 95 static bool psr2_global_enabled(struct drm_i915_private *dev_priv) 96 { 97 switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 98 case I915_PSR_DEBUG_DISABLE: 99 case I915_PSR_DEBUG_FORCE_PSR1: 100 return false; 101 default: 102 return true; 103 } 104 } 105 106 static void psr_irq_control(struct drm_i915_private *dev_priv) 107 { 108 enum transcoder trans_shift; 109 u32 mask, val; 110 i915_reg_t imr_reg; 111 112 /* 113 * gen12+ has registers relative to transcoder and one per transcoder 114 * using the same bit definition: handle it as TRANSCODER_EDP to force 115 * 0 shift in bit definition 116 */ 117 if (INTEL_GEN(dev_priv) >= 12) { 118 trans_shift = 0; 119 imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder); 120 } else { 121 trans_shift = dev_priv->psr.transcoder; 122 imr_reg = EDP_PSR_IMR; 123 } 124 125 mask = EDP_PSR_ERROR(trans_shift); 126 if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ) 127 mask |= EDP_PSR_POST_EXIT(trans_shift) | 128 EDP_PSR_PRE_ENTRY(trans_shift); 129 130 /* Warning: it is masking/setting reserved bits too */ 131 val = intel_de_read(dev_priv, imr_reg); 132 val &= ~EDP_PSR_TRANS_MASK(trans_shift); 133 val |= ~mask; 134 intel_de_write(dev_priv, imr_reg, val); 135 } 136 137 static void psr_event_print(struct drm_i915_private *i915, 138 u32 val, bool psr2_enabled) 139 { 140 drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val); 141 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 142 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n"); 143 if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) 144 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n"); 145 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 146 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n"); 147 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 148 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n"); 149 if (val & PSR_EVENT_GRAPHICS_RESET) 150 drm_dbg_kms(&i915->drm, "\tGraphics reset\n"); 151 if (val & PSR_EVENT_PCH_INTERRUPT) 152 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n"); 153 if (val & PSR_EVENT_MEMORY_UP) 154 drm_dbg_kms(&i915->drm, "\tMemory up\n"); 155 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 156 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n"); 157 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 158 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n"); 159 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 160 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n"); 161 if (val & PSR_EVENT_REGISTER_UPDATE) 162 drm_dbg_kms(&i915->drm, "\tRegister updated\n"); 163 if (val & PSR_EVENT_HDCP_ENABLE) 164 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n"); 165 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 166 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n"); 167 if (val & PSR_EVENT_VBI_ENABLE) 168 drm_dbg_kms(&i915->drm, "\tVBI enabled\n"); 169 if (val & PSR_EVENT_LPSP_MODE_EXIT) 170 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n"); 171 if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) 172 drm_dbg_kms(&i915->drm, "\tPSR disabled\n"); 173 } 174 175 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) 176 { 177 enum transcoder cpu_transcoder = dev_priv->psr.transcoder; 178 enum transcoder trans_shift; 179 i915_reg_t imr_reg; 180 ktime_t time_ns = ktime_get(); 181 182 if (INTEL_GEN(dev_priv) >= 12) { 183 trans_shift = 0; 184 imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder); 185 } else { 186 trans_shift = dev_priv->psr.transcoder; 187 imr_reg = EDP_PSR_IMR; 188 } 189 190 if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) { 191 dev_priv->psr.last_entry_attempt = time_ns; 192 drm_dbg_kms(&dev_priv->drm, 193 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 194 transcoder_name(cpu_transcoder)); 195 } 196 197 if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) { 198 dev_priv->psr.last_exit = time_ns; 199 drm_dbg_kms(&dev_priv->drm, 200 "[transcoder %s] PSR exit completed\n", 201 transcoder_name(cpu_transcoder)); 202 203 if (INTEL_GEN(dev_priv) >= 9) { 204 u32 val = intel_de_read(dev_priv, 205 PSR_EVENT(cpu_transcoder)); 206 bool psr2_enabled = dev_priv->psr.psr2_enabled; 207 208 intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder), 209 val); 210 psr_event_print(dev_priv, val, psr2_enabled); 211 } 212 } 213 214 if (psr_iir & EDP_PSR_ERROR(trans_shift)) { 215 u32 val; 216 217 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", 218 transcoder_name(cpu_transcoder)); 219 220 dev_priv->psr.irq_aux_error = true; 221 222 /* 223 * If this interruption is not masked it will keep 224 * interrupting so fast that it prevents the scheduled 225 * work to run. 226 * Also after a PSR error, we don't want to arm PSR 227 * again so we don't care about unmask the interruption 228 * or unset irq_aux_error. 229 */ 230 val = intel_de_read(dev_priv, imr_reg); 231 val |= EDP_PSR_ERROR(trans_shift); 232 intel_de_write(dev_priv, imr_reg, val); 233 234 schedule_work(&dev_priv->psr.work); 235 } 236 } 237 238 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) 239 { 240 u8 alpm_caps = 0; 241 242 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, 243 &alpm_caps) != 1) 244 return false; 245 return alpm_caps & DP_ALPM_CAP; 246 } 247 248 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 249 { 250 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 251 u8 val = 8; /* assume the worst if we can't read the value */ 252 253 if (drm_dp_dpcd_readb(&intel_dp->aux, 254 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 255 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 256 else 257 drm_dbg_kms(&i915->drm, 258 "Unable to get sink synchronization latency, assuming 8 frames\n"); 259 return val; 260 } 261 262 static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp) 263 { 264 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 265 u16 val; 266 ssize_t r; 267 268 /* 269 * Returning the default X granularity if granularity not required or 270 * if DPCD read fails 271 */ 272 if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) 273 return 4; 274 275 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &val, 2); 276 if (r != 2) 277 drm_dbg_kms(&i915->drm, 278 "Unable to read DP_PSR2_SU_X_GRANULARITY\n"); 279 280 /* 281 * Spec says that if the value read is 0 the default granularity should 282 * be used instead. 283 */ 284 if (r != 2 || val == 0) 285 val = 4; 286 287 return val; 288 } 289 290 void intel_psr_init_dpcd(struct intel_dp *intel_dp) 291 { 292 struct drm_i915_private *dev_priv = 293 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 294 295 if (dev_priv->psr.dp) { 296 drm_warn(&dev_priv->drm, 297 "More than one eDP panel found, PSR support should be extended\n"); 298 return; 299 } 300 301 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, 302 sizeof(intel_dp->psr_dpcd)); 303 304 if (!intel_dp->psr_dpcd[0]) 305 return; 306 drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n", 307 intel_dp->psr_dpcd[0]); 308 309 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { 310 drm_dbg_kms(&dev_priv->drm, 311 "PSR support not currently available for this panel\n"); 312 return; 313 } 314 315 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 316 drm_dbg_kms(&dev_priv->drm, 317 "Panel lacks power state control, PSR cannot be enabled\n"); 318 return; 319 } 320 321 dev_priv->psr.sink_support = true; 322 dev_priv->psr.sink_sync_latency = 323 intel_dp_get_sink_sync_latency(intel_dp); 324 325 dev_priv->psr.dp = intel_dp; 326 327 if (INTEL_GEN(dev_priv) >= 9 && 328 (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { 329 bool y_req = intel_dp->psr_dpcd[1] & 330 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 331 bool alpm = intel_dp_get_alpm_status(intel_dp); 332 333 /* 334 * All panels that supports PSR version 03h (PSR2 + 335 * Y-coordinate) can handle Y-coordinates in VSC but we are 336 * only sure that it is going to be used when required by the 337 * panel. This way panel is capable to do selective update 338 * without a aux frame sync. 339 * 340 * To support PSR version 02h and PSR version 03h without 341 * Y-coordinate requirement panels we would need to enable 342 * GTC first. 343 */ 344 dev_priv->psr.sink_psr2_support = y_req && alpm; 345 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n", 346 dev_priv->psr.sink_psr2_support ? "" : "not "); 347 348 if (dev_priv->psr.sink_psr2_support) { 349 dev_priv->psr.colorimetry_support = 350 intel_dp_get_colorimetry_status(intel_dp); 351 dev_priv->psr.su_x_granularity = 352 intel_dp_get_su_x_granulartiy(intel_dp); 353 } 354 } 355 } 356 357 static void hsw_psr_setup_aux(struct intel_dp *intel_dp) 358 { 359 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 360 u32 aux_clock_divider, aux_ctl; 361 int i; 362 static const u8 aux_msg[] = { 363 [0] = DP_AUX_NATIVE_WRITE << 4, 364 [1] = DP_SET_POWER >> 8, 365 [2] = DP_SET_POWER & 0xff, 366 [3] = 1 - 1, 367 [4] = DP_SET_POWER_D0, 368 }; 369 u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK | 370 EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | 371 EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | 372 EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; 373 374 BUILD_BUG_ON(sizeof(aux_msg) > 20); 375 for (i = 0; i < sizeof(aux_msg); i += 4) 376 intel_de_write(dev_priv, 377 EDP_PSR_AUX_DATA(dev_priv->psr.transcoder, i >> 2), 378 intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); 379 380 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 381 382 /* Start with bits set for DDI_AUX_CTL register */ 383 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), 384 aux_clock_divider); 385 386 /* Select only valid bits for SRD_AUX_CTL */ 387 aux_ctl &= psr_aux_mask; 388 intel_de_write(dev_priv, EDP_PSR_AUX_CTL(dev_priv->psr.transcoder), 389 aux_ctl); 390 } 391 392 static void intel_psr_enable_sink(struct intel_dp *intel_dp) 393 { 394 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 395 u8 dpcd_val = DP_PSR_ENABLE; 396 397 /* Enable ALPM at sink for psr2 */ 398 if (dev_priv->psr.psr2_enabled) { 399 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 400 DP_ALPM_ENABLE | 401 DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); 402 403 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 404 } else { 405 if (dev_priv->psr.link_standby) 406 dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; 407 408 if (INTEL_GEN(dev_priv) >= 8) 409 dpcd_val |= DP_PSR_CRC_VERIFICATION; 410 } 411 412 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); 413 414 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 415 } 416 417 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 418 { 419 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 420 u32 val = 0; 421 422 if (INTEL_GEN(dev_priv) >= 11) 423 val |= EDP_PSR_TP4_TIME_0US; 424 425 if (dev_priv->params.psr_safest_params) { 426 val |= EDP_PSR_TP1_TIME_2500us; 427 val |= EDP_PSR_TP2_TP3_TIME_2500us; 428 goto check_tp3_sel; 429 } 430 431 if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) 432 val |= EDP_PSR_TP1_TIME_0us; 433 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100) 434 val |= EDP_PSR_TP1_TIME_100us; 435 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500) 436 val |= EDP_PSR_TP1_TIME_500us; 437 else 438 val |= EDP_PSR_TP1_TIME_2500us; 439 440 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0) 441 val |= EDP_PSR_TP2_TP3_TIME_0us; 442 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) 443 val |= EDP_PSR_TP2_TP3_TIME_100us; 444 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) 445 val |= EDP_PSR_TP2_TP3_TIME_500us; 446 else 447 val |= EDP_PSR_TP2_TP3_TIME_2500us; 448 449 check_tp3_sel: 450 if (intel_dp_source_supports_hbr2(intel_dp) && 451 drm_dp_tps3_supported(intel_dp->dpcd)) 452 val |= EDP_PSR_TP1_TP3_SEL; 453 else 454 val |= EDP_PSR_TP1_TP2_SEL; 455 456 return val; 457 } 458 459 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 460 { 461 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 462 int idle_frames; 463 464 /* Let's use 6 as the minimum to cover all known cases including the 465 * off-by-one issue that HW has in some cases. 466 */ 467 idle_frames = max(6, dev_priv->vbt.psr.idle_frames); 468 idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); 469 470 if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf)) 471 idle_frames = 0xf; 472 473 return idle_frames; 474 } 475 476 static void hsw_activate_psr1(struct intel_dp *intel_dp) 477 { 478 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 479 u32 max_sleep_time = 0x1f; 480 u32 val = EDP_PSR_ENABLE; 481 482 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT; 483 484 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; 485 if (IS_HASWELL(dev_priv)) 486 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 487 488 if (dev_priv->psr.link_standby) 489 val |= EDP_PSR_LINK_STANDBY; 490 491 val |= intel_psr1_get_tp_time(intel_dp); 492 493 if (INTEL_GEN(dev_priv) >= 8) 494 val |= EDP_PSR_CRC_ENABLE; 495 496 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) & 497 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK); 498 intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), val); 499 } 500 501 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 502 { 503 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 504 u32 val = 0; 505 506 if (dev_priv->params.psr_safest_params) 507 return EDP_PSR2_TP2_TIME_2500us; 508 509 if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 510 dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 511 val |= EDP_PSR2_TP2_TIME_50us; 512 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 513 val |= EDP_PSR2_TP2_TIME_100us; 514 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 515 val |= EDP_PSR2_TP2_TIME_500us; 516 else 517 val |= EDP_PSR2_TP2_TIME_2500us; 518 519 return val; 520 } 521 522 static void hsw_activate_psr2(struct intel_dp *intel_dp) 523 { 524 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 525 u32 val; 526 527 val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT; 528 529 val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; 530 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 531 val |= EDP_Y_COORDINATE_ENABLE; 532 533 val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); 534 val |= intel_psr2_get_tp_time(intel_dp); 535 536 if (INTEL_GEN(dev_priv) >= 12) { 537 /* 538 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default 539 * values from BSpec. In order to setting an optimal power 540 * consumption, lower than 4k resoluition mode needs to decrese 541 * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution 542 * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE. 543 */ 544 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 545 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7); 546 val |= TGL_EDP_PSR2_FAST_WAKE(7); 547 } else if (INTEL_GEN(dev_priv) >= 9) { 548 val |= EDP_PSR2_IO_BUFFER_WAKE(7); 549 val |= EDP_PSR2_FAST_WAKE(7); 550 } 551 552 if (dev_priv->psr.psr2_sel_fetch_enabled) { 553 /* WA 1408330847 */ 554 if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) || 555 IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)) 556 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 557 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 558 DIS_RAM_BYPASS_PSR2_MAN_TRACK); 559 560 intel_de_write(dev_priv, 561 PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), 562 PSR2_MAN_TRK_CTL_ENABLE); 563 } else if (HAS_PSR2_SEL_FETCH(dev_priv)) { 564 intel_de_write(dev_priv, 565 PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), 0); 566 } 567 568 /* 569 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 570 * recommending keep this bit unset while PSR2 is enabled. 571 */ 572 intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), 0); 573 574 intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder), val); 575 } 576 577 static bool 578 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) 579 { 580 if (INTEL_GEN(dev_priv) < 9) 581 return false; 582 else if (INTEL_GEN(dev_priv) >= 12) 583 return trans == TRANSCODER_A; 584 else 585 return trans == TRANSCODER_EDP; 586 } 587 588 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate) 589 { 590 if (!cstate || !cstate->hw.active) 591 return 0; 592 593 return DIV_ROUND_UP(1000 * 1000, 594 drm_mode_vrefresh(&cstate->hw.adjusted_mode)); 595 } 596 597 static void psr2_program_idle_frames(struct drm_i915_private *dev_priv, 598 u32 idle_frames) 599 { 600 u32 val; 601 602 idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; 603 val = intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)); 604 val &= ~EDP_PSR2_IDLE_FRAME_MASK; 605 val |= idle_frames; 606 intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder), val); 607 } 608 609 static void tgl_psr2_enable_dc3co(struct drm_i915_private *dev_priv) 610 { 611 psr2_program_idle_frames(dev_priv, 0); 612 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO); 613 } 614 615 static void tgl_psr2_disable_dc3co(struct drm_i915_private *dev_priv) 616 { 617 struct intel_dp *intel_dp = dev_priv->psr.dp; 618 619 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 620 psr2_program_idle_frames(dev_priv, psr_compute_idle_frames(intel_dp)); 621 } 622 623 static void tgl_dc3co_disable_work(struct work_struct *work) 624 { 625 struct drm_i915_private *dev_priv = 626 container_of(work, typeof(*dev_priv), psr.dc3co_work.work); 627 628 mutex_lock(&dev_priv->psr.lock); 629 /* If delayed work is pending, it is not idle */ 630 if (delayed_work_pending(&dev_priv->psr.dc3co_work)) 631 goto unlock; 632 633 tgl_psr2_disable_dc3co(dev_priv); 634 unlock: 635 mutex_unlock(&dev_priv->psr.lock); 636 } 637 638 static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv) 639 { 640 if (!dev_priv->psr.dc3co_enabled) 641 return; 642 643 cancel_delayed_work(&dev_priv->psr.dc3co_work); 644 /* Before PSR2 exit disallow dc3co*/ 645 tgl_psr2_disable_dc3co(dev_priv); 646 } 647 648 static void 649 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 650 struct intel_crtc_state *crtc_state) 651 { 652 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; 653 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 654 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 655 u32 exit_scanlines; 656 657 if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)) 658 return; 659 660 /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/ 661 if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A || 662 dig_port->base.port != PORT_A) 663 return; 664 665 /* 666 * DC3CO Exit time 200us B.Spec 49196 667 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 668 */ 669 exit_scanlines = 670 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; 671 672 if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay)) 673 return; 674 675 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; 676 } 677 678 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, 679 struct intel_crtc_state *crtc_state) 680 { 681 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 682 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 683 struct intel_plane_state *plane_state; 684 struct intel_plane *plane; 685 int i; 686 687 if (!dev_priv->params.enable_psr2_sel_fetch) { 688 drm_dbg_kms(&dev_priv->drm, 689 "PSR2 sel fetch not enabled, disabled by parameter\n"); 690 return false; 691 } 692 693 if (crtc_state->uapi.async_flip) { 694 drm_dbg_kms(&dev_priv->drm, 695 "PSR2 sel fetch not enabled, async flip enabled\n"); 696 return false; 697 } 698 699 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 700 if (plane_state->uapi.rotation != DRM_MODE_ROTATE_0) { 701 drm_dbg_kms(&dev_priv->drm, 702 "PSR2 sel fetch not enabled, plane rotated\n"); 703 return false; 704 } 705 } 706 707 return crtc_state->enable_psr2_sel_fetch = true; 708 } 709 710 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 711 struct intel_crtc_state *crtc_state) 712 { 713 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 714 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 715 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 716 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 717 718 if (!dev_priv->psr.sink_psr2_support) 719 return false; 720 721 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { 722 drm_dbg_kms(&dev_priv->drm, 723 "PSR2 not supported in transcoder %s\n", 724 transcoder_name(crtc_state->cpu_transcoder)); 725 return false; 726 } 727 728 if (!psr2_global_enabled(dev_priv)) { 729 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); 730 return false; 731 } 732 733 /* 734 * DSC and PSR2 cannot be enabled simultaneously. If a requested 735 * resolution requires DSC to be enabled, priority is given to DSC 736 * over PSR2. 737 */ 738 if (crtc_state->dsc.compression_enable) { 739 drm_dbg_kms(&dev_priv->drm, 740 "PSR2 cannot be enabled since DSC is enabled\n"); 741 return false; 742 } 743 744 if (crtc_state->crc_enabled) { 745 drm_dbg_kms(&dev_priv->drm, 746 "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); 747 return false; 748 } 749 750 if (INTEL_GEN(dev_priv) >= 12) { 751 psr_max_h = 5120; 752 psr_max_v = 3200; 753 max_bpp = 30; 754 } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { 755 psr_max_h = 4096; 756 psr_max_v = 2304; 757 max_bpp = 24; 758 } else if (IS_GEN(dev_priv, 9)) { 759 psr_max_h = 3640; 760 psr_max_v = 2304; 761 max_bpp = 24; 762 } 763 764 if (crtc_state->pipe_bpp > max_bpp) { 765 drm_dbg_kms(&dev_priv->drm, 766 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 767 crtc_state->pipe_bpp, max_bpp); 768 return false; 769 } 770 771 /* 772 * HW sends SU blocks of size four scan lines, which means the starting 773 * X coordinate and Y granularity requirements will always be met. We 774 * only need to validate the SU block width is a multiple of 775 * x granularity. 776 */ 777 if (crtc_hdisplay % dev_priv->psr.su_x_granularity) { 778 drm_dbg_kms(&dev_priv->drm, 779 "PSR2 not enabled, hdisplay(%d) not multiple of %d\n", 780 crtc_hdisplay, dev_priv->psr.su_x_granularity); 781 return false; 782 } 783 784 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 785 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && 786 !HAS_PSR_HW_TRACKING(dev_priv)) { 787 drm_dbg_kms(&dev_priv->drm, 788 "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); 789 return false; 790 } 791 } 792 793 if (!crtc_state->enable_psr2_sel_fetch && 794 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { 795 drm_dbg_kms(&dev_priv->drm, 796 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 797 crtc_hdisplay, crtc_vdisplay, 798 psr_max_h, psr_max_v); 799 return false; 800 } 801 802 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); 803 return true; 804 } 805 806 void intel_psr_compute_config(struct intel_dp *intel_dp, 807 struct intel_crtc_state *crtc_state) 808 { 809 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 810 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 811 const struct drm_display_mode *adjusted_mode = 812 &crtc_state->hw.adjusted_mode; 813 int psr_setup_time; 814 815 /* 816 * Current PSR panels dont work reliably with VRR enabled 817 * So if VRR is enabled, do not enable PSR. 818 */ 819 if (crtc_state->vrr.enable) 820 return; 821 822 if (!CAN_PSR(dev_priv)) 823 return; 824 825 if (intel_dp != dev_priv->psr.dp) 826 return; 827 828 if (!psr_global_enabled(dev_priv)) { 829 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); 830 return; 831 } 832 833 /* 834 * HSW spec explicitly says PSR is tied to port A. 835 * BDW+ platforms have a instance of PSR registers per transcoder but 836 * for now it only supports one instance of PSR, so lets keep it 837 * hardcoded to PORT_A 838 */ 839 if (dig_port->base.port != PORT_A) { 840 drm_dbg_kms(&dev_priv->drm, 841 "PSR condition failed: Port not supported\n"); 842 return; 843 } 844 845 if (dev_priv->psr.sink_not_reliable) { 846 drm_dbg_kms(&dev_priv->drm, 847 "PSR sink implementation is not reliable\n"); 848 return; 849 } 850 851 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 852 drm_dbg_kms(&dev_priv->drm, 853 "PSR condition failed: Interlaced mode enabled\n"); 854 return; 855 } 856 857 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); 858 if (psr_setup_time < 0) { 859 drm_dbg_kms(&dev_priv->drm, 860 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 861 intel_dp->psr_dpcd[1]); 862 return; 863 } 864 865 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 866 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 867 drm_dbg_kms(&dev_priv->drm, 868 "PSR condition failed: PSR setup time (%d us) too long\n", 869 psr_setup_time); 870 return; 871 } 872 873 crtc_state->has_psr = true; 874 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); 875 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 876 } 877 878 static void intel_psr_activate(struct intel_dp *intel_dp) 879 { 880 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 881 882 if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) 883 drm_WARN_ON(&dev_priv->drm, 884 intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE); 885 886 drm_WARN_ON(&dev_priv->drm, 887 intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE); 888 drm_WARN_ON(&dev_priv->drm, dev_priv->psr.active); 889 lockdep_assert_held(&dev_priv->psr.lock); 890 891 /* psr1 and psr2 are mutually exclusive.*/ 892 if (dev_priv->psr.psr2_enabled) 893 hsw_activate_psr2(intel_dp); 894 else 895 hsw_activate_psr1(intel_dp); 896 897 dev_priv->psr.active = true; 898 } 899 900 static void intel_psr_enable_source(struct intel_dp *intel_dp, 901 const struct intel_crtc_state *crtc_state) 902 { 903 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 904 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 905 u32 mask; 906 907 /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+ 908 * use hardcoded values PSR AUX transactions 909 */ 910 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 911 hsw_psr_setup_aux(intel_dp); 912 913 if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) && 914 !IS_GEMINILAKE(dev_priv))) { 915 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder); 916 u32 chicken = intel_de_read(dev_priv, reg); 917 918 chicken |= PSR2_VSC_ENABLE_PROG_HEADER | 919 PSR2_ADD_VERTICAL_LINE_COUNT; 920 intel_de_write(dev_priv, reg, chicken); 921 } 922 923 /* 924 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 925 * mask LPSP to avoid dependency on other drivers that might block 926 * runtime_pm besides preventing other hw tracking issues now we 927 * can rely on frontbuffer tracking. 928 */ 929 mask = EDP_PSR_DEBUG_MASK_MEMUP | 930 EDP_PSR_DEBUG_MASK_HPD | 931 EDP_PSR_DEBUG_MASK_LPSP | 932 EDP_PSR_DEBUG_MASK_MAX_SLEEP; 933 934 if (INTEL_GEN(dev_priv) < 11) 935 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 936 937 intel_de_write(dev_priv, EDP_PSR_DEBUG(dev_priv->psr.transcoder), 938 mask); 939 940 psr_irq_control(dev_priv); 941 942 if (crtc_state->dc3co_exitline) { 943 u32 val; 944 945 /* 946 * TODO: if future platforms supports DC3CO in more than one 947 * transcoder, EXITLINE will need to be unset when disabling PSR 948 */ 949 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder)); 950 val &= ~EXITLINE_MASK; 951 val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT; 952 val |= EXITLINE_ENABLE; 953 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); 954 } 955 956 if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv)) 957 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, 958 dev_priv->psr.psr2_sel_fetch_enabled ? 959 IGNORE_PSR2_HW_TRACKING : 0); 960 } 961 962 static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, 963 const struct intel_crtc_state *crtc_state, 964 const struct drm_connector_state *conn_state) 965 { 966 struct intel_dp *intel_dp = dev_priv->psr.dp; 967 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 968 struct intel_encoder *encoder = &dig_port->base; 969 u32 val; 970 971 drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled); 972 973 dev_priv->psr.psr2_enabled = crtc_state->has_psr2; 974 dev_priv->psr.busy_frontbuffer_bits = 0; 975 dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 976 dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline; 977 dev_priv->psr.transcoder = crtc_state->cpu_transcoder; 978 /* DC5/DC6 requires at least 6 idle frames */ 979 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 980 dev_priv->psr.dc3co_exit_delay = val; 981 dev_priv->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; 982 983 /* 984 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 985 * will still keep the error set even after the reset done in the 986 * irq_preinstall and irq_uninstall hooks. 987 * And enabling in this situation cause the screen to freeze in the 988 * first time that PSR HW tries to activate so lets keep PSR disabled 989 * to avoid any rendering problems. 990 */ 991 if (INTEL_GEN(dev_priv) >= 12) { 992 val = intel_de_read(dev_priv, 993 TRANS_PSR_IIR(dev_priv->psr.transcoder)); 994 val &= EDP_PSR_ERROR(0); 995 } else { 996 val = intel_de_read(dev_priv, EDP_PSR_IIR); 997 val &= EDP_PSR_ERROR(dev_priv->psr.transcoder); 998 } 999 if (val) { 1000 dev_priv->psr.sink_not_reliable = true; 1001 drm_dbg_kms(&dev_priv->drm, 1002 "PSR interruption error set, not enabling PSR\n"); 1003 return; 1004 } 1005 1006 drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", 1007 dev_priv->psr.psr2_enabled ? "2" : "1"); 1008 intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, 1009 &dev_priv->psr.vsc); 1010 intel_write_dp_vsc_sdp(encoder, crtc_state, &dev_priv->psr.vsc); 1011 intel_psr_enable_sink(intel_dp); 1012 intel_psr_enable_source(intel_dp, crtc_state); 1013 dev_priv->psr.enabled = true; 1014 1015 intel_psr_activate(intel_dp); 1016 } 1017 1018 /** 1019 * intel_psr_enable - Enable PSR 1020 * @intel_dp: Intel DP 1021 * @crtc_state: new CRTC state 1022 * @conn_state: new CONNECTOR state 1023 * 1024 * This function can only be called after the pipe is fully trained and enabled. 1025 */ 1026 void intel_psr_enable(struct intel_dp *intel_dp, 1027 const struct intel_crtc_state *crtc_state, 1028 const struct drm_connector_state *conn_state) 1029 { 1030 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1031 1032 if (!CAN_PSR(dev_priv) || dev_priv->psr.dp != intel_dp) 1033 return; 1034 1035 if (!crtc_state->has_psr) 1036 return; 1037 1038 drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp); 1039 1040 mutex_lock(&dev_priv->psr.lock); 1041 intel_psr_enable_locked(dev_priv, crtc_state, conn_state); 1042 mutex_unlock(&dev_priv->psr.lock); 1043 } 1044 1045 static void intel_psr_exit(struct drm_i915_private *dev_priv) 1046 { 1047 u32 val; 1048 1049 if (!dev_priv->psr.active) { 1050 if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) { 1051 val = intel_de_read(dev_priv, 1052 EDP_PSR2_CTL(dev_priv->psr.transcoder)); 1053 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE); 1054 } 1055 1056 val = intel_de_read(dev_priv, 1057 EDP_PSR_CTL(dev_priv->psr.transcoder)); 1058 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE); 1059 1060 return; 1061 } 1062 1063 if (dev_priv->psr.psr2_enabled) { 1064 tgl_disallow_dc3co_on_psr2_exit(dev_priv); 1065 val = intel_de_read(dev_priv, 1066 EDP_PSR2_CTL(dev_priv->psr.transcoder)); 1067 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE)); 1068 val &= ~EDP_PSR2_ENABLE; 1069 intel_de_write(dev_priv, 1070 EDP_PSR2_CTL(dev_priv->psr.transcoder), val); 1071 } else { 1072 val = intel_de_read(dev_priv, 1073 EDP_PSR_CTL(dev_priv->psr.transcoder)); 1074 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE)); 1075 val &= ~EDP_PSR_ENABLE; 1076 intel_de_write(dev_priv, 1077 EDP_PSR_CTL(dev_priv->psr.transcoder), val); 1078 } 1079 dev_priv->psr.active = false; 1080 } 1081 1082 static void intel_psr_disable_locked(struct intel_dp *intel_dp) 1083 { 1084 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1085 i915_reg_t psr_status; 1086 u32 psr_status_mask; 1087 1088 lockdep_assert_held(&dev_priv->psr.lock); 1089 1090 if (!dev_priv->psr.enabled) 1091 return; 1092 1093 drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", 1094 dev_priv->psr.psr2_enabled ? "2" : "1"); 1095 1096 intel_psr_exit(dev_priv); 1097 1098 if (dev_priv->psr.psr2_enabled) { 1099 psr_status = EDP_PSR2_STATUS(dev_priv->psr.transcoder); 1100 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 1101 } else { 1102 psr_status = EDP_PSR_STATUS(dev_priv->psr.transcoder); 1103 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 1104 } 1105 1106 /* Wait till PSR is idle */ 1107 if (intel_de_wait_for_clear(dev_priv, psr_status, 1108 psr_status_mask, 2000)) 1109 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n"); 1110 1111 /* WA 1408330847 */ 1112 if (dev_priv->psr.psr2_sel_fetch_enabled && 1113 (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) || 1114 IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))) 1115 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1116 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0); 1117 1118 /* Disable PSR on Sink */ 1119 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 1120 1121 if (dev_priv->psr.psr2_enabled) 1122 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); 1123 1124 dev_priv->psr.enabled = false; 1125 } 1126 1127 /** 1128 * intel_psr_disable - Disable PSR 1129 * @intel_dp: Intel DP 1130 * @old_crtc_state: old CRTC state 1131 * 1132 * This function needs to be called before disabling pipe. 1133 */ 1134 void intel_psr_disable(struct intel_dp *intel_dp, 1135 const struct intel_crtc_state *old_crtc_state) 1136 { 1137 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1138 1139 if (!old_crtc_state->has_psr) 1140 return; 1141 1142 if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(dev_priv))) 1143 return; 1144 1145 mutex_lock(&dev_priv->psr.lock); 1146 1147 intel_psr_disable_locked(intel_dp); 1148 1149 mutex_unlock(&dev_priv->psr.lock); 1150 cancel_work_sync(&dev_priv->psr.work); 1151 cancel_delayed_work_sync(&dev_priv->psr.dc3co_work); 1152 } 1153 1154 static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv) 1155 { 1156 if (IS_TIGERLAKE(dev_priv)) 1157 /* 1158 * Writes to CURSURFLIVE in TGL are causing IOMMU errors and 1159 * visual glitches that are often reproduced when executing 1160 * CPU intensive workloads while a eDP 4K panel is attached. 1161 * 1162 * Manually exiting PSR causes the frontbuffer to be updated 1163 * without glitches and the IOMMU errors are also gone but 1164 * this comes at the cost of less time with PSR active. 1165 * 1166 * So using this workaround until this issue is root caused 1167 * and a better fix is found. 1168 */ 1169 intel_psr_exit(dev_priv); 1170 else if (INTEL_GEN(dev_priv) >= 9) 1171 /* 1172 * Display WA #0884: skl+ 1173 * This documented WA for bxt can be safely applied 1174 * broadly so we can force HW tracking to exit PSR 1175 * instead of disabling and re-enabling. 1176 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 1177 * but it makes more sense write to the current active 1178 * pipe. 1179 */ 1180 intel_de_write(dev_priv, CURSURFLIVE(dev_priv->psr.pipe), 0); 1181 else 1182 /* 1183 * A write to CURSURFLIVE do not cause HW tracking to exit PSR 1184 * on older gens so doing the manual exit instead. 1185 */ 1186 intel_psr_exit(dev_priv); 1187 } 1188 1189 void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, 1190 const struct intel_crtc_state *crtc_state, 1191 const struct intel_plane_state *plane_state, 1192 int color_plane) 1193 { 1194 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1195 enum pipe pipe = plane->pipe; 1196 const struct drm_rect *clip; 1197 u32 val, offset; 1198 int ret, x, y; 1199 1200 if (!crtc_state->enable_psr2_sel_fetch) 1201 return; 1202 1203 val = plane_state ? plane_state->ctl : 0; 1204 val &= plane->id == PLANE_CURSOR ? val : PLANE_SEL_FETCH_CTL_ENABLE; 1205 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val); 1206 if (!val || plane->id == PLANE_CURSOR) 1207 return; 1208 1209 clip = &plane_state->psr2_sel_fetch_area; 1210 1211 val = (clip->y1 + plane_state->uapi.dst.y1) << 16; 1212 val |= plane_state->uapi.dst.x1; 1213 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); 1214 1215 /* TODO: consider auxiliary surfaces */ 1216 x = plane_state->uapi.src.x1 >> 16; 1217 y = (plane_state->uapi.src.y1 >> 16) + clip->y1; 1218 ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset); 1219 if (ret) 1220 drm_warn_once(&dev_priv->drm, "skl_calc_main_surface_offset() returned %i\n", 1221 ret); 1222 val = y << 16 | x; 1223 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), 1224 val); 1225 1226 /* Sizes are 0 based */ 1227 val = (drm_rect_height(clip) - 1) << 16; 1228 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; 1229 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); 1230 } 1231 1232 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) 1233 { 1234 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1235 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1236 struct i915_psr *psr = &dev_priv->psr; 1237 1238 if (!HAS_PSR2_SEL_FETCH(dev_priv) || 1239 !crtc_state->enable_psr2_sel_fetch) 1240 return; 1241 1242 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(psr->transcoder), 1243 crtc_state->psr2_man_track_ctl); 1244 } 1245 1246 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, 1247 struct drm_rect *clip, bool full_update) 1248 { 1249 u32 val = PSR2_MAN_TRK_CTL_ENABLE; 1250 1251 if (full_update) { 1252 val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 1253 goto exit; 1254 } 1255 1256 if (clip->y1 == -1) 1257 goto exit; 1258 1259 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4); 1260 1261 val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; 1262 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1); 1263 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1); 1264 exit: 1265 crtc_state->psr2_man_track_ctl = val; 1266 } 1267 1268 static void clip_area_update(struct drm_rect *overlap_damage_area, 1269 struct drm_rect *damage_area) 1270 { 1271 if (overlap_damage_area->y1 == -1) { 1272 overlap_damage_area->y1 = damage_area->y1; 1273 overlap_damage_area->y2 = damage_area->y2; 1274 return; 1275 } 1276 1277 if (damage_area->y1 < overlap_damage_area->y1) 1278 overlap_damage_area->y1 = damage_area->y1; 1279 1280 if (damage_area->y2 > overlap_damage_area->y2) 1281 overlap_damage_area->y2 = damage_area->y2; 1282 } 1283 1284 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 1285 struct intel_crtc *crtc) 1286 { 1287 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 1288 struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 }; 1289 struct intel_plane_state *new_plane_state, *old_plane_state; 1290 struct intel_plane *plane; 1291 bool full_update = false; 1292 int i, ret; 1293 1294 if (!crtc_state->enable_psr2_sel_fetch) 1295 return 0; 1296 1297 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 1298 if (ret) 1299 return ret; 1300 1301 /* 1302 * Calculate minimal selective fetch area of each plane and calculate 1303 * the pipe damaged area. 1304 * In the next loop the plane selective fetch area will actually be set 1305 * using whole pipe damaged area. 1306 */ 1307 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1308 new_plane_state, i) { 1309 struct drm_rect src, damaged_area = { .y1 = -1 }; 1310 struct drm_mode_rect *damaged_clips; 1311 u32 num_clips, j; 1312 1313 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) 1314 continue; 1315 1316 if (!new_plane_state->uapi.visible && 1317 !old_plane_state->uapi.visible) 1318 continue; 1319 1320 /* 1321 * TODO: Not clear how to handle planes with negative position, 1322 * also planes are not updated if they have a negative X 1323 * position so for now doing a full update in this cases 1324 */ 1325 if (new_plane_state->uapi.dst.y1 < 0 || 1326 new_plane_state->uapi.dst.x1 < 0) { 1327 full_update = true; 1328 break; 1329 } 1330 1331 num_clips = drm_plane_get_damage_clips_count(&new_plane_state->uapi); 1332 1333 /* 1334 * If visibility or plane moved, mark the whole plane area as 1335 * damaged as it needs to be complete redraw in the new and old 1336 * position. 1337 */ 1338 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || 1339 !drm_rect_equals(&new_plane_state->uapi.dst, 1340 &old_plane_state->uapi.dst)) { 1341 if (old_plane_state->uapi.visible) { 1342 damaged_area.y1 = old_plane_state->uapi.dst.y1; 1343 damaged_area.y2 = old_plane_state->uapi.dst.y2; 1344 clip_area_update(&pipe_clip, &damaged_area); 1345 } 1346 1347 if (new_plane_state->uapi.visible) { 1348 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1349 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1350 clip_area_update(&pipe_clip, &damaged_area); 1351 } 1352 continue; 1353 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha || 1354 (!num_clips && 1355 new_plane_state->uapi.fb != old_plane_state->uapi.fb)) { 1356 /* 1357 * If the plane don't have damaged areas but the 1358 * framebuffer changed or alpha changed, mark the whole 1359 * plane area as damaged. 1360 */ 1361 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1362 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1363 clip_area_update(&pipe_clip, &damaged_area); 1364 continue; 1365 } 1366 1367 drm_rect_fp_to_int(&src, &new_plane_state->uapi.src); 1368 damaged_clips = drm_plane_get_damage_clips(&new_plane_state->uapi); 1369 1370 for (j = 0; j < num_clips; j++) { 1371 struct drm_rect clip; 1372 1373 clip.x1 = damaged_clips[j].x1; 1374 clip.y1 = damaged_clips[j].y1; 1375 clip.x2 = damaged_clips[j].x2; 1376 clip.y2 = damaged_clips[j].y2; 1377 if (drm_rect_intersect(&clip, &src)) 1378 clip_area_update(&damaged_area, &clip); 1379 } 1380 1381 if (damaged_area.y1 == -1) 1382 continue; 1383 1384 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; 1385 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; 1386 clip_area_update(&pipe_clip, &damaged_area); 1387 } 1388 1389 if (full_update) 1390 goto skip_sel_fetch_set_loop; 1391 1392 /* It must be aligned to 4 lines */ 1393 pipe_clip.y1 -= pipe_clip.y1 % 4; 1394 if (pipe_clip.y2 % 4) 1395 pipe_clip.y2 = ((pipe_clip.y2 / 4) + 1) * 4; 1396 1397 /* 1398 * Now that we have the pipe damaged area check if it intersect with 1399 * every plane, if it does set the plane selective fetch area. 1400 */ 1401 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1402 new_plane_state, i) { 1403 struct drm_rect *sel_fetch_area, inter; 1404 1405 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || 1406 !new_plane_state->uapi.visible) 1407 continue; 1408 1409 inter = pipe_clip; 1410 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) 1411 continue; 1412 1413 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 1414 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; 1415 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; 1416 } 1417 1418 skip_sel_fetch_set_loop: 1419 psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update); 1420 return 0; 1421 } 1422 1423 /** 1424 * intel_psr_update - Update PSR state 1425 * @intel_dp: Intel DP 1426 * @crtc_state: new CRTC state 1427 * @conn_state: new CONNECTOR state 1428 * 1429 * This functions will update PSR states, disabling, enabling or switching PSR 1430 * version when executing fastsets. For full modeset, intel_psr_disable() and 1431 * intel_psr_enable() should be called instead. 1432 */ 1433 void intel_psr_update(struct intel_dp *intel_dp, 1434 const struct intel_crtc_state *crtc_state, 1435 const struct drm_connector_state *conn_state) 1436 { 1437 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1438 struct i915_psr *psr = &dev_priv->psr; 1439 bool enable, psr2_enable; 1440 1441 if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp) 1442 return; 1443 1444 mutex_lock(&dev_priv->psr.lock); 1445 1446 enable = crtc_state->has_psr; 1447 psr2_enable = crtc_state->has_psr2; 1448 1449 if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) { 1450 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 1451 if (crtc_state->crc_enabled && psr->enabled) 1452 psr_force_hw_tracking_exit(dev_priv); 1453 else if (INTEL_GEN(dev_priv) < 9 && psr->enabled) { 1454 /* 1455 * Activate PSR again after a force exit when enabling 1456 * CRC in older gens 1457 */ 1458 if (!dev_priv->psr.active && 1459 !dev_priv->psr.busy_frontbuffer_bits) 1460 schedule_work(&dev_priv->psr.work); 1461 } 1462 1463 goto unlock; 1464 } 1465 1466 if (psr->enabled) 1467 intel_psr_disable_locked(intel_dp); 1468 1469 if (enable) 1470 intel_psr_enable_locked(dev_priv, crtc_state, conn_state); 1471 1472 unlock: 1473 mutex_unlock(&dev_priv->psr.lock); 1474 } 1475 1476 /** 1477 * intel_psr_wait_for_idle - wait for PSR1 to idle 1478 * @new_crtc_state: new CRTC state 1479 * @out_value: PSR status in case of failure 1480 * 1481 * This function is expected to be called from pipe_update_start() where it is 1482 * not expected to race with PSR enable or disable. 1483 * 1484 * Returns: 0 on success or -ETIMEOUT if PSR status does not idle. 1485 */ 1486 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state, 1487 u32 *out_value) 1488 { 1489 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1490 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1491 1492 if (!dev_priv->psr.enabled || !new_crtc_state->has_psr) 1493 return 0; 1494 1495 /* FIXME: Update this for PSR2 if we need to wait for idle */ 1496 if (READ_ONCE(dev_priv->psr.psr2_enabled)) 1497 return 0; 1498 1499 /* 1500 * From bspec: Panel Self Refresh (BDW+) 1501 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 1502 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 1503 * defensive enough to cover everything. 1504 */ 1505 1506 return __intel_wait_for_register(&dev_priv->uncore, 1507 EDP_PSR_STATUS(dev_priv->psr.transcoder), 1508 EDP_PSR_STATUS_STATE_MASK, 1509 EDP_PSR_STATUS_STATE_IDLE, 2, 50, 1510 out_value); 1511 } 1512 1513 static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv) 1514 { 1515 i915_reg_t reg; 1516 u32 mask; 1517 int err; 1518 1519 if (!dev_priv->psr.enabled) 1520 return false; 1521 1522 if (dev_priv->psr.psr2_enabled) { 1523 reg = EDP_PSR2_STATUS(dev_priv->psr.transcoder); 1524 mask = EDP_PSR2_STATUS_STATE_MASK; 1525 } else { 1526 reg = EDP_PSR_STATUS(dev_priv->psr.transcoder); 1527 mask = EDP_PSR_STATUS_STATE_MASK; 1528 } 1529 1530 mutex_unlock(&dev_priv->psr.lock); 1531 1532 err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); 1533 if (err) 1534 drm_err(&dev_priv->drm, 1535 "Timed out waiting for PSR Idle for re-enable\n"); 1536 1537 /* After the unlocked wait, verify that PSR is still wanted! */ 1538 mutex_lock(&dev_priv->psr.lock); 1539 return err == 0 && dev_priv->psr.enabled; 1540 } 1541 1542 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) 1543 { 1544 struct drm_connector_list_iter conn_iter; 1545 struct drm_device *dev = &dev_priv->drm; 1546 struct drm_modeset_acquire_ctx ctx; 1547 struct drm_atomic_state *state; 1548 struct drm_connector *conn; 1549 int err = 0; 1550 1551 state = drm_atomic_state_alloc(dev); 1552 if (!state) 1553 return -ENOMEM; 1554 1555 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1556 state->acquire_ctx = &ctx; 1557 1558 retry: 1559 1560 drm_connector_list_iter_begin(dev, &conn_iter); 1561 drm_for_each_connector_iter(conn, &conn_iter) { 1562 struct drm_connector_state *conn_state; 1563 struct drm_crtc_state *crtc_state; 1564 1565 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) 1566 continue; 1567 1568 conn_state = drm_atomic_get_connector_state(state, conn); 1569 if (IS_ERR(conn_state)) { 1570 err = PTR_ERR(conn_state); 1571 break; 1572 } 1573 1574 if (!conn_state->crtc) 1575 continue; 1576 1577 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); 1578 if (IS_ERR(crtc_state)) { 1579 err = PTR_ERR(crtc_state); 1580 break; 1581 } 1582 1583 /* Mark mode as changed to trigger a pipe->update() */ 1584 crtc_state->mode_changed = true; 1585 } 1586 drm_connector_list_iter_end(&conn_iter); 1587 1588 if (err == 0) 1589 err = drm_atomic_commit(state); 1590 1591 if (err == -EDEADLK) { 1592 drm_atomic_state_clear(state); 1593 err = drm_modeset_backoff(&ctx); 1594 if (!err) 1595 goto retry; 1596 } 1597 1598 drm_modeset_drop_locks(&ctx); 1599 drm_modeset_acquire_fini(&ctx); 1600 drm_atomic_state_put(state); 1601 1602 return err; 1603 } 1604 1605 int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val) 1606 { 1607 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 1608 u32 old_mode; 1609 int ret; 1610 1611 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || 1612 mode > I915_PSR_DEBUG_FORCE_PSR1) { 1613 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); 1614 return -EINVAL; 1615 } 1616 1617 ret = mutex_lock_interruptible(&dev_priv->psr.lock); 1618 if (ret) 1619 return ret; 1620 1621 old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK; 1622 dev_priv->psr.debug = val; 1623 1624 /* 1625 * Do it right away if it's already enabled, otherwise it will be done 1626 * when enabling the source. 1627 */ 1628 if (dev_priv->psr.enabled) 1629 psr_irq_control(dev_priv); 1630 1631 mutex_unlock(&dev_priv->psr.lock); 1632 1633 if (old_mode != mode) 1634 ret = intel_psr_fastset_force(dev_priv); 1635 1636 return ret; 1637 } 1638 1639 static void intel_psr_handle_irq(struct drm_i915_private *dev_priv) 1640 { 1641 struct i915_psr *psr = &dev_priv->psr; 1642 1643 intel_psr_disable_locked(psr->dp); 1644 psr->sink_not_reliable = true; 1645 /* let's make sure that sink is awaken */ 1646 drm_dp_dpcd_writeb(&psr->dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 1647 } 1648 1649 static void intel_psr_work(struct work_struct *work) 1650 { 1651 struct drm_i915_private *dev_priv = 1652 container_of(work, typeof(*dev_priv), psr.work); 1653 1654 mutex_lock(&dev_priv->psr.lock); 1655 1656 if (!dev_priv->psr.enabled) 1657 goto unlock; 1658 1659 if (READ_ONCE(dev_priv->psr.irq_aux_error)) 1660 intel_psr_handle_irq(dev_priv); 1661 1662 /* 1663 * We have to make sure PSR is ready for re-enable 1664 * otherwise it keeps disabled until next full enable/disable cycle. 1665 * PSR might take some time to get fully disabled 1666 * and be ready for re-enable. 1667 */ 1668 if (!__psr_wait_for_idle_locked(dev_priv)) 1669 goto unlock; 1670 1671 /* 1672 * The delayed work can race with an invalidate hence we need to 1673 * recheck. Since psr_flush first clears this and then reschedules we 1674 * won't ever miss a flush when bailing out here. 1675 */ 1676 if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active) 1677 goto unlock; 1678 1679 intel_psr_activate(dev_priv->psr.dp); 1680 unlock: 1681 mutex_unlock(&dev_priv->psr.lock); 1682 } 1683 1684 /** 1685 * intel_psr_invalidate - Invalidade PSR 1686 * @dev_priv: i915 device 1687 * @frontbuffer_bits: frontbuffer plane tracking bits 1688 * @origin: which operation caused the invalidate 1689 * 1690 * Since the hardware frontbuffer tracking has gaps we need to integrate 1691 * with the software frontbuffer tracking. This function gets called every 1692 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 1693 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 1694 * 1695 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 1696 */ 1697 void intel_psr_invalidate(struct drm_i915_private *dev_priv, 1698 unsigned frontbuffer_bits, enum fb_op_origin origin) 1699 { 1700 if (!CAN_PSR(dev_priv)) 1701 return; 1702 1703 if (origin == ORIGIN_FLIP) 1704 return; 1705 1706 mutex_lock(&dev_priv->psr.lock); 1707 if (!dev_priv->psr.enabled) { 1708 mutex_unlock(&dev_priv->psr.lock); 1709 return; 1710 } 1711 1712 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe); 1713 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; 1714 1715 if (frontbuffer_bits) 1716 intel_psr_exit(dev_priv); 1717 1718 mutex_unlock(&dev_priv->psr.lock); 1719 } 1720 1721 /* 1722 * When we will be completely rely on PSR2 S/W tracking in future, 1723 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP 1724 * event also therefore tgl_dc3co_flush() require to be changed 1725 * accordingly in future. 1726 */ 1727 static void 1728 tgl_dc3co_flush(struct drm_i915_private *dev_priv, 1729 unsigned int frontbuffer_bits, enum fb_op_origin origin) 1730 { 1731 mutex_lock(&dev_priv->psr.lock); 1732 1733 if (!dev_priv->psr.dc3co_enabled) 1734 goto unlock; 1735 1736 if (!dev_priv->psr.psr2_enabled || !dev_priv->psr.active) 1737 goto unlock; 1738 1739 /* 1740 * At every frontbuffer flush flip event modified delay of delayed work, 1741 * when delayed work schedules that means display has been idle. 1742 */ 1743 if (!(frontbuffer_bits & 1744 INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe))) 1745 goto unlock; 1746 1747 tgl_psr2_enable_dc3co(dev_priv); 1748 mod_delayed_work(system_wq, &dev_priv->psr.dc3co_work, 1749 dev_priv->psr.dc3co_exit_delay); 1750 1751 unlock: 1752 mutex_unlock(&dev_priv->psr.lock); 1753 } 1754 1755 /** 1756 * intel_psr_flush - Flush PSR 1757 * @dev_priv: i915 device 1758 * @frontbuffer_bits: frontbuffer plane tracking bits 1759 * @origin: which operation caused the flush 1760 * 1761 * Since the hardware frontbuffer tracking has gaps we need to integrate 1762 * with the software frontbuffer tracking. This function gets called every 1763 * time frontbuffer rendering has completed and flushed out to memory. PSR 1764 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 1765 * 1766 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 1767 */ 1768 void intel_psr_flush(struct drm_i915_private *dev_priv, 1769 unsigned frontbuffer_bits, enum fb_op_origin origin) 1770 { 1771 if (!CAN_PSR(dev_priv)) 1772 return; 1773 1774 if (origin == ORIGIN_FLIP) { 1775 tgl_dc3co_flush(dev_priv, frontbuffer_bits, origin); 1776 return; 1777 } 1778 1779 mutex_lock(&dev_priv->psr.lock); 1780 if (!dev_priv->psr.enabled) { 1781 mutex_unlock(&dev_priv->psr.lock); 1782 return; 1783 } 1784 1785 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe); 1786 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; 1787 1788 /* By definition flush = invalidate + flush */ 1789 if (frontbuffer_bits) 1790 psr_force_hw_tracking_exit(dev_priv); 1791 1792 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) 1793 schedule_work(&dev_priv->psr.work); 1794 mutex_unlock(&dev_priv->psr.lock); 1795 } 1796 1797 /** 1798 * intel_psr_init - Init basic PSR work and mutex. 1799 * @dev_priv: i915 device private 1800 * 1801 * This function is called only once at driver load to initialize basic 1802 * PSR stuff. 1803 */ 1804 void intel_psr_init(struct drm_i915_private *dev_priv) 1805 { 1806 if (!HAS_PSR(dev_priv)) 1807 return; 1808 1809 if (!dev_priv->psr.sink_support) 1810 return; 1811 1812 if (IS_HASWELL(dev_priv)) 1813 /* 1814 * HSW don't have PSR registers on the same space as transcoder 1815 * so set this to a value that when subtract to the register 1816 * in transcoder space results in the right offset for HSW 1817 */ 1818 dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE; 1819 1820 if (dev_priv->params.enable_psr == -1) 1821 if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable) 1822 dev_priv->params.enable_psr = 0; 1823 1824 /* Set link_standby x link_off defaults */ 1825 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 1826 /* HSW and BDW require workarounds that we don't implement. */ 1827 dev_priv->psr.link_standby = false; 1828 else if (INTEL_GEN(dev_priv) < 12) 1829 /* For new platforms up to TGL let's respect VBT back again */ 1830 dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; 1831 1832 INIT_WORK(&dev_priv->psr.work, intel_psr_work); 1833 INIT_DELAYED_WORK(&dev_priv->psr.dc3co_work, tgl_dc3co_disable_work); 1834 mutex_init(&dev_priv->psr.lock); 1835 } 1836 1837 static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 1838 u8 *status, u8 *error_status) 1839 { 1840 struct drm_dp_aux *aux = &intel_dp->aux; 1841 int ret; 1842 1843 ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status); 1844 if (ret != 1) 1845 return ret; 1846 1847 ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status); 1848 if (ret != 1) 1849 return ret; 1850 1851 *status = *status & DP_PSR_SINK_STATE_MASK; 1852 1853 return 0; 1854 } 1855 1856 static void psr_alpm_check(struct intel_dp *intel_dp) 1857 { 1858 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1859 struct drm_dp_aux *aux = &intel_dp->aux; 1860 struct i915_psr *psr = &dev_priv->psr; 1861 u8 val; 1862 int r; 1863 1864 if (!psr->psr2_enabled) 1865 return; 1866 1867 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); 1868 if (r != 1) { 1869 drm_err(&dev_priv->drm, "Error reading ALPM status\n"); 1870 return; 1871 } 1872 1873 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) { 1874 intel_psr_disable_locked(intel_dp); 1875 psr->sink_not_reliable = true; 1876 drm_dbg_kms(&dev_priv->drm, 1877 "ALPM lock timeout error, disabling PSR\n"); 1878 1879 /* Clearing error */ 1880 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); 1881 } 1882 } 1883 1884 static void psr_capability_changed_check(struct intel_dp *intel_dp) 1885 { 1886 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1887 struct i915_psr *psr = &dev_priv->psr; 1888 u8 val; 1889 int r; 1890 1891 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 1892 if (r != 1) { 1893 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n"); 1894 return; 1895 } 1896 1897 if (val & DP_PSR_CAPS_CHANGE) { 1898 intel_psr_disable_locked(intel_dp); 1899 psr->sink_not_reliable = true; 1900 drm_dbg_kms(&dev_priv->drm, 1901 "Sink PSR capability changed, disabling PSR\n"); 1902 1903 /* Clearing it */ 1904 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 1905 } 1906 } 1907 1908 void intel_psr_short_pulse(struct intel_dp *intel_dp) 1909 { 1910 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1911 struct i915_psr *psr = &dev_priv->psr; 1912 u8 status, error_status; 1913 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 1914 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 1915 DP_PSR_LINK_CRC_ERROR; 1916 1917 if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp)) 1918 return; 1919 1920 mutex_lock(&psr->lock); 1921 1922 if (!psr->enabled || psr->dp != intel_dp) 1923 goto exit; 1924 1925 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 1926 drm_err(&dev_priv->drm, 1927 "Error reading PSR status or error status\n"); 1928 goto exit; 1929 } 1930 1931 if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) { 1932 intel_psr_disable_locked(intel_dp); 1933 psr->sink_not_reliable = true; 1934 } 1935 1936 if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status) 1937 drm_dbg_kms(&dev_priv->drm, 1938 "PSR sink internal error, disabling PSR\n"); 1939 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 1940 drm_dbg_kms(&dev_priv->drm, 1941 "PSR RFB storage error, disabling PSR\n"); 1942 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 1943 drm_dbg_kms(&dev_priv->drm, 1944 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 1945 if (error_status & DP_PSR_LINK_CRC_ERROR) 1946 drm_dbg_kms(&dev_priv->drm, 1947 "PSR Link CRC error, disabling PSR\n"); 1948 1949 if (error_status & ~errors) 1950 drm_err(&dev_priv->drm, 1951 "PSR_ERROR_STATUS unhandled errors %x\n", 1952 error_status & ~errors); 1953 /* clear status register */ 1954 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 1955 1956 psr_alpm_check(intel_dp); 1957 psr_capability_changed_check(intel_dp); 1958 1959 exit: 1960 mutex_unlock(&psr->lock); 1961 } 1962 1963 bool intel_psr_enabled(struct intel_dp *intel_dp) 1964 { 1965 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1966 bool ret; 1967 1968 if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp)) 1969 return false; 1970 1971 mutex_lock(&dev_priv->psr.lock); 1972 ret = (dev_priv->psr.dp == intel_dp && dev_priv->psr.enabled); 1973 mutex_unlock(&dev_priv->psr.lock); 1974 1975 return ret; 1976 } 1977