1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_damage_helper.h> 26 27 #include "i915_drv.h" 28 #include "i915_reg.h" 29 #include "intel_atomic.h" 30 #include "intel_crtc.h" 31 #include "intel_de.h" 32 #include "intel_display_types.h" 33 #include "intel_dp.h" 34 #include "intel_dp_aux.h" 35 #include "intel_hdmi.h" 36 #include "intel_psr.h" 37 #include "intel_snps_phy.h" 38 #include "skl_universal_plane.h" 39 40 /** 41 * DOC: Panel Self Refresh (PSR/SRD) 42 * 43 * Since Haswell Display controller supports Panel Self-Refresh on display 44 * panels witch have a remote frame buffer (RFB) implemented according to PSR 45 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 46 * when system is idle but display is on as it eliminates display refresh 47 * request to DDR memory completely as long as the frame buffer for that 48 * display is unchanged. 49 * 50 * Panel Self Refresh must be supported by both Hardware (source) and 51 * Panel (sink). 52 * 53 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 54 * to power down the link and memory controller. For DSI panels the same idea 55 * is called "manual mode". 56 * 57 * The implementation uses the hardware-based PSR support which automatically 58 * enters/exits self-refresh mode. The hardware takes care of sending the 59 * required DP aux message and could even retrain the link (that part isn't 60 * enabled yet though). The hardware also keeps track of any frontbuffer 61 * changes to know when to exit self-refresh mode again. Unfortunately that 62 * part doesn't work too well, hence why the i915 PSR support uses the 63 * software frontbuffer tracking to make sure it doesn't miss a screen 64 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 65 * get called by the frontbuffer tracking code. Note that because of locking 66 * issues the self-refresh re-enable code is done from a work queue, which 67 * must be correctly synchronized/cancelled when shutting down the pipe." 68 * 69 * DC3CO (DC3 clock off) 70 * 71 * On top of PSR2, GEN12 adds a intermediate power savings state that turns 72 * clock off automatically during PSR2 idle state. 73 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep 74 * entry/exit allows the HW to enter a low-power state even when page flipping 75 * periodically (for instance a 30fps video playback scenario). 76 * 77 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), 78 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 79 * frames, if no other flip occurs and the function above is executed, DC3CO is 80 * disabled and PSR2 is configured to enter deep sleep, resetting again in case 81 * of another flip. 82 * Front buffer modifications do not trigger DC3CO activation on purpose as it 83 * would bring a lot of complexity and most of the moderns systems will only 84 * use page flips. 85 */ 86 87 static bool psr_global_enabled(struct intel_dp *intel_dp) 88 { 89 struct intel_connector *connector = intel_dp->attached_connector; 90 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 91 92 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 93 case I915_PSR_DEBUG_DEFAULT: 94 if (i915->params.enable_psr == -1) 95 return connector->panel.vbt.psr.enable; 96 return i915->params.enable_psr; 97 case I915_PSR_DEBUG_DISABLE: 98 return false; 99 default: 100 return true; 101 } 102 } 103 104 static bool psr2_global_enabled(struct intel_dp *intel_dp) 105 { 106 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 107 108 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 109 case I915_PSR_DEBUG_DISABLE: 110 case I915_PSR_DEBUG_FORCE_PSR1: 111 return false; 112 default: 113 if (i915->params.enable_psr == 1) 114 return false; 115 return true; 116 } 117 } 118 119 static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp) 120 { 121 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 122 123 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_ERROR : 124 EDP_PSR_ERROR(intel_dp->psr.transcoder); 125 } 126 127 static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp) 128 { 129 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 130 131 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_POST_EXIT : 132 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder); 133 } 134 135 static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp) 136 { 137 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 138 139 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_PRE_ENTRY : 140 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder); 141 } 142 143 static u32 psr_irq_mask_get(struct intel_dp *intel_dp) 144 { 145 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 146 147 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_MASK : 148 EDP_PSR_MASK(intel_dp->psr.transcoder); 149 } 150 151 static void psr_irq_control(struct intel_dp *intel_dp) 152 { 153 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 154 i915_reg_t imr_reg; 155 u32 mask, val; 156 157 if (DISPLAY_VER(dev_priv) >= 12) 158 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 159 else 160 imr_reg = EDP_PSR_IMR; 161 162 mask = psr_irq_psr_error_bit_get(intel_dp); 163 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) 164 mask |= psr_irq_post_exit_bit_get(intel_dp) | 165 psr_irq_pre_entry_bit_get(intel_dp); 166 167 val = intel_de_read(dev_priv, imr_reg); 168 val &= ~psr_irq_mask_get(intel_dp); 169 val |= ~mask; 170 intel_de_write(dev_priv, imr_reg, val); 171 } 172 173 static void psr_event_print(struct drm_i915_private *i915, 174 u32 val, bool psr2_enabled) 175 { 176 drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val); 177 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 178 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n"); 179 if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) 180 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n"); 181 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 182 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n"); 183 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 184 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n"); 185 if (val & PSR_EVENT_GRAPHICS_RESET) 186 drm_dbg_kms(&i915->drm, "\tGraphics reset\n"); 187 if (val & PSR_EVENT_PCH_INTERRUPT) 188 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n"); 189 if (val & PSR_EVENT_MEMORY_UP) 190 drm_dbg_kms(&i915->drm, "\tMemory up\n"); 191 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 192 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n"); 193 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 194 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n"); 195 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 196 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n"); 197 if (val & PSR_EVENT_REGISTER_UPDATE) 198 drm_dbg_kms(&i915->drm, "\tRegister updated\n"); 199 if (val & PSR_EVENT_HDCP_ENABLE) 200 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n"); 201 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 202 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n"); 203 if (val & PSR_EVENT_VBI_ENABLE) 204 drm_dbg_kms(&i915->drm, "\tVBI enabled\n"); 205 if (val & PSR_EVENT_LPSP_MODE_EXIT) 206 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n"); 207 if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) 208 drm_dbg_kms(&i915->drm, "\tPSR disabled\n"); 209 } 210 211 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) 212 { 213 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 214 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 215 ktime_t time_ns = ktime_get(); 216 i915_reg_t imr_reg; 217 218 if (DISPLAY_VER(dev_priv) >= 12) 219 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 220 else 221 imr_reg = EDP_PSR_IMR; 222 223 if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) { 224 intel_dp->psr.last_entry_attempt = time_ns; 225 drm_dbg_kms(&dev_priv->drm, 226 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 227 transcoder_name(cpu_transcoder)); 228 } 229 230 if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) { 231 intel_dp->psr.last_exit = time_ns; 232 drm_dbg_kms(&dev_priv->drm, 233 "[transcoder %s] PSR exit completed\n", 234 transcoder_name(cpu_transcoder)); 235 236 if (DISPLAY_VER(dev_priv) >= 9) { 237 u32 val = intel_de_read(dev_priv, 238 PSR_EVENT(cpu_transcoder)); 239 bool psr2_enabled = intel_dp->psr.psr2_enabled; 240 241 intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder), 242 val); 243 psr_event_print(dev_priv, val, psr2_enabled); 244 } 245 } 246 247 if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) { 248 u32 val; 249 250 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", 251 transcoder_name(cpu_transcoder)); 252 253 intel_dp->psr.irq_aux_error = true; 254 255 /* 256 * If this interruption is not masked it will keep 257 * interrupting so fast that it prevents the scheduled 258 * work to run. 259 * Also after a PSR error, we don't want to arm PSR 260 * again so we don't care about unmask the interruption 261 * or unset irq_aux_error. 262 */ 263 val = intel_de_read(dev_priv, imr_reg); 264 val |= psr_irq_psr_error_bit_get(intel_dp); 265 intel_de_write(dev_priv, imr_reg, val); 266 267 schedule_work(&intel_dp->psr.work); 268 } 269 } 270 271 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) 272 { 273 u8 alpm_caps = 0; 274 275 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, 276 &alpm_caps) != 1) 277 return false; 278 return alpm_caps & DP_ALPM_CAP; 279 } 280 281 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 282 { 283 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 284 u8 val = 8; /* assume the worst if we can't read the value */ 285 286 if (drm_dp_dpcd_readb(&intel_dp->aux, 287 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 288 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 289 else 290 drm_dbg_kms(&i915->drm, 291 "Unable to get sink synchronization latency, assuming 8 frames\n"); 292 return val; 293 } 294 295 static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) 296 { 297 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 298 ssize_t r; 299 u16 w; 300 u8 y; 301 302 /* If sink don't have specific granularity requirements set legacy ones */ 303 if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { 304 /* As PSR2 HW sends full lines, we do not care about x granularity */ 305 w = 4; 306 y = 4; 307 goto exit; 308 } 309 310 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2); 311 if (r != 2) 312 drm_dbg_kms(&i915->drm, 313 "Unable to read DP_PSR2_SU_X_GRANULARITY\n"); 314 /* 315 * Spec says that if the value read is 0 the default granularity should 316 * be used instead. 317 */ 318 if (r != 2 || w == 0) 319 w = 4; 320 321 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); 322 if (r != 1) { 323 drm_dbg_kms(&i915->drm, 324 "Unable to read DP_PSR2_SU_Y_GRANULARITY\n"); 325 y = 4; 326 } 327 if (y == 0) 328 y = 1; 329 330 exit: 331 intel_dp->psr.su_w_granularity = w; 332 intel_dp->psr.su_y_granularity = y; 333 } 334 335 void intel_psr_init_dpcd(struct intel_dp *intel_dp) 336 { 337 struct drm_i915_private *dev_priv = 338 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 339 340 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, 341 sizeof(intel_dp->psr_dpcd)); 342 343 if (!intel_dp->psr_dpcd[0]) 344 return; 345 drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n", 346 intel_dp->psr_dpcd[0]); 347 348 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { 349 drm_dbg_kms(&dev_priv->drm, 350 "PSR support not currently available for this panel\n"); 351 return; 352 } 353 354 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 355 drm_dbg_kms(&dev_priv->drm, 356 "Panel lacks power state control, PSR cannot be enabled\n"); 357 return; 358 } 359 360 intel_dp->psr.sink_support = true; 361 intel_dp->psr.sink_sync_latency = 362 intel_dp_get_sink_sync_latency(intel_dp); 363 364 if (DISPLAY_VER(dev_priv) >= 9 && 365 (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { 366 bool y_req = intel_dp->psr_dpcd[1] & 367 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 368 bool alpm = intel_dp_get_alpm_status(intel_dp); 369 370 /* 371 * All panels that supports PSR version 03h (PSR2 + 372 * Y-coordinate) can handle Y-coordinates in VSC but we are 373 * only sure that it is going to be used when required by the 374 * panel. This way panel is capable to do selective update 375 * without a aux frame sync. 376 * 377 * To support PSR version 02h and PSR version 03h without 378 * Y-coordinate requirement panels we would need to enable 379 * GTC first. 380 */ 381 intel_dp->psr.sink_psr2_support = y_req && alpm; 382 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n", 383 intel_dp->psr.sink_psr2_support ? "" : "not "); 384 385 if (intel_dp->psr.sink_psr2_support) { 386 intel_dp->psr.colorimetry_support = 387 intel_dp_get_colorimetry_status(intel_dp); 388 intel_dp_get_su_granularity(intel_dp); 389 } 390 } 391 } 392 393 static void intel_psr_enable_sink(struct intel_dp *intel_dp) 394 { 395 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 396 u8 dpcd_val = DP_PSR_ENABLE; 397 398 /* Enable ALPM at sink for psr2 */ 399 if (intel_dp->psr.psr2_enabled) { 400 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 401 DP_ALPM_ENABLE | 402 DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); 403 404 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 405 } else { 406 if (intel_dp->psr.link_standby) 407 dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; 408 409 if (DISPLAY_VER(dev_priv) >= 8) 410 dpcd_val |= DP_PSR_CRC_VERIFICATION; 411 } 412 413 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 414 dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; 415 416 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); 417 418 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 419 } 420 421 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 422 { 423 struct intel_connector *connector = intel_dp->attached_connector; 424 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 425 u32 val = 0; 426 427 if (DISPLAY_VER(dev_priv) >= 11) 428 val |= EDP_PSR_TP4_TIME_0US; 429 430 if (dev_priv->params.psr_safest_params) { 431 val |= EDP_PSR_TP1_TIME_2500us; 432 val |= EDP_PSR_TP2_TP3_TIME_2500us; 433 goto check_tp3_sel; 434 } 435 436 if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0) 437 val |= EDP_PSR_TP1_TIME_0us; 438 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100) 439 val |= EDP_PSR_TP1_TIME_100us; 440 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500) 441 val |= EDP_PSR_TP1_TIME_500us; 442 else 443 val |= EDP_PSR_TP1_TIME_2500us; 444 445 if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) 446 val |= EDP_PSR_TP2_TP3_TIME_0us; 447 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100) 448 val |= EDP_PSR_TP2_TP3_TIME_100us; 449 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500) 450 val |= EDP_PSR_TP2_TP3_TIME_500us; 451 else 452 val |= EDP_PSR_TP2_TP3_TIME_2500us; 453 454 check_tp3_sel: 455 if (intel_dp_source_supports_tps3(dev_priv) && 456 drm_dp_tps3_supported(intel_dp->dpcd)) 457 val |= EDP_PSR_TP1_TP3_SEL; 458 else 459 val |= EDP_PSR_TP1_TP2_SEL; 460 461 return val; 462 } 463 464 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 465 { 466 struct intel_connector *connector = intel_dp->attached_connector; 467 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 468 int idle_frames; 469 470 /* Let's use 6 as the minimum to cover all known cases including the 471 * off-by-one issue that HW has in some cases. 472 */ 473 idle_frames = max(6, connector->panel.vbt.psr.idle_frames); 474 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1); 475 476 if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf)) 477 idle_frames = 0xf; 478 479 return idle_frames; 480 } 481 482 static void hsw_activate_psr1(struct intel_dp *intel_dp) 483 { 484 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 485 u32 max_sleep_time = 0x1f; 486 u32 val = EDP_PSR_ENABLE; 487 488 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT; 489 490 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; 491 if (IS_HASWELL(dev_priv)) 492 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 493 494 if (intel_dp->psr.link_standby) 495 val |= EDP_PSR_LINK_STANDBY; 496 497 val |= intel_psr1_get_tp_time(intel_dp); 498 499 if (DISPLAY_VER(dev_priv) >= 8) 500 val |= EDP_PSR_CRC_ENABLE; 501 502 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) & 503 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK); 504 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val); 505 } 506 507 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 508 { 509 struct intel_connector *connector = intel_dp->attached_connector; 510 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 511 u32 val = 0; 512 513 if (dev_priv->params.psr_safest_params) 514 return EDP_PSR2_TP2_TIME_2500us; 515 516 if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 517 connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 518 val |= EDP_PSR2_TP2_TIME_50us; 519 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 520 val |= EDP_PSR2_TP2_TIME_100us; 521 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 522 val |= EDP_PSR2_TP2_TIME_500us; 523 else 524 val |= EDP_PSR2_TP2_TIME_2500us; 525 526 return val; 527 } 528 529 static void hsw_activate_psr2(struct intel_dp *intel_dp) 530 { 531 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 532 u32 val = EDP_PSR2_ENABLE; 533 534 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT; 535 536 if (DISPLAY_VER(dev_priv) <= 13 && !IS_ALDERLAKE_P(dev_priv)) 537 val |= EDP_SU_TRACK_ENABLE; 538 539 if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12) 540 val |= EDP_Y_COORDINATE_ENABLE; 541 542 val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2)); 543 val |= intel_psr2_get_tp_time(intel_dp); 544 545 if (DISPLAY_VER(dev_priv) >= 12) { 546 if (intel_dp->psr.io_wake_lines < 9 && 547 intel_dp->psr.fast_wake_lines < 9) 548 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 549 else 550 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3; 551 } 552 553 /* Wa_22012278275:adl-p */ 554 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { 555 static const u8 map[] = { 556 2, /* 5 lines */ 557 1, /* 6 lines */ 558 0, /* 7 lines */ 559 3, /* 8 lines */ 560 6, /* 9 lines */ 561 5, /* 10 lines */ 562 4, /* 11 lines */ 563 7, /* 12 lines */ 564 }; 565 /* 566 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see 567 * comments bellow for more information 568 */ 569 u32 tmp; 570 571 tmp = map[intel_dp->psr.io_wake_lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; 572 tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT; 573 val |= tmp; 574 575 tmp = map[intel_dp->psr.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; 576 tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT; 577 val |= tmp; 578 } else if (DISPLAY_VER(dev_priv) >= 12) { 579 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 580 val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); 581 } else if (DISPLAY_VER(dev_priv) >= 9) { 582 val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 583 val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); 584 } 585 586 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 587 val |= EDP_PSR2_SU_SDP_SCANLINE; 588 589 if (intel_dp->psr.psr2_sel_fetch_enabled) { 590 u32 tmp; 591 592 /* Wa_1408330847 */ 593 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 594 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 595 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 596 DIS_RAM_BYPASS_PSR2_MAN_TRACK); 597 598 tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); 599 drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); 600 } else if (HAS_PSR2_SEL_FETCH(dev_priv)) { 601 intel_de_write(dev_priv, 602 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0); 603 } 604 605 /* 606 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 607 * recommending keep this bit unset while PSR2 is enabled. 608 */ 609 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0); 610 611 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 612 } 613 614 static bool 615 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) 616 { 617 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 618 return trans == TRANSCODER_A || trans == TRANSCODER_B; 619 else if (DISPLAY_VER(dev_priv) >= 12) 620 return trans == TRANSCODER_A; 621 else 622 return trans == TRANSCODER_EDP; 623 } 624 625 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate) 626 { 627 if (!cstate || !cstate->hw.active) 628 return 0; 629 630 return DIV_ROUND_UP(1000 * 1000, 631 drm_mode_vrefresh(&cstate->hw.adjusted_mode)); 632 } 633 634 static void psr2_program_idle_frames(struct intel_dp *intel_dp, 635 u32 idle_frames) 636 { 637 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 638 u32 val; 639 640 idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; 641 val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder)); 642 val &= ~EDP_PSR2_IDLE_FRAME_MASK; 643 val |= idle_frames; 644 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 645 } 646 647 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) 648 { 649 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 650 651 psr2_program_idle_frames(intel_dp, 0); 652 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO); 653 } 654 655 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp) 656 { 657 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 658 659 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 660 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp)); 661 } 662 663 static void tgl_dc3co_disable_work(struct work_struct *work) 664 { 665 struct intel_dp *intel_dp = 666 container_of(work, typeof(*intel_dp), psr.dc3co_work.work); 667 668 mutex_lock(&intel_dp->psr.lock); 669 /* If delayed work is pending, it is not idle */ 670 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) 671 goto unlock; 672 673 tgl_psr2_disable_dc3co(intel_dp); 674 unlock: 675 mutex_unlock(&intel_dp->psr.lock); 676 } 677 678 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) 679 { 680 if (!intel_dp->psr.dc3co_exitline) 681 return; 682 683 cancel_delayed_work(&intel_dp->psr.dc3co_work); 684 /* Before PSR2 exit disallow dc3co*/ 685 tgl_psr2_disable_dc3co(intel_dp); 686 } 687 688 static bool 689 dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp, 690 struct intel_crtc_state *crtc_state) 691 { 692 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 693 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 694 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 695 enum port port = dig_port->base.port; 696 697 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 698 return pipe <= PIPE_B && port <= PORT_B; 699 else 700 return pipe == PIPE_A && port == PORT_A; 701 } 702 703 static void 704 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 705 struct intel_crtc_state *crtc_state) 706 { 707 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; 708 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 709 u32 exit_scanlines; 710 711 /* 712 * FIXME: Due to the changed sequence of activating/deactivating DC3CO, 713 * disable DC3CO until the changed dc3co activating/deactivating sequence 714 * is applied. B.Specs:49196 715 */ 716 return; 717 718 /* 719 * DMC's DC3CO exit mechanism has an issue with Selective Fecth 720 * TODO: when the issue is addressed, this restriction should be removed. 721 */ 722 if (crtc_state->enable_psr2_sel_fetch) 723 return; 724 725 if (!(dev_priv->display.dmc.allowed_dc_mask & DC_STATE_EN_DC3CO)) 726 return; 727 728 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) 729 return; 730 731 /* Wa_16011303918:adl-p */ 732 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 733 return; 734 735 /* 736 * DC3CO Exit time 200us B.Spec 49196 737 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 738 */ 739 exit_scanlines = 740 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; 741 742 if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay)) 743 return; 744 745 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; 746 } 747 748 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, 749 struct intel_crtc_state *crtc_state) 750 { 751 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 752 753 if (!dev_priv->params.enable_psr2_sel_fetch && 754 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 755 drm_dbg_kms(&dev_priv->drm, 756 "PSR2 sel fetch not enabled, disabled by parameter\n"); 757 return false; 758 } 759 760 if (crtc_state->uapi.async_flip) { 761 drm_dbg_kms(&dev_priv->drm, 762 "PSR2 sel fetch not enabled, async flip enabled\n"); 763 return false; 764 } 765 766 /* Wa_14010254185 Wa_14010103792 */ 767 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { 768 drm_dbg_kms(&dev_priv->drm, 769 "PSR2 sel fetch not enabled, missing the implementation of WAs\n"); 770 return false; 771 } 772 773 return crtc_state->enable_psr2_sel_fetch = true; 774 } 775 776 static bool psr2_granularity_check(struct intel_dp *intel_dp, 777 struct intel_crtc_state *crtc_state) 778 { 779 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 780 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 781 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 782 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 783 u16 y_granularity = 0; 784 785 /* PSR2 HW only send full lines so we only need to validate the width */ 786 if (crtc_hdisplay % intel_dp->psr.su_w_granularity) 787 return false; 788 789 if (crtc_vdisplay % intel_dp->psr.su_y_granularity) 790 return false; 791 792 /* HW tracking is only aligned to 4 lines */ 793 if (!crtc_state->enable_psr2_sel_fetch) 794 return intel_dp->psr.su_y_granularity == 4; 795 796 /* 797 * adl_p and mtl platforms have 1 line granularity. 798 * For other platforms with SW tracking we can adjust the y coordinates 799 * to match sink requirement if multiple of 4. 800 */ 801 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 802 y_granularity = intel_dp->psr.su_y_granularity; 803 else if (intel_dp->psr.su_y_granularity <= 2) 804 y_granularity = 4; 805 else if ((intel_dp->psr.su_y_granularity % 4) == 0) 806 y_granularity = intel_dp->psr.su_y_granularity; 807 808 if (y_granularity == 0 || crtc_vdisplay % y_granularity) 809 return false; 810 811 if (crtc_state->dsc.compression_enable && 812 vdsc_cfg->slice_height % y_granularity) 813 return false; 814 815 crtc_state->su_y_granularity = y_granularity; 816 return true; 817 } 818 819 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp, 820 struct intel_crtc_state *crtc_state) 821 { 822 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; 823 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 824 u32 hblank_total, hblank_ns, req_ns; 825 826 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; 827 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); 828 829 /* From spec: ((60 / number of lanes) + 11) * 1000 / symbol clock frequency MHz */ 830 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); 831 832 if ((hblank_ns - req_ns) > 100) 833 return true; 834 835 /* Not supported <13 / Wa_22012279113:adl-p */ 836 if (DISPLAY_VER(dev_priv) <= 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b) 837 return false; 838 839 crtc_state->req_psr2_sdp_prior_scanline = true; 840 return true; 841 } 842 843 static bool _compute_psr2_wake_times(struct intel_dp *intel_dp, 844 struct intel_crtc_state *crtc_state) 845 { 846 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 847 int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time; 848 u8 max_wake_lines; 849 850 if (DISPLAY_VER(i915) >= 12) { 851 io_wake_time = 42; 852 /* 853 * According to Bspec it's 42us, but based on testing 854 * it is not enough -> use 45 us. 855 */ 856 fast_wake_time = 45; 857 max_wake_lines = 12; 858 } else { 859 io_wake_time = 50; 860 fast_wake_time = 32; 861 max_wake_lines = 8; 862 } 863 864 io_wake_lines = intel_usecs_to_scanlines( 865 &crtc_state->uapi.adjusted_mode, io_wake_time); 866 fast_wake_lines = intel_usecs_to_scanlines( 867 &crtc_state->uapi.adjusted_mode, fast_wake_time); 868 869 if (io_wake_lines > max_wake_lines || 870 fast_wake_lines > max_wake_lines) 871 return false; 872 873 if (i915->params.psr_safest_params) 874 io_wake_lines = fast_wake_lines = max_wake_lines; 875 876 /* According to Bspec lower limit should be set as 7 lines. */ 877 intel_dp->psr.io_wake_lines = max(io_wake_lines, 7); 878 intel_dp->psr.fast_wake_lines = max(fast_wake_lines, 7); 879 880 return true; 881 } 882 883 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 884 struct intel_crtc_state *crtc_state) 885 { 886 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 887 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 888 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 889 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 890 891 if (!intel_dp->psr.sink_psr2_support) 892 return false; 893 894 /* JSL and EHL only supports eDP 1.3 */ 895 if (IS_JSL_EHL(dev_priv)) { 896 drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n"); 897 return false; 898 } 899 900 /* Wa_16011181250 */ 901 if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) || 902 IS_DG2(dev_priv)) { 903 drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n"); 904 return false; 905 } 906 907 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 908 drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n"); 909 return false; 910 } 911 912 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { 913 drm_dbg_kms(&dev_priv->drm, 914 "PSR2 not supported in transcoder %s\n", 915 transcoder_name(crtc_state->cpu_transcoder)); 916 return false; 917 } 918 919 if (!psr2_global_enabled(intel_dp)) { 920 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); 921 return false; 922 } 923 924 /* 925 * DSC and PSR2 cannot be enabled simultaneously. If a requested 926 * resolution requires DSC to be enabled, priority is given to DSC 927 * over PSR2. 928 */ 929 if (crtc_state->dsc.compression_enable && 930 (DISPLAY_VER(dev_priv) <= 13 && !IS_ALDERLAKE_P(dev_priv))) { 931 drm_dbg_kms(&dev_priv->drm, 932 "PSR2 cannot be enabled since DSC is enabled\n"); 933 return false; 934 } 935 936 if (crtc_state->crc_enabled) { 937 drm_dbg_kms(&dev_priv->drm, 938 "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); 939 return false; 940 } 941 942 if (DISPLAY_VER(dev_priv) >= 12) { 943 psr_max_h = 5120; 944 psr_max_v = 3200; 945 max_bpp = 30; 946 } else if (DISPLAY_VER(dev_priv) >= 10) { 947 psr_max_h = 4096; 948 psr_max_v = 2304; 949 max_bpp = 24; 950 } else if (DISPLAY_VER(dev_priv) == 9) { 951 psr_max_h = 3640; 952 psr_max_v = 2304; 953 max_bpp = 24; 954 } 955 956 if (crtc_state->pipe_bpp > max_bpp) { 957 drm_dbg_kms(&dev_priv->drm, 958 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 959 crtc_state->pipe_bpp, max_bpp); 960 return false; 961 } 962 963 /* Wa_16011303918:adl-p */ 964 if (crtc_state->vrr.enable && 965 IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 966 drm_dbg_kms(&dev_priv->drm, 967 "PSR2 not enabled, not compatible with HW stepping + VRR\n"); 968 return false; 969 } 970 971 if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) { 972 drm_dbg_kms(&dev_priv->drm, 973 "PSR2 not enabled, PSR2 SDP indication do not fit in hblank\n"); 974 return false; 975 } 976 977 if (!_compute_psr2_wake_times(intel_dp, crtc_state)) { 978 drm_dbg_kms(&dev_priv->drm, 979 "PSR2 not enabled, Unable to use long enough wake times\n"); 980 return false; 981 } 982 983 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 984 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && 985 !HAS_PSR_HW_TRACKING(dev_priv)) { 986 drm_dbg_kms(&dev_priv->drm, 987 "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); 988 return false; 989 } 990 } 991 992 /* Wa_2209313811 */ 993 if (!crtc_state->enable_psr2_sel_fetch && 994 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { 995 drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n"); 996 goto unsupported; 997 } 998 999 if (!psr2_granularity_check(intel_dp, crtc_state)) { 1000 drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n"); 1001 goto unsupported; 1002 } 1003 1004 if (!crtc_state->enable_psr2_sel_fetch && 1005 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { 1006 drm_dbg_kms(&dev_priv->drm, 1007 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 1008 crtc_hdisplay, crtc_vdisplay, 1009 psr_max_h, psr_max_v); 1010 goto unsupported; 1011 } 1012 1013 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); 1014 return true; 1015 1016 unsupported: 1017 crtc_state->enable_psr2_sel_fetch = false; 1018 return false; 1019 } 1020 1021 void intel_psr_compute_config(struct intel_dp *intel_dp, 1022 struct intel_crtc_state *crtc_state, 1023 struct drm_connector_state *conn_state) 1024 { 1025 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1026 const struct drm_display_mode *adjusted_mode = 1027 &crtc_state->hw.adjusted_mode; 1028 int psr_setup_time; 1029 1030 /* 1031 * Current PSR panels don't work reliably with VRR enabled 1032 * So if VRR is enabled, do not enable PSR. 1033 */ 1034 if (crtc_state->vrr.enable) 1035 return; 1036 1037 if (!CAN_PSR(intel_dp)) 1038 return; 1039 1040 if (!psr_global_enabled(intel_dp)) { 1041 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); 1042 return; 1043 } 1044 1045 if (intel_dp->psr.sink_not_reliable) { 1046 drm_dbg_kms(&dev_priv->drm, 1047 "PSR sink implementation is not reliable\n"); 1048 return; 1049 } 1050 1051 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 1052 drm_dbg_kms(&dev_priv->drm, 1053 "PSR condition failed: Interlaced mode enabled\n"); 1054 return; 1055 } 1056 1057 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); 1058 if (psr_setup_time < 0) { 1059 drm_dbg_kms(&dev_priv->drm, 1060 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 1061 intel_dp->psr_dpcd[1]); 1062 return; 1063 } 1064 1065 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 1066 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 1067 drm_dbg_kms(&dev_priv->drm, 1068 "PSR condition failed: PSR setup time (%d us) too long\n", 1069 psr_setup_time); 1070 return; 1071 } 1072 1073 crtc_state->has_psr = true; 1074 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); 1075 1076 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1077 intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, 1078 &crtc_state->psr_vsc); 1079 } 1080 1081 void intel_psr_get_config(struct intel_encoder *encoder, 1082 struct intel_crtc_state *pipe_config) 1083 { 1084 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1085 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1086 struct intel_dp *intel_dp; 1087 u32 val; 1088 1089 if (!dig_port) 1090 return; 1091 1092 intel_dp = &dig_port->dp; 1093 if (!CAN_PSR(intel_dp)) 1094 return; 1095 1096 mutex_lock(&intel_dp->psr.lock); 1097 if (!intel_dp->psr.enabled) 1098 goto unlock; 1099 1100 /* 1101 * Not possible to read EDP_PSR/PSR2_CTL registers as it is 1102 * enabled/disabled because of frontbuffer tracking and others. 1103 */ 1104 pipe_config->has_psr = true; 1105 pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; 1106 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1107 1108 if (!intel_dp->psr.psr2_enabled) 1109 goto unlock; 1110 1111 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 1112 val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); 1113 if (val & PSR2_MAN_TRK_CTL_ENABLE) 1114 pipe_config->enable_psr2_sel_fetch = true; 1115 } 1116 1117 if (DISPLAY_VER(dev_priv) >= 12) { 1118 val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder)); 1119 val &= EXITLINE_MASK; 1120 pipe_config->dc3co_exitline = val; 1121 } 1122 unlock: 1123 mutex_unlock(&intel_dp->psr.lock); 1124 } 1125 1126 static void intel_psr_activate(struct intel_dp *intel_dp) 1127 { 1128 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1129 enum transcoder transcoder = intel_dp->psr.transcoder; 1130 1131 if (transcoder_has_psr2(dev_priv, transcoder)) 1132 drm_WARN_ON(&dev_priv->drm, 1133 intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE); 1134 1135 drm_WARN_ON(&dev_priv->drm, 1136 intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE); 1137 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active); 1138 lockdep_assert_held(&intel_dp->psr.lock); 1139 1140 /* psr1 and psr2 are mutually exclusive.*/ 1141 if (intel_dp->psr.psr2_enabled) 1142 hsw_activate_psr2(intel_dp); 1143 else 1144 hsw_activate_psr1(intel_dp); 1145 1146 intel_dp->psr.active = true; 1147 } 1148 1149 static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp) 1150 { 1151 switch (intel_dp->psr.pipe) { 1152 case PIPE_A: 1153 return LATENCY_REPORTING_REMOVED_PIPE_A; 1154 case PIPE_B: 1155 return LATENCY_REPORTING_REMOVED_PIPE_B; 1156 case PIPE_C: 1157 return LATENCY_REPORTING_REMOVED_PIPE_C; 1158 case PIPE_D: 1159 return LATENCY_REPORTING_REMOVED_PIPE_D; 1160 default: 1161 MISSING_CASE(intel_dp->psr.pipe); 1162 return 0; 1163 } 1164 } 1165 1166 static void intel_psr_enable_source(struct intel_dp *intel_dp, 1167 const struct intel_crtc_state *crtc_state) 1168 { 1169 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1170 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1171 u32 mask; 1172 1173 /* 1174 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 1175 * mask LPSP to avoid dependency on other drivers that might block 1176 * runtime_pm besides preventing other hw tracking issues now we 1177 * can rely on frontbuffer tracking. 1178 */ 1179 mask = EDP_PSR_DEBUG_MASK_MEMUP | 1180 EDP_PSR_DEBUG_MASK_HPD | 1181 EDP_PSR_DEBUG_MASK_LPSP | 1182 EDP_PSR_DEBUG_MASK_MAX_SLEEP; 1183 1184 if (DISPLAY_VER(dev_priv) < 11) 1185 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 1186 1187 intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder), 1188 mask); 1189 1190 psr_irq_control(intel_dp); 1191 1192 if (intel_dp->psr.dc3co_exitline) { 1193 u32 val; 1194 1195 /* 1196 * TODO: if future platforms supports DC3CO in more than one 1197 * transcoder, EXITLINE will need to be unset when disabling PSR 1198 */ 1199 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder)); 1200 val &= ~EXITLINE_MASK; 1201 val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT; 1202 val |= EXITLINE_ENABLE; 1203 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); 1204 } 1205 1206 if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv)) 1207 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, 1208 intel_dp->psr.psr2_sel_fetch_enabled ? 1209 IGNORE_PSR2_HW_TRACKING : 0); 1210 1211 /* 1212 * Wa_16013835468 1213 * Wa_14015648006 1214 */ 1215 if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) || 1216 IS_DISPLAY_VER(dev_priv, 12, 13)) { 1217 u16 vtotal, vblank; 1218 1219 vtotal = crtc_state->uapi.adjusted_mode.crtc_vtotal - 1220 crtc_state->uapi.adjusted_mode.crtc_vdisplay; 1221 vblank = crtc_state->uapi.adjusted_mode.crtc_vblank_end - 1222 crtc_state->uapi.adjusted_mode.crtc_vblank_start; 1223 if (vblank > vtotal) 1224 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, 1225 wa_16013835468_bit_get(intel_dp)); 1226 } 1227 1228 if (intel_dp->psr.psr2_enabled) { 1229 if (DISPLAY_VER(dev_priv) == 9) 1230 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, 1231 PSR2_VSC_ENABLE_PROG_HEADER | 1232 PSR2_ADD_VERTICAL_LINE_COUNT); 1233 1234 /* 1235 * Wa_16014451276:adlp,mtl[a0,b0] 1236 * All supported adlp panels have 1-based X granularity, this may 1237 * cause issues if non-supported panels are used. 1238 */ 1239 if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1240 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 0, 1241 ADLP_1_BASED_X_GRANULARITY); 1242 else if (IS_ALDERLAKE_P(dev_priv)) 1243 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, 1244 ADLP_1_BASED_X_GRANULARITY); 1245 1246 /* Wa_16011168373:adl-p */ 1247 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1248 intel_de_rmw(dev_priv, 1249 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), 1250 TRANS_SET_CONTEXT_LATENCY_MASK, 1251 TRANS_SET_CONTEXT_LATENCY_VALUE(1)); 1252 1253 /* Wa_16012604467:adlp,mtl[a0,b0] */ 1254 if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1255 intel_de_rmw(dev_priv, 1256 MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0, 1257 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS); 1258 else if (IS_ALDERLAKE_P(dev_priv)) 1259 intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0, 1260 CLKGATE_DIS_MISC_DMASC_GATING_DIS); 1261 } 1262 } 1263 1264 static bool psr_interrupt_error_check(struct intel_dp *intel_dp) 1265 { 1266 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1267 u32 val; 1268 1269 /* 1270 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 1271 * will still keep the error set even after the reset done in the 1272 * irq_preinstall and irq_uninstall hooks. 1273 * And enabling in this situation cause the screen to freeze in the 1274 * first time that PSR HW tries to activate so lets keep PSR disabled 1275 * to avoid any rendering problems. 1276 */ 1277 if (DISPLAY_VER(dev_priv) >= 12) 1278 val = intel_de_read(dev_priv, 1279 TRANS_PSR_IIR(intel_dp->psr.transcoder)); 1280 else 1281 val = intel_de_read(dev_priv, EDP_PSR_IIR); 1282 val &= psr_irq_psr_error_bit_get(intel_dp); 1283 if (val) { 1284 intel_dp->psr.sink_not_reliable = true; 1285 drm_dbg_kms(&dev_priv->drm, 1286 "PSR interruption error set, not enabling PSR\n"); 1287 return false; 1288 } 1289 1290 return true; 1291 } 1292 1293 static void intel_psr_enable_locked(struct intel_dp *intel_dp, 1294 const struct intel_crtc_state *crtc_state) 1295 { 1296 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1297 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1298 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 1299 struct intel_encoder *encoder = &dig_port->base; 1300 u32 val; 1301 1302 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); 1303 1304 intel_dp->psr.psr2_enabled = crtc_state->has_psr2; 1305 intel_dp->psr.busy_frontbuffer_bits = 0; 1306 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1307 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; 1308 /* DC5/DC6 requires at least 6 idle frames */ 1309 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 1310 intel_dp->psr.dc3co_exit_delay = val; 1311 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; 1312 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; 1313 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 1314 intel_dp->psr.req_psr2_sdp_prior_scanline = 1315 crtc_state->req_psr2_sdp_prior_scanline; 1316 1317 if (!psr_interrupt_error_check(intel_dp)) 1318 return; 1319 1320 drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", 1321 intel_dp->psr.psr2_enabled ? "2" : "1"); 1322 intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc); 1323 intel_snps_phy_update_psr_power_state(dev_priv, phy, true); 1324 intel_psr_enable_sink(intel_dp); 1325 intel_psr_enable_source(intel_dp, crtc_state); 1326 intel_dp->psr.enabled = true; 1327 intel_dp->psr.paused = false; 1328 1329 intel_psr_activate(intel_dp); 1330 } 1331 1332 static void intel_psr_exit(struct intel_dp *intel_dp) 1333 { 1334 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1335 u32 val; 1336 1337 if (!intel_dp->psr.active) { 1338 if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) { 1339 val = intel_de_read(dev_priv, 1340 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1341 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE); 1342 } 1343 1344 val = intel_de_read(dev_priv, 1345 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1346 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE); 1347 1348 return; 1349 } 1350 1351 if (intel_dp->psr.psr2_enabled) { 1352 tgl_disallow_dc3co_on_psr2_exit(intel_dp); 1353 val = intel_de_read(dev_priv, 1354 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1355 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE)); 1356 val &= ~EDP_PSR2_ENABLE; 1357 intel_de_write(dev_priv, 1358 EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 1359 } else { 1360 val = intel_de_read(dev_priv, 1361 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1362 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE)); 1363 val &= ~EDP_PSR_ENABLE; 1364 intel_de_write(dev_priv, 1365 EDP_PSR_CTL(intel_dp->psr.transcoder), val); 1366 } 1367 intel_dp->psr.active = false; 1368 } 1369 1370 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) 1371 { 1372 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1373 i915_reg_t psr_status; 1374 u32 psr_status_mask; 1375 1376 if (intel_dp->psr.psr2_enabled) { 1377 psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 1378 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 1379 } else { 1380 psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder); 1381 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 1382 } 1383 1384 /* Wait till PSR is idle */ 1385 if (intel_de_wait_for_clear(dev_priv, psr_status, 1386 psr_status_mask, 2000)) 1387 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n"); 1388 } 1389 1390 static void intel_psr_disable_locked(struct intel_dp *intel_dp) 1391 { 1392 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1393 enum phy phy = intel_port_to_phy(dev_priv, 1394 dp_to_dig_port(intel_dp)->base.port); 1395 1396 lockdep_assert_held(&intel_dp->psr.lock); 1397 1398 if (!intel_dp->psr.enabled) 1399 return; 1400 1401 drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", 1402 intel_dp->psr.psr2_enabled ? "2" : "1"); 1403 1404 intel_psr_exit(intel_dp); 1405 intel_psr_wait_exit_locked(intel_dp); 1406 1407 /* Wa_1408330847 */ 1408 if (intel_dp->psr.psr2_sel_fetch_enabled && 1409 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1410 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1411 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0); 1412 1413 /* 1414 * Wa_16013835468 1415 * Wa_14015648006 1416 */ 1417 if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) || 1418 IS_DISPLAY_VER(dev_priv, 12, 13)) 1419 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 1420 wa_16013835468_bit_get(intel_dp), 0); 1421 1422 if (intel_dp->psr.psr2_enabled) { 1423 /* Wa_16011168373:adl-p */ 1424 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1425 intel_de_rmw(dev_priv, 1426 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), 1427 TRANS_SET_CONTEXT_LATENCY_MASK, 0); 1428 1429 /* Wa_16012604467:adlp,mtl[a0,b0] */ 1430 if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1431 intel_de_rmw(dev_priv, 1432 MTL_CLKGATE_DIS_TRANS(intel_dp->psr.transcoder), 1433 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); 1434 else if (IS_ALDERLAKE_P(dev_priv)) 1435 intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 1436 CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0); 1437 } 1438 1439 intel_snps_phy_update_psr_power_state(dev_priv, phy, false); 1440 1441 /* Disable PSR on Sink */ 1442 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 1443 1444 if (intel_dp->psr.psr2_enabled) 1445 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); 1446 1447 intel_dp->psr.enabled = false; 1448 intel_dp->psr.psr2_enabled = false; 1449 intel_dp->psr.psr2_sel_fetch_enabled = false; 1450 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 1451 } 1452 1453 /** 1454 * intel_psr_disable - Disable PSR 1455 * @intel_dp: Intel DP 1456 * @old_crtc_state: old CRTC state 1457 * 1458 * This function needs to be called before disabling pipe. 1459 */ 1460 void intel_psr_disable(struct intel_dp *intel_dp, 1461 const struct intel_crtc_state *old_crtc_state) 1462 { 1463 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1464 1465 if (!old_crtc_state->has_psr) 1466 return; 1467 1468 if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp))) 1469 return; 1470 1471 mutex_lock(&intel_dp->psr.lock); 1472 1473 intel_psr_disable_locked(intel_dp); 1474 1475 mutex_unlock(&intel_dp->psr.lock); 1476 cancel_work_sync(&intel_dp->psr.work); 1477 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); 1478 } 1479 1480 /** 1481 * intel_psr_pause - Pause PSR 1482 * @intel_dp: Intel DP 1483 * 1484 * This function need to be called after enabling psr. 1485 */ 1486 void intel_psr_pause(struct intel_dp *intel_dp) 1487 { 1488 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1489 struct intel_psr *psr = &intel_dp->psr; 1490 1491 if (!CAN_PSR(intel_dp)) 1492 return; 1493 1494 mutex_lock(&psr->lock); 1495 1496 if (!psr->enabled) { 1497 mutex_unlock(&psr->lock); 1498 return; 1499 } 1500 1501 /* If we ever hit this, we will need to add refcount to pause/resume */ 1502 drm_WARN_ON(&dev_priv->drm, psr->paused); 1503 1504 intel_psr_exit(intel_dp); 1505 intel_psr_wait_exit_locked(intel_dp); 1506 psr->paused = true; 1507 1508 mutex_unlock(&psr->lock); 1509 1510 cancel_work_sync(&psr->work); 1511 cancel_delayed_work_sync(&psr->dc3co_work); 1512 } 1513 1514 /** 1515 * intel_psr_resume - Resume PSR 1516 * @intel_dp: Intel DP 1517 * 1518 * This function need to be called after pausing psr. 1519 */ 1520 void intel_psr_resume(struct intel_dp *intel_dp) 1521 { 1522 struct intel_psr *psr = &intel_dp->psr; 1523 1524 if (!CAN_PSR(intel_dp)) 1525 return; 1526 1527 mutex_lock(&psr->lock); 1528 1529 if (!psr->paused) 1530 goto unlock; 1531 1532 psr->paused = false; 1533 intel_psr_activate(intel_dp); 1534 1535 unlock: 1536 mutex_unlock(&psr->lock); 1537 } 1538 1539 static u32 man_trk_ctl_enable_bit_get(struct drm_i915_private *dev_priv) 1540 { 1541 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ? 0 : 1542 PSR2_MAN_TRK_CTL_ENABLE; 1543 } 1544 1545 static u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private *dev_priv) 1546 { 1547 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ? 1548 ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME : 1549 PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 1550 } 1551 1552 static u32 man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev_priv) 1553 { 1554 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ? 1555 ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE : 1556 PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; 1557 } 1558 1559 static u32 man_trk_ctl_continuos_full_frame(struct drm_i915_private *dev_priv) 1560 { 1561 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ? 1562 ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME : 1563 PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME; 1564 } 1565 1566 static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) 1567 { 1568 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1569 1570 if (intel_dp->psr.psr2_sel_fetch_enabled) 1571 intel_de_write(dev_priv, 1572 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 1573 man_trk_ctl_enable_bit_get(dev_priv) | 1574 man_trk_ctl_partial_frame_bit_get(dev_priv) | 1575 man_trk_ctl_single_full_frame_bit_get(dev_priv) | 1576 man_trk_ctl_continuos_full_frame(dev_priv)); 1577 1578 /* 1579 * Display WA #0884: skl+ 1580 * This documented WA for bxt can be safely applied 1581 * broadly so we can force HW tracking to exit PSR 1582 * instead of disabling and re-enabling. 1583 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 1584 * but it makes more sense write to the current active 1585 * pipe. 1586 * 1587 * This workaround do not exist for platforms with display 10 or newer 1588 * but testing proved that it works for up display 13, for newer 1589 * than that testing will be needed. 1590 */ 1591 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 1592 } 1593 1594 void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane, 1595 const struct intel_crtc_state *crtc_state) 1596 { 1597 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1598 enum pipe pipe = plane->pipe; 1599 1600 if (!crtc_state->enable_psr2_sel_fetch) 1601 return; 1602 1603 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0); 1604 } 1605 1606 void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, 1607 const struct intel_crtc_state *crtc_state, 1608 const struct intel_plane_state *plane_state, 1609 int color_plane) 1610 { 1611 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1612 enum pipe pipe = plane->pipe; 1613 const struct drm_rect *clip; 1614 u32 val; 1615 int x, y; 1616 1617 if (!crtc_state->enable_psr2_sel_fetch) 1618 return; 1619 1620 if (plane->id == PLANE_CURSOR) { 1621 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 1622 plane_state->ctl); 1623 return; 1624 } 1625 1626 clip = &plane_state->psr2_sel_fetch_area; 1627 1628 val = (clip->y1 + plane_state->uapi.dst.y1) << 16; 1629 val |= plane_state->uapi.dst.x1; 1630 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); 1631 1632 x = plane_state->view.color_plane[color_plane].x; 1633 1634 /* 1635 * From Bspec: UV surface Start Y Position = half of Y plane Y 1636 * start position. 1637 */ 1638 if (!color_plane) 1639 y = plane_state->view.color_plane[color_plane].y + clip->y1; 1640 else 1641 y = plane_state->view.color_plane[color_plane].y + clip->y1 / 2; 1642 1643 val = y << 16 | x; 1644 1645 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), 1646 val); 1647 1648 /* Sizes are 0 based */ 1649 val = (drm_rect_height(clip) - 1) << 16; 1650 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; 1651 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); 1652 1653 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 1654 PLANE_SEL_FETCH_CTL_ENABLE); 1655 } 1656 1657 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) 1658 { 1659 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1660 struct intel_encoder *encoder; 1661 1662 if (!crtc_state->enable_psr2_sel_fetch) 1663 return; 1664 1665 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, 1666 crtc_state->uapi.encoder_mask) { 1667 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1668 1669 lockdep_assert_held(&intel_dp->psr.lock); 1670 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) 1671 return; 1672 break; 1673 } 1674 1675 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder), 1676 crtc_state->psr2_man_track_ctl); 1677 } 1678 1679 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, 1680 struct drm_rect *clip, bool full_update) 1681 { 1682 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1683 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1684 u32 val = man_trk_ctl_enable_bit_get(dev_priv); 1685 1686 /* SF partial frame enable has to be set even on full update */ 1687 val |= man_trk_ctl_partial_frame_bit_get(dev_priv); 1688 1689 if (full_update) { 1690 val |= man_trk_ctl_single_full_frame_bit_get(dev_priv); 1691 val |= man_trk_ctl_continuos_full_frame(dev_priv); 1692 goto exit; 1693 } 1694 1695 if (clip->y1 == -1) 1696 goto exit; 1697 1698 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) { 1699 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1); 1700 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 - 1); 1701 } else { 1702 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4); 1703 1704 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1); 1705 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1); 1706 } 1707 exit: 1708 crtc_state->psr2_man_track_ctl = val; 1709 } 1710 1711 static void clip_area_update(struct drm_rect *overlap_damage_area, 1712 struct drm_rect *damage_area, 1713 struct drm_rect *pipe_src) 1714 { 1715 if (!drm_rect_intersect(damage_area, pipe_src)) 1716 return; 1717 1718 if (overlap_damage_area->y1 == -1) { 1719 overlap_damage_area->y1 = damage_area->y1; 1720 overlap_damage_area->y2 = damage_area->y2; 1721 return; 1722 } 1723 1724 if (damage_area->y1 < overlap_damage_area->y1) 1725 overlap_damage_area->y1 = damage_area->y1; 1726 1727 if (damage_area->y2 > overlap_damage_area->y2) 1728 overlap_damage_area->y2 = damage_area->y2; 1729 } 1730 1731 static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state, 1732 struct drm_rect *pipe_clip) 1733 { 1734 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1735 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1736 u16 y_alignment; 1737 1738 /* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */ 1739 if (crtc_state->dsc.compression_enable && 1740 (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)) 1741 y_alignment = vdsc_cfg->slice_height; 1742 else 1743 y_alignment = crtc_state->su_y_granularity; 1744 1745 pipe_clip->y1 -= pipe_clip->y1 % y_alignment; 1746 if (pipe_clip->y2 % y_alignment) 1747 pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment; 1748 } 1749 1750 /* 1751 * TODO: Not clear how to handle planes with negative position, 1752 * also planes are not updated if they have a negative X 1753 * position so for now doing a full update in this cases 1754 * 1755 * Plane scaling and rotation is not supported by selective fetch and both 1756 * properties can change without a modeset, so need to be check at every 1757 * atomic commit. 1758 */ 1759 static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state) 1760 { 1761 if (plane_state->uapi.dst.y1 < 0 || 1762 plane_state->uapi.dst.x1 < 0 || 1763 plane_state->scaler_id >= 0 || 1764 plane_state->uapi.rotation != DRM_MODE_ROTATE_0) 1765 return false; 1766 1767 return true; 1768 } 1769 1770 /* 1771 * Check for pipe properties that is not supported by selective fetch. 1772 * 1773 * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed 1774 * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch 1775 * enabled and going to the full update path. 1776 */ 1777 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state) 1778 { 1779 if (crtc_state->scaler_state.scaler_id >= 0) 1780 return false; 1781 1782 return true; 1783 } 1784 1785 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 1786 struct intel_crtc *crtc) 1787 { 1788 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1789 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 1790 struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 }; 1791 struct intel_plane_state *new_plane_state, *old_plane_state; 1792 struct intel_plane *plane; 1793 bool full_update = false; 1794 int i, ret; 1795 1796 if (!crtc_state->enable_psr2_sel_fetch) 1797 return 0; 1798 1799 if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) { 1800 full_update = true; 1801 goto skip_sel_fetch_set_loop; 1802 } 1803 1804 /* 1805 * Calculate minimal selective fetch area of each plane and calculate 1806 * the pipe damaged area. 1807 * In the next loop the plane selective fetch area will actually be set 1808 * using whole pipe damaged area. 1809 */ 1810 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1811 new_plane_state, i) { 1812 struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1, 1813 .x2 = INT_MAX }; 1814 1815 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) 1816 continue; 1817 1818 if (!new_plane_state->uapi.visible && 1819 !old_plane_state->uapi.visible) 1820 continue; 1821 1822 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 1823 full_update = true; 1824 break; 1825 } 1826 1827 /* 1828 * If visibility or plane moved, mark the whole plane area as 1829 * damaged as it needs to be complete redraw in the new and old 1830 * position. 1831 */ 1832 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || 1833 !drm_rect_equals(&new_plane_state->uapi.dst, 1834 &old_plane_state->uapi.dst)) { 1835 if (old_plane_state->uapi.visible) { 1836 damaged_area.y1 = old_plane_state->uapi.dst.y1; 1837 damaged_area.y2 = old_plane_state->uapi.dst.y2; 1838 clip_area_update(&pipe_clip, &damaged_area, 1839 &crtc_state->pipe_src); 1840 } 1841 1842 if (new_plane_state->uapi.visible) { 1843 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1844 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1845 clip_area_update(&pipe_clip, &damaged_area, 1846 &crtc_state->pipe_src); 1847 } 1848 continue; 1849 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { 1850 /* If alpha changed mark the whole plane area as damaged */ 1851 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1852 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1853 clip_area_update(&pipe_clip, &damaged_area, 1854 &crtc_state->pipe_src); 1855 continue; 1856 } 1857 1858 src = drm_plane_state_src(&new_plane_state->uapi); 1859 drm_rect_fp_to_int(&src, &src); 1860 1861 if (!drm_atomic_helper_damage_merged(&old_plane_state->uapi, 1862 &new_plane_state->uapi, &damaged_area)) 1863 continue; 1864 1865 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; 1866 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; 1867 damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1; 1868 damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1; 1869 1870 clip_area_update(&pipe_clip, &damaged_area, &crtc_state->pipe_src); 1871 } 1872 1873 /* 1874 * TODO: For now we are just using full update in case 1875 * selective fetch area calculation fails. To optimize this we 1876 * should identify cases where this happens and fix the area 1877 * calculation for those. 1878 */ 1879 if (pipe_clip.y1 == -1) { 1880 drm_info_once(&dev_priv->drm, 1881 "Selective fetch area calculation failed in pipe %c\n", 1882 pipe_name(crtc->pipe)); 1883 full_update = true; 1884 } 1885 1886 if (full_update) 1887 goto skip_sel_fetch_set_loop; 1888 1889 /* Wa_14014971492 */ 1890 if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) || 1891 IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) && 1892 crtc_state->splitter.enable) 1893 pipe_clip.y1 = 0; 1894 1895 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 1896 if (ret) 1897 return ret; 1898 1899 intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip); 1900 1901 /* 1902 * Now that we have the pipe damaged area check if it intersect with 1903 * every plane, if it does set the plane selective fetch area. 1904 */ 1905 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1906 new_plane_state, i) { 1907 struct drm_rect *sel_fetch_area, inter; 1908 struct intel_plane *linked = new_plane_state->planar_linked_plane; 1909 1910 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || 1911 !new_plane_state->uapi.visible) 1912 continue; 1913 1914 inter = pipe_clip; 1915 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) 1916 continue; 1917 1918 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 1919 full_update = true; 1920 break; 1921 } 1922 1923 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 1924 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; 1925 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; 1926 crtc_state->update_planes |= BIT(plane->id); 1927 1928 /* 1929 * Sel_fetch_area is calculated for UV plane. Use 1930 * same area for Y plane as well. 1931 */ 1932 if (linked) { 1933 struct intel_plane_state *linked_new_plane_state; 1934 struct drm_rect *linked_sel_fetch_area; 1935 1936 linked_new_plane_state = intel_atomic_get_plane_state(state, linked); 1937 if (IS_ERR(linked_new_plane_state)) 1938 return PTR_ERR(linked_new_plane_state); 1939 1940 linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area; 1941 linked_sel_fetch_area->y1 = sel_fetch_area->y1; 1942 linked_sel_fetch_area->y2 = sel_fetch_area->y2; 1943 crtc_state->update_planes |= BIT(linked->id); 1944 } 1945 } 1946 1947 skip_sel_fetch_set_loop: 1948 psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update); 1949 return 0; 1950 } 1951 1952 void intel_psr_pre_plane_update(struct intel_atomic_state *state, 1953 struct intel_crtc *crtc) 1954 { 1955 struct drm_i915_private *i915 = to_i915(state->base.dev); 1956 const struct intel_crtc_state *old_crtc_state = 1957 intel_atomic_get_old_crtc_state(state, crtc); 1958 const struct intel_crtc_state *new_crtc_state = 1959 intel_atomic_get_new_crtc_state(state, crtc); 1960 struct intel_encoder *encoder; 1961 1962 if (!HAS_PSR(i915)) 1963 return; 1964 1965 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 1966 old_crtc_state->uapi.encoder_mask) { 1967 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1968 struct intel_psr *psr = &intel_dp->psr; 1969 bool needs_to_disable = false; 1970 1971 mutex_lock(&psr->lock); 1972 1973 /* 1974 * Reasons to disable: 1975 * - PSR disabled in new state 1976 * - All planes will go inactive 1977 * - Changing between PSR versions 1978 */ 1979 needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state); 1980 needs_to_disable |= !new_crtc_state->has_psr; 1981 needs_to_disable |= !new_crtc_state->active_planes; 1982 needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled; 1983 1984 if (psr->enabled && needs_to_disable) 1985 intel_psr_disable_locked(intel_dp); 1986 1987 mutex_unlock(&psr->lock); 1988 } 1989 } 1990 1991 static void _intel_psr_post_plane_update(const struct intel_atomic_state *state, 1992 const struct intel_crtc_state *crtc_state) 1993 { 1994 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1995 struct intel_encoder *encoder; 1996 1997 if (!crtc_state->has_psr) 1998 return; 1999 2000 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 2001 crtc_state->uapi.encoder_mask) { 2002 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2003 struct intel_psr *psr = &intel_dp->psr; 2004 2005 mutex_lock(&psr->lock); 2006 2007 if (psr->sink_not_reliable) 2008 goto exit; 2009 2010 drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes); 2011 2012 /* Only enable if there is active planes */ 2013 if (!psr->enabled && crtc_state->active_planes) 2014 intel_psr_enable_locked(intel_dp, crtc_state); 2015 2016 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 2017 if (crtc_state->crc_enabled && psr->enabled) 2018 psr_force_hw_tracking_exit(intel_dp); 2019 2020 exit: 2021 mutex_unlock(&psr->lock); 2022 } 2023 } 2024 2025 void intel_psr_post_plane_update(const struct intel_atomic_state *state) 2026 { 2027 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2028 struct intel_crtc_state *crtc_state; 2029 struct intel_crtc *crtc; 2030 int i; 2031 2032 if (!HAS_PSR(dev_priv)) 2033 return; 2034 2035 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) 2036 _intel_psr_post_plane_update(state, crtc_state); 2037 } 2038 2039 static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp) 2040 { 2041 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2042 2043 /* 2044 * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough. 2045 * As all higher states has bit 4 of PSR2 state set we can just wait for 2046 * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared. 2047 */ 2048 return intel_de_wait_for_clear(dev_priv, 2049 EDP_PSR2_STATUS(intel_dp->psr.transcoder), 2050 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50); 2051 } 2052 2053 static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp) 2054 { 2055 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2056 2057 /* 2058 * From bspec: Panel Self Refresh (BDW+) 2059 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 2060 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 2061 * defensive enough to cover everything. 2062 */ 2063 return intel_de_wait_for_clear(dev_priv, 2064 EDP_PSR_STATUS(intel_dp->psr.transcoder), 2065 EDP_PSR_STATUS_STATE_MASK, 50); 2066 } 2067 2068 /** 2069 * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update 2070 * @new_crtc_state: new CRTC state 2071 * 2072 * This function is expected to be called from pipe_update_start() where it is 2073 * not expected to race with PSR enable or disable. 2074 */ 2075 void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state) 2076 { 2077 struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev); 2078 struct intel_encoder *encoder; 2079 2080 if (!new_crtc_state->has_psr) 2081 return; 2082 2083 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, 2084 new_crtc_state->uapi.encoder_mask) { 2085 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2086 int ret; 2087 2088 lockdep_assert_held(&intel_dp->psr.lock); 2089 2090 if (!intel_dp->psr.enabled) 2091 continue; 2092 2093 if (intel_dp->psr.psr2_enabled) 2094 ret = _psr2_ready_for_pipe_update_locked(intel_dp); 2095 else 2096 ret = _psr1_ready_for_pipe_update_locked(intel_dp); 2097 2098 if (ret) 2099 drm_err(&dev_priv->drm, "PSR wait timed out, atomic update may fail\n"); 2100 } 2101 } 2102 2103 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) 2104 { 2105 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2106 i915_reg_t reg; 2107 u32 mask; 2108 int err; 2109 2110 if (!intel_dp->psr.enabled) 2111 return false; 2112 2113 if (intel_dp->psr.psr2_enabled) { 2114 reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 2115 mask = EDP_PSR2_STATUS_STATE_MASK; 2116 } else { 2117 reg = EDP_PSR_STATUS(intel_dp->psr.transcoder); 2118 mask = EDP_PSR_STATUS_STATE_MASK; 2119 } 2120 2121 mutex_unlock(&intel_dp->psr.lock); 2122 2123 err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); 2124 if (err) 2125 drm_err(&dev_priv->drm, 2126 "Timed out waiting for PSR Idle for re-enable\n"); 2127 2128 /* After the unlocked wait, verify that PSR is still wanted! */ 2129 mutex_lock(&intel_dp->psr.lock); 2130 return err == 0 && intel_dp->psr.enabled; 2131 } 2132 2133 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) 2134 { 2135 struct drm_connector_list_iter conn_iter; 2136 struct drm_modeset_acquire_ctx ctx; 2137 struct drm_atomic_state *state; 2138 struct drm_connector *conn; 2139 int err = 0; 2140 2141 state = drm_atomic_state_alloc(&dev_priv->drm); 2142 if (!state) 2143 return -ENOMEM; 2144 2145 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 2146 state->acquire_ctx = &ctx; 2147 2148 retry: 2149 2150 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 2151 drm_for_each_connector_iter(conn, &conn_iter) { 2152 struct drm_connector_state *conn_state; 2153 struct drm_crtc_state *crtc_state; 2154 2155 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) 2156 continue; 2157 2158 conn_state = drm_atomic_get_connector_state(state, conn); 2159 if (IS_ERR(conn_state)) { 2160 err = PTR_ERR(conn_state); 2161 break; 2162 } 2163 2164 if (!conn_state->crtc) 2165 continue; 2166 2167 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); 2168 if (IS_ERR(crtc_state)) { 2169 err = PTR_ERR(crtc_state); 2170 break; 2171 } 2172 2173 /* Mark mode as changed to trigger a pipe->update() */ 2174 crtc_state->mode_changed = true; 2175 } 2176 drm_connector_list_iter_end(&conn_iter); 2177 2178 if (err == 0) 2179 err = drm_atomic_commit(state); 2180 2181 if (err == -EDEADLK) { 2182 drm_atomic_state_clear(state); 2183 err = drm_modeset_backoff(&ctx); 2184 if (!err) 2185 goto retry; 2186 } 2187 2188 drm_modeset_drop_locks(&ctx); 2189 drm_modeset_acquire_fini(&ctx); 2190 drm_atomic_state_put(state); 2191 2192 return err; 2193 } 2194 2195 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) 2196 { 2197 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2198 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 2199 u32 old_mode; 2200 int ret; 2201 2202 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || 2203 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 2204 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); 2205 return -EINVAL; 2206 } 2207 2208 ret = mutex_lock_interruptible(&intel_dp->psr.lock); 2209 if (ret) 2210 return ret; 2211 2212 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; 2213 intel_dp->psr.debug = val; 2214 2215 /* 2216 * Do it right away if it's already enabled, otherwise it will be done 2217 * when enabling the source. 2218 */ 2219 if (intel_dp->psr.enabled) 2220 psr_irq_control(intel_dp); 2221 2222 mutex_unlock(&intel_dp->psr.lock); 2223 2224 if (old_mode != mode) 2225 ret = intel_psr_fastset_force(dev_priv); 2226 2227 return ret; 2228 } 2229 2230 static void intel_psr_handle_irq(struct intel_dp *intel_dp) 2231 { 2232 struct intel_psr *psr = &intel_dp->psr; 2233 2234 intel_psr_disable_locked(intel_dp); 2235 psr->sink_not_reliable = true; 2236 /* let's make sure that sink is awaken */ 2237 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 2238 } 2239 2240 static void intel_psr_work(struct work_struct *work) 2241 { 2242 struct intel_dp *intel_dp = 2243 container_of(work, typeof(*intel_dp), psr.work); 2244 2245 mutex_lock(&intel_dp->psr.lock); 2246 2247 if (!intel_dp->psr.enabled) 2248 goto unlock; 2249 2250 if (READ_ONCE(intel_dp->psr.irq_aux_error)) 2251 intel_psr_handle_irq(intel_dp); 2252 2253 /* 2254 * We have to make sure PSR is ready for re-enable 2255 * otherwise it keeps disabled until next full enable/disable cycle. 2256 * PSR might take some time to get fully disabled 2257 * and be ready for re-enable. 2258 */ 2259 if (!__psr_wait_for_idle_locked(intel_dp)) 2260 goto unlock; 2261 2262 /* 2263 * The delayed work can race with an invalidate hence we need to 2264 * recheck. Since psr_flush first clears this and then reschedules we 2265 * won't ever miss a flush when bailing out here. 2266 */ 2267 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) 2268 goto unlock; 2269 2270 intel_psr_activate(intel_dp); 2271 unlock: 2272 mutex_unlock(&intel_dp->psr.lock); 2273 } 2274 2275 static void _psr_invalidate_handle(struct intel_dp *intel_dp) 2276 { 2277 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2278 2279 if (intel_dp->psr.psr2_sel_fetch_enabled) { 2280 u32 val; 2281 2282 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { 2283 /* Send one update otherwise lag is observed in screen */ 2284 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 2285 return; 2286 } 2287 2288 val = man_trk_ctl_enable_bit_get(dev_priv) | 2289 man_trk_ctl_partial_frame_bit_get(dev_priv) | 2290 man_trk_ctl_continuos_full_frame(dev_priv); 2291 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), val); 2292 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 2293 intel_dp->psr.psr2_sel_fetch_cff_enabled = true; 2294 } else { 2295 intel_psr_exit(intel_dp); 2296 } 2297 } 2298 2299 /** 2300 * intel_psr_invalidate - Invalidate PSR 2301 * @dev_priv: i915 device 2302 * @frontbuffer_bits: frontbuffer plane tracking bits 2303 * @origin: which operation caused the invalidate 2304 * 2305 * Since the hardware frontbuffer tracking has gaps we need to integrate 2306 * with the software frontbuffer tracking. This function gets called every 2307 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 2308 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 2309 * 2310 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 2311 */ 2312 void intel_psr_invalidate(struct drm_i915_private *dev_priv, 2313 unsigned frontbuffer_bits, enum fb_op_origin origin) 2314 { 2315 struct intel_encoder *encoder; 2316 2317 if (origin == ORIGIN_FLIP) 2318 return; 2319 2320 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2321 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 2322 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2323 2324 mutex_lock(&intel_dp->psr.lock); 2325 if (!intel_dp->psr.enabled) { 2326 mutex_unlock(&intel_dp->psr.lock); 2327 continue; 2328 } 2329 2330 pipe_frontbuffer_bits &= 2331 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 2332 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; 2333 2334 if (pipe_frontbuffer_bits) 2335 _psr_invalidate_handle(intel_dp); 2336 2337 mutex_unlock(&intel_dp->psr.lock); 2338 } 2339 } 2340 /* 2341 * When we will be completely rely on PSR2 S/W tracking in future, 2342 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP 2343 * event also therefore tgl_dc3co_flush_locked() require to be changed 2344 * accordingly in future. 2345 */ 2346 static void 2347 tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits, 2348 enum fb_op_origin origin) 2349 { 2350 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled || 2351 !intel_dp->psr.active) 2352 return; 2353 2354 /* 2355 * At every frontbuffer flush flip event modified delay of delayed work, 2356 * when delayed work schedules that means display has been idle. 2357 */ 2358 if (!(frontbuffer_bits & 2359 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) 2360 return; 2361 2362 tgl_psr2_enable_dc3co(intel_dp); 2363 mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work, 2364 intel_dp->psr.dc3co_exit_delay); 2365 } 2366 2367 static void _psr_flush_handle(struct intel_dp *intel_dp) 2368 { 2369 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2370 2371 if (intel_dp->psr.psr2_sel_fetch_enabled) { 2372 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { 2373 /* can we turn CFF off? */ 2374 if (intel_dp->psr.busy_frontbuffer_bits == 0) { 2375 u32 val = man_trk_ctl_enable_bit_get(dev_priv) | 2376 man_trk_ctl_partial_frame_bit_get(dev_priv) | 2377 man_trk_ctl_single_full_frame_bit_get(dev_priv) | 2378 man_trk_ctl_continuos_full_frame(dev_priv); 2379 2380 /* 2381 * Set psr2_sel_fetch_cff_enabled as false to allow selective 2382 * updates. Still keep cff bit enabled as we don't have proper 2383 * SU configuration in case update is sent for any reason after 2384 * sff bit gets cleared by the HW on next vblank. 2385 */ 2386 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 2387 val); 2388 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 2389 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 2390 } 2391 } else { 2392 /* 2393 * continuous full frame is disabled, only a single full 2394 * frame is required 2395 */ 2396 psr_force_hw_tracking_exit(intel_dp); 2397 } 2398 } else { 2399 psr_force_hw_tracking_exit(intel_dp); 2400 2401 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) 2402 schedule_work(&intel_dp->psr.work); 2403 } 2404 } 2405 2406 /** 2407 * intel_psr_flush - Flush PSR 2408 * @dev_priv: i915 device 2409 * @frontbuffer_bits: frontbuffer plane tracking bits 2410 * @origin: which operation caused the flush 2411 * 2412 * Since the hardware frontbuffer tracking has gaps we need to integrate 2413 * with the software frontbuffer tracking. This function gets called every 2414 * time frontbuffer rendering has completed and flushed out to memory. PSR 2415 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 2416 * 2417 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 2418 */ 2419 void intel_psr_flush(struct drm_i915_private *dev_priv, 2420 unsigned frontbuffer_bits, enum fb_op_origin origin) 2421 { 2422 struct intel_encoder *encoder; 2423 2424 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2425 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 2426 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2427 2428 mutex_lock(&intel_dp->psr.lock); 2429 if (!intel_dp->psr.enabled) { 2430 mutex_unlock(&intel_dp->psr.lock); 2431 continue; 2432 } 2433 2434 pipe_frontbuffer_bits &= 2435 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 2436 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; 2437 2438 /* 2439 * If the PSR is paused by an explicit intel_psr_paused() call, 2440 * we have to ensure that the PSR is not activated until 2441 * intel_psr_resume() is called. 2442 */ 2443 if (intel_dp->psr.paused) 2444 goto unlock; 2445 2446 if (origin == ORIGIN_FLIP || 2447 (origin == ORIGIN_CURSOR_UPDATE && 2448 !intel_dp->psr.psr2_sel_fetch_enabled)) { 2449 tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin); 2450 goto unlock; 2451 } 2452 2453 if (pipe_frontbuffer_bits == 0) 2454 goto unlock; 2455 2456 /* By definition flush = invalidate + flush */ 2457 _psr_flush_handle(intel_dp); 2458 unlock: 2459 mutex_unlock(&intel_dp->psr.lock); 2460 } 2461 } 2462 2463 /** 2464 * intel_psr_init - Init basic PSR work and mutex. 2465 * @intel_dp: Intel DP 2466 * 2467 * This function is called after the initializing connector. 2468 * (the initializing of connector treats the handling of connector capabilities) 2469 * And it initializes basic PSR stuff for each DP Encoder. 2470 */ 2471 void intel_psr_init(struct intel_dp *intel_dp) 2472 { 2473 struct intel_connector *connector = intel_dp->attached_connector; 2474 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2475 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2476 2477 if (!HAS_PSR(dev_priv)) 2478 return; 2479 2480 /* 2481 * HSW spec explicitly says PSR is tied to port A. 2482 * BDW+ platforms have a instance of PSR registers per transcoder but 2483 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder 2484 * than eDP one. 2485 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11. 2486 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11. 2487 * But GEN12 supports a instance of PSR registers per transcoder. 2488 */ 2489 if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) { 2490 drm_dbg_kms(&dev_priv->drm, 2491 "PSR condition failed: Port not supported\n"); 2492 return; 2493 } 2494 2495 intel_dp->psr.source_support = true; 2496 2497 /* Set link_standby x link_off defaults */ 2498 if (DISPLAY_VER(dev_priv) < 12) 2499 /* For new platforms up to TGL let's respect VBT back again */ 2500 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link; 2501 2502 INIT_WORK(&intel_dp->psr.work, intel_psr_work); 2503 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); 2504 mutex_init(&intel_dp->psr.lock); 2505 } 2506 2507 static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 2508 u8 *status, u8 *error_status) 2509 { 2510 struct drm_dp_aux *aux = &intel_dp->aux; 2511 int ret; 2512 2513 ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status); 2514 if (ret != 1) 2515 return ret; 2516 2517 ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status); 2518 if (ret != 1) 2519 return ret; 2520 2521 *status = *status & DP_PSR_SINK_STATE_MASK; 2522 2523 return 0; 2524 } 2525 2526 static void psr_alpm_check(struct intel_dp *intel_dp) 2527 { 2528 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2529 struct drm_dp_aux *aux = &intel_dp->aux; 2530 struct intel_psr *psr = &intel_dp->psr; 2531 u8 val; 2532 int r; 2533 2534 if (!psr->psr2_enabled) 2535 return; 2536 2537 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); 2538 if (r != 1) { 2539 drm_err(&dev_priv->drm, "Error reading ALPM status\n"); 2540 return; 2541 } 2542 2543 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) { 2544 intel_psr_disable_locked(intel_dp); 2545 psr->sink_not_reliable = true; 2546 drm_dbg_kms(&dev_priv->drm, 2547 "ALPM lock timeout error, disabling PSR\n"); 2548 2549 /* Clearing error */ 2550 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); 2551 } 2552 } 2553 2554 static void psr_capability_changed_check(struct intel_dp *intel_dp) 2555 { 2556 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2557 struct intel_psr *psr = &intel_dp->psr; 2558 u8 val; 2559 int r; 2560 2561 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 2562 if (r != 1) { 2563 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n"); 2564 return; 2565 } 2566 2567 if (val & DP_PSR_CAPS_CHANGE) { 2568 intel_psr_disable_locked(intel_dp); 2569 psr->sink_not_reliable = true; 2570 drm_dbg_kms(&dev_priv->drm, 2571 "Sink PSR capability changed, disabling PSR\n"); 2572 2573 /* Clearing it */ 2574 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 2575 } 2576 } 2577 2578 void intel_psr_short_pulse(struct intel_dp *intel_dp) 2579 { 2580 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2581 struct intel_psr *psr = &intel_dp->psr; 2582 u8 status, error_status; 2583 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 2584 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 2585 DP_PSR_LINK_CRC_ERROR; 2586 2587 if (!CAN_PSR(intel_dp)) 2588 return; 2589 2590 mutex_lock(&psr->lock); 2591 2592 if (!psr->enabled) 2593 goto exit; 2594 2595 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 2596 drm_err(&dev_priv->drm, 2597 "Error reading PSR status or error status\n"); 2598 goto exit; 2599 } 2600 2601 if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) { 2602 intel_psr_disable_locked(intel_dp); 2603 psr->sink_not_reliable = true; 2604 } 2605 2606 if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status) 2607 drm_dbg_kms(&dev_priv->drm, 2608 "PSR sink internal error, disabling PSR\n"); 2609 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 2610 drm_dbg_kms(&dev_priv->drm, 2611 "PSR RFB storage error, disabling PSR\n"); 2612 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 2613 drm_dbg_kms(&dev_priv->drm, 2614 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 2615 if (error_status & DP_PSR_LINK_CRC_ERROR) 2616 drm_dbg_kms(&dev_priv->drm, 2617 "PSR Link CRC error, disabling PSR\n"); 2618 2619 if (error_status & ~errors) 2620 drm_err(&dev_priv->drm, 2621 "PSR_ERROR_STATUS unhandled errors %x\n", 2622 error_status & ~errors); 2623 /* clear status register */ 2624 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 2625 2626 psr_alpm_check(intel_dp); 2627 psr_capability_changed_check(intel_dp); 2628 2629 exit: 2630 mutex_unlock(&psr->lock); 2631 } 2632 2633 bool intel_psr_enabled(struct intel_dp *intel_dp) 2634 { 2635 bool ret; 2636 2637 if (!CAN_PSR(intel_dp)) 2638 return false; 2639 2640 mutex_lock(&intel_dp->psr.lock); 2641 ret = intel_dp->psr.enabled; 2642 mutex_unlock(&intel_dp->psr.lock); 2643 2644 return ret; 2645 } 2646 2647 /** 2648 * intel_psr_lock - grab PSR lock 2649 * @crtc_state: the crtc state 2650 * 2651 * This is initially meant to be used by around CRTC update, when 2652 * vblank sensitive registers are updated and we need grab the lock 2653 * before it to avoid vblank evasion. 2654 */ 2655 void intel_psr_lock(const struct intel_crtc_state *crtc_state) 2656 { 2657 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2658 struct intel_encoder *encoder; 2659 2660 if (!crtc_state->has_psr) 2661 return; 2662 2663 for_each_intel_encoder_mask_with_psr(&i915->drm, encoder, 2664 crtc_state->uapi.encoder_mask) { 2665 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2666 2667 mutex_lock(&intel_dp->psr.lock); 2668 break; 2669 } 2670 } 2671 2672 /** 2673 * intel_psr_unlock - release PSR lock 2674 * @crtc_state: the crtc state 2675 * 2676 * Release the PSR lock that was held during pipe update. 2677 */ 2678 void intel_psr_unlock(const struct intel_crtc_state *crtc_state) 2679 { 2680 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2681 struct intel_encoder *encoder; 2682 2683 if (!crtc_state->has_psr) 2684 return; 2685 2686 for_each_intel_encoder_mask_with_psr(&i915->drm, encoder, 2687 crtc_state->uapi.encoder_mask) { 2688 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2689 2690 mutex_unlock(&intel_dp->psr.lock); 2691 break; 2692 } 2693 } 2694