1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2020 Intel Corporation
4  */
5 
6 #include "g4x_dp.h"
7 #include "i915_drv.h"
8 #include "i915_reg.h"
9 #include "intel_de.h"
10 #include "intel_display_power_well.h"
11 #include "intel_display_types.h"
12 #include "intel_dp.h"
13 #include "intel_dpio_phy.h"
14 #include "intel_dpll.h"
15 #include "intel_lvds.h"
16 #include "intel_lvds_regs.h"
17 #include "intel_pps.h"
18 #include "intel_pps_regs.h"
19 #include "intel_quirks.h"
20 
21 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
22 				      enum pipe pipe);
23 
24 static void pps_init_delays(struct intel_dp *intel_dp);
25 static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);
26 
27 static const char *pps_name(struct drm_i915_private *i915,
28 			    struct intel_pps *pps)
29 {
30 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
31 		switch (pps->pps_pipe) {
32 		case INVALID_PIPE:
33 			/*
34 			 * FIXME would be nice if we can guarantee
35 			 * to always have a valid PPS when calling this.
36 			 */
37 			return "PPS <none>";
38 		case PIPE_A:
39 			return "PPS A";
40 		case PIPE_B:
41 			return "PPS B";
42 		default:
43 			MISSING_CASE(pps->pps_pipe);
44 			break;
45 		}
46 	} else {
47 		switch (pps->pps_idx) {
48 		case 0:
49 			return "PPS 0";
50 		case 1:
51 			return "PPS 1";
52 		default:
53 			MISSING_CASE(pps->pps_idx);
54 			break;
55 		}
56 	}
57 
58 	return "PPS <invalid>";
59 }
60 
61 intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
62 {
63 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
64 	intel_wakeref_t wakeref;
65 
66 	/*
67 	 * See intel_pps_reset_all() why we need a power domain reference here.
68 	 */
69 	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
70 	mutex_lock(&dev_priv->display.pps.mutex);
71 
72 	return wakeref;
73 }
74 
75 intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
76 				 intel_wakeref_t wakeref)
77 {
78 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
79 
80 	mutex_unlock(&dev_priv->display.pps.mutex);
81 	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
82 
83 	return 0;
84 }
85 
86 static void
87 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
88 {
89 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
90 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
91 	enum pipe pipe = intel_dp->pps.pps_pipe;
92 	bool pll_enabled, release_cl_override = false;
93 	enum dpio_phy phy = DPIO_PHY(pipe);
94 	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
95 	u32 DP;
96 
97 	if (drm_WARN(&dev_priv->drm,
98 		     intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
99 		     "skipping %s kick due to [ENCODER:%d:%s] being active\n",
100 		     pps_name(dev_priv, &intel_dp->pps),
101 		     dig_port->base.base.base.id, dig_port->base.base.name))
102 		return;
103 
104 	drm_dbg_kms(&dev_priv->drm,
105 		    "kicking %s for [ENCODER:%d:%s]\n",
106 		    pps_name(dev_priv, &intel_dp->pps),
107 		    dig_port->base.base.base.id, dig_port->base.base.name);
108 
109 	/* Preserve the BIOS-computed detected bit. This is
110 	 * supposed to be read-only.
111 	 */
112 	DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
113 	DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
114 	DP |= DP_PORT_WIDTH(1);
115 	DP |= DP_LINK_TRAIN_PAT_1;
116 
117 	if (IS_CHERRYVIEW(dev_priv))
118 		DP |= DP_PIPE_SEL_CHV(pipe);
119 	else
120 		DP |= DP_PIPE_SEL(pipe);
121 
122 	pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
123 
124 	/*
125 	 * The DPLL for the pipe must be enabled for this to work.
126 	 * So enable temporarily it if it's not already enabled.
127 	 */
128 	if (!pll_enabled) {
129 		release_cl_override = IS_CHERRYVIEW(dev_priv) &&
130 			!chv_phy_powergate_ch(dev_priv, phy, ch, true);
131 
132 		if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) {
133 			drm_err(&dev_priv->drm,
134 				"Failed to force on PLL for pipe %c!\n",
135 				pipe_name(pipe));
136 			return;
137 		}
138 	}
139 
140 	/*
141 	 * Similar magic as in intel_dp_enable_port().
142 	 * We _must_ do this port enable + disable trick
143 	 * to make this power sequencer lock onto the port.
144 	 * Otherwise even VDD force bit won't work.
145 	 */
146 	intel_de_write(dev_priv, intel_dp->output_reg, DP);
147 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
148 
149 	intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
150 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
151 
152 	intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
153 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
154 
155 	if (!pll_enabled) {
156 		vlv_force_pll_off(dev_priv, pipe);
157 
158 		if (release_cl_override)
159 			chv_phy_powergate_ch(dev_priv, phy, ch, false);
160 	}
161 }
162 
163 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
164 {
165 	struct intel_encoder *encoder;
166 	unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
167 
168 	/*
169 	 * We don't have power sequencer currently.
170 	 * Pick one that's not used by other ports.
171 	 */
172 	for_each_intel_dp(&dev_priv->drm, encoder) {
173 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
174 
175 		if (encoder->type == INTEL_OUTPUT_EDP) {
176 			drm_WARN_ON(&dev_priv->drm,
177 				    intel_dp->pps.active_pipe != INVALID_PIPE &&
178 				    intel_dp->pps.active_pipe !=
179 				    intel_dp->pps.pps_pipe);
180 
181 			if (intel_dp->pps.pps_pipe != INVALID_PIPE)
182 				pipes &= ~(1 << intel_dp->pps.pps_pipe);
183 		} else {
184 			drm_WARN_ON(&dev_priv->drm,
185 				    intel_dp->pps.pps_pipe != INVALID_PIPE);
186 
187 			if (intel_dp->pps.active_pipe != INVALID_PIPE)
188 				pipes &= ~(1 << intel_dp->pps.active_pipe);
189 		}
190 	}
191 
192 	if (pipes == 0)
193 		return INVALID_PIPE;
194 
195 	return ffs(pipes) - 1;
196 }
197 
198 static enum pipe
199 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
200 {
201 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
202 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
203 	enum pipe pipe;
204 
205 	lockdep_assert_held(&dev_priv->display.pps.mutex);
206 
207 	/* We should never land here with regular DP ports */
208 	drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
209 
210 	drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE &&
211 		    intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe);
212 
213 	if (intel_dp->pps.pps_pipe != INVALID_PIPE)
214 		return intel_dp->pps.pps_pipe;
215 
216 	pipe = vlv_find_free_pps(dev_priv);
217 
218 	/*
219 	 * Didn't find one. This should not happen since there
220 	 * are two power sequencers and up to two eDP ports.
221 	 */
222 	if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
223 		pipe = PIPE_A;
224 
225 	vlv_steal_power_sequencer(dev_priv, pipe);
226 	intel_dp->pps.pps_pipe = pipe;
227 
228 	drm_dbg_kms(&dev_priv->drm,
229 		    "picked %s for [ENCODER:%d:%s]\n",
230 		    pps_name(dev_priv, &intel_dp->pps),
231 		    dig_port->base.base.base.id, dig_port->base.base.name);
232 
233 	/* init power sequencer on this pipe and port */
234 	pps_init_delays(intel_dp);
235 	pps_init_registers(intel_dp, true);
236 
237 	/*
238 	 * Even vdd force doesn't work until we've made
239 	 * the power sequencer lock in on the port.
240 	 */
241 	vlv_power_sequencer_kick(intel_dp);
242 
243 	return intel_dp->pps.pps_pipe;
244 }
245 
246 static int
247 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
248 {
249 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
250 	int pps_idx = intel_dp->pps.pps_idx;
251 
252 	lockdep_assert_held(&dev_priv->display.pps.mutex);
253 
254 	/* We should never land here with regular DP ports */
255 	drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
256 
257 	if (!intel_dp->pps.pps_reset)
258 		return pps_idx;
259 
260 	intel_dp->pps.pps_reset = false;
261 
262 	/*
263 	 * Only the HW needs to be reprogrammed, the SW state is fixed and
264 	 * has been setup during connector init.
265 	 */
266 	pps_init_registers(intel_dp, false);
267 
268 	return pps_idx;
269 }
270 
271 typedef bool (*pps_check)(struct drm_i915_private *dev_priv, int pps_idx);
272 
273 static bool pps_has_pp_on(struct drm_i915_private *dev_priv, int pps_idx)
274 {
275 	return intel_de_read(dev_priv, PP_STATUS(pps_idx)) & PP_ON;
276 }
277 
278 static bool pps_has_vdd_on(struct drm_i915_private *dev_priv, int pps_idx)
279 {
280 	return intel_de_read(dev_priv, PP_CONTROL(pps_idx)) & EDP_FORCE_VDD;
281 }
282 
283 static bool pps_any(struct drm_i915_private *dev_priv, int pps_idx)
284 {
285 	return true;
286 }
287 
288 static enum pipe
289 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
290 		     enum port port, pps_check check)
291 {
292 	enum pipe pipe;
293 
294 	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
295 		u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
296 			PANEL_PORT_SELECT_MASK;
297 
298 		if (port_sel != PANEL_PORT_SELECT_VLV(port))
299 			continue;
300 
301 		if (!check(dev_priv, pipe))
302 			continue;
303 
304 		return pipe;
305 	}
306 
307 	return INVALID_PIPE;
308 }
309 
310 static void
311 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
312 {
313 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
314 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
315 	enum port port = dig_port->base.port;
316 
317 	lockdep_assert_held(&dev_priv->display.pps.mutex);
318 
319 	/* try to find a pipe with this port selected */
320 	/* first pick one where the panel is on */
321 	intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
322 						      pps_has_pp_on);
323 	/* didn't find one? pick one where vdd is on */
324 	if (intel_dp->pps.pps_pipe == INVALID_PIPE)
325 		intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
326 							      pps_has_vdd_on);
327 	/* didn't find one? pick one with just the correct port */
328 	if (intel_dp->pps.pps_pipe == INVALID_PIPE)
329 		intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
330 							      pps_any);
331 
332 	/* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
333 	if (intel_dp->pps.pps_pipe == INVALID_PIPE) {
334 		drm_dbg_kms(&dev_priv->drm,
335 			    "[ENCODER:%d:%s] no initial power sequencer\n",
336 			    dig_port->base.base.base.id, dig_port->base.base.name);
337 		return;
338 	}
339 
340 	drm_dbg_kms(&dev_priv->drm,
341 		    "[ENCODER:%d:%s] initial power sequencer: %s\n",
342 		    dig_port->base.base.base.id, dig_port->base.base.name,
343 		    pps_name(dev_priv, &intel_dp->pps));
344 }
345 
346 static int intel_num_pps(struct drm_i915_private *i915)
347 {
348 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
349 		return 2;
350 
351 	if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
352 		return 2;
353 
354 	if (INTEL_PCH_TYPE(i915) >= PCH_DG1)
355 		return 1;
356 
357 	if (INTEL_PCH_TYPE(i915) >= PCH_ICP)
358 		return 2;
359 
360 	return 1;
361 }
362 
363 static bool intel_pps_is_valid(struct intel_dp *intel_dp)
364 {
365 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
366 
367 	if (intel_dp->pps.pps_idx == 1 &&
368 	    INTEL_PCH_TYPE(i915) >= PCH_ICP &&
369 	    INTEL_PCH_TYPE(i915) < PCH_MTP)
370 		return intel_de_read(i915, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;
371 
372 	return true;
373 }
374 
375 static int
376 bxt_initial_pps_idx(struct drm_i915_private *i915, pps_check check)
377 {
378 	int pps_idx, pps_num = intel_num_pps(i915);
379 
380 	for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
381 		if (check(i915, pps_idx))
382 			return pps_idx;
383 	}
384 
385 	return -1;
386 }
387 
388 static bool
389 pps_initial_setup(struct intel_dp *intel_dp)
390 {
391 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
392 	struct intel_connector *connector = intel_dp->attached_connector;
393 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
394 
395 	lockdep_assert_held(&i915->display.pps.mutex);
396 
397 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
398 		vlv_initial_power_sequencer_setup(intel_dp);
399 		return true;
400 	}
401 
402 	/* first ask the VBT */
403 	if (intel_num_pps(i915) > 1)
404 		intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;
405 	else
406 		intel_dp->pps.pps_idx = 0;
407 
408 	if (drm_WARN_ON(&i915->drm, intel_dp->pps.pps_idx >= intel_num_pps(i915)))
409 		intel_dp->pps.pps_idx = -1;
410 
411 	/* VBT wasn't parsed yet? pick one where the panel is on */
412 	if (intel_dp->pps.pps_idx < 0)
413 		intel_dp->pps.pps_idx = bxt_initial_pps_idx(i915, pps_has_pp_on);
414 	/* didn't find one? pick one where vdd is on */
415 	if (intel_dp->pps.pps_idx < 0)
416 		intel_dp->pps.pps_idx = bxt_initial_pps_idx(i915, pps_has_vdd_on);
417 	/* didn't find one? pick any */
418 	if (intel_dp->pps.pps_idx < 0) {
419 		intel_dp->pps.pps_idx = bxt_initial_pps_idx(i915, pps_any);
420 
421 		drm_dbg_kms(&i915->drm,
422 			    "[ENCODER:%d:%s] no initial power sequencer, assuming %s\n",
423 			    encoder->base.base.id, encoder->base.name,
424 			    pps_name(i915, &intel_dp->pps));
425 	} else {
426 		drm_dbg_kms(&i915->drm,
427 			    "[ENCODER:%d:%s] initial power sequencer: %s\n",
428 			    encoder->base.base.id, encoder->base.name,
429 			    pps_name(i915, &intel_dp->pps));
430 	}
431 
432 	return intel_pps_is_valid(intel_dp);
433 }
434 
435 void intel_pps_reset_all(struct drm_i915_private *dev_priv)
436 {
437 	struct intel_encoder *encoder;
438 
439 	if (drm_WARN_ON(&dev_priv->drm, !IS_LP(dev_priv)))
440 		return;
441 
442 	if (!HAS_DISPLAY(dev_priv))
443 		return;
444 
445 	/*
446 	 * We can't grab pps_mutex here due to deadlock with power_domain
447 	 * mutex when power_domain functions are called while holding pps_mutex.
448 	 * That also means that in order to use pps_pipe the code needs to
449 	 * hold both a power domain reference and pps_mutex, and the power domain
450 	 * reference get/put must be done while _not_ holding pps_mutex.
451 	 * pps_{lock,unlock}() do these steps in the correct order, so one
452 	 * should use them always.
453 	 */
454 
455 	for_each_intel_dp(&dev_priv->drm, encoder) {
456 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
457 
458 		drm_WARN_ON(&dev_priv->drm,
459 			    intel_dp->pps.active_pipe != INVALID_PIPE);
460 
461 		if (encoder->type != INTEL_OUTPUT_EDP)
462 			continue;
463 
464 		if (DISPLAY_VER(dev_priv) >= 9)
465 			intel_dp->pps.pps_reset = true;
466 		else
467 			intel_dp->pps.pps_pipe = INVALID_PIPE;
468 	}
469 }
470 
471 struct pps_registers {
472 	i915_reg_t pp_ctrl;
473 	i915_reg_t pp_stat;
474 	i915_reg_t pp_on;
475 	i915_reg_t pp_off;
476 	i915_reg_t pp_div;
477 };
478 
479 static void intel_pps_get_registers(struct intel_dp *intel_dp,
480 				    struct pps_registers *regs)
481 {
482 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
483 	int pps_idx;
484 
485 	memset(regs, 0, sizeof(*regs));
486 
487 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
488 		pps_idx = vlv_power_sequencer_pipe(intel_dp);
489 	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
490 		pps_idx = bxt_power_sequencer_idx(intel_dp);
491 	else
492 		pps_idx = intel_dp->pps.pps_idx;
493 
494 	regs->pp_ctrl = PP_CONTROL(pps_idx);
495 	regs->pp_stat = PP_STATUS(pps_idx);
496 	regs->pp_on = PP_ON_DELAYS(pps_idx);
497 	regs->pp_off = PP_OFF_DELAYS(pps_idx);
498 
499 	/* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
500 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ||
501 	    INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
502 		regs->pp_div = INVALID_MMIO_REG;
503 	else
504 		regs->pp_div = PP_DIVISOR(pps_idx);
505 }
506 
507 static i915_reg_t
508 _pp_ctrl_reg(struct intel_dp *intel_dp)
509 {
510 	struct pps_registers regs;
511 
512 	intel_pps_get_registers(intel_dp, &regs);
513 
514 	return regs.pp_ctrl;
515 }
516 
517 static i915_reg_t
518 _pp_stat_reg(struct intel_dp *intel_dp)
519 {
520 	struct pps_registers regs;
521 
522 	intel_pps_get_registers(intel_dp, &regs);
523 
524 	return regs.pp_stat;
525 }
526 
527 static bool edp_have_panel_power(struct intel_dp *intel_dp)
528 {
529 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
530 
531 	lockdep_assert_held(&dev_priv->display.pps.mutex);
532 
533 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
534 	    intel_dp->pps.pps_pipe == INVALID_PIPE)
535 		return false;
536 
537 	return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
538 }
539 
540 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
541 {
542 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
543 
544 	lockdep_assert_held(&dev_priv->display.pps.mutex);
545 
546 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
547 	    intel_dp->pps.pps_pipe == INVALID_PIPE)
548 		return false;
549 
550 	return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
551 }
552 
553 void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
554 {
555 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
556 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
557 
558 	if (!intel_dp_is_edp(intel_dp))
559 		return;
560 
561 	if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
562 		drm_WARN(&dev_priv->drm, 1,
563 			 "[ENCODER:%d:%s] %s powered off while attempting AUX CH communication.\n",
564 			 dig_port->base.base.base.id, dig_port->base.base.name,
565 			 pps_name(dev_priv, &intel_dp->pps));
566 		drm_dbg_kms(&dev_priv->drm,
567 			    "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
568 			    dig_port->base.base.base.id, dig_port->base.base.name,
569 			    pps_name(dev_priv, &intel_dp->pps),
570 			    intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
571 			    intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
572 	}
573 }
574 
575 #define IDLE_ON_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
576 #define IDLE_ON_VALUE		(PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
577 
578 #define IDLE_OFF_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
579 #define IDLE_OFF_VALUE		(0     | PP_SEQUENCE_NONE | 0                     | 0)
580 
581 #define IDLE_CYCLE_MASK		(PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
582 #define IDLE_CYCLE_VALUE	(0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
583 
584 static void intel_pps_verify_state(struct intel_dp *intel_dp);
585 
586 static void wait_panel_status(struct intel_dp *intel_dp,
587 			      u32 mask, u32 value)
588 {
589 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
590 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
591 	i915_reg_t pp_stat_reg, pp_ctrl_reg;
592 
593 	lockdep_assert_held(&dev_priv->display.pps.mutex);
594 
595 	intel_pps_verify_state(intel_dp);
596 
597 	pp_stat_reg = _pp_stat_reg(intel_dp);
598 	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
599 
600 	drm_dbg_kms(&dev_priv->drm,
601 		    "[ENCODER:%d:%s] %s mask: 0x%08x value: 0x%08x PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
602 		    dig_port->base.base.base.id, dig_port->base.base.name,
603 		    pps_name(dev_priv, &intel_dp->pps),
604 		    mask, value,
605 		    intel_de_read(dev_priv, pp_stat_reg),
606 		    intel_de_read(dev_priv, pp_ctrl_reg));
607 
608 	if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
609 				       mask, value, 5000))
610 		drm_err(&dev_priv->drm,
611 			"[ENCODER:%d:%s] %s panel status timeout: PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
612 			dig_port->base.base.base.id, dig_port->base.base.name,
613 			pps_name(dev_priv, &intel_dp->pps),
614 			intel_de_read(dev_priv, pp_stat_reg),
615 			intel_de_read(dev_priv, pp_ctrl_reg));
616 
617 	drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
618 }
619 
620 static void wait_panel_on(struct intel_dp *intel_dp)
621 {
622 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
623 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
624 
625 	drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] %s wait for panel power on\n",
626 		    dig_port->base.base.base.id, dig_port->base.base.name,
627 		    pps_name(i915, &intel_dp->pps));
628 	wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
629 }
630 
631 static void wait_panel_off(struct intel_dp *intel_dp)
632 {
633 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
634 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
635 
636 	drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] %s wait for panel power off time\n",
637 		    dig_port->base.base.base.id, dig_port->base.base.name,
638 		    pps_name(i915, &intel_dp->pps));
639 	wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
640 }
641 
642 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
643 {
644 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
645 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
646 	ktime_t panel_power_on_time;
647 	s64 panel_power_off_duration;
648 
649 	drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] %s wait for panel power cycle\n",
650 		    dig_port->base.base.base.id, dig_port->base.base.name,
651 		    pps_name(i915, &intel_dp->pps));
652 
653 	/* take the difference of current time and panel power off time
654 	 * and then make panel wait for t11_t12 if needed. */
655 	panel_power_on_time = ktime_get_boottime();
656 	panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);
657 
658 	/* When we disable the VDD override bit last we have to do the manual
659 	 * wait. */
660 	if (panel_power_off_duration < (s64)intel_dp->pps.panel_power_cycle_delay)
661 		wait_remaining_ms_from_jiffies(jiffies,
662 				       intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration);
663 
664 	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
665 }
666 
667 void intel_pps_wait_power_cycle(struct intel_dp *intel_dp)
668 {
669 	intel_wakeref_t wakeref;
670 
671 	if (!intel_dp_is_edp(intel_dp))
672 		return;
673 
674 	with_intel_pps_lock(intel_dp, wakeref)
675 		wait_panel_power_cycle(intel_dp);
676 }
677 
678 static void wait_backlight_on(struct intel_dp *intel_dp)
679 {
680 	wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on,
681 				       intel_dp->pps.backlight_on_delay);
682 }
683 
684 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
685 {
686 	wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off,
687 				       intel_dp->pps.backlight_off_delay);
688 }
689 
690 /* Read the current pp_control value, unlocking the register if it
691  * is locked
692  */
693 
694 static  u32 ilk_get_pp_control(struct intel_dp *intel_dp)
695 {
696 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
697 	u32 control;
698 
699 	lockdep_assert_held(&dev_priv->display.pps.mutex);
700 
701 	control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
702 	if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
703 			(control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
704 		control &= ~PANEL_UNLOCK_MASK;
705 		control |= PANEL_UNLOCK_REGS;
706 	}
707 	return control;
708 }
709 
710 /*
711  * Must be paired with intel_pps_vdd_off_unlocked().
712  * Must hold pps_mutex around the whole on/off sequence.
713  * Can be nested with intel_pps_vdd_{on,off}() calls.
714  */
715 bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
716 {
717 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
718 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
719 	u32 pp;
720 	i915_reg_t pp_stat_reg, pp_ctrl_reg;
721 	bool need_to_disable = !intel_dp->pps.want_panel_vdd;
722 
723 	lockdep_assert_held(&dev_priv->display.pps.mutex);
724 
725 	if (!intel_dp_is_edp(intel_dp))
726 		return false;
727 
728 	cancel_delayed_work(&intel_dp->pps.panel_vdd_work);
729 	intel_dp->pps.want_panel_vdd = true;
730 
731 	if (edp_have_panel_vdd(intel_dp))
732 		return need_to_disable;
733 
734 	drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
735 	intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
736 							    intel_aux_power_domain(dig_port));
737 
738 	pp_stat_reg = _pp_stat_reg(intel_dp);
739 	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
740 
741 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s turning VDD on\n",
742 		    dig_port->base.base.base.id, dig_port->base.base.name,
743 		    pps_name(dev_priv, &intel_dp->pps));
744 
745 	if (!edp_have_panel_power(intel_dp))
746 		wait_panel_power_cycle(intel_dp);
747 
748 	pp = ilk_get_pp_control(intel_dp);
749 	pp |= EDP_FORCE_VDD;
750 
751 	intel_de_write(dev_priv, pp_ctrl_reg, pp);
752 	intel_de_posting_read(dev_priv, pp_ctrl_reg);
753 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
754 		    dig_port->base.base.base.id, dig_port->base.base.name,
755 		    pps_name(dev_priv, &intel_dp->pps),
756 		    intel_de_read(dev_priv, pp_stat_reg),
757 		    intel_de_read(dev_priv, pp_ctrl_reg));
758 	/*
759 	 * If the panel wasn't on, delay before accessing aux channel
760 	 */
761 	if (!edp_have_panel_power(intel_dp)) {
762 		drm_dbg_kms(&dev_priv->drm,
763 			    "[ENCODER:%d:%s] %s panel power wasn't enabled\n",
764 			    dig_port->base.base.base.id, dig_port->base.base.name,
765 			    pps_name(dev_priv, &intel_dp->pps));
766 		msleep(intel_dp->pps.panel_power_up_delay);
767 	}
768 
769 	return need_to_disable;
770 }
771 
772 /*
773  * Must be paired with intel_pps_off().
774  * Nested calls to these functions are not allowed since
775  * we drop the lock. Caller must use some higher level
776  * locking to prevent nested calls from other threads.
777  */
778 void intel_pps_vdd_on(struct intel_dp *intel_dp)
779 {
780 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
781 	intel_wakeref_t wakeref;
782 	bool vdd;
783 
784 	if (!intel_dp_is_edp(intel_dp))
785 		return;
786 
787 	vdd = false;
788 	with_intel_pps_lock(intel_dp, wakeref)
789 		vdd = intel_pps_vdd_on_unlocked(intel_dp);
790 	I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] %s VDD already requested on\n",
791 			dp_to_dig_port(intel_dp)->base.base.base.id,
792 			dp_to_dig_port(intel_dp)->base.base.name,
793 			pps_name(i915, &intel_dp->pps));
794 }
795 
796 static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
797 {
798 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
799 	struct intel_digital_port *dig_port =
800 		dp_to_dig_port(intel_dp);
801 	u32 pp;
802 	i915_reg_t pp_stat_reg, pp_ctrl_reg;
803 
804 	lockdep_assert_held(&dev_priv->display.pps.mutex);
805 
806 	drm_WARN_ON(&dev_priv->drm, intel_dp->pps.want_panel_vdd);
807 
808 	if (!edp_have_panel_vdd(intel_dp))
809 		return;
810 
811 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s turning VDD off\n",
812 		    dig_port->base.base.base.id, dig_port->base.base.name,
813 		    pps_name(dev_priv, &intel_dp->pps));
814 
815 	pp = ilk_get_pp_control(intel_dp);
816 	pp &= ~EDP_FORCE_VDD;
817 
818 	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
819 	pp_stat_reg = _pp_stat_reg(intel_dp);
820 
821 	intel_de_write(dev_priv, pp_ctrl_reg, pp);
822 	intel_de_posting_read(dev_priv, pp_ctrl_reg);
823 
824 	/* Make sure sequencer is idle before allowing subsequent activity */
825 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
826 		    dig_port->base.base.base.id, dig_port->base.base.name,
827 		    pps_name(dev_priv, &intel_dp->pps),
828 		    intel_de_read(dev_priv, pp_stat_reg),
829 		    intel_de_read(dev_priv, pp_ctrl_reg));
830 
831 	if ((pp & PANEL_POWER_ON) == 0)
832 		intel_dp->pps.panel_power_off_time = ktime_get_boottime();
833 
834 	intel_display_power_put(dev_priv,
835 				intel_aux_power_domain(dig_port),
836 				fetch_and_zero(&intel_dp->pps.vdd_wakeref));
837 }
838 
839 void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
840 {
841 	intel_wakeref_t wakeref;
842 
843 	if (!intel_dp_is_edp(intel_dp))
844 		return;
845 
846 	cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work);
847 	/*
848 	 * vdd might still be enabled due to the delayed vdd off.
849 	 * Make sure vdd is actually turned off here.
850 	 */
851 	with_intel_pps_lock(intel_dp, wakeref)
852 		intel_pps_vdd_off_sync_unlocked(intel_dp);
853 }
854 
855 static void edp_panel_vdd_work(struct work_struct *__work)
856 {
857 	struct intel_pps *pps = container_of(to_delayed_work(__work),
858 					     struct intel_pps, panel_vdd_work);
859 	struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps);
860 	intel_wakeref_t wakeref;
861 
862 	with_intel_pps_lock(intel_dp, wakeref) {
863 		if (!intel_dp->pps.want_panel_vdd)
864 			intel_pps_vdd_off_sync_unlocked(intel_dp);
865 	}
866 }
867 
868 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
869 {
870 	unsigned long delay;
871 
872 	/*
873 	 * We may not yet know the real power sequencing delays,
874 	 * so keep VDD enabled until we're done with init.
875 	 */
876 	if (intel_dp->pps.initializing)
877 		return;
878 
879 	/*
880 	 * Queue the timer to fire a long time from now (relative to the power
881 	 * down delay) to keep the panel power up across a sequence of
882 	 * operations.
883 	 */
884 	delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5);
885 	schedule_delayed_work(&intel_dp->pps.panel_vdd_work, delay);
886 }
887 
888 /*
889  * Must be paired with edp_panel_vdd_on().
890  * Must hold pps_mutex around the whole on/off sequence.
891  * Can be nested with intel_pps_vdd_{on,off}() calls.
892  */
893 void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
894 {
895 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
896 
897 	lockdep_assert_held(&dev_priv->display.pps.mutex);
898 
899 	if (!intel_dp_is_edp(intel_dp))
900 		return;
901 
902 	I915_STATE_WARN(!intel_dp->pps.want_panel_vdd, "[ENCODER:%d:%s] %s VDD not forced on",
903 			dp_to_dig_port(intel_dp)->base.base.base.id,
904 			dp_to_dig_port(intel_dp)->base.base.name,
905 			pps_name(dev_priv, &intel_dp->pps));
906 
907 	intel_dp->pps.want_panel_vdd = false;
908 
909 	if (sync)
910 		intel_pps_vdd_off_sync_unlocked(intel_dp);
911 	else
912 		edp_panel_vdd_schedule_off(intel_dp);
913 }
914 
915 void intel_pps_on_unlocked(struct intel_dp *intel_dp)
916 {
917 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
918 	u32 pp;
919 	i915_reg_t pp_ctrl_reg;
920 
921 	lockdep_assert_held(&dev_priv->display.pps.mutex);
922 
923 	if (!intel_dp_is_edp(intel_dp))
924 		return;
925 
926 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s turn panel power on\n",
927 		    dp_to_dig_port(intel_dp)->base.base.base.id,
928 		    dp_to_dig_port(intel_dp)->base.base.name,
929 		    pps_name(dev_priv, &intel_dp->pps));
930 
931 	if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
932 		     "[ENCODER:%d:%s] %s panel power already on\n",
933 		     dp_to_dig_port(intel_dp)->base.base.base.id,
934 		     dp_to_dig_port(intel_dp)->base.base.name,
935 		     pps_name(dev_priv, &intel_dp->pps)))
936 		return;
937 
938 	wait_panel_power_cycle(intel_dp);
939 
940 	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
941 	pp = ilk_get_pp_control(intel_dp);
942 	if (IS_IRONLAKE(dev_priv)) {
943 		/* ILK workaround: disable reset around power sequence */
944 		pp &= ~PANEL_POWER_RESET;
945 		intel_de_write(dev_priv, pp_ctrl_reg, pp);
946 		intel_de_posting_read(dev_priv, pp_ctrl_reg);
947 	}
948 
949 	pp |= PANEL_POWER_ON;
950 	if (!IS_IRONLAKE(dev_priv))
951 		pp |= PANEL_POWER_RESET;
952 
953 	intel_de_write(dev_priv, pp_ctrl_reg, pp);
954 	intel_de_posting_read(dev_priv, pp_ctrl_reg);
955 
956 	wait_panel_on(intel_dp);
957 	intel_dp->pps.last_power_on = jiffies;
958 
959 	if (IS_IRONLAKE(dev_priv)) {
960 		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
961 		intel_de_write(dev_priv, pp_ctrl_reg, pp);
962 		intel_de_posting_read(dev_priv, pp_ctrl_reg);
963 	}
964 }
965 
966 void intel_pps_on(struct intel_dp *intel_dp)
967 {
968 	intel_wakeref_t wakeref;
969 
970 	if (!intel_dp_is_edp(intel_dp))
971 		return;
972 
973 	with_intel_pps_lock(intel_dp, wakeref)
974 		intel_pps_on_unlocked(intel_dp);
975 }
976 
977 void intel_pps_off_unlocked(struct intel_dp *intel_dp)
978 {
979 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
980 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
981 	u32 pp;
982 	i915_reg_t pp_ctrl_reg;
983 
984 	lockdep_assert_held(&dev_priv->display.pps.mutex);
985 
986 	if (!intel_dp_is_edp(intel_dp))
987 		return;
988 
989 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s turn panel power off\n",
990 		    dig_port->base.base.base.id, dig_port->base.base.name,
991 		    pps_name(dev_priv, &intel_dp->pps));
992 
993 	drm_WARN(&dev_priv->drm, !intel_dp->pps.want_panel_vdd,
994 		 "[ENCODER:%d:%s] %s need VDD to turn off panel\n",
995 		 dig_port->base.base.base.id, dig_port->base.base.name,
996 		 pps_name(dev_priv, &intel_dp->pps));
997 
998 	pp = ilk_get_pp_control(intel_dp);
999 	/* We need to switch off panel power _and_ force vdd, for otherwise some
1000 	 * panels get very unhappy and cease to work. */
1001 	pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1002 		EDP_BLC_ENABLE);
1003 
1004 	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1005 
1006 	intel_dp->pps.want_panel_vdd = false;
1007 
1008 	intel_de_write(dev_priv, pp_ctrl_reg, pp);
1009 	intel_de_posting_read(dev_priv, pp_ctrl_reg);
1010 
1011 	wait_panel_off(intel_dp);
1012 	intel_dp->pps.panel_power_off_time = ktime_get_boottime();
1013 
1014 	/* We got a reference when we enabled the VDD. */
1015 	intel_display_power_put(dev_priv,
1016 				intel_aux_power_domain(dig_port),
1017 				fetch_and_zero(&intel_dp->pps.vdd_wakeref));
1018 }
1019 
1020 void intel_pps_off(struct intel_dp *intel_dp)
1021 {
1022 	intel_wakeref_t wakeref;
1023 
1024 	if (!intel_dp_is_edp(intel_dp))
1025 		return;
1026 
1027 	with_intel_pps_lock(intel_dp, wakeref)
1028 		intel_pps_off_unlocked(intel_dp);
1029 }
1030 
1031 /* Enable backlight in the panel power control. */
1032 void intel_pps_backlight_on(struct intel_dp *intel_dp)
1033 {
1034 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1035 	intel_wakeref_t wakeref;
1036 
1037 	/*
1038 	 * If we enable the backlight right away following a panel power
1039 	 * on, we may see slight flicker as the panel syncs with the eDP
1040 	 * link.  So delay a bit to make sure the image is solid before
1041 	 * allowing it to appear.
1042 	 */
1043 	wait_backlight_on(intel_dp);
1044 
1045 	with_intel_pps_lock(intel_dp, wakeref) {
1046 		i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1047 		u32 pp;
1048 
1049 		pp = ilk_get_pp_control(intel_dp);
1050 		pp |= EDP_BLC_ENABLE;
1051 
1052 		intel_de_write(dev_priv, pp_ctrl_reg, pp);
1053 		intel_de_posting_read(dev_priv, pp_ctrl_reg);
1054 	}
1055 }
1056 
1057 /* Disable backlight in the panel power control. */
1058 void intel_pps_backlight_off(struct intel_dp *intel_dp)
1059 {
1060 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1061 	intel_wakeref_t wakeref;
1062 
1063 	if (!intel_dp_is_edp(intel_dp))
1064 		return;
1065 
1066 	with_intel_pps_lock(intel_dp, wakeref) {
1067 		i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1068 		u32 pp;
1069 
1070 		pp = ilk_get_pp_control(intel_dp);
1071 		pp &= ~EDP_BLC_ENABLE;
1072 
1073 		intel_de_write(dev_priv, pp_ctrl_reg, pp);
1074 		intel_de_posting_read(dev_priv, pp_ctrl_reg);
1075 	}
1076 
1077 	intel_dp->pps.last_backlight_off = jiffies;
1078 	edp_wait_backlight_off(intel_dp);
1079 }
1080 
1081 /*
1082  * Hook for controlling the panel power control backlight through the bl_power
1083  * sysfs attribute. Take care to handle multiple calls.
1084  */
1085 void intel_pps_backlight_power(struct intel_connector *connector, bool enable)
1086 {
1087 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
1088 	struct intel_dp *intel_dp = intel_attached_dp(connector);
1089 	intel_wakeref_t wakeref;
1090 	bool is_enabled;
1091 
1092 	is_enabled = false;
1093 	with_intel_pps_lock(intel_dp, wakeref)
1094 		is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1095 	if (is_enabled == enable)
1096 		return;
1097 
1098 	drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
1099 		    enable ? "enable" : "disable");
1100 
1101 	if (enable)
1102 		intel_pps_backlight_on(intel_dp);
1103 	else
1104 		intel_pps_backlight_off(intel_dp);
1105 }
1106 
1107 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
1108 {
1109 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1110 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1111 	enum pipe pipe = intel_dp->pps.pps_pipe;
1112 	i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
1113 
1114 	drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
1115 
1116 	if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
1117 		return;
1118 
1119 	intel_pps_vdd_off_sync_unlocked(intel_dp);
1120 
1121 	/*
1122 	 * VLV seems to get confused when multiple power sequencers
1123 	 * have the same port selected (even if only one has power/vdd
1124 	 * enabled). The failure manifests as vlv_wait_port_ready() failing
1125 	 * CHV on the other hand doesn't seem to mind having the same port
1126 	 * selected in multiple power sequencers, but let's clear the
1127 	 * port select always when logically disconnecting a power sequencer
1128 	 * from a port.
1129 	 */
1130 	drm_dbg_kms(&dev_priv->drm,
1131 		    "detaching %s from [ENCODER:%d:%s]\n",
1132 		    pps_name(dev_priv, &intel_dp->pps),
1133 		    dig_port->base.base.base.id, dig_port->base.base.name);
1134 	intel_de_write(dev_priv, pp_on_reg, 0);
1135 	intel_de_posting_read(dev_priv, pp_on_reg);
1136 
1137 	intel_dp->pps.pps_pipe = INVALID_PIPE;
1138 }
1139 
1140 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
1141 				      enum pipe pipe)
1142 {
1143 	struct intel_encoder *encoder;
1144 
1145 	lockdep_assert_held(&dev_priv->display.pps.mutex);
1146 
1147 	for_each_intel_dp(&dev_priv->drm, encoder) {
1148 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1149 
1150 		drm_WARN(&dev_priv->drm, intel_dp->pps.active_pipe == pipe,
1151 			 "stealing PPS %c from active [ENCODER:%d:%s]\n",
1152 			 pipe_name(pipe), encoder->base.base.id,
1153 			 encoder->base.name);
1154 
1155 		if (intel_dp->pps.pps_pipe != pipe)
1156 			continue;
1157 
1158 		drm_dbg_kms(&dev_priv->drm,
1159 			    "stealing PPS %c from [ENCODER:%d:%s]\n",
1160 			    pipe_name(pipe), encoder->base.base.id,
1161 			    encoder->base.name);
1162 
1163 		/* make sure vdd is off before we steal it */
1164 		vlv_detach_power_sequencer(intel_dp);
1165 	}
1166 }
1167 
1168 void vlv_pps_init(struct intel_encoder *encoder,
1169 		  const struct intel_crtc_state *crtc_state)
1170 {
1171 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1172 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1173 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1174 
1175 	lockdep_assert_held(&dev_priv->display.pps.mutex);
1176 
1177 	drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
1178 
1179 	if (intel_dp->pps.pps_pipe != INVALID_PIPE &&
1180 	    intel_dp->pps.pps_pipe != crtc->pipe) {
1181 		/*
1182 		 * If another power sequencer was being used on this
1183 		 * port previously make sure to turn off vdd there while
1184 		 * we still have control of it.
1185 		 */
1186 		vlv_detach_power_sequencer(intel_dp);
1187 	}
1188 
1189 	/*
1190 	 * We may be stealing the power
1191 	 * sequencer from another port.
1192 	 */
1193 	vlv_steal_power_sequencer(dev_priv, crtc->pipe);
1194 
1195 	intel_dp->pps.active_pipe = crtc->pipe;
1196 
1197 	if (!intel_dp_is_edp(intel_dp))
1198 		return;
1199 
1200 	/* now it's all ours */
1201 	intel_dp->pps.pps_pipe = crtc->pipe;
1202 
1203 	drm_dbg_kms(&dev_priv->drm,
1204 		    "initializing %s for [ENCODER:%d:%s]\n",
1205 		    pps_name(dev_priv, &intel_dp->pps),
1206 		    encoder->base.base.id, encoder->base.name);
1207 
1208 	/* init power sequencer on this pipe and port */
1209 	pps_init_delays(intel_dp);
1210 	pps_init_registers(intel_dp, true);
1211 }
1212 
1213 static void pps_vdd_init(struct intel_dp *intel_dp)
1214 {
1215 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1216 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1217 
1218 	lockdep_assert_held(&dev_priv->display.pps.mutex);
1219 
1220 	if (!edp_have_panel_vdd(intel_dp))
1221 		return;
1222 
1223 	/*
1224 	 * The VDD bit needs a power domain reference, so if the bit is
1225 	 * already enabled when we boot or resume, grab this reference and
1226 	 * schedule a vdd off, so we don't hold on to the reference
1227 	 * indefinitely.
1228 	 */
1229 	drm_dbg_kms(&dev_priv->drm,
1230 		    "[ENCODER:%d:%s] %s VDD left on by BIOS, adjusting state tracking\n",
1231 		    dig_port->base.base.base.id, dig_port->base.base.name,
1232 		    pps_name(dev_priv, &intel_dp->pps));
1233 	drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
1234 	intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
1235 							    intel_aux_power_domain(dig_port));
1236 }
1237 
1238 bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp)
1239 {
1240 	intel_wakeref_t wakeref;
1241 	bool have_power = false;
1242 
1243 	with_intel_pps_lock(intel_dp, wakeref) {
1244 		have_power = edp_have_panel_power(intel_dp) ||
1245 			     edp_have_panel_vdd(intel_dp);
1246 	}
1247 
1248 	return have_power;
1249 }
1250 
1251 static void pps_init_timestamps(struct intel_dp *intel_dp)
1252 {
1253 	/*
1254 	 * Initialize panel power off time to 0, assuming panel power could have
1255 	 * been toggled between kernel boot and now only by a previously loaded
1256 	 * and removed i915, which has already ensured sufficient power off
1257 	 * delay at module remove.
1258 	 */
1259 	intel_dp->pps.panel_power_off_time = 0;
1260 	intel_dp->pps.last_power_on = jiffies;
1261 	intel_dp->pps.last_backlight_off = jiffies;
1262 }
1263 
1264 static void
1265 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
1266 {
1267 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1268 	u32 pp_on, pp_off, pp_ctl;
1269 	struct pps_registers regs;
1270 
1271 	intel_pps_get_registers(intel_dp, &regs);
1272 
1273 	pp_ctl = ilk_get_pp_control(intel_dp);
1274 
1275 	/* Ensure PPS is unlocked */
1276 	if (!HAS_DDI(dev_priv))
1277 		intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
1278 
1279 	pp_on = intel_de_read(dev_priv, regs.pp_on);
1280 	pp_off = intel_de_read(dev_priv, regs.pp_off);
1281 
1282 	/* Pull timing values out of registers */
1283 	seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
1284 	seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
1285 	seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
1286 	seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
1287 
1288 	if (i915_mmio_reg_valid(regs.pp_div)) {
1289 		u32 pp_div;
1290 
1291 		pp_div = intel_de_read(dev_priv, regs.pp_div);
1292 
1293 		seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
1294 	} else {
1295 		seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
1296 	}
1297 }
1298 
1299 static void
1300 intel_pps_dump_state(struct intel_dp *intel_dp, const char *state_name,
1301 		     const struct edp_power_seq *seq)
1302 {
1303 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1304 
1305 	drm_dbg_kms(&i915->drm, "%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
1306 		    state_name,
1307 		    seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
1308 }
1309 
1310 static void
1311 intel_pps_verify_state(struct intel_dp *intel_dp)
1312 {
1313 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1314 	struct edp_power_seq hw;
1315 	struct edp_power_seq *sw = &intel_dp->pps.pps_delays;
1316 
1317 	intel_pps_readout_hw_state(intel_dp, &hw);
1318 
1319 	if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
1320 	    hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
1321 		drm_err(&i915->drm, "PPS state mismatch\n");
1322 		intel_pps_dump_state(intel_dp, "sw", sw);
1323 		intel_pps_dump_state(intel_dp, "hw", &hw);
1324 	}
1325 }
1326 
1327 static bool pps_delays_valid(struct edp_power_seq *delays)
1328 {
1329 	return delays->t1_t3 || delays->t8 || delays->t9 ||
1330 		delays->t10 || delays->t11_t12;
1331 }
1332 
1333 static void pps_init_delays_bios(struct intel_dp *intel_dp,
1334 				 struct edp_power_seq *bios)
1335 {
1336 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1337 
1338 	lockdep_assert_held(&dev_priv->display.pps.mutex);
1339 
1340 	if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays))
1341 		intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays);
1342 
1343 	*bios = intel_dp->pps.bios_pps_delays;
1344 
1345 	intel_pps_dump_state(intel_dp, "bios", bios);
1346 }
1347 
1348 static void pps_init_delays_vbt(struct intel_dp *intel_dp,
1349 				struct edp_power_seq *vbt)
1350 {
1351 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1352 	struct intel_connector *connector = intel_dp->attached_connector;
1353 
1354 	*vbt = connector->panel.vbt.edp.pps;
1355 
1356 	if (!pps_delays_valid(vbt))
1357 		return;
1358 
1359 	/* On Toshiba Satellite P50-C-18C system the VBT T12 delay
1360 	 * of 500ms appears to be too short. Ocassionally the panel
1361 	 * just fails to power back on. Increasing the delay to 800ms
1362 	 * seems sufficient to avoid this problem.
1363 	 */
1364 	if (intel_has_quirk(dev_priv, QUIRK_INCREASE_T12_DELAY)) {
1365 		vbt->t11_t12 = max_t(u16, vbt->t11_t12, 1300 * 10);
1366 		drm_dbg_kms(&dev_priv->drm,
1367 			    "Increasing T12 panel delay as per the quirk to %d\n",
1368 			    vbt->t11_t12);
1369 	}
1370 
1371 	/* T11_T12 delay is special and actually in units of 100ms, but zero
1372 	 * based in the hw (so we need to add 100 ms). But the sw vbt
1373 	 * table multiplies it with 1000 to make it in units of 100usec,
1374 	 * too. */
1375 	vbt->t11_t12 += 100 * 10;
1376 
1377 	intel_pps_dump_state(intel_dp, "vbt", vbt);
1378 }
1379 
1380 static void pps_init_delays_spec(struct intel_dp *intel_dp,
1381 				 struct edp_power_seq *spec)
1382 {
1383 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1384 
1385 	lockdep_assert_held(&dev_priv->display.pps.mutex);
1386 
1387 	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
1388 	 * our hw here, which are all in 100usec. */
1389 	spec->t1_t3 = 210 * 10;
1390 	spec->t8 = 50 * 10; /* no limit for t8, use t7 instead */
1391 	spec->t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
1392 	spec->t10 = 500 * 10;
1393 	/* This one is special and actually in units of 100ms, but zero
1394 	 * based in the hw (so we need to add 100 ms). But the sw vbt
1395 	 * table multiplies it with 1000 to make it in units of 100usec,
1396 	 * too. */
1397 	spec->t11_t12 = (510 + 100) * 10;
1398 
1399 	intel_pps_dump_state(intel_dp, "spec", spec);
1400 }
1401 
1402 static void pps_init_delays(struct intel_dp *intel_dp)
1403 {
1404 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1405 	struct edp_power_seq cur, vbt, spec,
1406 		*final = &intel_dp->pps.pps_delays;
1407 
1408 	lockdep_assert_held(&dev_priv->display.pps.mutex);
1409 
1410 	/* already initialized? */
1411 	if (pps_delays_valid(final))
1412 		return;
1413 
1414 	pps_init_delays_bios(intel_dp, &cur);
1415 	pps_init_delays_vbt(intel_dp, &vbt);
1416 	pps_init_delays_spec(intel_dp, &spec);
1417 
1418 	/* Use the max of the register settings and vbt. If both are
1419 	 * unset, fall back to the spec limits. */
1420 #define assign_final(field)	final->field = (max(cur.field, vbt.field) == 0 ? \
1421 				       spec.field : \
1422 				       max(cur.field, vbt.field))
1423 	assign_final(t1_t3);
1424 	assign_final(t8);
1425 	assign_final(t9);
1426 	assign_final(t10);
1427 	assign_final(t11_t12);
1428 #undef assign_final
1429 
1430 #define get_delay(field)	(DIV_ROUND_UP(final->field, 10))
1431 	intel_dp->pps.panel_power_up_delay = get_delay(t1_t3);
1432 	intel_dp->pps.backlight_on_delay = get_delay(t8);
1433 	intel_dp->pps.backlight_off_delay = get_delay(t9);
1434 	intel_dp->pps.panel_power_down_delay = get_delay(t10);
1435 	intel_dp->pps.panel_power_cycle_delay = get_delay(t11_t12);
1436 #undef get_delay
1437 
1438 	drm_dbg_kms(&dev_priv->drm,
1439 		    "panel power up delay %d, power down delay %d, power cycle delay %d\n",
1440 		    intel_dp->pps.panel_power_up_delay,
1441 		    intel_dp->pps.panel_power_down_delay,
1442 		    intel_dp->pps.panel_power_cycle_delay);
1443 
1444 	drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
1445 		    intel_dp->pps.backlight_on_delay,
1446 		    intel_dp->pps.backlight_off_delay);
1447 
1448 	/*
1449 	 * We override the HW backlight delays to 1 because we do manual waits
1450 	 * on them. For T8, even BSpec recommends doing it. For T9, if we
1451 	 * don't do this, we'll end up waiting for the backlight off delay
1452 	 * twice: once when we do the manual sleep, and once when we disable
1453 	 * the panel and wait for the PP_STATUS bit to become zero.
1454 	 */
1455 	final->t8 = 1;
1456 	final->t9 = 1;
1457 
1458 	/*
1459 	 * HW has only a 100msec granularity for t11_t12 so round it up
1460 	 * accordingly.
1461 	 */
1462 	final->t11_t12 = roundup(final->t11_t12, 100 * 10);
1463 }
1464 
1465 static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd)
1466 {
1467 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1468 	u32 pp_on, pp_off, port_sel = 0;
1469 	int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
1470 	struct pps_registers regs;
1471 	enum port port = dp_to_dig_port(intel_dp)->base.port;
1472 	const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;
1473 
1474 	lockdep_assert_held(&dev_priv->display.pps.mutex);
1475 
1476 	intel_pps_get_registers(intel_dp, &regs);
1477 
1478 	/*
1479 	 * On some VLV machines the BIOS can leave the VDD
1480 	 * enabled even on power sequencers which aren't
1481 	 * hooked up to any port. This would mess up the
1482 	 * power domain tracking the first time we pick
1483 	 * one of these power sequencers for use since
1484 	 * intel_pps_vdd_on_unlocked() would notice that the VDD was
1485 	 * already on and therefore wouldn't grab the power
1486 	 * domain reference. Disable VDD first to avoid this.
1487 	 * This also avoids spuriously turning the VDD on as
1488 	 * soon as the new power sequencer gets initialized.
1489 	 */
1490 	if (force_disable_vdd) {
1491 		u32 pp = ilk_get_pp_control(intel_dp);
1492 
1493 		drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
1494 			 "Panel power already on\n");
1495 
1496 		if (pp & EDP_FORCE_VDD)
1497 			drm_dbg_kms(&dev_priv->drm,
1498 				    "VDD already on, disabling first\n");
1499 
1500 		pp &= ~EDP_FORCE_VDD;
1501 
1502 		intel_de_write(dev_priv, regs.pp_ctrl, pp);
1503 	}
1504 
1505 	pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
1506 		REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
1507 	pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
1508 		REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
1509 
1510 	/* Haswell doesn't have any port selection bits for the panel
1511 	 * power sequencer any more. */
1512 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1513 		port_sel = PANEL_PORT_SELECT_VLV(port);
1514 	} else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
1515 		switch (port) {
1516 		case PORT_A:
1517 			port_sel = PANEL_PORT_SELECT_DPA;
1518 			break;
1519 		case PORT_C:
1520 			port_sel = PANEL_PORT_SELECT_DPC;
1521 			break;
1522 		case PORT_D:
1523 			port_sel = PANEL_PORT_SELECT_DPD;
1524 			break;
1525 		default:
1526 			MISSING_CASE(port);
1527 			break;
1528 		}
1529 	}
1530 
1531 	pp_on |= port_sel;
1532 
1533 	intel_de_write(dev_priv, regs.pp_on, pp_on);
1534 	intel_de_write(dev_priv, regs.pp_off, pp_off);
1535 
1536 	/*
1537 	 * Compute the divisor for the pp clock, simply match the Bspec formula.
1538 	 */
1539 	if (i915_mmio_reg_valid(regs.pp_div))
1540 		intel_de_write(dev_priv, regs.pp_div,
1541 			       REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
1542 	else
1543 		intel_de_rmw(dev_priv, regs.pp_ctrl, BXT_POWER_CYCLE_DELAY_MASK,
1544 			     REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK,
1545 					    DIV_ROUND_UP(seq->t11_t12, 1000)));
1546 
1547 	drm_dbg_kms(&dev_priv->drm,
1548 		    "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
1549 		    intel_de_read(dev_priv, regs.pp_on),
1550 		    intel_de_read(dev_priv, regs.pp_off),
1551 		    i915_mmio_reg_valid(regs.pp_div) ?
1552 		    intel_de_read(dev_priv, regs.pp_div) :
1553 		    (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
1554 }
1555 
1556 void intel_pps_encoder_reset(struct intel_dp *intel_dp)
1557 {
1558 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1559 	intel_wakeref_t wakeref;
1560 
1561 	if (!intel_dp_is_edp(intel_dp))
1562 		return;
1563 
1564 	with_intel_pps_lock(intel_dp, wakeref) {
1565 		/*
1566 		 * Reinit the power sequencer also on the resume path, in case
1567 		 * BIOS did something nasty with it.
1568 		 */
1569 		if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1570 			vlv_initial_power_sequencer_setup(intel_dp);
1571 
1572 		pps_init_delays(intel_dp);
1573 		pps_init_registers(intel_dp, false);
1574 		pps_vdd_init(intel_dp);
1575 
1576 		if (edp_have_panel_vdd(intel_dp))
1577 			edp_panel_vdd_schedule_off(intel_dp);
1578 	}
1579 }
1580 
1581 bool intel_pps_init(struct intel_dp *intel_dp)
1582 {
1583 	intel_wakeref_t wakeref;
1584 	bool ret;
1585 
1586 	intel_dp->pps.initializing = true;
1587 	INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
1588 
1589 	pps_init_timestamps(intel_dp);
1590 
1591 	with_intel_pps_lock(intel_dp, wakeref) {
1592 		ret = pps_initial_setup(intel_dp);
1593 
1594 		pps_init_delays(intel_dp);
1595 		pps_init_registers(intel_dp, false);
1596 		pps_vdd_init(intel_dp);
1597 	}
1598 
1599 	return ret;
1600 }
1601 
1602 static void pps_init_late(struct intel_dp *intel_dp)
1603 {
1604 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1605 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1606 	struct intel_connector *connector = intel_dp->attached_connector;
1607 
1608 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1609 		return;
1610 
1611 	if (intel_num_pps(i915) < 2)
1612 		return;
1613 
1614 	drm_WARN(&i915->drm, connector->panel.vbt.backlight.controller >= 0 &&
1615 		 intel_dp->pps.pps_idx != connector->panel.vbt.backlight.controller,
1616 		 "[ENCODER:%d:%s] power sequencer mismatch: %d (initial) vs. %d (VBT)\n",
1617 		 encoder->base.base.id, encoder->base.name,
1618 		 intel_dp->pps.pps_idx, connector->panel.vbt.backlight.controller);
1619 
1620 	if (connector->panel.vbt.backlight.controller >= 0)
1621 		intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;
1622 }
1623 
1624 void intel_pps_init_late(struct intel_dp *intel_dp)
1625 {
1626 	intel_wakeref_t wakeref;
1627 
1628 	with_intel_pps_lock(intel_dp, wakeref) {
1629 		/* Reinit delays after per-panel info has been parsed from VBT */
1630 		pps_init_late(intel_dp);
1631 
1632 		memset(&intel_dp->pps.pps_delays, 0, sizeof(intel_dp->pps.pps_delays));
1633 		pps_init_delays(intel_dp);
1634 		pps_init_registers(intel_dp, false);
1635 
1636 		intel_dp->pps.initializing = false;
1637 
1638 		if (edp_have_panel_vdd(intel_dp))
1639 			edp_panel_vdd_schedule_off(intel_dp);
1640 	}
1641 }
1642 
1643 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
1644 {
1645 	int pps_num;
1646 	int pps_idx;
1647 
1648 	if (!HAS_DISPLAY(dev_priv) || HAS_DDI(dev_priv))
1649 		return;
1650 	/*
1651 	 * This w/a is needed at least on CPT/PPT, but to be sure apply it
1652 	 * everywhere where registers can be write protected.
1653 	 */
1654 	pps_num = intel_num_pps(dev_priv);
1655 
1656 	for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
1657 		u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
1658 
1659 		val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
1660 		intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
1661 	}
1662 }
1663 
1664 void intel_pps_setup(struct drm_i915_private *i915)
1665 {
1666 	if (HAS_PCH_SPLIT(i915) || IS_GEMINILAKE(i915) || IS_BROXTON(i915))
1667 		i915->display.pps.mmio_base = PCH_PPS_BASE;
1668 	else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1669 		i915->display.pps.mmio_base = VLV_PPS_BASE;
1670 	else
1671 		i915->display.pps.mmio_base = PPS_BASE;
1672 }
1673 
1674 void assert_pps_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1675 {
1676 	i915_reg_t pp_reg;
1677 	u32 val;
1678 	enum pipe panel_pipe = INVALID_PIPE;
1679 	bool locked = true;
1680 
1681 	if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
1682 		return;
1683 
1684 	if (HAS_PCH_SPLIT(dev_priv)) {
1685 		u32 port_sel;
1686 
1687 		pp_reg = PP_CONTROL(0);
1688 		port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1689 
1690 		switch (port_sel) {
1691 		case PANEL_PORT_SELECT_LVDS:
1692 			intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1693 			break;
1694 		case PANEL_PORT_SELECT_DPA:
1695 			g4x_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1696 			break;
1697 		case PANEL_PORT_SELECT_DPC:
1698 			g4x_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1699 			break;
1700 		case PANEL_PORT_SELECT_DPD:
1701 			g4x_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1702 			break;
1703 		default:
1704 			MISSING_CASE(port_sel);
1705 			break;
1706 		}
1707 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1708 		/* presumably write lock depends on pipe, not port select */
1709 		pp_reg = PP_CONTROL(pipe);
1710 		panel_pipe = pipe;
1711 	} else {
1712 		u32 port_sel;
1713 
1714 		pp_reg = PP_CONTROL(0);
1715 		port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1716 
1717 		drm_WARN_ON(&dev_priv->drm,
1718 			    port_sel != PANEL_PORT_SELECT_LVDS);
1719 		intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1720 	}
1721 
1722 	val = intel_de_read(dev_priv, pp_reg);
1723 	if (!(val & PANEL_POWER_ON) ||
1724 	    ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1725 		locked = false;
1726 
1727 	I915_STATE_WARN(panel_pipe == pipe && locked,
1728 			"panel assertion failure, pipe %c regs locked\n",
1729 			pipe_name(pipe));
1730 }
1731