1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "gem/i915_gem_region.h" 7 #include "i915_drv.h" 8 #include "intel_atomic_plane.h" 9 #include "intel_display.h" 10 #include "intel_display_types.h" 11 #include "intel_fb.h" 12 #include "intel_plane_initial.h" 13 14 static bool 15 intel_reuse_initial_plane_obj(struct drm_i915_private *i915, 16 const struct intel_initial_plane_config *plane_config, 17 struct drm_framebuffer **fb, 18 struct i915_vma **vma) 19 { 20 struct intel_crtc *crtc; 21 22 for_each_intel_crtc(&i915->drm, crtc) { 23 struct intel_crtc_state *crtc_state = 24 to_intel_crtc_state(crtc->base.state); 25 struct intel_plane *plane = 26 to_intel_plane(crtc->base.primary); 27 struct intel_plane_state *plane_state = 28 to_intel_plane_state(plane->base.state); 29 30 if (!crtc_state->uapi.active) 31 continue; 32 33 if (!plane_state->ggtt_vma) 34 continue; 35 36 if (intel_plane_ggtt_offset(plane_state) == plane_config->base) { 37 *fb = plane_state->hw.fb; 38 *vma = plane_state->ggtt_vma; 39 return true; 40 } 41 } 42 43 return false; 44 } 45 46 static struct i915_vma * 47 initial_plane_vma(struct drm_i915_private *i915, 48 struct intel_initial_plane_config *plane_config) 49 { 50 struct intel_memory_region *mem; 51 struct drm_i915_gem_object *obj; 52 struct i915_vma *vma; 53 resource_size_t phys_base; 54 u32 base, size; 55 u64 pinctl; 56 57 if (plane_config->size == 0) 58 return NULL; 59 60 base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT); 61 if (IS_DGFX(i915)) { 62 gen8_pte_t __iomem *gte = to_gt(i915)->ggtt->gsm; 63 gen8_pte_t pte; 64 65 gte += base / I915_GTT_PAGE_SIZE; 66 67 pte = ioread64(gte); 68 if (!(pte & GEN12_GGTT_PTE_LM)) { 69 drm_err(&i915->drm, 70 "Initial plane programming missing PTE_LM bit\n"); 71 return NULL; 72 } 73 74 phys_base = pte & I915_GTT_PAGE_MASK; 75 mem = i915->mm.regions[INTEL_REGION_LMEM]; 76 77 /* 78 * We don't currently expect this to ever be placed in the 79 * stolen portion. 80 */ 81 if (phys_base >= resource_size(&mem->region)) { 82 drm_err(&i915->drm, 83 "Initial plane programming using invalid range, phys_base=%pa\n", 84 &phys_base); 85 return NULL; 86 } 87 88 drm_dbg(&i915->drm, 89 "Using phys_base=%pa, based on initial plane programming\n", 90 &phys_base); 91 } else { 92 phys_base = base; 93 mem = i915->mm.stolen_region; 94 } 95 96 if (!mem) 97 return NULL; 98 99 size = round_up(plane_config->base + plane_config->size, 100 mem->min_page_size); 101 size -= base; 102 103 /* 104 * If the FB is too big, just don't use it since fbdev is not very 105 * important and we should probably use that space with FBC or other 106 * features. 107 */ 108 if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) && 109 mem == i915->mm.stolen_region && 110 size * 2 > i915->stolen_usable_size) 111 return NULL; 112 113 obj = i915_gem_object_create_region_at(mem, phys_base, size, 0); 114 if (IS_ERR(obj)) 115 return NULL; 116 117 /* 118 * Mark it WT ahead of time to avoid changing the 119 * cache_level during fbdev initialization. The 120 * unbind there would get stuck waiting for rcu. 121 */ 122 i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ? 123 I915_CACHE_WT : I915_CACHE_NONE); 124 125 switch (plane_config->tiling) { 126 case I915_TILING_NONE: 127 break; 128 case I915_TILING_X: 129 case I915_TILING_Y: 130 obj->tiling_and_stride = 131 plane_config->fb->base.pitches[0] | 132 plane_config->tiling; 133 break; 134 default: 135 MISSING_CASE(plane_config->tiling); 136 goto err_obj; 137 } 138 139 vma = i915_vma_instance(obj, &to_gt(i915)->ggtt->vm, NULL); 140 if (IS_ERR(vma)) 141 goto err_obj; 142 143 pinctl = PIN_GLOBAL | PIN_OFFSET_FIXED | base; 144 if (HAS_GMCH(i915)) 145 pinctl |= PIN_MAPPABLE; 146 if (i915_vma_pin(vma, 0, 0, pinctl)) 147 goto err_obj; 148 149 if (i915_gem_object_is_tiled(obj) && 150 !i915_vma_is_map_and_fenceable(vma)) 151 goto err_obj; 152 153 return vma; 154 155 err_obj: 156 i915_gem_object_put(obj); 157 return NULL; 158 } 159 160 static bool 161 intel_alloc_initial_plane_obj(struct intel_crtc *crtc, 162 struct intel_initial_plane_config *plane_config) 163 { 164 struct drm_device *dev = crtc->base.dev; 165 struct drm_i915_private *dev_priv = to_i915(dev); 166 struct drm_mode_fb_cmd2 mode_cmd = { 0 }; 167 struct drm_framebuffer *fb = &plane_config->fb->base; 168 struct i915_vma *vma; 169 170 switch (fb->modifier) { 171 case DRM_FORMAT_MOD_LINEAR: 172 case I915_FORMAT_MOD_X_TILED: 173 case I915_FORMAT_MOD_Y_TILED: 174 break; 175 default: 176 drm_dbg(&dev_priv->drm, 177 "Unsupported modifier for initial FB: 0x%llx\n", 178 fb->modifier); 179 return false; 180 } 181 182 vma = initial_plane_vma(dev_priv, plane_config); 183 if (!vma) 184 return false; 185 186 mode_cmd.pixel_format = fb->format->format; 187 mode_cmd.width = fb->width; 188 mode_cmd.height = fb->height; 189 mode_cmd.pitches[0] = fb->pitches[0]; 190 mode_cmd.modifier[0] = fb->modifier; 191 mode_cmd.flags = DRM_MODE_FB_MODIFIERS; 192 193 if (intel_framebuffer_init(to_intel_framebuffer(fb), 194 vma->obj, &mode_cmd)) { 195 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n"); 196 goto err_vma; 197 } 198 199 plane_config->vma = vma; 200 return true; 201 202 err_vma: 203 i915_vma_put(vma); 204 return false; 205 } 206 207 static void 208 intel_find_initial_plane_obj(struct intel_crtc *crtc, 209 struct intel_initial_plane_config *plane_config) 210 { 211 struct drm_device *dev = crtc->base.dev; 212 struct drm_i915_private *dev_priv = to_i915(dev); 213 struct intel_plane *plane = 214 to_intel_plane(crtc->base.primary); 215 struct intel_plane_state *plane_state = 216 to_intel_plane_state(plane->base.state); 217 struct drm_framebuffer *fb; 218 struct i915_vma *vma; 219 220 /* 221 * TODO: 222 * Disable planes if get_initial_plane_config() failed. 223 * Make sure things work if the surface base is not page aligned. 224 */ 225 if (!plane_config->fb) 226 return; 227 228 if (intel_alloc_initial_plane_obj(crtc, plane_config)) { 229 fb = &plane_config->fb->base; 230 vma = plane_config->vma; 231 goto valid_fb; 232 } 233 234 /* 235 * Failed to alloc the obj, check to see if we should share 236 * an fb with another CRTC instead 237 */ 238 if (intel_reuse_initial_plane_obj(dev_priv, plane_config, &fb, &vma)) 239 goto valid_fb; 240 241 /* 242 * We've failed to reconstruct the BIOS FB. Current display state 243 * indicates that the primary plane is visible, but has a NULL FB, 244 * which will lead to problems later if we don't fix it up. The 245 * simplest solution is to just disable the primary plane now and 246 * pretend the BIOS never had it enabled. 247 */ 248 intel_plane_disable_noatomic(crtc, plane); 249 250 return; 251 252 valid_fb: 253 plane_state->uapi.rotation = plane_config->rotation; 254 intel_fb_fill_view(to_intel_framebuffer(fb), 255 plane_state->uapi.rotation, &plane_state->view); 256 257 __i915_vma_pin(vma); 258 plane_state->ggtt_vma = i915_vma_get(vma); 259 if (intel_plane_uses_fence(plane_state) && 260 i915_vma_pin_fence(vma) == 0 && vma->fence) 261 plane_state->flags |= PLANE_HAS_FENCE; 262 263 plane_state->uapi.src_x = 0; 264 plane_state->uapi.src_y = 0; 265 plane_state->uapi.src_w = fb->width << 16; 266 plane_state->uapi.src_h = fb->height << 16; 267 268 plane_state->uapi.crtc_x = 0; 269 plane_state->uapi.crtc_y = 0; 270 plane_state->uapi.crtc_w = fb->width; 271 plane_state->uapi.crtc_h = fb->height; 272 273 if (plane_config->tiling) 274 dev_priv->preserve_bios_swizzle = true; 275 276 plane_state->uapi.fb = fb; 277 drm_framebuffer_get(fb); 278 279 plane_state->uapi.crtc = &crtc->base; 280 intel_plane_copy_uapi_to_hw_state(plane_state, plane_state, crtc); 281 282 atomic_or(plane->frontbuffer_bit, &to_intel_frontbuffer(fb)->bits); 283 } 284 285 static void plane_config_fini(struct intel_initial_plane_config *plane_config) 286 { 287 if (plane_config->fb) { 288 struct drm_framebuffer *fb = &plane_config->fb->base; 289 290 /* We may only have the stub and not a full framebuffer */ 291 if (drm_framebuffer_read_refcount(fb)) 292 drm_framebuffer_put(fb); 293 else 294 kfree(fb); 295 } 296 297 if (plane_config->vma) 298 i915_vma_put(plane_config->vma); 299 } 300 301 void intel_crtc_initial_plane_config(struct intel_crtc *crtc) 302 { 303 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 304 struct intel_initial_plane_config plane_config = {}; 305 306 /* 307 * Note that reserving the BIOS fb up front prevents us 308 * from stuffing other stolen allocations like the ring 309 * on top. This prevents some ugliness at boot time, and 310 * can even allow for smooth boot transitions if the BIOS 311 * fb is large enough for the active pipe configuration. 312 */ 313 dev_priv->display->get_initial_plane_config(crtc, &plane_config); 314 315 /* 316 * If the fb is shared between multiple heads, we'll 317 * just get the first one. 318 */ 319 intel_find_initial_plane_obj(crtc, &plane_config); 320 321 plane_config_fini(&plane_config); 322 } 323