1 /*
2  * Copyright © 2013 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Author: Damien Lespiau <damien.lespiau@intel.com>
24  *
25  */
26 
27 #include <linux/circ_buf.h>
28 #include <linux/ctype.h>
29 #include <linux/debugfs.h>
30 #include <linux/seq_file.h>
31 
32 #include "intel_atomic.h"
33 #include "intel_drv.h"
34 #include "intel_pipe_crc.h"
35 
36 static const char * const pipe_crc_sources[] = {
37 	[INTEL_PIPE_CRC_SOURCE_NONE] = "none",
38 	[INTEL_PIPE_CRC_SOURCE_PLANE1] = "plane1",
39 	[INTEL_PIPE_CRC_SOURCE_PLANE2] = "plane2",
40 	[INTEL_PIPE_CRC_SOURCE_PLANE3] = "plane3",
41 	[INTEL_PIPE_CRC_SOURCE_PLANE4] = "plane4",
42 	[INTEL_PIPE_CRC_SOURCE_PLANE5] = "plane5",
43 	[INTEL_PIPE_CRC_SOURCE_PLANE6] = "plane6",
44 	[INTEL_PIPE_CRC_SOURCE_PLANE7] = "plane7",
45 	[INTEL_PIPE_CRC_SOURCE_PIPE] = "pipe",
46 	[INTEL_PIPE_CRC_SOURCE_TV] = "TV",
47 	[INTEL_PIPE_CRC_SOURCE_DP_B] = "DP-B",
48 	[INTEL_PIPE_CRC_SOURCE_DP_C] = "DP-C",
49 	[INTEL_PIPE_CRC_SOURCE_DP_D] = "DP-D",
50 	[INTEL_PIPE_CRC_SOURCE_AUTO] = "auto",
51 };
52 
53 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
54 				 u32 *val)
55 {
56 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
57 		*source = INTEL_PIPE_CRC_SOURCE_PIPE;
58 
59 	switch (*source) {
60 	case INTEL_PIPE_CRC_SOURCE_PIPE:
61 		*val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
62 		break;
63 	case INTEL_PIPE_CRC_SOURCE_NONE:
64 		*val = 0;
65 		break;
66 	default:
67 		return -EINVAL;
68 	}
69 
70 	return 0;
71 }
72 
73 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
74 				     enum pipe pipe,
75 				     enum intel_pipe_crc_source *source)
76 {
77 	struct drm_device *dev = &dev_priv->drm;
78 	struct intel_encoder *encoder;
79 	struct intel_crtc *crtc;
80 	struct intel_digital_port *dig_port;
81 	int ret = 0;
82 
83 	*source = INTEL_PIPE_CRC_SOURCE_PIPE;
84 
85 	drm_modeset_lock_all(dev);
86 	for_each_intel_encoder(dev, encoder) {
87 		if (!encoder->base.crtc)
88 			continue;
89 
90 		crtc = to_intel_crtc(encoder->base.crtc);
91 
92 		if (crtc->pipe != pipe)
93 			continue;
94 
95 		switch (encoder->type) {
96 		case INTEL_OUTPUT_TVOUT:
97 			*source = INTEL_PIPE_CRC_SOURCE_TV;
98 			break;
99 		case INTEL_OUTPUT_DP:
100 		case INTEL_OUTPUT_EDP:
101 			dig_port = enc_to_dig_port(&encoder->base);
102 			switch (dig_port->base.port) {
103 			case PORT_B:
104 				*source = INTEL_PIPE_CRC_SOURCE_DP_B;
105 				break;
106 			case PORT_C:
107 				*source = INTEL_PIPE_CRC_SOURCE_DP_C;
108 				break;
109 			case PORT_D:
110 				*source = INTEL_PIPE_CRC_SOURCE_DP_D;
111 				break;
112 			default:
113 				WARN(1, "nonexisting DP port %c\n",
114 				     port_name(dig_port->base.port));
115 				break;
116 			}
117 			break;
118 		default:
119 			break;
120 		}
121 	}
122 	drm_modeset_unlock_all(dev);
123 
124 	return ret;
125 }
126 
127 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
128 				enum pipe pipe,
129 				enum intel_pipe_crc_source *source,
130 				u32 *val)
131 {
132 	bool need_stable_symbols = false;
133 
134 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
135 		int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
136 		if (ret)
137 			return ret;
138 	}
139 
140 	switch (*source) {
141 	case INTEL_PIPE_CRC_SOURCE_PIPE:
142 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
143 		break;
144 	case INTEL_PIPE_CRC_SOURCE_DP_B:
145 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
146 		need_stable_symbols = true;
147 		break;
148 	case INTEL_PIPE_CRC_SOURCE_DP_C:
149 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
150 		need_stable_symbols = true;
151 		break;
152 	case INTEL_PIPE_CRC_SOURCE_DP_D:
153 		if (!IS_CHERRYVIEW(dev_priv))
154 			return -EINVAL;
155 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
156 		need_stable_symbols = true;
157 		break;
158 	case INTEL_PIPE_CRC_SOURCE_NONE:
159 		*val = 0;
160 		break;
161 	default:
162 		return -EINVAL;
163 	}
164 
165 	/*
166 	 * When the pipe CRC tap point is after the transcoders we need
167 	 * to tweak symbol-level features to produce a deterministic series of
168 	 * symbols for a given frame. We need to reset those features only once
169 	 * a frame (instead of every nth symbol):
170 	 *   - DC-balance: used to ensure a better clock recovery from the data
171 	 *     link (SDVO)
172 	 *   - DisplayPort scrambling: used for EMI reduction
173 	 */
174 	if (need_stable_symbols) {
175 		u32 tmp = I915_READ(PORT_DFT2_G4X);
176 
177 		tmp |= DC_BALANCE_RESET_VLV;
178 		switch (pipe) {
179 		case PIPE_A:
180 			tmp |= PIPE_A_SCRAMBLE_RESET;
181 			break;
182 		case PIPE_B:
183 			tmp |= PIPE_B_SCRAMBLE_RESET;
184 			break;
185 		case PIPE_C:
186 			tmp |= PIPE_C_SCRAMBLE_RESET;
187 			break;
188 		default:
189 			return -EINVAL;
190 		}
191 		I915_WRITE(PORT_DFT2_G4X, tmp);
192 	}
193 
194 	return 0;
195 }
196 
197 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
198 				 enum pipe pipe,
199 				 enum intel_pipe_crc_source *source,
200 				 u32 *val)
201 {
202 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
203 		int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
204 		if (ret)
205 			return ret;
206 	}
207 
208 	switch (*source) {
209 	case INTEL_PIPE_CRC_SOURCE_PIPE:
210 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
211 		break;
212 	case INTEL_PIPE_CRC_SOURCE_TV:
213 		if (!SUPPORTS_TV(dev_priv))
214 			return -EINVAL;
215 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
216 		break;
217 	case INTEL_PIPE_CRC_SOURCE_NONE:
218 		*val = 0;
219 		break;
220 	default:
221 		/*
222 		 * The DP CRC source doesn't work on g4x.
223 		 * It can be made to work to some degree by selecting
224 		 * the correct CRC source before the port is enabled,
225 		 * and not touching the CRC source bits again until
226 		 * the port is disabled. But even then the bits
227 		 * eventually get stuck and a reboot is needed to get
228 		 * working CRCs on the pipe again. Let's simply
229 		 * refuse to use DP CRCs on g4x.
230 		 */
231 		return -EINVAL;
232 	}
233 
234 	return 0;
235 }
236 
237 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
238 					 enum pipe pipe)
239 {
240 	u32 tmp = I915_READ(PORT_DFT2_G4X);
241 
242 	switch (pipe) {
243 	case PIPE_A:
244 		tmp &= ~PIPE_A_SCRAMBLE_RESET;
245 		break;
246 	case PIPE_B:
247 		tmp &= ~PIPE_B_SCRAMBLE_RESET;
248 		break;
249 	case PIPE_C:
250 		tmp &= ~PIPE_C_SCRAMBLE_RESET;
251 		break;
252 	default:
253 		return;
254 	}
255 	if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
256 		tmp &= ~DC_BALANCE_RESET_VLV;
257 	I915_WRITE(PORT_DFT2_G4X, tmp);
258 }
259 
260 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
261 				u32 *val)
262 {
263 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
264 		*source = INTEL_PIPE_CRC_SOURCE_PIPE;
265 
266 	switch (*source) {
267 	case INTEL_PIPE_CRC_SOURCE_PLANE1:
268 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
269 		break;
270 	case INTEL_PIPE_CRC_SOURCE_PLANE2:
271 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
272 		break;
273 	case INTEL_PIPE_CRC_SOURCE_PIPE:
274 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
275 		break;
276 	case INTEL_PIPE_CRC_SOURCE_NONE:
277 		*val = 0;
278 		break;
279 	default:
280 		return -EINVAL;
281 	}
282 
283 	return 0;
284 }
285 
286 static void
287 intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
288 {
289 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
290 	struct intel_crtc_state *pipe_config;
291 	struct drm_atomic_state *state;
292 	struct drm_modeset_acquire_ctx ctx;
293 	int ret;
294 
295 	drm_modeset_acquire_init(&ctx, 0);
296 
297 	state = drm_atomic_state_alloc(&dev_priv->drm);
298 	if (!state) {
299 		ret = -ENOMEM;
300 		goto unlock;
301 	}
302 
303 	state->acquire_ctx = &ctx;
304 
305 retry:
306 	pipe_config = intel_atomic_get_crtc_state(state, crtc);
307 	if (IS_ERR(pipe_config)) {
308 		ret = PTR_ERR(pipe_config);
309 		goto put_state;
310 	}
311 
312 	pipe_config->base.mode_changed = pipe_config->has_psr;
313 	pipe_config->crc_enabled = enable;
314 
315 	if (IS_HASWELL(dev_priv) &&
316 	    pipe_config->base.active && crtc->pipe == PIPE_A &&
317 	    pipe_config->cpu_transcoder == TRANSCODER_EDP)
318 		pipe_config->base.mode_changed = true;
319 
320 	ret = drm_atomic_commit(state);
321 
322 put_state:
323 	if (ret == -EDEADLK) {
324 		drm_atomic_state_clear(state);
325 		drm_modeset_backoff(&ctx);
326 		goto retry;
327 	}
328 
329 	drm_atomic_state_put(state);
330 unlock:
331 	WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
332 	drm_modeset_drop_locks(&ctx);
333 	drm_modeset_acquire_fini(&ctx);
334 }
335 
336 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
337 				enum pipe pipe,
338 				enum intel_pipe_crc_source *source,
339 				u32 *val)
340 {
341 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
342 		*source = INTEL_PIPE_CRC_SOURCE_PIPE;
343 
344 	switch (*source) {
345 	case INTEL_PIPE_CRC_SOURCE_PLANE1:
346 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
347 		break;
348 	case INTEL_PIPE_CRC_SOURCE_PLANE2:
349 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
350 		break;
351 	case INTEL_PIPE_CRC_SOURCE_PIPE:
352 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
353 		break;
354 	case INTEL_PIPE_CRC_SOURCE_NONE:
355 		*val = 0;
356 		break;
357 	default:
358 		return -EINVAL;
359 	}
360 
361 	return 0;
362 }
363 
364 static int skl_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
365 				enum pipe pipe,
366 				enum intel_pipe_crc_source *source,
367 				u32 *val)
368 {
369 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
370 		*source = INTEL_PIPE_CRC_SOURCE_PIPE;
371 
372 	switch (*source) {
373 	case INTEL_PIPE_CRC_SOURCE_PLANE1:
374 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_1_SKL;
375 		break;
376 	case INTEL_PIPE_CRC_SOURCE_PLANE2:
377 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_2_SKL;
378 		break;
379 	case INTEL_PIPE_CRC_SOURCE_PLANE3:
380 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_3_SKL;
381 		break;
382 	case INTEL_PIPE_CRC_SOURCE_PLANE4:
383 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_4_SKL;
384 		break;
385 	case INTEL_PIPE_CRC_SOURCE_PLANE5:
386 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_5_SKL;
387 		break;
388 	case INTEL_PIPE_CRC_SOURCE_PLANE6:
389 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_6_SKL;
390 		break;
391 	case INTEL_PIPE_CRC_SOURCE_PLANE7:
392 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_7_SKL;
393 		break;
394 	case INTEL_PIPE_CRC_SOURCE_PIPE:
395 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DMUX_SKL;
396 		break;
397 	case INTEL_PIPE_CRC_SOURCE_NONE:
398 		*val = 0;
399 		break;
400 	default:
401 		return -EINVAL;
402 	}
403 
404 	return 0;
405 }
406 
407 static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
408 			       enum pipe pipe,
409 			       enum intel_pipe_crc_source *source, u32 *val)
410 {
411 	if (IS_GEN(dev_priv, 2))
412 		return i8xx_pipe_crc_ctl_reg(source, val);
413 	else if (INTEL_GEN(dev_priv) < 5)
414 		return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
415 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
416 		return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
417 	else if (IS_GEN_RANGE(dev_priv, 5, 6))
418 		return ilk_pipe_crc_ctl_reg(source, val);
419 	else if (INTEL_GEN(dev_priv) < 9)
420 		return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
421 	else
422 		return skl_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
423 }
424 
425 static int
426 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
427 {
428 	int i;
429 
430 	if (!buf) {
431 		*s = INTEL_PIPE_CRC_SOURCE_NONE;
432 		return 0;
433 	}
434 
435 	i = match_string(pipe_crc_sources, ARRAY_SIZE(pipe_crc_sources), buf);
436 	if (i < 0)
437 		return i;
438 
439 	*s = i;
440 	return 0;
441 }
442 
443 void intel_display_crc_init(struct drm_i915_private *dev_priv)
444 {
445 	enum pipe pipe;
446 
447 	for_each_pipe(dev_priv, pipe) {
448 		struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
449 
450 		spin_lock_init(&pipe_crc->lock);
451 	}
452 }
453 
454 static int i8xx_crc_source_valid(struct drm_i915_private *dev_priv,
455 				 const enum intel_pipe_crc_source source)
456 {
457 	switch (source) {
458 	case INTEL_PIPE_CRC_SOURCE_PIPE:
459 	case INTEL_PIPE_CRC_SOURCE_NONE:
460 		return 0;
461 	default:
462 		return -EINVAL;
463 	}
464 }
465 
466 static int i9xx_crc_source_valid(struct drm_i915_private *dev_priv,
467 				 const enum intel_pipe_crc_source source)
468 {
469 	switch (source) {
470 	case INTEL_PIPE_CRC_SOURCE_PIPE:
471 	case INTEL_PIPE_CRC_SOURCE_TV:
472 	case INTEL_PIPE_CRC_SOURCE_NONE:
473 		return 0;
474 	default:
475 		return -EINVAL;
476 	}
477 }
478 
479 static int vlv_crc_source_valid(struct drm_i915_private *dev_priv,
480 				const enum intel_pipe_crc_source source)
481 {
482 	switch (source) {
483 	case INTEL_PIPE_CRC_SOURCE_PIPE:
484 	case INTEL_PIPE_CRC_SOURCE_DP_B:
485 	case INTEL_PIPE_CRC_SOURCE_DP_C:
486 	case INTEL_PIPE_CRC_SOURCE_DP_D:
487 	case INTEL_PIPE_CRC_SOURCE_NONE:
488 		return 0;
489 	default:
490 		return -EINVAL;
491 	}
492 }
493 
494 static int ilk_crc_source_valid(struct drm_i915_private *dev_priv,
495 				const enum intel_pipe_crc_source source)
496 {
497 	switch (source) {
498 	case INTEL_PIPE_CRC_SOURCE_PIPE:
499 	case INTEL_PIPE_CRC_SOURCE_PLANE1:
500 	case INTEL_PIPE_CRC_SOURCE_PLANE2:
501 	case INTEL_PIPE_CRC_SOURCE_NONE:
502 		return 0;
503 	default:
504 		return -EINVAL;
505 	}
506 }
507 
508 static int ivb_crc_source_valid(struct drm_i915_private *dev_priv,
509 				const enum intel_pipe_crc_source source)
510 {
511 	switch (source) {
512 	case INTEL_PIPE_CRC_SOURCE_PIPE:
513 	case INTEL_PIPE_CRC_SOURCE_PLANE1:
514 	case INTEL_PIPE_CRC_SOURCE_PLANE2:
515 	case INTEL_PIPE_CRC_SOURCE_NONE:
516 		return 0;
517 	default:
518 		return -EINVAL;
519 	}
520 }
521 
522 static int skl_crc_source_valid(struct drm_i915_private *dev_priv,
523 				const enum intel_pipe_crc_source source)
524 {
525 	switch (source) {
526 	case INTEL_PIPE_CRC_SOURCE_PIPE:
527 	case INTEL_PIPE_CRC_SOURCE_PLANE1:
528 	case INTEL_PIPE_CRC_SOURCE_PLANE2:
529 	case INTEL_PIPE_CRC_SOURCE_PLANE3:
530 	case INTEL_PIPE_CRC_SOURCE_PLANE4:
531 	case INTEL_PIPE_CRC_SOURCE_PLANE5:
532 	case INTEL_PIPE_CRC_SOURCE_PLANE6:
533 	case INTEL_PIPE_CRC_SOURCE_PLANE7:
534 	case INTEL_PIPE_CRC_SOURCE_NONE:
535 		return 0;
536 	default:
537 		return -EINVAL;
538 	}
539 }
540 
541 static int
542 intel_is_valid_crc_source(struct drm_i915_private *dev_priv,
543 			  const enum intel_pipe_crc_source source)
544 {
545 	if (IS_GEN(dev_priv, 2))
546 		return i8xx_crc_source_valid(dev_priv, source);
547 	else if (INTEL_GEN(dev_priv) < 5)
548 		return i9xx_crc_source_valid(dev_priv, source);
549 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
550 		return vlv_crc_source_valid(dev_priv, source);
551 	else if (IS_GEN_RANGE(dev_priv, 5, 6))
552 		return ilk_crc_source_valid(dev_priv, source);
553 	else if (INTEL_GEN(dev_priv) < 9)
554 		return ivb_crc_source_valid(dev_priv, source);
555 	else
556 		return skl_crc_source_valid(dev_priv, source);
557 }
558 
559 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
560 					      size_t *count)
561 {
562 	*count = ARRAY_SIZE(pipe_crc_sources);
563 	return pipe_crc_sources;
564 }
565 
566 int intel_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
567 				 size_t *values_cnt)
568 {
569 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
570 	enum intel_pipe_crc_source source;
571 
572 	if (display_crc_ctl_parse_source(source_name, &source) < 0) {
573 		DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
574 		return -EINVAL;
575 	}
576 
577 	if (source == INTEL_PIPE_CRC_SOURCE_AUTO ||
578 	    intel_is_valid_crc_source(dev_priv, source) == 0) {
579 		*values_cnt = 5;
580 		return 0;
581 	}
582 
583 	return -EINVAL;
584 }
585 
586 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name)
587 {
588 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
589 	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
590 	enum intel_display_power_domain power_domain;
591 	enum intel_pipe_crc_source source;
592 	intel_wakeref_t wakeref;
593 	u32 val = 0; /* shut up gcc */
594 	int ret = 0;
595 	bool enable;
596 
597 	if (display_crc_ctl_parse_source(source_name, &source) < 0) {
598 		DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
599 		return -EINVAL;
600 	}
601 
602 	power_domain = POWER_DOMAIN_PIPE(crtc->index);
603 	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
604 	if (!wakeref) {
605 		DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
606 		return -EIO;
607 	}
608 
609 	enable = source != INTEL_PIPE_CRC_SOURCE_NONE;
610 	if (enable)
611 		intel_crtc_crc_setup_workarounds(to_intel_crtc(crtc), true);
612 
613 	ret = get_new_crc_ctl_reg(dev_priv, crtc->index, &source, &val);
614 	if (ret != 0)
615 		goto out;
616 
617 	pipe_crc->source = source;
618 	I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
619 	POSTING_READ(PIPE_CRC_CTL(crtc->index));
620 
621 	if (!source) {
622 		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
623 			vlv_undo_pipe_scramble_reset(dev_priv, crtc->index);
624 	}
625 
626 	pipe_crc->skipped = 0;
627 
628 out:
629 	if (!enable)
630 		intel_crtc_crc_setup_workarounds(to_intel_crtc(crtc), false);
631 
632 	intel_display_power_put(dev_priv, power_domain, wakeref);
633 
634 	return ret;
635 }
636 
637 void intel_crtc_enable_pipe_crc(struct intel_crtc *intel_crtc)
638 {
639 	struct drm_crtc *crtc = &intel_crtc->base;
640 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
641 	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
642 	u32 val = 0;
643 
644 	if (!crtc->crc.opened)
645 		return;
646 
647 	if (get_new_crc_ctl_reg(dev_priv, crtc->index, &pipe_crc->source, &val) < 0)
648 		return;
649 
650 	/* Don't need pipe_crc->lock here, IRQs are not generated. */
651 	pipe_crc->skipped = 0;
652 
653 	I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
654 	POSTING_READ(PIPE_CRC_CTL(crtc->index));
655 }
656 
657 void intel_crtc_disable_pipe_crc(struct intel_crtc *intel_crtc)
658 {
659 	struct drm_crtc *crtc = &intel_crtc->base;
660 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
661 	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
662 
663 	/* Swallow crc's until we stop generating them. */
664 	spin_lock_irq(&pipe_crc->lock);
665 	pipe_crc->skipped = INT_MIN;
666 	spin_unlock_irq(&pipe_crc->lock);
667 
668 	I915_WRITE(PIPE_CRC_CTL(crtc->index), 0);
669 	POSTING_READ(PIPE_CRC_CTL(crtc->index));
670 	synchronize_irq(dev_priv->drm.irq);
671 }
672