1 /*
2  * Copyright © 2013 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Author: Damien Lespiau <damien.lespiau@intel.com>
24  *
25  */
26 
27 #include <linux/circ_buf.h>
28 #include <linux/ctype.h>
29 #include <linux/debugfs.h>
30 #include <linux/seq_file.h>
31 
32 #include "i915_irq.h"
33 #include "i915_reg.h"
34 #include "intel_atomic.h"
35 #include "intel_de.h"
36 #include "intel_display_types.h"
37 #include "intel_pipe_crc.h"
38 
39 static const char * const pipe_crc_sources[] = {
40 	[INTEL_PIPE_CRC_SOURCE_NONE] = "none",
41 	[INTEL_PIPE_CRC_SOURCE_PLANE1] = "plane1",
42 	[INTEL_PIPE_CRC_SOURCE_PLANE2] = "plane2",
43 	[INTEL_PIPE_CRC_SOURCE_PLANE3] = "plane3",
44 	[INTEL_PIPE_CRC_SOURCE_PLANE4] = "plane4",
45 	[INTEL_PIPE_CRC_SOURCE_PLANE5] = "plane5",
46 	[INTEL_PIPE_CRC_SOURCE_PLANE6] = "plane6",
47 	[INTEL_PIPE_CRC_SOURCE_PLANE7] = "plane7",
48 	[INTEL_PIPE_CRC_SOURCE_PIPE] = "pipe",
49 	[INTEL_PIPE_CRC_SOURCE_TV] = "TV",
50 	[INTEL_PIPE_CRC_SOURCE_DP_B] = "DP-B",
51 	[INTEL_PIPE_CRC_SOURCE_DP_C] = "DP-C",
52 	[INTEL_PIPE_CRC_SOURCE_DP_D] = "DP-D",
53 	[INTEL_PIPE_CRC_SOURCE_AUTO] = "auto",
54 };
55 
56 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
57 				 u32 *val)
58 {
59 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
60 		*source = INTEL_PIPE_CRC_SOURCE_PIPE;
61 
62 	switch (*source) {
63 	case INTEL_PIPE_CRC_SOURCE_PIPE:
64 		*val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
65 		break;
66 	case INTEL_PIPE_CRC_SOURCE_NONE:
67 		*val = 0;
68 		break;
69 	default:
70 		return -EINVAL;
71 	}
72 
73 	return 0;
74 }
75 
76 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
77 				     enum pipe pipe,
78 				     enum intel_pipe_crc_source *source)
79 {
80 	struct intel_encoder *encoder;
81 	struct intel_crtc *crtc;
82 	struct intel_digital_port *dig_port;
83 	int ret = 0;
84 
85 	*source = INTEL_PIPE_CRC_SOURCE_PIPE;
86 
87 	drm_modeset_lock_all(&dev_priv->drm);
88 	for_each_intel_encoder(&dev_priv->drm, encoder) {
89 		if (!encoder->base.crtc)
90 			continue;
91 
92 		crtc = to_intel_crtc(encoder->base.crtc);
93 
94 		if (crtc->pipe != pipe)
95 			continue;
96 
97 		switch (encoder->type) {
98 		case INTEL_OUTPUT_TVOUT:
99 			*source = INTEL_PIPE_CRC_SOURCE_TV;
100 			break;
101 		case INTEL_OUTPUT_DP:
102 		case INTEL_OUTPUT_EDP:
103 			dig_port = enc_to_dig_port(encoder);
104 			switch (dig_port->base.port) {
105 			case PORT_B:
106 				*source = INTEL_PIPE_CRC_SOURCE_DP_B;
107 				break;
108 			case PORT_C:
109 				*source = INTEL_PIPE_CRC_SOURCE_DP_C;
110 				break;
111 			case PORT_D:
112 				*source = INTEL_PIPE_CRC_SOURCE_DP_D;
113 				break;
114 			default:
115 				drm_WARN(&dev_priv->drm, 1, "nonexisting DP port %c\n",
116 					 port_name(dig_port->base.port));
117 				break;
118 			}
119 			break;
120 		default:
121 			break;
122 		}
123 	}
124 	drm_modeset_unlock_all(&dev_priv->drm);
125 
126 	return ret;
127 }
128 
129 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
130 				enum pipe pipe,
131 				enum intel_pipe_crc_source *source,
132 				u32 *val)
133 {
134 	bool need_stable_symbols = false;
135 
136 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
137 		int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
138 		if (ret)
139 			return ret;
140 	}
141 
142 	switch (*source) {
143 	case INTEL_PIPE_CRC_SOURCE_PIPE:
144 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
145 		break;
146 	case INTEL_PIPE_CRC_SOURCE_DP_B:
147 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
148 		need_stable_symbols = true;
149 		break;
150 	case INTEL_PIPE_CRC_SOURCE_DP_C:
151 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
152 		need_stable_symbols = true;
153 		break;
154 	case INTEL_PIPE_CRC_SOURCE_DP_D:
155 		if (!IS_CHERRYVIEW(dev_priv))
156 			return -EINVAL;
157 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
158 		need_stable_symbols = true;
159 		break;
160 	case INTEL_PIPE_CRC_SOURCE_NONE:
161 		*val = 0;
162 		break;
163 	default:
164 		return -EINVAL;
165 	}
166 
167 	/*
168 	 * When the pipe CRC tap point is after the transcoders we need
169 	 * to tweak symbol-level features to produce a deterministic series of
170 	 * symbols for a given frame. We need to reset those features only once
171 	 * a frame (instead of every nth symbol):
172 	 *   - DC-balance: used to ensure a better clock recovery from the data
173 	 *     link (SDVO)
174 	 *   - DisplayPort scrambling: used for EMI reduction
175 	 */
176 	if (need_stable_symbols) {
177 		u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X);
178 
179 		tmp |= DC_BALANCE_RESET_VLV;
180 		switch (pipe) {
181 		case PIPE_A:
182 			tmp |= PIPE_A_SCRAMBLE_RESET;
183 			break;
184 		case PIPE_B:
185 			tmp |= PIPE_B_SCRAMBLE_RESET;
186 			break;
187 		case PIPE_C:
188 			tmp |= PIPE_C_SCRAMBLE_RESET;
189 			break;
190 		default:
191 			return -EINVAL;
192 		}
193 		intel_de_write(dev_priv, PORT_DFT2_G4X, tmp);
194 	}
195 
196 	return 0;
197 }
198 
199 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
200 				 enum pipe pipe,
201 				 enum intel_pipe_crc_source *source,
202 				 u32 *val)
203 {
204 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
205 		int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
206 		if (ret)
207 			return ret;
208 	}
209 
210 	switch (*source) {
211 	case INTEL_PIPE_CRC_SOURCE_PIPE:
212 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
213 		break;
214 	case INTEL_PIPE_CRC_SOURCE_TV:
215 		if (!SUPPORTS_TV(dev_priv))
216 			return -EINVAL;
217 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
218 		break;
219 	case INTEL_PIPE_CRC_SOURCE_NONE:
220 		*val = 0;
221 		break;
222 	default:
223 		/*
224 		 * The DP CRC source doesn't work on g4x.
225 		 * It can be made to work to some degree by selecting
226 		 * the correct CRC source before the port is enabled,
227 		 * and not touching the CRC source bits again until
228 		 * the port is disabled. But even then the bits
229 		 * eventually get stuck and a reboot is needed to get
230 		 * working CRCs on the pipe again. Let's simply
231 		 * refuse to use DP CRCs on g4x.
232 		 */
233 		return -EINVAL;
234 	}
235 
236 	return 0;
237 }
238 
239 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
240 					 enum pipe pipe)
241 {
242 	u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X);
243 
244 	switch (pipe) {
245 	case PIPE_A:
246 		tmp &= ~PIPE_A_SCRAMBLE_RESET;
247 		break;
248 	case PIPE_B:
249 		tmp &= ~PIPE_B_SCRAMBLE_RESET;
250 		break;
251 	case PIPE_C:
252 		tmp &= ~PIPE_C_SCRAMBLE_RESET;
253 		break;
254 	default:
255 		return;
256 	}
257 	if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
258 		tmp &= ~DC_BALANCE_RESET_VLV;
259 	intel_de_write(dev_priv, PORT_DFT2_G4X, tmp);
260 }
261 
262 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
263 				u32 *val)
264 {
265 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
266 		*source = INTEL_PIPE_CRC_SOURCE_PIPE;
267 
268 	switch (*source) {
269 	case INTEL_PIPE_CRC_SOURCE_PLANE1:
270 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
271 		break;
272 	case INTEL_PIPE_CRC_SOURCE_PLANE2:
273 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
274 		break;
275 	case INTEL_PIPE_CRC_SOURCE_PIPE:
276 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
277 		break;
278 	case INTEL_PIPE_CRC_SOURCE_NONE:
279 		*val = 0;
280 		break;
281 	default:
282 		return -EINVAL;
283 	}
284 
285 	return 0;
286 }
287 
288 static void
289 intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
290 {
291 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
292 	struct intel_crtc_state *pipe_config;
293 	struct drm_atomic_state *state;
294 	struct drm_modeset_acquire_ctx ctx;
295 	int ret;
296 
297 	drm_modeset_acquire_init(&ctx, 0);
298 
299 	state = drm_atomic_state_alloc(&dev_priv->drm);
300 	if (!state) {
301 		ret = -ENOMEM;
302 		goto unlock;
303 	}
304 
305 	state->acquire_ctx = &ctx;
306 
307 retry:
308 	pipe_config = intel_atomic_get_crtc_state(state, crtc);
309 	if (IS_ERR(pipe_config)) {
310 		ret = PTR_ERR(pipe_config);
311 		goto put_state;
312 	}
313 
314 	pipe_config->uapi.mode_changed = pipe_config->has_psr;
315 	pipe_config->crc_enabled = enable;
316 
317 	if (IS_HASWELL(dev_priv) &&
318 	    pipe_config->hw.active && crtc->pipe == PIPE_A &&
319 	    pipe_config->cpu_transcoder == TRANSCODER_EDP)
320 		pipe_config->uapi.mode_changed = true;
321 
322 	ret = drm_atomic_commit(state);
323 
324 put_state:
325 	if (ret == -EDEADLK) {
326 		drm_atomic_state_clear(state);
327 		drm_modeset_backoff(&ctx);
328 		goto retry;
329 	}
330 
331 	drm_atomic_state_put(state);
332 unlock:
333 	drm_WARN(&dev_priv->drm, ret,
334 		 "Toggling workaround to %i returns %i\n", enable, ret);
335 	drm_modeset_drop_locks(&ctx);
336 	drm_modeset_acquire_fini(&ctx);
337 }
338 
339 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
340 				enum pipe pipe,
341 				enum intel_pipe_crc_source *source,
342 				u32 *val)
343 {
344 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
345 		*source = INTEL_PIPE_CRC_SOURCE_PIPE;
346 
347 	switch (*source) {
348 	case INTEL_PIPE_CRC_SOURCE_PLANE1:
349 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
350 		break;
351 	case INTEL_PIPE_CRC_SOURCE_PLANE2:
352 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
353 		break;
354 	case INTEL_PIPE_CRC_SOURCE_PIPE:
355 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
356 		break;
357 	case INTEL_PIPE_CRC_SOURCE_NONE:
358 		*val = 0;
359 		break;
360 	default:
361 		return -EINVAL;
362 	}
363 
364 	return 0;
365 }
366 
367 static int skl_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
368 				enum pipe pipe,
369 				enum intel_pipe_crc_source *source,
370 				u32 *val)
371 {
372 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
373 		*source = INTEL_PIPE_CRC_SOURCE_PIPE;
374 
375 	switch (*source) {
376 	case INTEL_PIPE_CRC_SOURCE_PLANE1:
377 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_1_SKL;
378 		break;
379 	case INTEL_PIPE_CRC_SOURCE_PLANE2:
380 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_2_SKL;
381 		break;
382 	case INTEL_PIPE_CRC_SOURCE_PLANE3:
383 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_3_SKL;
384 		break;
385 	case INTEL_PIPE_CRC_SOURCE_PLANE4:
386 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_4_SKL;
387 		break;
388 	case INTEL_PIPE_CRC_SOURCE_PLANE5:
389 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_5_SKL;
390 		break;
391 	case INTEL_PIPE_CRC_SOURCE_PLANE6:
392 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_6_SKL;
393 		break;
394 	case INTEL_PIPE_CRC_SOURCE_PLANE7:
395 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_7_SKL;
396 		break;
397 	case INTEL_PIPE_CRC_SOURCE_PIPE:
398 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DMUX_SKL;
399 		break;
400 	case INTEL_PIPE_CRC_SOURCE_NONE:
401 		*val = 0;
402 		break;
403 	default:
404 		return -EINVAL;
405 	}
406 
407 	return 0;
408 }
409 
410 static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
411 			       enum pipe pipe,
412 			       enum intel_pipe_crc_source *source, u32 *val)
413 {
414 	if (DISPLAY_VER(dev_priv) == 2)
415 		return i8xx_pipe_crc_ctl_reg(source, val);
416 	else if (DISPLAY_VER(dev_priv) < 5)
417 		return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
418 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
419 		return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
420 	else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv))
421 		return ilk_pipe_crc_ctl_reg(source, val);
422 	else if (DISPLAY_VER(dev_priv) < 9)
423 		return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
424 	else
425 		return skl_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
426 }
427 
428 static int
429 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
430 {
431 	int i;
432 
433 	if (!buf) {
434 		*s = INTEL_PIPE_CRC_SOURCE_NONE;
435 		return 0;
436 	}
437 
438 	i = match_string(pipe_crc_sources, ARRAY_SIZE(pipe_crc_sources), buf);
439 	if (i < 0)
440 		return i;
441 
442 	*s = i;
443 	return 0;
444 }
445 
446 void intel_crtc_crc_init(struct intel_crtc *crtc)
447 {
448 	struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
449 
450 	spin_lock_init(&pipe_crc->lock);
451 }
452 
453 static int i8xx_crc_source_valid(struct drm_i915_private *dev_priv,
454 				 const enum intel_pipe_crc_source source)
455 {
456 	switch (source) {
457 	case INTEL_PIPE_CRC_SOURCE_PIPE:
458 	case INTEL_PIPE_CRC_SOURCE_NONE:
459 		return 0;
460 	default:
461 		return -EINVAL;
462 	}
463 }
464 
465 static int i9xx_crc_source_valid(struct drm_i915_private *dev_priv,
466 				 const enum intel_pipe_crc_source source)
467 {
468 	switch (source) {
469 	case INTEL_PIPE_CRC_SOURCE_PIPE:
470 	case INTEL_PIPE_CRC_SOURCE_TV:
471 	case INTEL_PIPE_CRC_SOURCE_NONE:
472 		return 0;
473 	default:
474 		return -EINVAL;
475 	}
476 }
477 
478 static int vlv_crc_source_valid(struct drm_i915_private *dev_priv,
479 				const enum intel_pipe_crc_source source)
480 {
481 	switch (source) {
482 	case INTEL_PIPE_CRC_SOURCE_PIPE:
483 	case INTEL_PIPE_CRC_SOURCE_DP_B:
484 	case INTEL_PIPE_CRC_SOURCE_DP_C:
485 	case INTEL_PIPE_CRC_SOURCE_DP_D:
486 	case INTEL_PIPE_CRC_SOURCE_NONE:
487 		return 0;
488 	default:
489 		return -EINVAL;
490 	}
491 }
492 
493 static int ilk_crc_source_valid(struct drm_i915_private *dev_priv,
494 				const enum intel_pipe_crc_source source)
495 {
496 	switch (source) {
497 	case INTEL_PIPE_CRC_SOURCE_PIPE:
498 	case INTEL_PIPE_CRC_SOURCE_PLANE1:
499 	case INTEL_PIPE_CRC_SOURCE_PLANE2:
500 	case INTEL_PIPE_CRC_SOURCE_NONE:
501 		return 0;
502 	default:
503 		return -EINVAL;
504 	}
505 }
506 
507 static int ivb_crc_source_valid(struct drm_i915_private *dev_priv,
508 				const enum intel_pipe_crc_source source)
509 {
510 	switch (source) {
511 	case INTEL_PIPE_CRC_SOURCE_PIPE:
512 	case INTEL_PIPE_CRC_SOURCE_PLANE1:
513 	case INTEL_PIPE_CRC_SOURCE_PLANE2:
514 	case INTEL_PIPE_CRC_SOURCE_NONE:
515 		return 0;
516 	default:
517 		return -EINVAL;
518 	}
519 }
520 
521 static int skl_crc_source_valid(struct drm_i915_private *dev_priv,
522 				const enum intel_pipe_crc_source source)
523 {
524 	switch (source) {
525 	case INTEL_PIPE_CRC_SOURCE_PIPE:
526 	case INTEL_PIPE_CRC_SOURCE_PLANE1:
527 	case INTEL_PIPE_CRC_SOURCE_PLANE2:
528 	case INTEL_PIPE_CRC_SOURCE_PLANE3:
529 	case INTEL_PIPE_CRC_SOURCE_PLANE4:
530 	case INTEL_PIPE_CRC_SOURCE_PLANE5:
531 	case INTEL_PIPE_CRC_SOURCE_PLANE6:
532 	case INTEL_PIPE_CRC_SOURCE_PLANE7:
533 	case INTEL_PIPE_CRC_SOURCE_NONE:
534 		return 0;
535 	default:
536 		return -EINVAL;
537 	}
538 }
539 
540 static int
541 intel_is_valid_crc_source(struct drm_i915_private *dev_priv,
542 			  const enum intel_pipe_crc_source source)
543 {
544 	if (DISPLAY_VER(dev_priv) == 2)
545 		return i8xx_crc_source_valid(dev_priv, source);
546 	else if (DISPLAY_VER(dev_priv) < 5)
547 		return i9xx_crc_source_valid(dev_priv, source);
548 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
549 		return vlv_crc_source_valid(dev_priv, source);
550 	else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv))
551 		return ilk_crc_source_valid(dev_priv, source);
552 	else if (DISPLAY_VER(dev_priv) < 9)
553 		return ivb_crc_source_valid(dev_priv, source);
554 	else
555 		return skl_crc_source_valid(dev_priv, source);
556 }
557 
558 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
559 					      size_t *count)
560 {
561 	*count = ARRAY_SIZE(pipe_crc_sources);
562 	return pipe_crc_sources;
563 }
564 
565 int intel_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
566 				 size_t *values_cnt)
567 {
568 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
569 	enum intel_pipe_crc_source source;
570 
571 	if (display_crc_ctl_parse_source(source_name, &source) < 0) {
572 		drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name);
573 		return -EINVAL;
574 	}
575 
576 	if (source == INTEL_PIPE_CRC_SOURCE_AUTO ||
577 	    intel_is_valid_crc_source(dev_priv, source) == 0) {
578 		*values_cnt = 5;
579 		return 0;
580 	}
581 
582 	return -EINVAL;
583 }
584 
585 int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name)
586 {
587 	struct intel_crtc *crtc = to_intel_crtc(_crtc);
588 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
589 	struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
590 	enum intel_display_power_domain power_domain;
591 	enum intel_pipe_crc_source source;
592 	enum pipe pipe = crtc->pipe;
593 	intel_wakeref_t wakeref;
594 	u32 val = 0; /* shut up gcc */
595 	int ret = 0;
596 	bool enable;
597 
598 	if (display_crc_ctl_parse_source(source_name, &source) < 0) {
599 		drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name);
600 		return -EINVAL;
601 	}
602 
603 	power_domain = POWER_DOMAIN_PIPE(pipe);
604 	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
605 	if (!wakeref) {
606 		drm_dbg_kms(&dev_priv->drm,
607 			    "Trying to capture CRC while pipe is off\n");
608 		return -EIO;
609 	}
610 
611 	enable = source != INTEL_PIPE_CRC_SOURCE_NONE;
612 	if (enable)
613 		intel_crtc_crc_setup_workarounds(crtc, true);
614 
615 	ret = get_new_crc_ctl_reg(dev_priv, pipe, &source, &val);
616 	if (ret != 0)
617 		goto out;
618 
619 	pipe_crc->source = source;
620 	intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), val);
621 	intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
622 
623 	if (!source) {
624 		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
625 			vlv_undo_pipe_scramble_reset(dev_priv, pipe);
626 	}
627 
628 	pipe_crc->skipped = 0;
629 
630 out:
631 	if (!enable)
632 		intel_crtc_crc_setup_workarounds(crtc, false);
633 
634 	intel_display_power_put(dev_priv, power_domain, wakeref);
635 
636 	return ret;
637 }
638 
639 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
640 {
641 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
642 	struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
643 	enum pipe pipe = crtc->pipe;
644 	u32 val = 0;
645 
646 	if (!crtc->base.crc.opened)
647 		return;
648 
649 	if (get_new_crc_ctl_reg(dev_priv, pipe, &pipe_crc->source, &val) < 0)
650 		return;
651 
652 	/* Don't need pipe_crc->lock here, IRQs are not generated. */
653 	pipe_crc->skipped = 0;
654 
655 	intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), val);
656 	intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
657 }
658 
659 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
660 {
661 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
662 	struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
663 	enum pipe pipe = crtc->pipe;
664 
665 	/* Swallow crc's until we stop generating them. */
666 	spin_lock_irq(&pipe_crc->lock);
667 	pipe_crc->skipped = INT_MIN;
668 	spin_unlock_irq(&pipe_crc->lock);
669 
670 	intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), 0);
671 	intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
672 	intel_synchronize_irq(dev_priv);
673 }
674