1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "g4x_dp.h" 7 #include "i915_reg.h" 8 #include "intel_crt.h" 9 #include "intel_de.h" 10 #include "intel_display_types.h" 11 #include "intel_fdi.h" 12 #include "intel_fdi_regs.h" 13 #include "intel_lvds.h" 14 #include "intel_lvds_regs.h" 15 #include "intel_pch_display.h" 16 #include "intel_pch_refclk.h" 17 #include "intel_pps.h" 18 #include "intel_sdvo.h" 19 20 bool intel_has_pch_trancoder(struct drm_i915_private *i915, 21 enum pipe pch_transcoder) 22 { 23 return HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915) || 24 (HAS_PCH_LPT_H(i915) && pch_transcoder == PIPE_A); 25 } 26 27 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) 28 { 29 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 30 31 if (HAS_PCH_LPT(i915)) 32 return PIPE_A; 33 else 34 return crtc->pipe; 35 } 36 37 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, 38 enum pipe pipe, enum port port, 39 i915_reg_t dp_reg) 40 { 41 enum pipe port_pipe; 42 bool state; 43 44 state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe); 45 46 I915_STATE_WARN(state && port_pipe == pipe, 47 "PCH DP %c enabled on transcoder %c, should be disabled\n", 48 port_name(port), pipe_name(pipe)); 49 50 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, 51 "IBX PCH DP %c still using transcoder B\n", 52 port_name(port)); 53 } 54 55 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, 56 enum pipe pipe, enum port port, 57 i915_reg_t hdmi_reg) 58 { 59 enum pipe port_pipe; 60 bool state; 61 62 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe); 63 64 I915_STATE_WARN(state && port_pipe == pipe, 65 "PCH HDMI %c enabled on transcoder %c, should be disabled\n", 66 port_name(port), pipe_name(pipe)); 67 68 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, 69 "IBX PCH HDMI %c still using transcoder B\n", 70 port_name(port)); 71 } 72 73 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, 74 enum pipe pipe) 75 { 76 enum pipe port_pipe; 77 78 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B); 79 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C); 80 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D); 81 82 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) && 83 port_pipe == pipe, 84 "PCH VGA enabled on transcoder %c, should be disabled\n", 85 pipe_name(pipe)); 86 87 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) && 88 port_pipe == pipe, 89 "PCH LVDS enabled on transcoder %c, should be disabled\n", 90 pipe_name(pipe)); 91 92 /* PCH SDVOB multiplex with HDMIB */ 93 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB); 94 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC); 95 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID); 96 } 97 98 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 99 enum pipe pipe) 100 { 101 u32 val; 102 bool enabled; 103 104 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe)); 105 enabled = !!(val & TRANS_ENABLE); 106 I915_STATE_WARN(enabled, 107 "transcoder assertion failed, should be off on pipe %c but is still active\n", 108 pipe_name(pipe)); 109 } 110 111 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv, 112 enum port port, i915_reg_t hdmi_reg) 113 { 114 u32 val = intel_de_read(dev_priv, hdmi_reg); 115 116 if (val & SDVO_ENABLE || 117 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A)) 118 return; 119 120 drm_dbg_kms(&dev_priv->drm, 121 "Sanitizing transcoder select for HDMI %c\n", 122 port_name(port)); 123 124 val &= ~SDVO_PIPE_SEL_MASK; 125 val |= SDVO_PIPE_SEL(PIPE_A); 126 127 intel_de_write(dev_priv, hdmi_reg, val); 128 } 129 130 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv, 131 enum port port, i915_reg_t dp_reg) 132 { 133 u32 val = intel_de_read(dev_priv, dp_reg); 134 135 if (val & DP_PORT_EN || 136 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A)) 137 return; 138 139 drm_dbg_kms(&dev_priv->drm, 140 "Sanitizing transcoder select for DP %c\n", 141 port_name(port)); 142 143 val &= ~DP_PIPE_SEL_MASK; 144 val |= DP_PIPE_SEL(PIPE_A); 145 146 intel_de_write(dev_priv, dp_reg, val); 147 } 148 149 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv) 150 { 151 /* 152 * The BIOS may select transcoder B on some of the PCH 153 * ports even it doesn't enable the port. This would trip 154 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled(). 155 * Sanitize the transcoder select bits to prevent that. We 156 * assume that the BIOS never actually enabled the port, 157 * because if it did we'd actually have to toggle the port 158 * on and back off to make the transcoder A select stick 159 * (see. intel_dp_link_down(), intel_disable_hdmi(), 160 * intel_disable_sdvo()). 161 */ 162 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B); 163 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C); 164 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D); 165 166 /* PCH SDVOB multiplex with HDMIB */ 167 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB); 168 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC); 169 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID); 170 } 171 172 static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc, 173 const struct intel_link_m_n *m_n) 174 { 175 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 176 enum pipe pipe = crtc->pipe; 177 178 intel_set_m_n(dev_priv, m_n, 179 PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe), 180 PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); 181 } 182 183 static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc, 184 const struct intel_link_m_n *m_n) 185 { 186 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 187 enum pipe pipe = crtc->pipe; 188 189 intel_set_m_n(dev_priv, m_n, 190 PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe), 191 PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe)); 192 } 193 194 void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc, 195 struct intel_link_m_n *m_n) 196 { 197 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 198 enum pipe pipe = crtc->pipe; 199 200 intel_get_m_n(dev_priv, m_n, 201 PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe), 202 PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); 203 } 204 205 void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc, 206 struct intel_link_m_n *m_n) 207 { 208 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 209 enum pipe pipe = crtc->pipe; 210 211 intel_get_m_n(dev_priv, m_n, 212 PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe), 213 PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe)); 214 } 215 216 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state, 217 enum pipe pch_transcoder) 218 { 219 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 220 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 221 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 222 223 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder), 224 intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder))); 225 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder), 226 intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder))); 227 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder), 228 intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder))); 229 230 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder), 231 intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder))); 232 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder), 233 intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder))); 234 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder), 235 intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder))); 236 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder), 237 intel_de_read(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder))); 238 } 239 240 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) 241 { 242 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 243 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 244 enum pipe pipe = crtc->pipe; 245 i915_reg_t reg; 246 u32 val, pipeconf_val; 247 248 /* Make sure PCH DPLL is enabled */ 249 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll); 250 251 /* FDI must be feeding us bits for PCH ports */ 252 assert_fdi_tx_enabled(dev_priv, pipe); 253 assert_fdi_rx_enabled(dev_priv, pipe); 254 255 if (HAS_PCH_CPT(dev_priv)) { 256 reg = TRANS_CHICKEN2(pipe); 257 val = intel_de_read(dev_priv, reg); 258 /* 259 * Workaround: Set the timing override bit 260 * before enabling the pch transcoder. 261 */ 262 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 263 /* Configure frame start delay to match the CPU */ 264 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 265 val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 266 intel_de_write(dev_priv, reg, val); 267 } 268 269 reg = PCH_TRANSCONF(pipe); 270 val = intel_de_read(dev_priv, reg); 271 pipeconf_val = intel_de_read(dev_priv, TRANSCONF(pipe)); 272 273 if (HAS_PCH_IBX(dev_priv)) { 274 /* Configure frame start delay to match the CPU */ 275 val &= ~TRANS_FRAME_START_DELAY_MASK; 276 val |= TRANS_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 277 278 /* 279 * Make the BPC in transcoder be consistent with 280 * that in pipeconf reg. For HDMI we must use 8bpc 281 * here for both 8bpc and 12bpc. 282 */ 283 val &= ~TRANSCONF_BPC_MASK; 284 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 285 val |= TRANSCONF_BPC_8; 286 else 287 val |= pipeconf_val & TRANSCONF_BPC_MASK; 288 } 289 290 val &= ~TRANS_INTERLACE_MASK; 291 if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_ILK) == TRANSCONF_INTERLACE_IF_ID_ILK) { 292 if (HAS_PCH_IBX(dev_priv) && 293 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 294 val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX; 295 else 296 val |= TRANS_INTERLACE_INTERLACED; 297 } else { 298 val |= TRANS_INTERLACE_PROGRESSIVE; 299 } 300 301 intel_de_write(dev_priv, reg, val | TRANS_ENABLE); 302 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100)) 303 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n", 304 pipe_name(pipe)); 305 } 306 307 static void ilk_disable_pch_transcoder(struct intel_crtc *crtc) 308 { 309 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 310 enum pipe pipe = crtc->pipe; 311 i915_reg_t reg; 312 313 /* FDI relies on the transcoder */ 314 assert_fdi_tx_disabled(dev_priv, pipe); 315 assert_fdi_rx_disabled(dev_priv, pipe); 316 317 /* Ports must be off as well */ 318 assert_pch_ports_disabled(dev_priv, pipe); 319 320 reg = PCH_TRANSCONF(pipe); 321 intel_de_rmw(dev_priv, reg, TRANS_ENABLE, 0); 322 /* wait for PCH transcoder off, transcoder state */ 323 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50)) 324 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n", 325 pipe_name(pipe)); 326 327 if (HAS_PCH_CPT(dev_priv)) 328 /* Workaround: Clear the timing override chicken bit again. */ 329 intel_de_rmw(dev_priv, TRANS_CHICKEN2(pipe), 330 TRANS_CHICKEN2_TIMING_OVERRIDE, 0); 331 } 332 333 void ilk_pch_pre_enable(struct intel_atomic_state *state, 334 struct intel_crtc *crtc) 335 { 336 const struct intel_crtc_state *crtc_state = 337 intel_atomic_get_new_crtc_state(state, crtc); 338 339 /* 340 * Note: FDI PLL enabling _must_ be done before we enable the 341 * cpu pipes, hence this is separate from all the other fdi/pch 342 * enabling. 343 */ 344 ilk_fdi_pll_enable(crtc_state); 345 } 346 347 /* 348 * Enable PCH resources required for PCH ports: 349 * - PCH PLLs 350 * - FDI training & RX/TX 351 * - update transcoder timings 352 * - DP transcoding bits 353 * - transcoder 354 */ 355 void ilk_pch_enable(struct intel_atomic_state *state, 356 struct intel_crtc *crtc) 357 { 358 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 359 const struct intel_crtc_state *crtc_state = 360 intel_atomic_get_new_crtc_state(state, crtc); 361 enum pipe pipe = crtc->pipe; 362 u32 temp; 363 364 assert_pch_transcoder_disabled(dev_priv, pipe); 365 366 /* For PCH output, training FDI link */ 367 intel_fdi_link_train(crtc, crtc_state); 368 369 /* 370 * We need to program the right clock selection 371 * before writing the pixel multiplier into the DPLL. 372 */ 373 if (HAS_PCH_CPT(dev_priv)) { 374 u32 sel; 375 376 temp = intel_de_read(dev_priv, PCH_DPLL_SEL); 377 temp |= TRANS_DPLL_ENABLE(pipe); 378 sel = TRANS_DPLLB_SEL(pipe); 379 if (crtc_state->shared_dpll == 380 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) 381 temp |= sel; 382 else 383 temp &= ~sel; 384 intel_de_write(dev_priv, PCH_DPLL_SEL, temp); 385 } 386 387 /* 388 * XXX: pch pll's can be enabled any time before we enable the PCH 389 * transcoder, and we actually should do this to not upset any PCH 390 * transcoder that already use the clock when we share it. 391 * 392 * Note that enable_shared_dpll tries to do the right thing, but 393 * get_shared_dpll unconditionally resets the pll - we need that 394 * to have the right LVDS enable sequence. 395 */ 396 intel_enable_shared_dpll(crtc_state); 397 398 /* set transcoder timing, panel must allow it */ 399 assert_pps_unlocked(dev_priv, pipe); 400 if (intel_crtc_has_dp_encoder(crtc_state)) { 401 intel_pch_transcoder_set_m1_n1(crtc, &crtc_state->dp_m_n); 402 intel_pch_transcoder_set_m2_n2(crtc, &crtc_state->dp_m2_n2); 403 } 404 ilk_pch_transcoder_set_timings(crtc_state, pipe); 405 406 intel_fdi_normal_train(crtc); 407 408 /* For PCH DP, enable TRANS_DP_CTL */ 409 if (HAS_PCH_CPT(dev_priv) && 410 intel_crtc_has_dp_encoder(crtc_state)) { 411 const struct drm_display_mode *adjusted_mode = 412 &crtc_state->hw.adjusted_mode; 413 u32 bpc = (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) >> 5; 414 i915_reg_t reg = TRANS_DP_CTL(pipe); 415 enum port port; 416 417 temp = intel_de_read(dev_priv, reg); 418 temp &= ~(TRANS_DP_PORT_SEL_MASK | 419 TRANS_DP_VSYNC_ACTIVE_HIGH | 420 TRANS_DP_HSYNC_ACTIVE_HIGH | 421 TRANS_DP_BPC_MASK); 422 temp |= TRANS_DP_OUTPUT_ENABLE; 423 temp |= bpc << 9; /* same format but at 11:9 */ 424 425 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 426 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; 427 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 428 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; 429 430 port = intel_get_crtc_new_encoder(state, crtc_state)->port; 431 drm_WARN_ON(&dev_priv->drm, port < PORT_B || port > PORT_D); 432 temp |= TRANS_DP_PORT_SEL(port); 433 434 intel_de_write(dev_priv, reg, temp); 435 } 436 437 ilk_enable_pch_transcoder(crtc_state); 438 } 439 440 void ilk_pch_disable(struct intel_atomic_state *state, 441 struct intel_crtc *crtc) 442 { 443 ilk_fdi_disable(crtc); 444 } 445 446 void ilk_pch_post_disable(struct intel_atomic_state *state, 447 struct intel_crtc *crtc) 448 { 449 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 450 enum pipe pipe = crtc->pipe; 451 452 ilk_disable_pch_transcoder(crtc); 453 454 if (HAS_PCH_CPT(dev_priv)) { 455 /* disable TRANS_DP_CTL */ 456 intel_de_rmw(dev_priv, TRANS_DP_CTL(pipe), 457 TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK, 458 TRANS_DP_PORT_SEL_NONE); 459 460 /* disable DPLL_SEL */ 461 intel_de_rmw(dev_priv, PCH_DPLL_SEL, 462 TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe), 0); 463 } 464 465 ilk_fdi_pll_disable(crtc); 466 } 467 468 static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state) 469 { 470 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 471 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 472 473 /* read out port_clock from the DPLL */ 474 i9xx_crtc_clock_get(crtc, crtc_state); 475 476 /* 477 * In case there is an active pipe without active ports, 478 * we may need some idea for the dotclock anyway. 479 * Calculate one based on the FDI configuration. 480 */ 481 crtc_state->hw.adjusted_mode.crtc_clock = 482 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, crtc_state), 483 &crtc_state->fdi_m_n); 484 } 485 486 void ilk_pch_get_config(struct intel_crtc_state *crtc_state) 487 { 488 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 489 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 490 struct intel_shared_dpll *pll; 491 enum pipe pipe = crtc->pipe; 492 enum intel_dpll_id pll_id; 493 bool pll_active; 494 u32 tmp; 495 496 if ((intel_de_read(dev_priv, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0) 497 return; 498 499 crtc_state->has_pch_encoder = true; 500 501 tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe)); 502 crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> 503 FDI_DP_PORT_WIDTH_SHIFT) + 1; 504 505 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, 506 &crtc_state->fdi_m_n); 507 508 if (HAS_PCH_IBX(dev_priv)) { 509 /* 510 * The pipe->pch transcoder and pch transcoder->pll 511 * mapping is fixed. 512 */ 513 pll_id = (enum intel_dpll_id) pipe; 514 } else { 515 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL); 516 if (tmp & TRANS_DPLLB_SEL(pipe)) 517 pll_id = DPLL_ID_PCH_PLL_B; 518 else 519 pll_id = DPLL_ID_PCH_PLL_A; 520 } 521 522 crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id); 523 pll = crtc_state->shared_dpll; 524 525 pll_active = intel_dpll_get_hw_state(dev_priv, pll, 526 &crtc_state->dpll_hw_state); 527 drm_WARN_ON(&dev_priv->drm, !pll_active); 528 529 tmp = crtc_state->dpll_hw_state.dpll; 530 crtc_state->pixel_multiplier = 531 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) 532 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; 533 534 ilk_pch_clock_get(crtc_state); 535 } 536 537 static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) 538 { 539 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 540 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 541 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 542 u32 val, pipeconf_val; 543 544 /* FDI must be feeding us bits for PCH ports */ 545 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); 546 assert_fdi_rx_enabled(dev_priv, PIPE_A); 547 548 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); 549 /* Workaround: set timing override bit. */ 550 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 551 /* Configure frame start delay to match the CPU */ 552 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 553 val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 554 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); 555 556 val = TRANS_ENABLE; 557 pipeconf_val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); 558 559 if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_HSW) == TRANSCONF_INTERLACE_IF_ID_ILK) 560 val |= TRANS_INTERLACE_INTERLACED; 561 else 562 val |= TRANS_INTERLACE_PROGRESSIVE; 563 564 intel_de_write(dev_priv, LPT_TRANSCONF, val); 565 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF, 566 TRANS_STATE_ENABLE, 100)) 567 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n"); 568 } 569 570 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) 571 { 572 intel_de_rmw(dev_priv, LPT_TRANSCONF, TRANS_ENABLE, 0); 573 /* wait for PCH transcoder off, transcoder state */ 574 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF, 575 TRANS_STATE_ENABLE, 50)) 576 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n"); 577 578 /* Workaround: clear timing override bit. */ 579 intel_de_rmw(dev_priv, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0); 580 } 581 582 void lpt_pch_enable(struct intel_atomic_state *state, 583 struct intel_crtc *crtc) 584 { 585 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 586 const struct intel_crtc_state *crtc_state = 587 intel_atomic_get_new_crtc_state(state, crtc); 588 589 assert_pch_transcoder_disabled(dev_priv, PIPE_A); 590 591 lpt_program_iclkip(crtc_state); 592 593 /* Set transcoder timing. */ 594 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A); 595 596 lpt_enable_pch_transcoder(crtc_state); 597 } 598 599 void lpt_pch_disable(struct intel_atomic_state *state, 600 struct intel_crtc *crtc) 601 { 602 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 603 604 lpt_disable_pch_transcoder(dev_priv); 605 606 lpt_disable_iclkip(dev_priv); 607 } 608 609 void lpt_pch_get_config(struct intel_crtc_state *crtc_state) 610 { 611 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 612 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 613 u32 tmp; 614 615 if ((intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) == 0) 616 return; 617 618 crtc_state->has_pch_encoder = true; 619 620 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 621 crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> 622 FDI_DP_PORT_WIDTH_SHIFT) + 1; 623 624 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, 625 &crtc_state->fdi_m_n); 626 627 crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); 628 } 629 630 void intel_pch_sanitize(struct drm_i915_private *i915) 631 { 632 if (HAS_PCH_IBX(i915)) 633 ibx_sanitize_pch_ports(i915); 634 } 635