1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "g4x_dp.h" 7 #include "intel_crt.h" 8 #include "intel_de.h" 9 #include "intel_display_types.h" 10 #include "intel_fdi.h" 11 #include "intel_lvds.h" 12 #include "intel_pch_display.h" 13 #include "intel_pch_refclk.h" 14 #include "intel_pps.h" 15 #include "intel_sdvo.h" 16 17 bool intel_has_pch_trancoder(struct drm_i915_private *i915, 18 enum pipe pch_transcoder) 19 { 20 return HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915) || 21 (HAS_PCH_LPT_H(i915) && pch_transcoder == PIPE_A); 22 } 23 24 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) 25 { 26 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 27 28 if (HAS_PCH_LPT(i915)) 29 return PIPE_A; 30 else 31 return crtc->pipe; 32 } 33 34 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, 35 enum pipe pipe, enum port port, 36 i915_reg_t dp_reg) 37 { 38 enum pipe port_pipe; 39 bool state; 40 41 state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe); 42 43 I915_STATE_WARN(state && port_pipe == pipe, 44 "PCH DP %c enabled on transcoder %c, should be disabled\n", 45 port_name(port), pipe_name(pipe)); 46 47 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, 48 "IBX PCH DP %c still using transcoder B\n", 49 port_name(port)); 50 } 51 52 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, 53 enum pipe pipe, enum port port, 54 i915_reg_t hdmi_reg) 55 { 56 enum pipe port_pipe; 57 bool state; 58 59 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe); 60 61 I915_STATE_WARN(state && port_pipe == pipe, 62 "PCH HDMI %c enabled on transcoder %c, should be disabled\n", 63 port_name(port), pipe_name(pipe)); 64 65 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, 66 "IBX PCH HDMI %c still using transcoder B\n", 67 port_name(port)); 68 } 69 70 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, 71 enum pipe pipe) 72 { 73 enum pipe port_pipe; 74 75 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B); 76 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C); 77 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D); 78 79 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) && 80 port_pipe == pipe, 81 "PCH VGA enabled on transcoder %c, should be disabled\n", 82 pipe_name(pipe)); 83 84 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) && 85 port_pipe == pipe, 86 "PCH LVDS enabled on transcoder %c, should be disabled\n", 87 pipe_name(pipe)); 88 89 /* PCH SDVOB multiplex with HDMIB */ 90 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB); 91 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC); 92 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID); 93 } 94 95 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 96 enum pipe pipe) 97 { 98 u32 val; 99 bool enabled; 100 101 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe)); 102 enabled = !!(val & TRANS_ENABLE); 103 I915_STATE_WARN(enabled, 104 "transcoder assertion failed, should be off on pipe %c but is still active\n", 105 pipe_name(pipe)); 106 } 107 108 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv, 109 enum port port, i915_reg_t hdmi_reg) 110 { 111 u32 val = intel_de_read(dev_priv, hdmi_reg); 112 113 if (val & SDVO_ENABLE || 114 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A)) 115 return; 116 117 drm_dbg_kms(&dev_priv->drm, 118 "Sanitizing transcoder select for HDMI %c\n", 119 port_name(port)); 120 121 val &= ~SDVO_PIPE_SEL_MASK; 122 val |= SDVO_PIPE_SEL(PIPE_A); 123 124 intel_de_write(dev_priv, hdmi_reg, val); 125 } 126 127 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv, 128 enum port port, i915_reg_t dp_reg) 129 { 130 u32 val = intel_de_read(dev_priv, dp_reg); 131 132 if (val & DP_PORT_EN || 133 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A)) 134 return; 135 136 drm_dbg_kms(&dev_priv->drm, 137 "Sanitizing transcoder select for DP %c\n", 138 port_name(port)); 139 140 val &= ~DP_PIPE_SEL_MASK; 141 val |= DP_PIPE_SEL(PIPE_A); 142 143 intel_de_write(dev_priv, dp_reg, val); 144 } 145 146 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv) 147 { 148 /* 149 * The BIOS may select transcoder B on some of the PCH 150 * ports even it doesn't enable the port. This would trip 151 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled(). 152 * Sanitize the transcoder select bits to prevent that. We 153 * assume that the BIOS never actually enabled the port, 154 * because if it did we'd actually have to toggle the port 155 * on and back off to make the transcoder A select stick 156 * (see. intel_dp_link_down(), intel_disable_hdmi(), 157 * intel_disable_sdvo()). 158 */ 159 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B); 160 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C); 161 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D); 162 163 /* PCH SDVOB multiplex with HDMIB */ 164 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB); 165 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC); 166 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID); 167 } 168 169 static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc, 170 const struct intel_link_m_n *m_n) 171 { 172 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 173 enum pipe pipe = crtc->pipe; 174 175 intel_set_m_n(dev_priv, m_n, 176 PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe), 177 PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); 178 } 179 180 static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc, 181 const struct intel_link_m_n *m_n) 182 { 183 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 184 enum pipe pipe = crtc->pipe; 185 186 intel_set_m_n(dev_priv, m_n, 187 PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe), 188 PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe)); 189 } 190 191 void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc, 192 struct intel_link_m_n *m_n) 193 { 194 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 195 enum pipe pipe = crtc->pipe; 196 197 intel_get_m_n(dev_priv, m_n, 198 PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe), 199 PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); 200 } 201 202 void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc, 203 struct intel_link_m_n *m_n) 204 { 205 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 206 enum pipe pipe = crtc->pipe; 207 208 intel_get_m_n(dev_priv, m_n, 209 PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe), 210 PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe)); 211 } 212 213 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state, 214 enum pipe pch_transcoder) 215 { 216 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 217 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 218 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 219 220 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder), 221 intel_de_read(dev_priv, HTOTAL(cpu_transcoder))); 222 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder), 223 intel_de_read(dev_priv, HBLANK(cpu_transcoder))); 224 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder), 225 intel_de_read(dev_priv, HSYNC(cpu_transcoder))); 226 227 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder), 228 intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); 229 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder), 230 intel_de_read(dev_priv, VBLANK(cpu_transcoder))); 231 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder), 232 intel_de_read(dev_priv, VSYNC(cpu_transcoder))); 233 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder), 234 intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder))); 235 } 236 237 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) 238 { 239 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 240 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 241 enum pipe pipe = crtc->pipe; 242 i915_reg_t reg; 243 u32 val, pipeconf_val; 244 245 /* Make sure PCH DPLL is enabled */ 246 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll); 247 248 /* FDI must be feeding us bits for PCH ports */ 249 assert_fdi_tx_enabled(dev_priv, pipe); 250 assert_fdi_rx_enabled(dev_priv, pipe); 251 252 if (HAS_PCH_CPT(dev_priv)) { 253 reg = TRANS_CHICKEN2(pipe); 254 val = intel_de_read(dev_priv, reg); 255 /* 256 * Workaround: Set the timing override bit 257 * before enabling the pch transcoder. 258 */ 259 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 260 /* Configure frame start delay to match the CPU */ 261 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 262 val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 263 intel_de_write(dev_priv, reg, val); 264 } 265 266 reg = PCH_TRANSCONF(pipe); 267 val = intel_de_read(dev_priv, reg); 268 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe)); 269 270 if (HAS_PCH_IBX(dev_priv)) { 271 /* Configure frame start delay to match the CPU */ 272 val &= ~TRANS_FRAME_START_DELAY_MASK; 273 val |= TRANS_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 274 275 /* 276 * Make the BPC in transcoder be consistent with 277 * that in pipeconf reg. For HDMI we must use 8bpc 278 * here for both 8bpc and 12bpc. 279 */ 280 val &= ~PIPECONF_BPC_MASK; 281 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 282 val |= PIPECONF_BPC_8; 283 else 284 val |= pipeconf_val & PIPECONF_BPC_MASK; 285 } 286 287 val &= ~TRANS_INTERLACE_MASK; 288 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_ILK) == PIPECONF_INTERLACE_IF_ID_ILK) { 289 if (HAS_PCH_IBX(dev_priv) && 290 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 291 val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX; 292 else 293 val |= TRANS_INTERLACE_INTERLACED; 294 } else { 295 val |= TRANS_INTERLACE_PROGRESSIVE; 296 } 297 298 intel_de_write(dev_priv, reg, val | TRANS_ENABLE); 299 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100)) 300 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n", 301 pipe_name(pipe)); 302 } 303 304 static void ilk_disable_pch_transcoder(struct intel_crtc *crtc) 305 { 306 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 307 enum pipe pipe = crtc->pipe; 308 i915_reg_t reg; 309 u32 val; 310 311 /* FDI relies on the transcoder */ 312 assert_fdi_tx_disabled(dev_priv, pipe); 313 assert_fdi_rx_disabled(dev_priv, pipe); 314 315 /* Ports must be off as well */ 316 assert_pch_ports_disabled(dev_priv, pipe); 317 318 reg = PCH_TRANSCONF(pipe); 319 val = intel_de_read(dev_priv, reg); 320 val &= ~TRANS_ENABLE; 321 intel_de_write(dev_priv, reg, val); 322 /* wait for PCH transcoder off, transcoder state */ 323 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50)) 324 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n", 325 pipe_name(pipe)); 326 327 if (HAS_PCH_CPT(dev_priv)) { 328 /* Workaround: Clear the timing override chicken bit again. */ 329 reg = TRANS_CHICKEN2(pipe); 330 val = intel_de_read(dev_priv, reg); 331 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; 332 intel_de_write(dev_priv, reg, val); 333 } 334 } 335 336 void ilk_pch_pre_enable(struct intel_atomic_state *state, 337 struct intel_crtc *crtc) 338 { 339 const struct intel_crtc_state *crtc_state = 340 intel_atomic_get_new_crtc_state(state, crtc); 341 342 /* 343 * Note: FDI PLL enabling _must_ be done before we enable the 344 * cpu pipes, hence this is separate from all the other fdi/pch 345 * enabling. 346 */ 347 ilk_fdi_pll_enable(crtc_state); 348 } 349 350 /* 351 * Enable PCH resources required for PCH ports: 352 * - PCH PLLs 353 * - FDI training & RX/TX 354 * - update transcoder timings 355 * - DP transcoding bits 356 * - transcoder 357 */ 358 void ilk_pch_enable(struct intel_atomic_state *state, 359 struct intel_crtc *crtc) 360 { 361 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 362 const struct intel_crtc_state *crtc_state = 363 intel_atomic_get_new_crtc_state(state, crtc); 364 enum pipe pipe = crtc->pipe; 365 u32 temp; 366 367 assert_pch_transcoder_disabled(dev_priv, pipe); 368 369 /* For PCH output, training FDI link */ 370 intel_fdi_link_train(crtc, crtc_state); 371 372 /* 373 * We need to program the right clock selection 374 * before writing the pixel multiplier into the DPLL. 375 */ 376 if (HAS_PCH_CPT(dev_priv)) { 377 u32 sel; 378 379 temp = intel_de_read(dev_priv, PCH_DPLL_SEL); 380 temp |= TRANS_DPLL_ENABLE(pipe); 381 sel = TRANS_DPLLB_SEL(pipe); 382 if (crtc_state->shared_dpll == 383 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) 384 temp |= sel; 385 else 386 temp &= ~sel; 387 intel_de_write(dev_priv, PCH_DPLL_SEL, temp); 388 } 389 390 /* 391 * XXX: pch pll's can be enabled any time before we enable the PCH 392 * transcoder, and we actually should do this to not upset any PCH 393 * transcoder that already use the clock when we share it. 394 * 395 * Note that enable_shared_dpll tries to do the right thing, but 396 * get_shared_dpll unconditionally resets the pll - we need that 397 * to have the right LVDS enable sequence. 398 */ 399 intel_enable_shared_dpll(crtc_state); 400 401 /* set transcoder timing, panel must allow it */ 402 assert_pps_unlocked(dev_priv, pipe); 403 if (intel_crtc_has_dp_encoder(crtc_state)) { 404 intel_pch_transcoder_set_m1_n1(crtc, &crtc_state->dp_m_n); 405 intel_pch_transcoder_set_m2_n2(crtc, &crtc_state->dp_m2_n2); 406 } 407 ilk_pch_transcoder_set_timings(crtc_state, pipe); 408 409 intel_fdi_normal_train(crtc); 410 411 /* For PCH DP, enable TRANS_DP_CTL */ 412 if (HAS_PCH_CPT(dev_priv) && 413 intel_crtc_has_dp_encoder(crtc_state)) { 414 const struct drm_display_mode *adjusted_mode = 415 &crtc_state->hw.adjusted_mode; 416 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; 417 i915_reg_t reg = TRANS_DP_CTL(pipe); 418 enum port port; 419 420 temp = intel_de_read(dev_priv, reg); 421 temp &= ~(TRANS_DP_PORT_SEL_MASK | 422 TRANS_DP_VSYNC_ACTIVE_HIGH | 423 TRANS_DP_HSYNC_ACTIVE_HIGH | 424 TRANS_DP_BPC_MASK); 425 temp |= TRANS_DP_OUTPUT_ENABLE; 426 temp |= bpc << 9; /* same format but at 11:9 */ 427 428 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 429 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; 430 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 431 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; 432 433 port = intel_get_crtc_new_encoder(state, crtc_state)->port; 434 drm_WARN_ON(&dev_priv->drm, port < PORT_B || port > PORT_D); 435 temp |= TRANS_DP_PORT_SEL(port); 436 437 intel_de_write(dev_priv, reg, temp); 438 } 439 440 ilk_enable_pch_transcoder(crtc_state); 441 } 442 443 void ilk_pch_disable(struct intel_atomic_state *state, 444 struct intel_crtc *crtc) 445 { 446 ilk_fdi_disable(crtc); 447 } 448 449 void ilk_pch_post_disable(struct intel_atomic_state *state, 450 struct intel_crtc *crtc) 451 { 452 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 453 enum pipe pipe = crtc->pipe; 454 455 ilk_disable_pch_transcoder(crtc); 456 457 if (HAS_PCH_CPT(dev_priv)) { 458 i915_reg_t reg; 459 u32 temp; 460 461 /* disable TRANS_DP_CTL */ 462 reg = TRANS_DP_CTL(pipe); 463 temp = intel_de_read(dev_priv, reg); 464 temp &= ~(TRANS_DP_OUTPUT_ENABLE | 465 TRANS_DP_PORT_SEL_MASK); 466 temp |= TRANS_DP_PORT_SEL_NONE; 467 intel_de_write(dev_priv, reg, temp); 468 469 /* disable DPLL_SEL */ 470 temp = intel_de_read(dev_priv, PCH_DPLL_SEL); 471 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); 472 intel_de_write(dev_priv, PCH_DPLL_SEL, temp); 473 } 474 475 ilk_fdi_pll_disable(crtc); 476 } 477 478 static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state) 479 { 480 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 481 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 482 483 /* read out port_clock from the DPLL */ 484 i9xx_crtc_clock_get(crtc, crtc_state); 485 486 /* 487 * In case there is an active pipe without active ports, 488 * we may need some idea for the dotclock anyway. 489 * Calculate one based on the FDI configuration. 490 */ 491 crtc_state->hw.adjusted_mode.crtc_clock = 492 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, crtc_state), 493 &crtc_state->fdi_m_n); 494 } 495 496 void ilk_pch_get_config(struct intel_crtc_state *crtc_state) 497 { 498 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 499 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 500 struct intel_shared_dpll *pll; 501 enum pipe pipe = crtc->pipe; 502 enum intel_dpll_id pll_id; 503 bool pll_active; 504 u32 tmp; 505 506 if ((intel_de_read(dev_priv, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0) 507 return; 508 509 crtc_state->has_pch_encoder = true; 510 511 tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe)); 512 crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> 513 FDI_DP_PORT_WIDTH_SHIFT) + 1; 514 515 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, 516 &crtc_state->fdi_m_n); 517 518 if (HAS_PCH_IBX(dev_priv)) { 519 /* 520 * The pipe->pch transcoder and pch transcoder->pll 521 * mapping is fixed. 522 */ 523 pll_id = (enum intel_dpll_id) pipe; 524 } else { 525 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL); 526 if (tmp & TRANS_DPLLB_SEL(pipe)) 527 pll_id = DPLL_ID_PCH_PLL_B; 528 else 529 pll_id = DPLL_ID_PCH_PLL_A; 530 } 531 532 crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id); 533 pll = crtc_state->shared_dpll; 534 535 pll_active = intel_dpll_get_hw_state(dev_priv, pll, 536 &crtc_state->dpll_hw_state); 537 drm_WARN_ON(&dev_priv->drm, !pll_active); 538 539 tmp = crtc_state->dpll_hw_state.dpll; 540 crtc_state->pixel_multiplier = 541 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) 542 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; 543 544 ilk_pch_clock_get(crtc_state); 545 } 546 547 static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) 548 { 549 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 550 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 551 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 552 u32 val, pipeconf_val; 553 554 /* FDI must be feeding us bits for PCH ports */ 555 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); 556 assert_fdi_rx_enabled(dev_priv, PIPE_A); 557 558 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); 559 /* Workaround: set timing override bit. */ 560 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 561 /* Configure frame start delay to match the CPU */ 562 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 563 val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 564 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); 565 566 val = TRANS_ENABLE; 567 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 568 569 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == PIPECONF_INTERLACE_IF_ID_ILK) 570 val |= TRANS_INTERLACE_INTERLACED; 571 else 572 val |= TRANS_INTERLACE_PROGRESSIVE; 573 574 intel_de_write(dev_priv, LPT_TRANSCONF, val); 575 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF, 576 TRANS_STATE_ENABLE, 100)) 577 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n"); 578 } 579 580 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) 581 { 582 u32 val; 583 584 val = intel_de_read(dev_priv, LPT_TRANSCONF); 585 val &= ~TRANS_ENABLE; 586 intel_de_write(dev_priv, LPT_TRANSCONF, val); 587 /* wait for PCH transcoder off, transcoder state */ 588 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF, 589 TRANS_STATE_ENABLE, 50)) 590 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n"); 591 592 /* Workaround: clear timing override bit. */ 593 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); 594 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; 595 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); 596 } 597 598 void lpt_pch_enable(struct intel_atomic_state *state, 599 struct intel_crtc *crtc) 600 { 601 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 602 const struct intel_crtc_state *crtc_state = 603 intel_atomic_get_new_crtc_state(state, crtc); 604 605 assert_pch_transcoder_disabled(dev_priv, PIPE_A); 606 607 lpt_program_iclkip(crtc_state); 608 609 /* Set transcoder timing. */ 610 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A); 611 612 lpt_enable_pch_transcoder(crtc_state); 613 } 614 615 void lpt_pch_disable(struct intel_atomic_state *state, 616 struct intel_crtc *crtc) 617 { 618 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 619 620 lpt_disable_pch_transcoder(dev_priv); 621 622 lpt_disable_iclkip(dev_priv); 623 } 624 625 void lpt_pch_get_config(struct intel_crtc_state *crtc_state) 626 { 627 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 628 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 629 u32 tmp; 630 631 if ((intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) == 0) 632 return; 633 634 crtc_state->has_pch_encoder = true; 635 636 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 637 crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> 638 FDI_DP_PORT_WIDTH_SHIFT) + 1; 639 640 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, 641 &crtc_state->fdi_m_n); 642 643 crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); 644 } 645 646 void intel_pch_sanitize(struct drm_i915_private *i915) 647 { 648 if (HAS_PCH_IBX(i915)) 649 ibx_sanitize_pch_ports(i915); 650 } 651