1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "g4x_dp.h" 7 #include "intel_crt.h" 8 #include "intel_de.h" 9 #include "intel_display_types.h" 10 #include "intel_fdi.h" 11 #include "intel_lvds.h" 12 #include "intel_pch_display.h" 13 #include "intel_pch_refclk.h" 14 #include "intel_pps.h" 15 #include "intel_sdvo.h" 16 17 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, 18 enum pipe pipe, enum port port, 19 i915_reg_t dp_reg) 20 { 21 enum pipe port_pipe; 22 bool state; 23 24 state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe); 25 26 I915_STATE_WARN(state && port_pipe == pipe, 27 "PCH DP %c enabled on transcoder %c, should be disabled\n", 28 port_name(port), pipe_name(pipe)); 29 30 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, 31 "IBX PCH DP %c still using transcoder B\n", 32 port_name(port)); 33 } 34 35 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, 36 enum pipe pipe, enum port port, 37 i915_reg_t hdmi_reg) 38 { 39 enum pipe port_pipe; 40 bool state; 41 42 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe); 43 44 I915_STATE_WARN(state && port_pipe == pipe, 45 "PCH HDMI %c enabled on transcoder %c, should be disabled\n", 46 port_name(port), pipe_name(pipe)); 47 48 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, 49 "IBX PCH HDMI %c still using transcoder B\n", 50 port_name(port)); 51 } 52 53 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, 54 enum pipe pipe) 55 { 56 enum pipe port_pipe; 57 58 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B); 59 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C); 60 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D); 61 62 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) && 63 port_pipe == pipe, 64 "PCH VGA enabled on transcoder %c, should be disabled\n", 65 pipe_name(pipe)); 66 67 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) && 68 port_pipe == pipe, 69 "PCH LVDS enabled on transcoder %c, should be disabled\n", 70 pipe_name(pipe)); 71 72 /* PCH SDVOB multiplex with HDMIB */ 73 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB); 74 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC); 75 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID); 76 } 77 78 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 79 enum pipe pipe) 80 { 81 u32 val; 82 bool enabled; 83 84 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe)); 85 enabled = !!(val & TRANS_ENABLE); 86 I915_STATE_WARN(enabled, 87 "transcoder assertion failed, should be off on pipe %c but is still active\n", 88 pipe_name(pipe)); 89 } 90 91 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state, 92 enum pipe pch_transcoder) 93 { 94 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 95 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 96 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 97 98 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder), 99 intel_de_read(dev_priv, HTOTAL(cpu_transcoder))); 100 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder), 101 intel_de_read(dev_priv, HBLANK(cpu_transcoder))); 102 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder), 103 intel_de_read(dev_priv, HSYNC(cpu_transcoder))); 104 105 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder), 106 intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); 107 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder), 108 intel_de_read(dev_priv, VBLANK(cpu_transcoder))); 109 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder), 110 intel_de_read(dev_priv, VSYNC(cpu_transcoder))); 111 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder), 112 intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder))); 113 } 114 115 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) 116 { 117 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 118 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 119 enum pipe pipe = crtc->pipe; 120 i915_reg_t reg; 121 u32 val, pipeconf_val; 122 123 /* Make sure PCH DPLL is enabled */ 124 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll); 125 126 /* FDI must be feeding us bits for PCH ports */ 127 assert_fdi_tx_enabled(dev_priv, pipe); 128 assert_fdi_rx_enabled(dev_priv, pipe); 129 130 if (HAS_PCH_CPT(dev_priv)) { 131 reg = TRANS_CHICKEN2(pipe); 132 val = intel_de_read(dev_priv, reg); 133 /* 134 * Workaround: Set the timing override bit 135 * before enabling the pch transcoder. 136 */ 137 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 138 /* Configure frame start delay to match the CPU */ 139 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 140 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1); 141 intel_de_write(dev_priv, reg, val); 142 } 143 144 reg = PCH_TRANSCONF(pipe); 145 val = intel_de_read(dev_priv, reg); 146 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe)); 147 148 if (HAS_PCH_IBX(dev_priv)) { 149 /* Configure frame start delay to match the CPU */ 150 val &= ~TRANS_FRAME_START_DELAY_MASK; 151 val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1); 152 153 /* 154 * Make the BPC in transcoder be consistent with 155 * that in pipeconf reg. For HDMI we must use 8bpc 156 * here for both 8bpc and 12bpc. 157 */ 158 val &= ~PIPECONF_BPC_MASK; 159 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 160 val |= PIPECONF_8BPC; 161 else 162 val |= pipeconf_val & PIPECONF_BPC_MASK; 163 } 164 165 val &= ~TRANS_INTERLACE_MASK; 166 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) { 167 if (HAS_PCH_IBX(dev_priv) && 168 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 169 val |= TRANS_LEGACY_INTERLACED_ILK; 170 else 171 val |= TRANS_INTERLACED; 172 } else { 173 val |= TRANS_PROGRESSIVE; 174 } 175 176 intel_de_write(dev_priv, reg, val | TRANS_ENABLE); 177 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100)) 178 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n", 179 pipe_name(pipe)); 180 } 181 182 static void ilk_disable_pch_transcoder(struct intel_crtc *crtc) 183 { 184 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 185 enum pipe pipe = crtc->pipe; 186 i915_reg_t reg; 187 u32 val; 188 189 /* FDI relies on the transcoder */ 190 assert_fdi_tx_disabled(dev_priv, pipe); 191 assert_fdi_rx_disabled(dev_priv, pipe); 192 193 /* Ports must be off as well */ 194 assert_pch_ports_disabled(dev_priv, pipe); 195 196 reg = PCH_TRANSCONF(pipe); 197 val = intel_de_read(dev_priv, reg); 198 val &= ~TRANS_ENABLE; 199 intel_de_write(dev_priv, reg, val); 200 /* wait for PCH transcoder off, transcoder state */ 201 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50)) 202 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n", 203 pipe_name(pipe)); 204 205 if (HAS_PCH_CPT(dev_priv)) { 206 /* Workaround: Clear the timing override chicken bit again. */ 207 reg = TRANS_CHICKEN2(pipe); 208 val = intel_de_read(dev_priv, reg); 209 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; 210 intel_de_write(dev_priv, reg, val); 211 } 212 } 213 214 /* 215 * Enable PCH resources required for PCH ports: 216 * - PCH PLLs 217 * - FDI training & RX/TX 218 * - update transcoder timings 219 * - DP transcoding bits 220 * - transcoder 221 */ 222 void ilk_pch_enable(struct intel_atomic_state *state, 223 struct intel_crtc *crtc) 224 { 225 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 226 const struct intel_crtc_state *crtc_state = 227 intel_atomic_get_new_crtc_state(state, crtc); 228 enum pipe pipe = crtc->pipe; 229 u32 temp; 230 231 assert_pch_transcoder_disabled(dev_priv, pipe); 232 233 /* For PCH output, training FDI link */ 234 intel_fdi_link_train(crtc, crtc_state); 235 236 /* 237 * We need to program the right clock selection 238 * before writing the pixel multiplier into the DPLL. 239 */ 240 if (HAS_PCH_CPT(dev_priv)) { 241 u32 sel; 242 243 temp = intel_de_read(dev_priv, PCH_DPLL_SEL); 244 temp |= TRANS_DPLL_ENABLE(pipe); 245 sel = TRANS_DPLLB_SEL(pipe); 246 if (crtc_state->shared_dpll == 247 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) 248 temp |= sel; 249 else 250 temp &= ~sel; 251 intel_de_write(dev_priv, PCH_DPLL_SEL, temp); 252 } 253 254 /* 255 * XXX: pch pll's can be enabled any time before we enable the PCH 256 * transcoder, and we actually should do this to not upset any PCH 257 * transcoder that already use the clock when we share it. 258 * 259 * Note that enable_shared_dpll tries to do the right thing, but 260 * get_shared_dpll unconditionally resets the pll - we need that 261 * to have the right LVDS enable sequence. 262 */ 263 intel_enable_shared_dpll(crtc_state); 264 265 /* set transcoder timing, panel must allow it */ 266 assert_pps_unlocked(dev_priv, pipe); 267 ilk_pch_transcoder_set_timings(crtc_state, pipe); 268 269 intel_fdi_normal_train(crtc); 270 271 /* For PCH DP, enable TRANS_DP_CTL */ 272 if (HAS_PCH_CPT(dev_priv) && 273 intel_crtc_has_dp_encoder(crtc_state)) { 274 const struct drm_display_mode *adjusted_mode = 275 &crtc_state->hw.adjusted_mode; 276 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; 277 i915_reg_t reg = TRANS_DP_CTL(pipe); 278 enum port port; 279 280 temp = intel_de_read(dev_priv, reg); 281 temp &= ~(TRANS_DP_PORT_SEL_MASK | 282 TRANS_DP_SYNC_MASK | 283 TRANS_DP_BPC_MASK); 284 temp |= TRANS_DP_OUTPUT_ENABLE; 285 temp |= bpc << 9; /* same format but at 11:9 */ 286 287 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 288 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; 289 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 290 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; 291 292 port = intel_get_crtc_new_encoder(state, crtc_state)->port; 293 drm_WARN_ON(&dev_priv->drm, port < PORT_B || port > PORT_D); 294 temp |= TRANS_DP_PORT_SEL(port); 295 296 intel_de_write(dev_priv, reg, temp); 297 } 298 299 ilk_enable_pch_transcoder(crtc_state); 300 } 301 302 void ilk_pch_disable(struct intel_atomic_state *state, 303 struct intel_crtc *crtc) 304 { 305 ilk_fdi_disable(crtc); 306 } 307 308 void ilk_pch_post_disable(struct intel_atomic_state *state, 309 struct intel_crtc *crtc) 310 { 311 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 312 enum pipe pipe = crtc->pipe; 313 314 ilk_disable_pch_transcoder(crtc); 315 316 if (HAS_PCH_CPT(dev_priv)) { 317 i915_reg_t reg; 318 u32 temp; 319 320 /* disable TRANS_DP_CTL */ 321 reg = TRANS_DP_CTL(pipe); 322 temp = intel_de_read(dev_priv, reg); 323 temp &= ~(TRANS_DP_OUTPUT_ENABLE | 324 TRANS_DP_PORT_SEL_MASK); 325 temp |= TRANS_DP_PORT_SEL_NONE; 326 intel_de_write(dev_priv, reg, temp); 327 328 /* disable DPLL_SEL */ 329 temp = intel_de_read(dev_priv, PCH_DPLL_SEL); 330 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); 331 intel_de_write(dev_priv, PCH_DPLL_SEL, temp); 332 } 333 334 ilk_fdi_pll_disable(crtc); 335 } 336 337 static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state) 338 { 339 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 340 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 341 342 /* read out port_clock from the DPLL */ 343 i9xx_crtc_clock_get(crtc, crtc_state); 344 345 /* 346 * In case there is an active pipe without active ports, 347 * we may need some idea for the dotclock anyway. 348 * Calculate one based on the FDI configuration. 349 */ 350 crtc_state->hw.adjusted_mode.crtc_clock = 351 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, crtc_state), 352 &crtc_state->fdi_m_n); 353 } 354 355 void ilk_pch_get_config(struct intel_crtc_state *crtc_state) 356 { 357 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 358 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 359 struct intel_shared_dpll *pll; 360 enum pipe pipe = crtc->pipe; 361 enum intel_dpll_id pll_id; 362 bool pll_active; 363 u32 tmp; 364 365 if ((intel_de_read(dev_priv, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0) 366 return; 367 368 crtc_state->has_pch_encoder = true; 369 370 tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe)); 371 crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> 372 FDI_DP_PORT_WIDTH_SHIFT) + 1; 373 374 ilk_get_fdi_m_n_config(crtc, crtc_state); 375 376 if (HAS_PCH_IBX(dev_priv)) { 377 /* 378 * The pipe->pch transcoder and pch transcoder->pll 379 * mapping is fixed. 380 */ 381 pll_id = (enum intel_dpll_id) pipe; 382 } else { 383 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL); 384 if (tmp & TRANS_DPLLB_SEL(pipe)) 385 pll_id = DPLL_ID_PCH_PLL_B; 386 else 387 pll_id = DPLL_ID_PCH_PLL_A; 388 } 389 390 crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id); 391 pll = crtc_state->shared_dpll; 392 393 pll_active = intel_dpll_get_hw_state(dev_priv, pll, 394 &crtc_state->dpll_hw_state); 395 drm_WARN_ON(&dev_priv->drm, !pll_active); 396 397 tmp = crtc_state->dpll_hw_state.dpll; 398 crtc_state->pixel_multiplier = 399 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) 400 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; 401 402 ilk_pch_clock_get(crtc_state); 403 } 404 405 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, 406 enum transcoder cpu_transcoder) 407 { 408 u32 val, pipeconf_val; 409 410 /* FDI must be feeding us bits for PCH ports */ 411 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); 412 assert_fdi_rx_enabled(dev_priv, PIPE_A); 413 414 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); 415 /* Workaround: set timing override bit. */ 416 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 417 /* Configure frame start delay to match the CPU */ 418 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 419 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1); 420 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); 421 422 val = TRANS_ENABLE; 423 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 424 425 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == 426 PIPECONF_INTERLACED_ILK) 427 val |= TRANS_INTERLACED; 428 else 429 val |= TRANS_PROGRESSIVE; 430 431 intel_de_write(dev_priv, LPT_TRANSCONF, val); 432 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF, 433 TRANS_STATE_ENABLE, 100)) 434 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n"); 435 } 436 437 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) 438 { 439 u32 val; 440 441 val = intel_de_read(dev_priv, LPT_TRANSCONF); 442 val &= ~TRANS_ENABLE; 443 intel_de_write(dev_priv, LPT_TRANSCONF, val); 444 /* wait for PCH transcoder off, transcoder state */ 445 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF, 446 TRANS_STATE_ENABLE, 50)) 447 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n"); 448 449 /* Workaround: clear timing override bit. */ 450 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); 451 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; 452 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); 453 } 454 455 void lpt_pch_enable(struct intel_atomic_state *state, 456 struct intel_crtc *crtc) 457 { 458 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 459 const struct intel_crtc_state *crtc_state = 460 intel_atomic_get_new_crtc_state(state, crtc); 461 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 462 463 assert_pch_transcoder_disabled(dev_priv, PIPE_A); 464 465 lpt_program_iclkip(crtc_state); 466 467 /* Set transcoder timing. */ 468 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A); 469 470 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); 471 } 472 473 void lpt_pch_disable(struct intel_atomic_state *state, 474 struct intel_crtc *crtc) 475 { 476 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 477 478 lpt_disable_pch_transcoder(dev_priv); 479 480 lpt_disable_iclkip(dev_priv); 481 } 482 483 void lpt_pch_get_config(struct intel_crtc_state *crtc_state) 484 { 485 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 486 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 487 u32 tmp; 488 489 if ((intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) == 0) 490 return; 491 492 crtc_state->has_pch_encoder = true; 493 494 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 495 crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> 496 FDI_DP_PORT_WIDTH_SHIFT) + 1; 497 498 ilk_get_fdi_m_n_config(crtc, crtc_state); 499 500 crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); 501 } 502