1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "g4x_dp.h" 7 #include "intel_crt.h" 8 #include "intel_de.h" 9 #include "intel_display_types.h" 10 #include "intel_fdi.h" 11 #include "intel_lvds.h" 12 #include "intel_pch_display.h" 13 #include "intel_pch_refclk.h" 14 #include "intel_pps.h" 15 #include "intel_sdvo.h" 16 17 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, 18 enum pipe pipe, enum port port, 19 i915_reg_t dp_reg) 20 { 21 enum pipe port_pipe; 22 bool state; 23 24 state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe); 25 26 I915_STATE_WARN(state && port_pipe == pipe, 27 "PCH DP %c enabled on transcoder %c, should be disabled\n", 28 port_name(port), pipe_name(pipe)); 29 30 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, 31 "IBX PCH DP %c still using transcoder B\n", 32 port_name(port)); 33 } 34 35 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, 36 enum pipe pipe, enum port port, 37 i915_reg_t hdmi_reg) 38 { 39 enum pipe port_pipe; 40 bool state; 41 42 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe); 43 44 I915_STATE_WARN(state && port_pipe == pipe, 45 "PCH HDMI %c enabled on transcoder %c, should be disabled\n", 46 port_name(port), pipe_name(pipe)); 47 48 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, 49 "IBX PCH HDMI %c still using transcoder B\n", 50 port_name(port)); 51 } 52 53 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, 54 enum pipe pipe) 55 { 56 enum pipe port_pipe; 57 58 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B); 59 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C); 60 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D); 61 62 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) && 63 port_pipe == pipe, 64 "PCH VGA enabled on transcoder %c, should be disabled\n", 65 pipe_name(pipe)); 66 67 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) && 68 port_pipe == pipe, 69 "PCH LVDS enabled on transcoder %c, should be disabled\n", 70 pipe_name(pipe)); 71 72 /* PCH SDVOB multiplex with HDMIB */ 73 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB); 74 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC); 75 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID); 76 } 77 78 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 79 enum pipe pipe) 80 { 81 u32 val; 82 bool enabled; 83 84 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe)); 85 enabled = !!(val & TRANS_ENABLE); 86 I915_STATE_WARN(enabled, 87 "transcoder assertion failed, should be off on pipe %c but is still active\n", 88 pipe_name(pipe)); 89 } 90 91 static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc, 92 const struct intel_link_m_n *m_n) 93 { 94 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 95 enum pipe pipe = crtc->pipe; 96 97 intel_set_m_n(dev_priv, m_n, 98 PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe), 99 PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); 100 } 101 102 static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc, 103 const struct intel_link_m_n *m_n) 104 { 105 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 106 enum pipe pipe = crtc->pipe; 107 108 intel_set_m_n(dev_priv, m_n, 109 PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe), 110 PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe)); 111 } 112 113 void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc, 114 struct intel_link_m_n *m_n) 115 { 116 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 117 enum pipe pipe = crtc->pipe; 118 119 intel_get_m_n(dev_priv, m_n, 120 PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe), 121 PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); 122 } 123 124 void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc, 125 struct intel_link_m_n *m_n) 126 { 127 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 128 enum pipe pipe = crtc->pipe; 129 130 intel_get_m_n(dev_priv, m_n, 131 PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe), 132 PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe)); 133 } 134 135 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state, 136 enum pipe pch_transcoder) 137 { 138 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 139 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 140 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 141 142 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder), 143 intel_de_read(dev_priv, HTOTAL(cpu_transcoder))); 144 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder), 145 intel_de_read(dev_priv, HBLANK(cpu_transcoder))); 146 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder), 147 intel_de_read(dev_priv, HSYNC(cpu_transcoder))); 148 149 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder), 150 intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); 151 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder), 152 intel_de_read(dev_priv, VBLANK(cpu_transcoder))); 153 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder), 154 intel_de_read(dev_priv, VSYNC(cpu_transcoder))); 155 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder), 156 intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder))); 157 } 158 159 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) 160 { 161 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 162 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 163 enum pipe pipe = crtc->pipe; 164 i915_reg_t reg; 165 u32 val, pipeconf_val; 166 167 /* Make sure PCH DPLL is enabled */ 168 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll); 169 170 /* FDI must be feeding us bits for PCH ports */ 171 assert_fdi_tx_enabled(dev_priv, pipe); 172 assert_fdi_rx_enabled(dev_priv, pipe); 173 174 if (HAS_PCH_CPT(dev_priv)) { 175 reg = TRANS_CHICKEN2(pipe); 176 val = intel_de_read(dev_priv, reg); 177 /* 178 * Workaround: Set the timing override bit 179 * before enabling the pch transcoder. 180 */ 181 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 182 /* Configure frame start delay to match the CPU */ 183 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 184 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1); 185 intel_de_write(dev_priv, reg, val); 186 } 187 188 reg = PCH_TRANSCONF(pipe); 189 val = intel_de_read(dev_priv, reg); 190 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe)); 191 192 if (HAS_PCH_IBX(dev_priv)) { 193 /* Configure frame start delay to match the CPU */ 194 val &= ~TRANS_FRAME_START_DELAY_MASK; 195 val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1); 196 197 /* 198 * Make the BPC in transcoder be consistent with 199 * that in pipeconf reg. For HDMI we must use 8bpc 200 * here for both 8bpc and 12bpc. 201 */ 202 val &= ~PIPECONF_BPC_MASK; 203 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 204 val |= PIPECONF_BPC_8; 205 else 206 val |= pipeconf_val & PIPECONF_BPC_MASK; 207 } 208 209 val &= ~TRANS_INTERLACE_MASK; 210 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_ILK) == PIPECONF_INTERLACE_IF_ID_ILK) { 211 if (HAS_PCH_IBX(dev_priv) && 212 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 213 val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX; 214 else 215 val |= TRANS_INTERLACE_INTERLACED; 216 } else { 217 val |= TRANS_INTERLACE_PROGRESSIVE; 218 } 219 220 intel_de_write(dev_priv, reg, val | TRANS_ENABLE); 221 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100)) 222 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n", 223 pipe_name(pipe)); 224 } 225 226 static void ilk_disable_pch_transcoder(struct intel_crtc *crtc) 227 { 228 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 229 enum pipe pipe = crtc->pipe; 230 i915_reg_t reg; 231 u32 val; 232 233 /* FDI relies on the transcoder */ 234 assert_fdi_tx_disabled(dev_priv, pipe); 235 assert_fdi_rx_disabled(dev_priv, pipe); 236 237 /* Ports must be off as well */ 238 assert_pch_ports_disabled(dev_priv, pipe); 239 240 reg = PCH_TRANSCONF(pipe); 241 val = intel_de_read(dev_priv, reg); 242 val &= ~TRANS_ENABLE; 243 intel_de_write(dev_priv, reg, val); 244 /* wait for PCH transcoder off, transcoder state */ 245 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50)) 246 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n", 247 pipe_name(pipe)); 248 249 if (HAS_PCH_CPT(dev_priv)) { 250 /* Workaround: Clear the timing override chicken bit again. */ 251 reg = TRANS_CHICKEN2(pipe); 252 val = intel_de_read(dev_priv, reg); 253 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; 254 intel_de_write(dev_priv, reg, val); 255 } 256 } 257 258 void ilk_pch_pre_enable(struct intel_atomic_state *state, 259 struct intel_crtc *crtc) 260 { 261 const struct intel_crtc_state *crtc_state = 262 intel_atomic_get_new_crtc_state(state, crtc); 263 264 /* 265 * Note: FDI PLL enabling _must_ be done before we enable the 266 * cpu pipes, hence this is separate from all the other fdi/pch 267 * enabling. 268 */ 269 ilk_fdi_pll_enable(crtc_state); 270 } 271 272 /* 273 * Enable PCH resources required for PCH ports: 274 * - PCH PLLs 275 * - FDI training & RX/TX 276 * - update transcoder timings 277 * - DP transcoding bits 278 * - transcoder 279 */ 280 void ilk_pch_enable(struct intel_atomic_state *state, 281 struct intel_crtc *crtc) 282 { 283 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 284 const struct intel_crtc_state *crtc_state = 285 intel_atomic_get_new_crtc_state(state, crtc); 286 enum pipe pipe = crtc->pipe; 287 u32 temp; 288 289 assert_pch_transcoder_disabled(dev_priv, pipe); 290 291 /* For PCH output, training FDI link */ 292 intel_fdi_link_train(crtc, crtc_state); 293 294 /* 295 * We need to program the right clock selection 296 * before writing the pixel multiplier into the DPLL. 297 */ 298 if (HAS_PCH_CPT(dev_priv)) { 299 u32 sel; 300 301 temp = intel_de_read(dev_priv, PCH_DPLL_SEL); 302 temp |= TRANS_DPLL_ENABLE(pipe); 303 sel = TRANS_DPLLB_SEL(pipe); 304 if (crtc_state->shared_dpll == 305 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) 306 temp |= sel; 307 else 308 temp &= ~sel; 309 intel_de_write(dev_priv, PCH_DPLL_SEL, temp); 310 } 311 312 /* 313 * XXX: pch pll's can be enabled any time before we enable the PCH 314 * transcoder, and we actually should do this to not upset any PCH 315 * transcoder that already use the clock when we share it. 316 * 317 * Note that enable_shared_dpll tries to do the right thing, but 318 * get_shared_dpll unconditionally resets the pll - we need that 319 * to have the right LVDS enable sequence. 320 */ 321 intel_enable_shared_dpll(crtc_state); 322 323 /* set transcoder timing, panel must allow it */ 324 assert_pps_unlocked(dev_priv, pipe); 325 if (intel_crtc_has_dp_encoder(crtc_state)) { 326 intel_pch_transcoder_set_m1_n1(crtc, &crtc_state->dp_m_n); 327 intel_pch_transcoder_set_m2_n2(crtc, &crtc_state->dp_m2_n2); 328 } 329 ilk_pch_transcoder_set_timings(crtc_state, pipe); 330 331 intel_fdi_normal_train(crtc); 332 333 /* For PCH DP, enable TRANS_DP_CTL */ 334 if (HAS_PCH_CPT(dev_priv) && 335 intel_crtc_has_dp_encoder(crtc_state)) { 336 const struct drm_display_mode *adjusted_mode = 337 &crtc_state->hw.adjusted_mode; 338 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; 339 i915_reg_t reg = TRANS_DP_CTL(pipe); 340 enum port port; 341 342 temp = intel_de_read(dev_priv, reg); 343 temp &= ~(TRANS_DP_PORT_SEL_MASK | 344 TRANS_DP_VSYNC_ACTIVE_HIGH | 345 TRANS_DP_HSYNC_ACTIVE_HIGH | 346 TRANS_DP_BPC_MASK); 347 temp |= TRANS_DP_OUTPUT_ENABLE; 348 temp |= bpc << 9; /* same format but at 11:9 */ 349 350 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 351 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; 352 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 353 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; 354 355 port = intel_get_crtc_new_encoder(state, crtc_state)->port; 356 drm_WARN_ON(&dev_priv->drm, port < PORT_B || port > PORT_D); 357 temp |= TRANS_DP_PORT_SEL(port); 358 359 intel_de_write(dev_priv, reg, temp); 360 } 361 362 ilk_enable_pch_transcoder(crtc_state); 363 } 364 365 void ilk_pch_disable(struct intel_atomic_state *state, 366 struct intel_crtc *crtc) 367 { 368 ilk_fdi_disable(crtc); 369 } 370 371 void ilk_pch_post_disable(struct intel_atomic_state *state, 372 struct intel_crtc *crtc) 373 { 374 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 375 enum pipe pipe = crtc->pipe; 376 377 ilk_disable_pch_transcoder(crtc); 378 379 if (HAS_PCH_CPT(dev_priv)) { 380 i915_reg_t reg; 381 u32 temp; 382 383 /* disable TRANS_DP_CTL */ 384 reg = TRANS_DP_CTL(pipe); 385 temp = intel_de_read(dev_priv, reg); 386 temp &= ~(TRANS_DP_OUTPUT_ENABLE | 387 TRANS_DP_PORT_SEL_MASK); 388 temp |= TRANS_DP_PORT_SEL_NONE; 389 intel_de_write(dev_priv, reg, temp); 390 391 /* disable DPLL_SEL */ 392 temp = intel_de_read(dev_priv, PCH_DPLL_SEL); 393 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); 394 intel_de_write(dev_priv, PCH_DPLL_SEL, temp); 395 } 396 397 ilk_fdi_pll_disable(crtc); 398 } 399 400 static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state) 401 { 402 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 403 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 404 405 /* read out port_clock from the DPLL */ 406 i9xx_crtc_clock_get(crtc, crtc_state); 407 408 /* 409 * In case there is an active pipe without active ports, 410 * we may need some idea for the dotclock anyway. 411 * Calculate one based on the FDI configuration. 412 */ 413 crtc_state->hw.adjusted_mode.crtc_clock = 414 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, crtc_state), 415 &crtc_state->fdi_m_n); 416 } 417 418 void ilk_pch_get_config(struct intel_crtc_state *crtc_state) 419 { 420 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 421 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 422 struct intel_shared_dpll *pll; 423 enum pipe pipe = crtc->pipe; 424 enum intel_dpll_id pll_id; 425 bool pll_active; 426 u32 tmp; 427 428 if ((intel_de_read(dev_priv, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0) 429 return; 430 431 crtc_state->has_pch_encoder = true; 432 433 tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe)); 434 crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> 435 FDI_DP_PORT_WIDTH_SHIFT) + 1; 436 437 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, 438 &crtc_state->fdi_m_n); 439 440 if (HAS_PCH_IBX(dev_priv)) { 441 /* 442 * The pipe->pch transcoder and pch transcoder->pll 443 * mapping is fixed. 444 */ 445 pll_id = (enum intel_dpll_id) pipe; 446 } else { 447 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL); 448 if (tmp & TRANS_DPLLB_SEL(pipe)) 449 pll_id = DPLL_ID_PCH_PLL_B; 450 else 451 pll_id = DPLL_ID_PCH_PLL_A; 452 } 453 454 crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id); 455 pll = crtc_state->shared_dpll; 456 457 pll_active = intel_dpll_get_hw_state(dev_priv, pll, 458 &crtc_state->dpll_hw_state); 459 drm_WARN_ON(&dev_priv->drm, !pll_active); 460 461 tmp = crtc_state->dpll_hw_state.dpll; 462 crtc_state->pixel_multiplier = 463 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) 464 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; 465 466 ilk_pch_clock_get(crtc_state); 467 } 468 469 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, 470 enum transcoder cpu_transcoder) 471 { 472 u32 val, pipeconf_val; 473 474 /* FDI must be feeding us bits for PCH ports */ 475 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); 476 assert_fdi_rx_enabled(dev_priv, PIPE_A); 477 478 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); 479 /* Workaround: set timing override bit. */ 480 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 481 /* Configure frame start delay to match the CPU */ 482 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 483 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1); 484 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); 485 486 val = TRANS_ENABLE; 487 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 488 489 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == PIPECONF_INTERLACE_IF_ID_ILK) 490 val |= TRANS_INTERLACE_INTERLACED; 491 else 492 val |= TRANS_INTERLACE_PROGRESSIVE; 493 494 intel_de_write(dev_priv, LPT_TRANSCONF, val); 495 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF, 496 TRANS_STATE_ENABLE, 100)) 497 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n"); 498 } 499 500 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) 501 { 502 u32 val; 503 504 val = intel_de_read(dev_priv, LPT_TRANSCONF); 505 val &= ~TRANS_ENABLE; 506 intel_de_write(dev_priv, LPT_TRANSCONF, val); 507 /* wait for PCH transcoder off, transcoder state */ 508 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF, 509 TRANS_STATE_ENABLE, 50)) 510 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n"); 511 512 /* Workaround: clear timing override bit. */ 513 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); 514 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; 515 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); 516 } 517 518 void lpt_pch_enable(struct intel_atomic_state *state, 519 struct intel_crtc *crtc) 520 { 521 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 522 const struct intel_crtc_state *crtc_state = 523 intel_atomic_get_new_crtc_state(state, crtc); 524 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 525 526 assert_pch_transcoder_disabled(dev_priv, PIPE_A); 527 528 lpt_program_iclkip(crtc_state); 529 530 /* Set transcoder timing. */ 531 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A); 532 533 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); 534 } 535 536 void lpt_pch_disable(struct intel_atomic_state *state, 537 struct intel_crtc *crtc) 538 { 539 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 540 541 lpt_disable_pch_transcoder(dev_priv); 542 543 lpt_disable_iclkip(dev_priv); 544 } 545 546 void lpt_pch_get_config(struct intel_crtc_state *crtc_state) 547 { 548 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 550 u32 tmp; 551 552 if ((intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) == 0) 553 return; 554 555 crtc_state->has_pch_encoder = true; 556 557 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 558 crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> 559 FDI_DP_PORT_WIDTH_SHIFT) + 1; 560 561 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, 562 &crtc_state->fdi_m_n); 563 564 crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); 565 } 566