1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2021 Intel Corporation
4  */
5 
6 #include "g4x_dp.h"
7 #include "i915_reg.h"
8 #include "intel_crt.h"
9 #include "intel_de.h"
10 #include "intel_display_types.h"
11 #include "intel_fdi.h"
12 #include "intel_fdi_regs.h"
13 #include "intel_lvds.h"
14 #include "intel_lvds_regs.h"
15 #include "intel_pch_display.h"
16 #include "intel_pch_refclk.h"
17 #include "intel_pps.h"
18 #include "intel_sdvo.h"
19 
20 bool intel_has_pch_trancoder(struct drm_i915_private *i915,
21 			     enum pipe pch_transcoder)
22 {
23 	return HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915) ||
24 		(HAS_PCH_LPT_H(i915) && pch_transcoder == PIPE_A);
25 }
26 
27 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
28 {
29 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
30 
31 	if (HAS_PCH_LPT(i915))
32 		return PIPE_A;
33 	else
34 		return crtc->pipe;
35 }
36 
37 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
38 				   enum pipe pipe, enum port port,
39 				   i915_reg_t dp_reg)
40 {
41 	enum pipe port_pipe;
42 	bool state;
43 
44 	state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
45 
46 	I915_STATE_WARN(dev_priv, state && port_pipe == pipe,
47 			"PCH DP %c enabled on transcoder %c, should be disabled\n",
48 			port_name(port), pipe_name(pipe));
49 
50 	I915_STATE_WARN(dev_priv,
51 			HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
52 			"IBX PCH DP %c still using transcoder B\n",
53 			port_name(port));
54 }
55 
56 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
57 				     enum pipe pipe, enum port port,
58 				     i915_reg_t hdmi_reg)
59 {
60 	enum pipe port_pipe;
61 	bool state;
62 
63 	state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
64 
65 	I915_STATE_WARN(dev_priv, state && port_pipe == pipe,
66 			"PCH HDMI %c enabled on transcoder %c, should be disabled\n",
67 			port_name(port), pipe_name(pipe));
68 
69 	I915_STATE_WARN(dev_priv,
70 			HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
71 			"IBX PCH HDMI %c still using transcoder B\n",
72 			port_name(port));
73 }
74 
75 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
76 				      enum pipe pipe)
77 {
78 	enum pipe port_pipe;
79 
80 	assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
81 	assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
82 	assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
83 
84 	I915_STATE_WARN(dev_priv,
85 			intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) && port_pipe == pipe,
86 			"PCH VGA enabled on transcoder %c, should be disabled\n",
87 			pipe_name(pipe));
88 
89 	I915_STATE_WARN(dev_priv,
90 			intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) && port_pipe == pipe,
91 			"PCH LVDS enabled on transcoder %c, should be disabled\n",
92 			pipe_name(pipe));
93 
94 	/* PCH SDVOB multiplex with HDMIB */
95 	assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
96 	assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
97 	assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
98 }
99 
100 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
101 					   enum pipe pipe)
102 {
103 	u32 val;
104 	bool enabled;
105 
106 	val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
107 	enabled = !!(val & TRANS_ENABLE);
108 	I915_STATE_WARN(dev_priv, enabled,
109 			"transcoder assertion failed, should be off on pipe %c but is still active\n",
110 			pipe_name(pipe));
111 }
112 
113 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
114 				       enum port port, i915_reg_t hdmi_reg)
115 {
116 	u32 val = intel_de_read(dev_priv, hdmi_reg);
117 
118 	if (val & SDVO_ENABLE ||
119 	    (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
120 		return;
121 
122 	drm_dbg_kms(&dev_priv->drm,
123 		    "Sanitizing transcoder select for HDMI %c\n",
124 		    port_name(port));
125 
126 	val &= ~SDVO_PIPE_SEL_MASK;
127 	val |= SDVO_PIPE_SEL(PIPE_A);
128 
129 	intel_de_write(dev_priv, hdmi_reg, val);
130 }
131 
132 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
133 				     enum port port, i915_reg_t dp_reg)
134 {
135 	u32 val = intel_de_read(dev_priv, dp_reg);
136 
137 	if (val & DP_PORT_EN ||
138 	    (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
139 		return;
140 
141 	drm_dbg_kms(&dev_priv->drm,
142 		    "Sanitizing transcoder select for DP %c\n",
143 		    port_name(port));
144 
145 	val &= ~DP_PIPE_SEL_MASK;
146 	val |= DP_PIPE_SEL(PIPE_A);
147 
148 	intel_de_write(dev_priv, dp_reg, val);
149 }
150 
151 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
152 {
153 	/*
154 	 * The BIOS may select transcoder B on some of the PCH
155 	 * ports even it doesn't enable the port. This would trip
156 	 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
157 	 * Sanitize the transcoder select bits to prevent that. We
158 	 * assume that the BIOS never actually enabled the port,
159 	 * because if it did we'd actually have to toggle the port
160 	 * on and back off to make the transcoder A select stick
161 	 * (see. intel_dp_link_down(), intel_disable_hdmi(),
162 	 * intel_disable_sdvo()).
163 	 */
164 	ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
165 	ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
166 	ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
167 
168 	/* PCH SDVOB multiplex with HDMIB */
169 	ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
170 	ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
171 	ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
172 }
173 
174 static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc,
175 					   const struct intel_link_m_n *m_n)
176 {
177 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
178 	enum pipe pipe = crtc->pipe;
179 
180 	intel_set_m_n(dev_priv, m_n,
181 		      PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
182 		      PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
183 }
184 
185 static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc,
186 					   const struct intel_link_m_n *m_n)
187 {
188 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
189 	enum pipe pipe = crtc->pipe;
190 
191 	intel_set_m_n(dev_priv, m_n,
192 		      PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
193 		      PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
194 }
195 
196 void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc,
197 				    struct intel_link_m_n *m_n)
198 {
199 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
200 	enum pipe pipe = crtc->pipe;
201 
202 	intel_get_m_n(dev_priv, m_n,
203 		      PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
204 		      PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
205 }
206 
207 void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc,
208 				    struct intel_link_m_n *m_n)
209 {
210 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
211 	enum pipe pipe = crtc->pipe;
212 
213 	intel_get_m_n(dev_priv, m_n,
214 		      PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
215 		      PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
216 }
217 
218 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
219 					   enum pipe pch_transcoder)
220 {
221 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
222 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
223 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
224 
225 	intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
226 		       intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder)));
227 	intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
228 		       intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)));
229 	intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
230 		       intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)));
231 
232 	intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
233 		       intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)));
234 	intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
235 		       intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)));
236 	intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
237 		       intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)));
238 	intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
239 		       intel_de_read(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder)));
240 }
241 
242 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
243 {
244 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
245 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
246 	enum pipe pipe = crtc->pipe;
247 	i915_reg_t reg;
248 	u32 val, pipeconf_val;
249 
250 	/* Make sure PCH DPLL is enabled */
251 	assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
252 
253 	/* FDI must be feeding us bits for PCH ports */
254 	assert_fdi_tx_enabled(dev_priv, pipe);
255 	assert_fdi_rx_enabled(dev_priv, pipe);
256 
257 	if (HAS_PCH_CPT(dev_priv)) {
258 		reg = TRANS_CHICKEN2(pipe);
259 		val = intel_de_read(dev_priv, reg);
260 		/*
261 		 * Workaround: Set the timing override bit
262 		 * before enabling the pch transcoder.
263 		 */
264 		val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
265 		/* Configure frame start delay to match the CPU */
266 		val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
267 		val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
268 		intel_de_write(dev_priv, reg, val);
269 	}
270 
271 	reg = PCH_TRANSCONF(pipe);
272 	val = intel_de_read(dev_priv, reg);
273 	pipeconf_val = intel_de_read(dev_priv, TRANSCONF(pipe));
274 
275 	if (HAS_PCH_IBX(dev_priv)) {
276 		/* Configure frame start delay to match the CPU */
277 		val &= ~TRANS_FRAME_START_DELAY_MASK;
278 		val |= TRANS_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
279 
280 		/*
281 		 * Make the BPC in transcoder be consistent with
282 		 * that in pipeconf reg. For HDMI we must use 8bpc
283 		 * here for both 8bpc and 12bpc.
284 		 */
285 		val &= ~TRANSCONF_BPC_MASK;
286 		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
287 			val |= TRANSCONF_BPC_8;
288 		else
289 			val |= pipeconf_val & TRANSCONF_BPC_MASK;
290 	}
291 
292 	val &= ~TRANS_INTERLACE_MASK;
293 	if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_ILK) == TRANSCONF_INTERLACE_IF_ID_ILK) {
294 		if (HAS_PCH_IBX(dev_priv) &&
295 		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
296 			val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX;
297 		else
298 			val |= TRANS_INTERLACE_INTERLACED;
299 	} else {
300 		val |= TRANS_INTERLACE_PROGRESSIVE;
301 	}
302 
303 	intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
304 	if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
305 		drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
306 			pipe_name(pipe));
307 }
308 
309 static void ilk_disable_pch_transcoder(struct intel_crtc *crtc)
310 {
311 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
312 	enum pipe pipe = crtc->pipe;
313 	i915_reg_t reg;
314 
315 	/* FDI relies on the transcoder */
316 	assert_fdi_tx_disabled(dev_priv, pipe);
317 	assert_fdi_rx_disabled(dev_priv, pipe);
318 
319 	/* Ports must be off as well */
320 	assert_pch_ports_disabled(dev_priv, pipe);
321 
322 	reg = PCH_TRANSCONF(pipe);
323 	intel_de_rmw(dev_priv, reg, TRANS_ENABLE, 0);
324 	/* wait for PCH transcoder off, transcoder state */
325 	if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
326 		drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
327 			pipe_name(pipe));
328 
329 	if (HAS_PCH_CPT(dev_priv))
330 		/* Workaround: Clear the timing override chicken bit again. */
331 		intel_de_rmw(dev_priv, TRANS_CHICKEN2(pipe),
332 			     TRANS_CHICKEN2_TIMING_OVERRIDE, 0);
333 }
334 
335 void ilk_pch_pre_enable(struct intel_atomic_state *state,
336 			struct intel_crtc *crtc)
337 {
338 	const struct intel_crtc_state *crtc_state =
339 		intel_atomic_get_new_crtc_state(state, crtc);
340 
341 	/*
342 	 * Note: FDI PLL enabling _must_ be done before we enable the
343 	 * cpu pipes, hence this is separate from all the other fdi/pch
344 	 * enabling.
345 	 */
346 	ilk_fdi_pll_enable(crtc_state);
347 }
348 
349 /*
350  * Enable PCH resources required for PCH ports:
351  *   - PCH PLLs
352  *   - FDI training & RX/TX
353  *   - update transcoder timings
354  *   - DP transcoding bits
355  *   - transcoder
356  */
357 void ilk_pch_enable(struct intel_atomic_state *state,
358 		    struct intel_crtc *crtc)
359 {
360 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
361 	const struct intel_crtc_state *crtc_state =
362 		intel_atomic_get_new_crtc_state(state, crtc);
363 	enum pipe pipe = crtc->pipe;
364 	u32 temp;
365 
366 	assert_pch_transcoder_disabled(dev_priv, pipe);
367 
368 	/* For PCH output, training FDI link */
369 	intel_fdi_link_train(crtc, crtc_state);
370 
371 	/*
372 	 * We need to program the right clock selection
373 	 * before writing the pixel multiplier into the DPLL.
374 	 */
375 	if (HAS_PCH_CPT(dev_priv)) {
376 		u32 sel;
377 
378 		temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
379 		temp |= TRANS_DPLL_ENABLE(pipe);
380 		sel = TRANS_DPLLB_SEL(pipe);
381 		if (crtc_state->shared_dpll ==
382 		    intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
383 			temp |= sel;
384 		else
385 			temp &= ~sel;
386 		intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
387 	}
388 
389 	/*
390 	 * XXX: pch pll's can be enabled any time before we enable the PCH
391 	 * transcoder, and we actually should do this to not upset any PCH
392 	 * transcoder that already use the clock when we share it.
393 	 *
394 	 * Note that enable_shared_dpll tries to do the right thing, but
395 	 * get_shared_dpll unconditionally resets the pll - we need that
396 	 * to have the right LVDS enable sequence.
397 	 */
398 	intel_enable_shared_dpll(crtc_state);
399 
400 	/* set transcoder timing, panel must allow it */
401 	assert_pps_unlocked(dev_priv, pipe);
402 	if (intel_crtc_has_dp_encoder(crtc_state)) {
403 		intel_pch_transcoder_set_m1_n1(crtc, &crtc_state->dp_m_n);
404 		intel_pch_transcoder_set_m2_n2(crtc, &crtc_state->dp_m2_n2);
405 	}
406 	ilk_pch_transcoder_set_timings(crtc_state, pipe);
407 
408 	intel_fdi_normal_train(crtc);
409 
410 	/* For PCH DP, enable TRANS_DP_CTL */
411 	if (HAS_PCH_CPT(dev_priv) &&
412 	    intel_crtc_has_dp_encoder(crtc_state)) {
413 		const struct drm_display_mode *adjusted_mode =
414 			&crtc_state->hw.adjusted_mode;
415 		u32 bpc = (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) >> 5;
416 		i915_reg_t reg = TRANS_DP_CTL(pipe);
417 		enum port port;
418 
419 		temp = intel_de_read(dev_priv, reg);
420 		temp &= ~(TRANS_DP_PORT_SEL_MASK |
421 			  TRANS_DP_VSYNC_ACTIVE_HIGH |
422 			  TRANS_DP_HSYNC_ACTIVE_HIGH |
423 			  TRANS_DP_BPC_MASK);
424 		temp |= TRANS_DP_OUTPUT_ENABLE;
425 		temp |= bpc << 9; /* same format but at 11:9 */
426 
427 		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
428 			temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
429 		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
430 			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
431 
432 		port = intel_get_crtc_new_encoder(state, crtc_state)->port;
433 		drm_WARN_ON(&dev_priv->drm, port < PORT_B || port > PORT_D);
434 		temp |= TRANS_DP_PORT_SEL(port);
435 
436 		intel_de_write(dev_priv, reg, temp);
437 	}
438 
439 	ilk_enable_pch_transcoder(crtc_state);
440 }
441 
442 void ilk_pch_disable(struct intel_atomic_state *state,
443 		     struct intel_crtc *crtc)
444 {
445 	ilk_fdi_disable(crtc);
446 }
447 
448 void ilk_pch_post_disable(struct intel_atomic_state *state,
449 			  struct intel_crtc *crtc)
450 {
451 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
452 	enum pipe pipe = crtc->pipe;
453 
454 	ilk_disable_pch_transcoder(crtc);
455 
456 	if (HAS_PCH_CPT(dev_priv)) {
457 		/* disable TRANS_DP_CTL */
458 		intel_de_rmw(dev_priv, TRANS_DP_CTL(pipe),
459 			     TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK,
460 			     TRANS_DP_PORT_SEL_NONE);
461 
462 		/* disable DPLL_SEL */
463 		intel_de_rmw(dev_priv, PCH_DPLL_SEL,
464 			     TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe), 0);
465 	}
466 
467 	ilk_fdi_pll_disable(crtc);
468 }
469 
470 static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
471 {
472 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
473 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
474 
475 	/* read out port_clock from the DPLL */
476 	i9xx_crtc_clock_get(crtc, crtc_state);
477 
478 	/*
479 	 * In case there is an active pipe without active ports,
480 	 * we may need some idea for the dotclock anyway.
481 	 * Calculate one based on the FDI configuration.
482 	 */
483 	crtc_state->hw.adjusted_mode.crtc_clock =
484 		intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, crtc_state),
485 					 &crtc_state->fdi_m_n);
486 }
487 
488 void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
489 {
490 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
491 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
492 	struct intel_shared_dpll *pll;
493 	enum pipe pipe = crtc->pipe;
494 	enum intel_dpll_id pll_id;
495 	bool pll_active;
496 	u32 tmp;
497 
498 	if ((intel_de_read(dev_priv, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
499 		return;
500 
501 	crtc_state->has_pch_encoder = true;
502 
503 	tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
504 	crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
505 				 FDI_DP_PORT_WIDTH_SHIFT) + 1;
506 
507 	intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
508 				       &crtc_state->fdi_m_n);
509 
510 	if (HAS_PCH_IBX(dev_priv)) {
511 		/*
512 		 * The pipe->pch transcoder and pch transcoder->pll
513 		 * mapping is fixed.
514 		 */
515 		pll_id = (enum intel_dpll_id) pipe;
516 	} else {
517 		tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
518 		if (tmp & TRANS_DPLLB_SEL(pipe))
519 			pll_id = DPLL_ID_PCH_PLL_B;
520 		else
521 			pll_id = DPLL_ID_PCH_PLL_A;
522 	}
523 
524 	crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
525 	pll = crtc_state->shared_dpll;
526 
527 	pll_active = intel_dpll_get_hw_state(dev_priv, pll,
528 					     &crtc_state->dpll_hw_state);
529 	drm_WARN_ON(&dev_priv->drm, !pll_active);
530 
531 	tmp = crtc_state->dpll_hw_state.dpll;
532 	crtc_state->pixel_multiplier =
533 		((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
534 		 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
535 
536 	ilk_pch_clock_get(crtc_state);
537 }
538 
539 static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
540 {
541 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
542 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
543 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
544 	u32 val, pipeconf_val;
545 
546 	/* FDI must be feeding us bits for PCH ports */
547 	assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
548 	assert_fdi_rx_enabled(dev_priv, PIPE_A);
549 
550 	val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
551 	/* Workaround: set timing override bit. */
552 	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
553 	/* Configure frame start delay to match the CPU */
554 	val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
555 	val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
556 	intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
557 
558 	val = TRANS_ENABLE;
559 	pipeconf_val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
560 
561 	if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_HSW) == TRANSCONF_INTERLACE_IF_ID_ILK)
562 		val |= TRANS_INTERLACE_INTERLACED;
563 	else
564 		val |= TRANS_INTERLACE_PROGRESSIVE;
565 
566 	intel_de_write(dev_priv, LPT_TRANSCONF, val);
567 	if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
568 				  TRANS_STATE_ENABLE, 100))
569 		drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
570 }
571 
572 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
573 {
574 	intel_de_rmw(dev_priv, LPT_TRANSCONF, TRANS_ENABLE, 0);
575 	/* wait for PCH transcoder off, transcoder state */
576 	if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
577 				    TRANS_STATE_ENABLE, 50))
578 		drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
579 
580 	/* Workaround: clear timing override bit. */
581 	intel_de_rmw(dev_priv, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0);
582 }
583 
584 void lpt_pch_enable(struct intel_atomic_state *state,
585 		    struct intel_crtc *crtc)
586 {
587 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
588 	const struct intel_crtc_state *crtc_state =
589 		intel_atomic_get_new_crtc_state(state, crtc);
590 
591 	assert_pch_transcoder_disabled(dev_priv, PIPE_A);
592 
593 	lpt_program_iclkip(crtc_state);
594 
595 	/* Set transcoder timing. */
596 	ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
597 
598 	lpt_enable_pch_transcoder(crtc_state);
599 }
600 
601 void lpt_pch_disable(struct intel_atomic_state *state,
602 		     struct intel_crtc *crtc)
603 {
604 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
605 
606 	lpt_disable_pch_transcoder(dev_priv);
607 
608 	lpt_disable_iclkip(dev_priv);
609 }
610 
611 void lpt_pch_get_config(struct intel_crtc_state *crtc_state)
612 {
613 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
614 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
615 	u32 tmp;
616 
617 	if ((intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) == 0)
618 		return;
619 
620 	crtc_state->has_pch_encoder = true;
621 
622 	tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
623 	crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
624 				 FDI_DP_PORT_WIDTH_SHIFT) + 1;
625 
626 	intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
627 				       &crtc_state->fdi_m_n);
628 
629 	crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
630 }
631 
632 void intel_pch_sanitize(struct drm_i915_private *i915)
633 {
634 	if (HAS_PCH_IBX(i915))
635 		ibx_sanitize_pch_ports(i915);
636 }
637