1 /* 2 * Copyright © 2009 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel@ffwll.ch> 25 * 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27 */ 28 29 #include <drm/drm_fourcc.h> 30 31 #include "gem/i915_gem_pm.h" 32 #include "gt/intel_gpu_commands.h" 33 #include "gt/intel_ring.h" 34 35 #include "i915_drv.h" 36 #include "i915_reg.h" 37 #include "intel_display_types.h" 38 #include "intel_frontbuffer.h" 39 #include "intel_overlay.h" 40 41 /* Limits for overlay size. According to intel doc, the real limits are: 42 * Y width: 4095, UV width (planar): 2047, Y height: 2047, 43 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 44 * the mininum of both. */ 45 #define IMAGE_MAX_WIDTH 2048 46 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 47 /* on 830 and 845 these large limits result in the card hanging */ 48 #define IMAGE_MAX_WIDTH_LEGACY 1024 49 #define IMAGE_MAX_HEIGHT_LEGACY 1088 50 51 /* overlay register definitions */ 52 /* OCMD register */ 53 #define OCMD_TILED_SURFACE (0x1<<19) 54 #define OCMD_MIRROR_MASK (0x3<<17) 55 #define OCMD_MIRROR_MODE (0x3<<17) 56 #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 57 #define OCMD_MIRROR_VERTICAL (0x2<<17) 58 #define OCMD_MIRROR_BOTH (0x3<<17) 59 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 60 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 61 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 62 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 63 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 64 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 65 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 66 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 67 #define OCMD_YUV_422_PACKED (0x8<<10) 68 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 69 #define OCMD_YUV_420_PLANAR (0xc<<10) 70 #define OCMD_YUV_422_PLANAR (0xd<<10) 71 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 72 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 73 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 74 #define OCMD_BUF_TYPE_MASK (0x1<<5) 75 #define OCMD_BUF_TYPE_FRAME (0x0<<5) 76 #define OCMD_BUF_TYPE_FIELD (0x1<<5) 77 #define OCMD_TEST_MODE (0x1<<4) 78 #define OCMD_BUFFER_SELECT (0x3<<2) 79 #define OCMD_BUFFER0 (0x0<<2) 80 #define OCMD_BUFFER1 (0x1<<2) 81 #define OCMD_FIELD_SELECT (0x1<<2) 82 #define OCMD_FIELD0 (0x0<<1) 83 #define OCMD_FIELD1 (0x1<<1) 84 #define OCMD_ENABLE (0x1<<0) 85 86 /* OCONFIG register */ 87 #define OCONF_PIPE_MASK (0x1<<18) 88 #define OCONF_PIPE_A (0x0<<18) 89 #define OCONF_PIPE_B (0x1<<18) 90 #define OCONF_GAMMA2_ENABLE (0x1<<16) 91 #define OCONF_CSC_MODE_BT601 (0x0<<5) 92 #define OCONF_CSC_MODE_BT709 (0x1<<5) 93 #define OCONF_CSC_BYPASS (0x1<<4) 94 #define OCONF_CC_OUT_8BIT (0x1<<3) 95 #define OCONF_TEST_MODE (0x1<<2) 96 #define OCONF_THREE_LINE_BUFFER (0x1<<0) 97 #define OCONF_TWO_LINE_BUFFER (0x0<<0) 98 99 /* DCLRKM (dst-key) register */ 100 #define DST_KEY_ENABLE (0x1<<31) 101 #define CLK_RGB24_MASK 0x0 102 #define CLK_RGB16_MASK 0x070307 103 #define CLK_RGB15_MASK 0x070707 104 105 #define RGB30_TO_COLORKEY(c) \ 106 ((((c) & 0x3fc00000) >> 6) | (((c) & 0x000ff000) >> 4) | (((c) & 0x000003fc) >> 2)) 107 #define RGB16_TO_COLORKEY(c) \ 108 ((((c) & 0xf800) << 8) | (((c) & 0x07e0) << 5) | (((c) & 0x001f) << 3)) 109 #define RGB15_TO_COLORKEY(c) \ 110 ((((c) & 0x7c00) << 9) | (((c) & 0x03e0) << 6) | (((c) & 0x001f) << 3)) 111 #define RGB8I_TO_COLORKEY(c) \ 112 ((((c) & 0xff) << 16) | (((c) & 0xff) << 8) | (((c) & 0xff) << 0)) 113 114 /* overlay flip addr flag */ 115 #define OFC_UPDATE 0x1 116 117 /* polyphase filter coefficients */ 118 #define N_HORIZ_Y_TAPS 5 119 #define N_VERT_Y_TAPS 3 120 #define N_HORIZ_UV_TAPS 3 121 #define N_VERT_UV_TAPS 3 122 #define N_PHASES 17 123 #define MAX_TAPS 5 124 125 /* memory bufferd overlay registers */ 126 struct overlay_registers { 127 u32 OBUF_0Y; 128 u32 OBUF_1Y; 129 u32 OBUF_0U; 130 u32 OBUF_0V; 131 u32 OBUF_1U; 132 u32 OBUF_1V; 133 u32 OSTRIDE; 134 u32 YRGB_VPH; 135 u32 UV_VPH; 136 u32 HORZ_PH; 137 u32 INIT_PHS; 138 u32 DWINPOS; 139 u32 DWINSZ; 140 u32 SWIDTH; 141 u32 SWIDTHSW; 142 u32 SHEIGHT; 143 u32 YRGBSCALE; 144 u32 UVSCALE; 145 u32 OCLRC0; 146 u32 OCLRC1; 147 u32 DCLRKV; 148 u32 DCLRKM; 149 u32 SCLRKVH; 150 u32 SCLRKVL; 151 u32 SCLRKEN; 152 u32 OCONFIG; 153 u32 OCMD; 154 u32 RESERVED1; /* 0x6C */ 155 u32 OSTART_0Y; 156 u32 OSTART_1Y; 157 u32 OSTART_0U; 158 u32 OSTART_0V; 159 u32 OSTART_1U; 160 u32 OSTART_1V; 161 u32 OTILEOFF_0Y; 162 u32 OTILEOFF_1Y; 163 u32 OTILEOFF_0U; 164 u32 OTILEOFF_0V; 165 u32 OTILEOFF_1U; 166 u32 OTILEOFF_1V; 167 u32 FASTHSCALE; /* 0xA0 */ 168 u32 UVSCALEV; /* 0xA4 */ 169 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 170 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 171 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 172 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 173 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 174 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 175 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 176 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 177 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 178 }; 179 180 struct intel_overlay { 181 struct drm_i915_private *i915; 182 struct intel_context *context; 183 struct intel_crtc *crtc; 184 struct i915_vma *vma; 185 struct i915_vma *old_vma; 186 struct intel_frontbuffer *frontbuffer; 187 bool active; 188 bool pfit_active; 189 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 190 u32 color_key:24; 191 u32 color_key_enabled:1; 192 u32 brightness, contrast, saturation; 193 u32 old_xscale, old_yscale; 194 /* register access */ 195 struct drm_i915_gem_object *reg_bo; 196 struct overlay_registers __iomem *regs; 197 u32 flip_addr; 198 /* flip handling */ 199 struct i915_active last_flip; 200 void (*flip_complete)(struct intel_overlay *ovl); 201 }; 202 203 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, 204 bool enable) 205 { 206 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 207 u8 val; 208 209 /* WA_OVERLAY_CLKGATE:alm */ 210 if (enable) 211 intel_de_write(dev_priv, DSPCLK_GATE_D, 0); 212 else 213 intel_de_write(dev_priv, DSPCLK_GATE_D, 214 OVRUNIT_CLOCK_GATE_DISABLE); 215 216 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 217 pci_bus_read_config_byte(pdev->bus, 218 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); 219 if (enable) 220 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; 221 else 222 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 223 pci_bus_write_config_byte(pdev->bus, 224 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 225 } 226 227 static struct i915_request * 228 alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *)) 229 { 230 struct i915_request *rq; 231 int err; 232 233 overlay->flip_complete = fn; 234 235 rq = i915_request_create(overlay->context); 236 if (IS_ERR(rq)) 237 return rq; 238 239 err = i915_active_add_request(&overlay->last_flip, rq); 240 if (err) { 241 i915_request_add(rq); 242 return ERR_PTR(err); 243 } 244 245 return rq; 246 } 247 248 /* overlay needs to be disable in OCMD reg */ 249 static int intel_overlay_on(struct intel_overlay *overlay) 250 { 251 struct drm_i915_private *dev_priv = overlay->i915; 252 struct i915_request *rq; 253 u32 *cs; 254 255 drm_WARN_ON(&dev_priv->drm, overlay->active); 256 257 rq = alloc_request(overlay, NULL); 258 if (IS_ERR(rq)) 259 return PTR_ERR(rq); 260 261 cs = intel_ring_begin(rq, 4); 262 if (IS_ERR(cs)) { 263 i915_request_add(rq); 264 return PTR_ERR(cs); 265 } 266 267 overlay->active = true; 268 269 if (IS_I830(dev_priv)) 270 i830_overlay_clock_gating(dev_priv, false); 271 272 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 273 *cs++ = overlay->flip_addr | OFC_UPDATE; 274 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 275 *cs++ = MI_NOOP; 276 intel_ring_advance(rq, cs); 277 278 i915_request_add(rq); 279 280 return i915_active_wait(&overlay->last_flip); 281 } 282 283 static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 284 struct i915_vma *vma) 285 { 286 enum pipe pipe = overlay->crtc->pipe; 287 struct intel_frontbuffer *frontbuffer = NULL; 288 289 drm_WARN_ON(&overlay->i915->drm, overlay->old_vma); 290 291 if (vma) 292 frontbuffer = intel_frontbuffer_get(vma->obj); 293 294 intel_frontbuffer_track(overlay->frontbuffer, frontbuffer, 295 INTEL_FRONTBUFFER_OVERLAY(pipe)); 296 297 if (overlay->frontbuffer) 298 intel_frontbuffer_put(overlay->frontbuffer); 299 overlay->frontbuffer = frontbuffer; 300 301 intel_frontbuffer_flip_prepare(overlay->i915, 302 INTEL_FRONTBUFFER_OVERLAY(pipe)); 303 304 overlay->old_vma = overlay->vma; 305 if (vma) 306 overlay->vma = i915_vma_get(vma); 307 else 308 overlay->vma = NULL; 309 } 310 311 /* overlay needs to be enabled in OCMD reg */ 312 static int intel_overlay_continue(struct intel_overlay *overlay, 313 struct i915_vma *vma, 314 bool load_polyphase_filter) 315 { 316 struct drm_i915_private *dev_priv = overlay->i915; 317 struct i915_request *rq; 318 u32 flip_addr = overlay->flip_addr; 319 u32 tmp, *cs; 320 321 drm_WARN_ON(&dev_priv->drm, !overlay->active); 322 323 if (load_polyphase_filter) 324 flip_addr |= OFC_UPDATE; 325 326 /* check for underruns */ 327 tmp = intel_de_read(dev_priv, DOVSTA); 328 if (tmp & (1 << 17)) 329 drm_dbg(&dev_priv->drm, "overlay underrun, DOVSTA: %x\n", tmp); 330 331 rq = alloc_request(overlay, NULL); 332 if (IS_ERR(rq)) 333 return PTR_ERR(rq); 334 335 cs = intel_ring_begin(rq, 2); 336 if (IS_ERR(cs)) { 337 i915_request_add(rq); 338 return PTR_ERR(cs); 339 } 340 341 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 342 *cs++ = flip_addr; 343 intel_ring_advance(rq, cs); 344 345 intel_overlay_flip_prepare(overlay, vma); 346 i915_request_add(rq); 347 348 return 0; 349 } 350 351 static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 352 { 353 struct i915_vma *vma; 354 355 vma = fetch_and_zero(&overlay->old_vma); 356 if (drm_WARN_ON(&overlay->i915->drm, !vma)) 357 return; 358 359 intel_frontbuffer_flip_complete(overlay->i915, 360 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 361 362 i915_vma_unpin(vma); 363 i915_vma_put(vma); 364 } 365 366 static void 367 intel_overlay_release_old_vid_tail(struct intel_overlay *overlay) 368 { 369 intel_overlay_release_old_vma(overlay); 370 } 371 372 static void intel_overlay_off_tail(struct intel_overlay *overlay) 373 { 374 struct drm_i915_private *dev_priv = overlay->i915; 375 376 intel_overlay_release_old_vma(overlay); 377 378 overlay->crtc->overlay = NULL; 379 overlay->crtc = NULL; 380 overlay->active = false; 381 382 if (IS_I830(dev_priv)) 383 i830_overlay_clock_gating(dev_priv, true); 384 } 385 386 static void intel_overlay_last_flip_retire(struct i915_active *active) 387 { 388 struct intel_overlay *overlay = 389 container_of(active, typeof(*overlay), last_flip); 390 391 if (overlay->flip_complete) 392 overlay->flip_complete(overlay); 393 } 394 395 /* overlay needs to be disabled in OCMD reg */ 396 static int intel_overlay_off(struct intel_overlay *overlay) 397 { 398 struct i915_request *rq; 399 u32 *cs, flip_addr = overlay->flip_addr; 400 401 drm_WARN_ON(&overlay->i915->drm, !overlay->active); 402 403 /* According to intel docs the overlay hw may hang (when switching 404 * off) without loading the filter coeffs. It is however unclear whether 405 * this applies to the disabling of the overlay or to the switching off 406 * of the hw. Do it in both cases */ 407 flip_addr |= OFC_UPDATE; 408 409 rq = alloc_request(overlay, intel_overlay_off_tail); 410 if (IS_ERR(rq)) 411 return PTR_ERR(rq); 412 413 cs = intel_ring_begin(rq, 6); 414 if (IS_ERR(cs)) { 415 i915_request_add(rq); 416 return PTR_ERR(cs); 417 } 418 419 /* wait for overlay to go idle */ 420 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 421 *cs++ = flip_addr; 422 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 423 424 /* turn overlay off */ 425 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; 426 *cs++ = flip_addr; 427 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 428 429 intel_ring_advance(rq, cs); 430 431 intel_overlay_flip_prepare(overlay, NULL); 432 i915_request_add(rq); 433 434 return i915_active_wait(&overlay->last_flip); 435 } 436 437 /* recover from an interruption due to a signal 438 * We have to be careful not to repeat work forever an make forward progess. */ 439 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) 440 { 441 return i915_active_wait(&overlay->last_flip); 442 } 443 444 /* Wait for pending overlay flip and release old frame. 445 * Needs to be called before the overlay register are changed 446 * via intel_overlay_(un)map_regs 447 */ 448 static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 449 { 450 struct drm_i915_private *dev_priv = overlay->i915; 451 struct i915_request *rq; 452 u32 *cs; 453 454 /* 455 * Only wait if there is actually an old frame to release to 456 * guarantee forward progress. 457 */ 458 if (!overlay->old_vma) 459 return 0; 460 461 if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { 462 intel_overlay_release_old_vid_tail(overlay); 463 return 0; 464 } 465 466 rq = alloc_request(overlay, intel_overlay_release_old_vid_tail); 467 if (IS_ERR(rq)) 468 return PTR_ERR(rq); 469 470 cs = intel_ring_begin(rq, 2); 471 if (IS_ERR(cs)) { 472 i915_request_add(rq); 473 return PTR_ERR(cs); 474 } 475 476 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 477 *cs++ = MI_NOOP; 478 intel_ring_advance(rq, cs); 479 480 i915_request_add(rq); 481 482 return i915_active_wait(&overlay->last_flip); 483 } 484 485 void intel_overlay_reset(struct drm_i915_private *dev_priv) 486 { 487 struct intel_overlay *overlay = dev_priv->overlay; 488 489 if (!overlay) 490 return; 491 492 overlay->old_xscale = 0; 493 overlay->old_yscale = 0; 494 overlay->crtc = NULL; 495 overlay->active = false; 496 } 497 498 static int packed_depth_bytes(u32 format) 499 { 500 switch (format & I915_OVERLAY_DEPTH_MASK) { 501 case I915_OVERLAY_YUV422: 502 return 4; 503 case I915_OVERLAY_YUV411: 504 /* return 6; not implemented */ 505 default: 506 return -EINVAL; 507 } 508 } 509 510 static int packed_width_bytes(u32 format, short width) 511 { 512 switch (format & I915_OVERLAY_DEPTH_MASK) { 513 case I915_OVERLAY_YUV422: 514 return width << 1; 515 default: 516 return -EINVAL; 517 } 518 } 519 520 static int uv_hsubsampling(u32 format) 521 { 522 switch (format & I915_OVERLAY_DEPTH_MASK) { 523 case I915_OVERLAY_YUV422: 524 case I915_OVERLAY_YUV420: 525 return 2; 526 case I915_OVERLAY_YUV411: 527 case I915_OVERLAY_YUV410: 528 return 4; 529 default: 530 return -EINVAL; 531 } 532 } 533 534 static int uv_vsubsampling(u32 format) 535 { 536 switch (format & I915_OVERLAY_DEPTH_MASK) { 537 case I915_OVERLAY_YUV420: 538 case I915_OVERLAY_YUV410: 539 return 2; 540 case I915_OVERLAY_YUV422: 541 case I915_OVERLAY_YUV411: 542 return 1; 543 default: 544 return -EINVAL; 545 } 546 } 547 548 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) 549 { 550 u32 sw; 551 552 if (DISPLAY_VER(dev_priv) == 2) 553 sw = ALIGN((offset & 31) + width, 32); 554 else 555 sw = ALIGN((offset & 63) + width, 64); 556 557 if (sw == 0) 558 return 0; 559 560 return (sw - 32) >> 3; 561 } 562 563 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 564 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 565 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 566 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 567 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 568 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 569 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 570 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 571 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 572 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 573 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 574 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 575 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 576 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 577 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 578 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 579 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 580 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 581 }; 582 583 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 584 [ 0] = { 0x3000, 0x1800, 0x1800, }, 585 [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 586 [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 587 [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 588 [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 589 [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 590 [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 591 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 592 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 593 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 594 [10] = { 0xb100, 0x1eb8, 0x3620, }, 595 [11] = { 0xb100, 0x1f18, 0x34a0, }, 596 [12] = { 0xb100, 0x1f68, 0x3360, }, 597 [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 598 [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 599 [15] = { 0xb060, 0x1ff0, 0x30a0, }, 600 [16] = { 0x3000, 0x0800, 0x3000, }, 601 }; 602 603 static void update_polyphase_filter(struct overlay_registers __iomem *regs) 604 { 605 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 606 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 607 sizeof(uv_static_hcoeffs)); 608 } 609 610 static bool update_scaling_factors(struct intel_overlay *overlay, 611 struct overlay_registers __iomem *regs, 612 struct drm_intel_overlay_put_image *params) 613 { 614 /* fixed point with a 12 bit shift */ 615 u32 xscale, yscale, xscale_UV, yscale_UV; 616 #define FP_SHIFT 12 617 #define FRACT_MASK 0xfff 618 bool scale_changed = false; 619 int uv_hscale = uv_hsubsampling(params->flags); 620 int uv_vscale = uv_vsubsampling(params->flags); 621 622 if (params->dst_width > 1) 623 xscale = ((params->src_scan_width - 1) << FP_SHIFT) / 624 params->dst_width; 625 else 626 xscale = 1 << FP_SHIFT; 627 628 if (params->dst_height > 1) 629 yscale = ((params->src_scan_height - 1) << FP_SHIFT) / 630 params->dst_height; 631 else 632 yscale = 1 << FP_SHIFT; 633 634 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 635 xscale_UV = xscale/uv_hscale; 636 yscale_UV = yscale/uv_vscale; 637 /* make the Y scale to UV scale ratio an exact multiply */ 638 xscale = xscale_UV * uv_hscale; 639 yscale = yscale_UV * uv_vscale; 640 /*} else { 641 xscale_UV = 0; 642 yscale_UV = 0; 643 }*/ 644 645 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 646 scale_changed = true; 647 overlay->old_xscale = xscale; 648 overlay->old_yscale = yscale; 649 650 iowrite32(((yscale & FRACT_MASK) << 20) | 651 ((xscale >> FP_SHIFT) << 16) | 652 ((xscale & FRACT_MASK) << 3), 653 ®s->YRGBSCALE); 654 655 iowrite32(((yscale_UV & FRACT_MASK) << 20) | 656 ((xscale_UV >> FP_SHIFT) << 16) | 657 ((xscale_UV & FRACT_MASK) << 3), 658 ®s->UVSCALE); 659 660 iowrite32((((yscale >> FP_SHIFT) << 16) | 661 ((yscale_UV >> FP_SHIFT) << 0)), 662 ®s->UVSCALEV); 663 664 if (scale_changed) 665 update_polyphase_filter(regs); 666 667 return scale_changed; 668 } 669 670 static void update_colorkey(struct intel_overlay *overlay, 671 struct overlay_registers __iomem *regs) 672 { 673 const struct intel_plane_state *state = 674 to_intel_plane_state(overlay->crtc->base.primary->state); 675 u32 key = overlay->color_key; 676 u32 format = 0; 677 u32 flags = 0; 678 679 if (overlay->color_key_enabled) 680 flags |= DST_KEY_ENABLE; 681 682 if (state->uapi.visible) 683 format = state->hw.fb->format->format; 684 685 switch (format) { 686 case DRM_FORMAT_C8: 687 key = RGB8I_TO_COLORKEY(key); 688 flags |= CLK_RGB24_MASK; 689 break; 690 case DRM_FORMAT_XRGB1555: 691 key = RGB15_TO_COLORKEY(key); 692 flags |= CLK_RGB15_MASK; 693 break; 694 case DRM_FORMAT_RGB565: 695 key = RGB16_TO_COLORKEY(key); 696 flags |= CLK_RGB16_MASK; 697 break; 698 case DRM_FORMAT_XRGB2101010: 699 case DRM_FORMAT_XBGR2101010: 700 key = RGB30_TO_COLORKEY(key); 701 flags |= CLK_RGB24_MASK; 702 break; 703 default: 704 flags |= CLK_RGB24_MASK; 705 break; 706 } 707 708 iowrite32(key, ®s->DCLRKV); 709 iowrite32(flags, ®s->DCLRKM); 710 } 711 712 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) 713 { 714 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 715 716 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 717 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 718 case I915_OVERLAY_YUV422: 719 cmd |= OCMD_YUV_422_PLANAR; 720 break; 721 case I915_OVERLAY_YUV420: 722 cmd |= OCMD_YUV_420_PLANAR; 723 break; 724 case I915_OVERLAY_YUV411: 725 case I915_OVERLAY_YUV410: 726 cmd |= OCMD_YUV_410_PLANAR; 727 break; 728 } 729 } else { /* YUV packed */ 730 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 731 case I915_OVERLAY_YUV422: 732 cmd |= OCMD_YUV_422_PACKED; 733 break; 734 case I915_OVERLAY_YUV411: 735 cmd |= OCMD_YUV_411_PACKED; 736 break; 737 } 738 739 switch (params->flags & I915_OVERLAY_SWAP_MASK) { 740 case I915_OVERLAY_NO_SWAP: 741 break; 742 case I915_OVERLAY_UV_SWAP: 743 cmd |= OCMD_UV_SWAP; 744 break; 745 case I915_OVERLAY_Y_SWAP: 746 cmd |= OCMD_Y_SWAP; 747 break; 748 case I915_OVERLAY_Y_AND_UV_SWAP: 749 cmd |= OCMD_Y_AND_UV_SWAP; 750 break; 751 } 752 } 753 754 return cmd; 755 } 756 757 static struct i915_vma *intel_overlay_pin_fb(struct drm_i915_gem_object *new_bo) 758 { 759 struct i915_gem_ww_ctx ww; 760 struct i915_vma *vma; 761 int ret; 762 763 i915_gem_ww_ctx_init(&ww, true); 764 retry: 765 ret = i915_gem_object_lock(new_bo, &ww); 766 if (!ret) { 767 vma = i915_gem_object_pin_to_display_plane(new_bo, &ww, 0, 768 NULL, PIN_MAPPABLE); 769 ret = PTR_ERR_OR_ZERO(vma); 770 } 771 if (ret == -EDEADLK) { 772 ret = i915_gem_ww_ctx_backoff(&ww); 773 if (!ret) 774 goto retry; 775 } 776 i915_gem_ww_ctx_fini(&ww); 777 if (ret) 778 return ERR_PTR(ret); 779 780 return vma; 781 } 782 783 static int intel_overlay_do_put_image(struct intel_overlay *overlay, 784 struct drm_i915_gem_object *new_bo, 785 struct drm_intel_overlay_put_image *params) 786 { 787 struct overlay_registers __iomem *regs = overlay->regs; 788 struct drm_i915_private *dev_priv = overlay->i915; 789 u32 swidth, swidthsw, sheight, ostride; 790 enum pipe pipe = overlay->crtc->pipe; 791 bool scale_changed = false; 792 struct i915_vma *vma; 793 int ret, tmp_width; 794 795 drm_WARN_ON(&dev_priv->drm, 796 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 797 798 ret = intel_overlay_release_old_vid(overlay); 799 if (ret != 0) 800 return ret; 801 802 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 803 804 vma = intel_overlay_pin_fb(new_bo); 805 if (IS_ERR(vma)) 806 goto out_pin_section; 807 808 i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB); 809 810 if (!overlay->active) { 811 const struct intel_crtc_state *crtc_state = 812 overlay->crtc->config; 813 u32 oconfig = 0; 814 815 if (crtc_state->gamma_enable && 816 crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 817 oconfig |= OCONF_CC_OUT_8BIT; 818 if (crtc_state->gamma_enable) 819 oconfig |= OCONF_GAMMA2_ENABLE; 820 if (DISPLAY_VER(dev_priv) == 4) 821 oconfig |= OCONF_CSC_MODE_BT709; 822 oconfig |= pipe == 0 ? 823 OCONF_PIPE_A : OCONF_PIPE_B; 824 iowrite32(oconfig, ®s->OCONFIG); 825 826 ret = intel_overlay_on(overlay); 827 if (ret != 0) 828 goto out_unpin; 829 } 830 831 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS); 832 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ); 833 834 if (params->flags & I915_OVERLAY_YUV_PACKED) 835 tmp_width = packed_width_bytes(params->flags, 836 params->src_width); 837 else 838 tmp_width = params->src_width; 839 840 swidth = params->src_width; 841 swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width); 842 sheight = params->src_height; 843 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); 844 ostride = params->stride_Y; 845 846 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 847 int uv_hscale = uv_hsubsampling(params->flags); 848 int uv_vscale = uv_vsubsampling(params->flags); 849 u32 tmp_U, tmp_V; 850 851 swidth |= (params->src_width / uv_hscale) << 16; 852 sheight |= (params->src_height / uv_vscale) << 16; 853 854 tmp_U = calc_swidthsw(dev_priv, params->offset_U, 855 params->src_width / uv_hscale); 856 tmp_V = calc_swidthsw(dev_priv, params->offset_V, 857 params->src_width / uv_hscale); 858 swidthsw |= max(tmp_U, tmp_V) << 16; 859 860 iowrite32(i915_ggtt_offset(vma) + params->offset_U, 861 ®s->OBUF_0U); 862 iowrite32(i915_ggtt_offset(vma) + params->offset_V, 863 ®s->OBUF_0V); 864 865 ostride |= params->stride_UV << 16; 866 } 867 868 iowrite32(swidth, ®s->SWIDTH); 869 iowrite32(swidthsw, ®s->SWIDTHSW); 870 iowrite32(sheight, ®s->SHEIGHT); 871 iowrite32(ostride, ®s->OSTRIDE); 872 873 scale_changed = update_scaling_factors(overlay, regs, params); 874 875 update_colorkey(overlay, regs); 876 877 iowrite32(overlay_cmd_reg(params), ®s->OCMD); 878 879 ret = intel_overlay_continue(overlay, vma, scale_changed); 880 if (ret) 881 goto out_unpin; 882 883 return 0; 884 885 out_unpin: 886 i915_vma_unpin(vma); 887 out_pin_section: 888 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 889 890 return ret; 891 } 892 893 int intel_overlay_switch_off(struct intel_overlay *overlay) 894 { 895 struct drm_i915_private *dev_priv = overlay->i915; 896 int ret; 897 898 drm_WARN_ON(&dev_priv->drm, 899 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 900 901 ret = intel_overlay_recover_from_interrupt(overlay); 902 if (ret != 0) 903 return ret; 904 905 if (!overlay->active) 906 return 0; 907 908 ret = intel_overlay_release_old_vid(overlay); 909 if (ret != 0) 910 return ret; 911 912 iowrite32(0, &overlay->regs->OCMD); 913 914 return intel_overlay_off(overlay); 915 } 916 917 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 918 struct intel_crtc *crtc) 919 { 920 if (!crtc->active) 921 return -EINVAL; 922 923 /* can't use the overlay with double wide pipe */ 924 if (crtc->config->double_wide) 925 return -EINVAL; 926 927 return 0; 928 } 929 930 static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 931 { 932 struct drm_i915_private *dev_priv = overlay->i915; 933 u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL); 934 u32 ratio; 935 936 /* XXX: This is not the same logic as in the xorg driver, but more in 937 * line with the intel documentation for the i965 938 */ 939 if (DISPLAY_VER(dev_priv) >= 4) { 940 /* on i965 use the PGM reg to read out the autoscaler values */ 941 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; 942 } else { 943 if (pfit_control & VERT_AUTO_SCALE) 944 ratio = intel_de_read(dev_priv, PFIT_AUTO_RATIOS); 945 else 946 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS); 947 ratio >>= PFIT_VERT_SCALE_SHIFT; 948 } 949 950 overlay->pfit_vscale_ratio = ratio; 951 } 952 953 static int check_overlay_dst(struct intel_overlay *overlay, 954 struct drm_intel_overlay_put_image *rec) 955 { 956 const struct intel_crtc_state *pipe_config = 957 overlay->crtc->config; 958 959 if (rec->dst_x < pipe_config->pipe_src_w && 960 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && 961 rec->dst_y < pipe_config->pipe_src_h && 962 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) 963 return 0; 964 else 965 return -EINVAL; 966 } 967 968 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) 969 { 970 u32 tmp; 971 972 /* downscaling limit is 8.0 */ 973 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16; 974 if (tmp > 7) 975 return -EINVAL; 976 977 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16; 978 if (tmp > 7) 979 return -EINVAL; 980 981 return 0; 982 } 983 984 static int check_overlay_src(struct drm_i915_private *dev_priv, 985 struct drm_intel_overlay_put_image *rec, 986 struct drm_i915_gem_object *new_bo) 987 { 988 int uv_hscale = uv_hsubsampling(rec->flags); 989 int uv_vscale = uv_vsubsampling(rec->flags); 990 u32 stride_mask; 991 int depth; 992 u32 tmp; 993 994 /* check src dimensions */ 995 if (IS_I845G(dev_priv) || IS_I830(dev_priv)) { 996 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 997 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 998 return -EINVAL; 999 } else { 1000 if (rec->src_height > IMAGE_MAX_HEIGHT || 1001 rec->src_width > IMAGE_MAX_WIDTH) 1002 return -EINVAL; 1003 } 1004 1005 /* better safe than sorry, use 4 as the maximal subsampling ratio */ 1006 if (rec->src_height < N_VERT_Y_TAPS*4 || 1007 rec->src_width < N_HORIZ_Y_TAPS*4) 1008 return -EINVAL; 1009 1010 /* check alignment constraints */ 1011 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1012 case I915_OVERLAY_RGB: 1013 /* not implemented */ 1014 return -EINVAL; 1015 1016 case I915_OVERLAY_YUV_PACKED: 1017 if (uv_vscale != 1) 1018 return -EINVAL; 1019 1020 depth = packed_depth_bytes(rec->flags); 1021 if (depth < 0) 1022 return depth; 1023 1024 /* ignore UV planes */ 1025 rec->stride_UV = 0; 1026 rec->offset_U = 0; 1027 rec->offset_V = 0; 1028 /* check pixel alignment */ 1029 if (rec->offset_Y % depth) 1030 return -EINVAL; 1031 break; 1032 1033 case I915_OVERLAY_YUV_PLANAR: 1034 if (uv_vscale < 0 || uv_hscale < 0) 1035 return -EINVAL; 1036 /* no offset restrictions for planar formats */ 1037 break; 1038 1039 default: 1040 return -EINVAL; 1041 } 1042 1043 if (rec->src_width % uv_hscale) 1044 return -EINVAL; 1045 1046 /* stride checking */ 1047 if (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1048 stride_mask = 255; 1049 else 1050 stride_mask = 63; 1051 1052 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1053 return -EINVAL; 1054 if (DISPLAY_VER(dev_priv) == 4 && rec->stride_Y < 512) 1055 return -EINVAL; 1056 1057 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1058 4096 : 8192; 1059 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 1060 return -EINVAL; 1061 1062 /* check buffer dimensions */ 1063 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1064 case I915_OVERLAY_RGB: 1065 case I915_OVERLAY_YUV_PACKED: 1066 /* always 4 Y values per depth pixels */ 1067 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 1068 return -EINVAL; 1069 1070 tmp = rec->stride_Y*rec->src_height; 1071 if (rec->offset_Y + tmp > new_bo->base.size) 1072 return -EINVAL; 1073 break; 1074 1075 case I915_OVERLAY_YUV_PLANAR: 1076 if (rec->src_width > rec->stride_Y) 1077 return -EINVAL; 1078 if (rec->src_width/uv_hscale > rec->stride_UV) 1079 return -EINVAL; 1080 1081 tmp = rec->stride_Y * rec->src_height; 1082 if (rec->offset_Y + tmp > new_bo->base.size) 1083 return -EINVAL; 1084 1085 tmp = rec->stride_UV * (rec->src_height / uv_vscale); 1086 if (rec->offset_U + tmp > new_bo->base.size || 1087 rec->offset_V + tmp > new_bo->base.size) 1088 return -EINVAL; 1089 break; 1090 } 1091 1092 return 0; 1093 } 1094 1095 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1096 struct drm_file *file_priv) 1097 { 1098 struct drm_intel_overlay_put_image *params = data; 1099 struct drm_i915_private *dev_priv = to_i915(dev); 1100 struct intel_overlay *overlay; 1101 struct drm_crtc *drmmode_crtc; 1102 struct intel_crtc *crtc; 1103 struct drm_i915_gem_object *new_bo; 1104 int ret; 1105 1106 overlay = dev_priv->overlay; 1107 if (!overlay) { 1108 drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n"); 1109 return -ENODEV; 1110 } 1111 1112 if (!(params->flags & I915_OVERLAY_ENABLE)) { 1113 drm_modeset_lock_all(dev); 1114 ret = intel_overlay_switch_off(overlay); 1115 drm_modeset_unlock_all(dev); 1116 1117 return ret; 1118 } 1119 1120 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id); 1121 if (!drmmode_crtc) 1122 return -ENOENT; 1123 crtc = to_intel_crtc(drmmode_crtc); 1124 1125 new_bo = i915_gem_object_lookup(file_priv, params->bo_handle); 1126 if (!new_bo) 1127 return -ENOENT; 1128 1129 drm_modeset_lock_all(dev); 1130 1131 if (i915_gem_object_is_tiled(new_bo)) { 1132 drm_dbg_kms(&dev_priv->drm, 1133 "buffer used for overlay image can not be tiled\n"); 1134 ret = -EINVAL; 1135 goto out_unlock; 1136 } 1137 1138 ret = intel_overlay_recover_from_interrupt(overlay); 1139 if (ret != 0) 1140 goto out_unlock; 1141 1142 if (overlay->crtc != crtc) { 1143 ret = intel_overlay_switch_off(overlay); 1144 if (ret != 0) 1145 goto out_unlock; 1146 1147 ret = check_overlay_possible_on_crtc(overlay, crtc); 1148 if (ret != 0) 1149 goto out_unlock; 1150 1151 overlay->crtc = crtc; 1152 crtc->overlay = overlay; 1153 1154 /* line too wide, i.e. one-line-mode */ 1155 if (crtc->config->pipe_src_w > 1024 && 1156 crtc->config->gmch_pfit.control & PFIT_ENABLE) { 1157 overlay->pfit_active = true; 1158 update_pfit_vscale_ratio(overlay); 1159 } else 1160 overlay->pfit_active = false; 1161 } 1162 1163 ret = check_overlay_dst(overlay, params); 1164 if (ret != 0) 1165 goto out_unlock; 1166 1167 if (overlay->pfit_active) { 1168 params->dst_y = (((u32)params->dst_y << 12) / 1169 overlay->pfit_vscale_ratio); 1170 /* shifting right rounds downwards, so add 1 */ 1171 params->dst_height = (((u32)params->dst_height << 12) / 1172 overlay->pfit_vscale_ratio) + 1; 1173 } 1174 1175 if (params->src_scan_height > params->src_height || 1176 params->src_scan_width > params->src_width) { 1177 ret = -EINVAL; 1178 goto out_unlock; 1179 } 1180 1181 ret = check_overlay_src(dev_priv, params, new_bo); 1182 if (ret != 0) 1183 goto out_unlock; 1184 1185 /* Check scaling after src size to prevent a divide-by-zero. */ 1186 ret = check_overlay_scaling(params); 1187 if (ret != 0) 1188 goto out_unlock; 1189 1190 ret = intel_overlay_do_put_image(overlay, new_bo, params); 1191 if (ret != 0) 1192 goto out_unlock; 1193 1194 drm_modeset_unlock_all(dev); 1195 i915_gem_object_put(new_bo); 1196 1197 return 0; 1198 1199 out_unlock: 1200 drm_modeset_unlock_all(dev); 1201 i915_gem_object_put(new_bo); 1202 1203 return ret; 1204 } 1205 1206 static void update_reg_attrs(struct intel_overlay *overlay, 1207 struct overlay_registers __iomem *regs) 1208 { 1209 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 1210 ®s->OCLRC0); 1211 iowrite32(overlay->saturation, ®s->OCLRC1); 1212 } 1213 1214 static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 1215 { 1216 int i; 1217 1218 if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 1219 return false; 1220 1221 for (i = 0; i < 3; i++) { 1222 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 1223 return false; 1224 } 1225 1226 return true; 1227 } 1228 1229 static bool check_gamma5_errata(u32 gamma5) 1230 { 1231 int i; 1232 1233 for (i = 0; i < 3; i++) { 1234 if (((gamma5 >> i*8) & 0xff) == 0x80) 1235 return false; 1236 } 1237 1238 return true; 1239 } 1240 1241 static int check_gamma(struct drm_intel_overlay_attrs *attrs) 1242 { 1243 if (!check_gamma_bounds(0, attrs->gamma0) || 1244 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 1245 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 1246 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 1247 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 1248 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 1249 !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 1250 return -EINVAL; 1251 1252 if (!check_gamma5_errata(attrs->gamma5)) 1253 return -EINVAL; 1254 1255 return 0; 1256 } 1257 1258 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1259 struct drm_file *file_priv) 1260 { 1261 struct drm_intel_overlay_attrs *attrs = data; 1262 struct drm_i915_private *dev_priv = to_i915(dev); 1263 struct intel_overlay *overlay; 1264 int ret; 1265 1266 overlay = dev_priv->overlay; 1267 if (!overlay) { 1268 drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n"); 1269 return -ENODEV; 1270 } 1271 1272 drm_modeset_lock_all(dev); 1273 1274 ret = -EINVAL; 1275 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 1276 attrs->color_key = overlay->color_key; 1277 attrs->brightness = overlay->brightness; 1278 attrs->contrast = overlay->contrast; 1279 attrs->saturation = overlay->saturation; 1280 1281 if (DISPLAY_VER(dev_priv) != 2) { 1282 attrs->gamma0 = intel_de_read(dev_priv, OGAMC0); 1283 attrs->gamma1 = intel_de_read(dev_priv, OGAMC1); 1284 attrs->gamma2 = intel_de_read(dev_priv, OGAMC2); 1285 attrs->gamma3 = intel_de_read(dev_priv, OGAMC3); 1286 attrs->gamma4 = intel_de_read(dev_priv, OGAMC4); 1287 attrs->gamma5 = intel_de_read(dev_priv, OGAMC5); 1288 } 1289 } else { 1290 if (attrs->brightness < -128 || attrs->brightness > 127) 1291 goto out_unlock; 1292 if (attrs->contrast > 255) 1293 goto out_unlock; 1294 if (attrs->saturation > 1023) 1295 goto out_unlock; 1296 1297 overlay->color_key = attrs->color_key; 1298 overlay->brightness = attrs->brightness; 1299 overlay->contrast = attrs->contrast; 1300 overlay->saturation = attrs->saturation; 1301 1302 update_reg_attrs(overlay, overlay->regs); 1303 1304 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1305 if (DISPLAY_VER(dev_priv) == 2) 1306 goto out_unlock; 1307 1308 if (overlay->active) { 1309 ret = -EBUSY; 1310 goto out_unlock; 1311 } 1312 1313 ret = check_gamma(attrs); 1314 if (ret) 1315 goto out_unlock; 1316 1317 intel_de_write(dev_priv, OGAMC0, attrs->gamma0); 1318 intel_de_write(dev_priv, OGAMC1, attrs->gamma1); 1319 intel_de_write(dev_priv, OGAMC2, attrs->gamma2); 1320 intel_de_write(dev_priv, OGAMC3, attrs->gamma3); 1321 intel_de_write(dev_priv, OGAMC4, attrs->gamma4); 1322 intel_de_write(dev_priv, OGAMC5, attrs->gamma5); 1323 } 1324 } 1325 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1326 1327 ret = 0; 1328 out_unlock: 1329 drm_modeset_unlock_all(dev); 1330 1331 return ret; 1332 } 1333 1334 static int get_registers(struct intel_overlay *overlay, bool use_phys) 1335 { 1336 struct drm_i915_private *i915 = overlay->i915; 1337 struct drm_i915_gem_object *obj; 1338 struct i915_vma *vma; 1339 int err; 1340 1341 obj = i915_gem_object_create_stolen(i915, PAGE_SIZE); 1342 if (IS_ERR(obj)) 1343 obj = i915_gem_object_create_internal(i915, PAGE_SIZE); 1344 if (IS_ERR(obj)) 1345 return PTR_ERR(obj); 1346 1347 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); 1348 if (IS_ERR(vma)) { 1349 err = PTR_ERR(vma); 1350 goto err_put_bo; 1351 } 1352 1353 if (use_phys) 1354 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl); 1355 else 1356 overlay->flip_addr = i915_ggtt_offset(vma); 1357 overlay->regs = i915_vma_pin_iomap(vma); 1358 i915_vma_unpin(vma); 1359 1360 if (IS_ERR(overlay->regs)) { 1361 err = PTR_ERR(overlay->regs); 1362 goto err_put_bo; 1363 } 1364 1365 overlay->reg_bo = obj; 1366 return 0; 1367 1368 err_put_bo: 1369 i915_gem_object_put(obj); 1370 return err; 1371 } 1372 1373 void intel_overlay_setup(struct drm_i915_private *dev_priv) 1374 { 1375 struct intel_overlay *overlay; 1376 struct intel_engine_cs *engine; 1377 int ret; 1378 1379 if (!HAS_OVERLAY(dev_priv)) 1380 return; 1381 1382 engine = dev_priv->gt.engine[RCS0]; 1383 if (!engine || !engine->kernel_context) 1384 return; 1385 1386 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 1387 if (!overlay) 1388 return; 1389 1390 overlay->i915 = dev_priv; 1391 overlay->context = engine->kernel_context; 1392 GEM_BUG_ON(!overlay->context); 1393 1394 overlay->color_key = 0x0101fe; 1395 overlay->color_key_enabled = true; 1396 overlay->brightness = -19; 1397 overlay->contrast = 75; 1398 overlay->saturation = 146; 1399 1400 i915_active_init(&overlay->last_flip, 1401 NULL, intel_overlay_last_flip_retire, 0); 1402 1403 ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv)); 1404 if (ret) 1405 goto out_free; 1406 1407 memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1408 update_polyphase_filter(overlay->regs); 1409 update_reg_attrs(overlay, overlay->regs); 1410 1411 dev_priv->overlay = overlay; 1412 drm_info(&dev_priv->drm, "Initialized overlay support.\n"); 1413 return; 1414 1415 out_free: 1416 kfree(overlay); 1417 } 1418 1419 void intel_overlay_cleanup(struct drm_i915_private *dev_priv) 1420 { 1421 struct intel_overlay *overlay; 1422 1423 overlay = fetch_and_zero(&dev_priv->overlay); 1424 if (!overlay) 1425 return; 1426 1427 /* 1428 * The bo's should be free'd by the generic code already. 1429 * Furthermore modesetting teardown happens beforehand so the 1430 * hardware should be off already. 1431 */ 1432 drm_WARN_ON(&dev_priv->drm, overlay->active); 1433 1434 i915_gem_object_put(overlay->reg_bo); 1435 i915_active_fini(&overlay->last_flip); 1436 1437 kfree(overlay); 1438 } 1439 1440 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1441 1442 struct intel_overlay_error_state { 1443 struct overlay_registers regs; 1444 unsigned long base; 1445 u32 dovsta; 1446 u32 isr; 1447 }; 1448 1449 struct intel_overlay_error_state * 1450 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) 1451 { 1452 struct intel_overlay *overlay = dev_priv->overlay; 1453 struct intel_overlay_error_state *error; 1454 1455 if (!overlay || !overlay->active) 1456 return NULL; 1457 1458 error = kmalloc(sizeof(*error), GFP_ATOMIC); 1459 if (error == NULL) 1460 return NULL; 1461 1462 error->dovsta = intel_de_read(dev_priv, DOVSTA); 1463 error->isr = intel_de_read(dev_priv, GEN2_ISR); 1464 error->base = overlay->flip_addr; 1465 1466 memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs)); 1467 1468 return error; 1469 } 1470 1471 void 1472 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m, 1473 struct intel_overlay_error_state *error) 1474 { 1475 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1476 error->dovsta, error->isr); 1477 i915_error_printf(m, " Register file at 0x%08lx:\n", 1478 error->base); 1479 1480 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) 1481 P(OBUF_0Y); 1482 P(OBUF_1Y); 1483 P(OBUF_0U); 1484 P(OBUF_0V); 1485 P(OBUF_1U); 1486 P(OBUF_1V); 1487 P(OSTRIDE); 1488 P(YRGB_VPH); 1489 P(UV_VPH); 1490 P(HORZ_PH); 1491 P(INIT_PHS); 1492 P(DWINPOS); 1493 P(DWINSZ); 1494 P(SWIDTH); 1495 P(SWIDTHSW); 1496 P(SHEIGHT); 1497 P(YRGBSCALE); 1498 P(UVSCALE); 1499 P(OCLRC0); 1500 P(OCLRC1); 1501 P(DCLRKV); 1502 P(DCLRKM); 1503 P(SCLRKVH); 1504 P(SCLRKVL); 1505 P(SCLRKEN); 1506 P(OCONFIG); 1507 P(OCMD); 1508 P(OSTART_0Y); 1509 P(OSTART_1Y); 1510 P(OSTART_0U); 1511 P(OSTART_0V); 1512 P(OSTART_1U); 1513 P(OSTART_1V); 1514 P(OTILEOFF_0Y); 1515 P(OTILEOFF_1Y); 1516 P(OTILEOFF_0U); 1517 P(OTILEOFF_0V); 1518 P(OTILEOFF_1U); 1519 P(OTILEOFF_1V); 1520 P(FASTHSCALE); 1521 P(UVSCALEV); 1522 #undef P 1523 } 1524 1525 #endif 1526