1 /* 2 * Copyright © 2009 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel@ffwll.ch> 25 * 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27 */ 28 29 #include <drm/drm_fourcc.h> 30 #include <drm/i915_drm.h> 31 32 #include "gem/i915_gem_pm.h" 33 34 #include "i915_drv.h" 35 #include "i915_reg.h" 36 #include "intel_drv.h" 37 #include "intel_frontbuffer.h" 38 #include "intel_overlay.h" 39 40 /* Limits for overlay size. According to intel doc, the real limits are: 41 * Y width: 4095, UV width (planar): 2047, Y height: 2047, 42 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 43 * the mininum of both. */ 44 #define IMAGE_MAX_WIDTH 2048 45 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 46 /* on 830 and 845 these large limits result in the card hanging */ 47 #define IMAGE_MAX_WIDTH_LEGACY 1024 48 #define IMAGE_MAX_HEIGHT_LEGACY 1088 49 50 /* overlay register definitions */ 51 /* OCMD register */ 52 #define OCMD_TILED_SURFACE (0x1<<19) 53 #define OCMD_MIRROR_MASK (0x3<<17) 54 #define OCMD_MIRROR_MODE (0x3<<17) 55 #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 56 #define OCMD_MIRROR_VERTICAL (0x2<<17) 57 #define OCMD_MIRROR_BOTH (0x3<<17) 58 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 59 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 60 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 61 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 62 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 63 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 64 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 65 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 66 #define OCMD_YUV_422_PACKED (0x8<<10) 67 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 68 #define OCMD_YUV_420_PLANAR (0xc<<10) 69 #define OCMD_YUV_422_PLANAR (0xd<<10) 70 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 71 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 72 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 73 #define OCMD_BUF_TYPE_MASK (0x1<<5) 74 #define OCMD_BUF_TYPE_FRAME (0x0<<5) 75 #define OCMD_BUF_TYPE_FIELD (0x1<<5) 76 #define OCMD_TEST_MODE (0x1<<4) 77 #define OCMD_BUFFER_SELECT (0x3<<2) 78 #define OCMD_BUFFER0 (0x0<<2) 79 #define OCMD_BUFFER1 (0x1<<2) 80 #define OCMD_FIELD_SELECT (0x1<<2) 81 #define OCMD_FIELD0 (0x0<<1) 82 #define OCMD_FIELD1 (0x1<<1) 83 #define OCMD_ENABLE (0x1<<0) 84 85 /* OCONFIG register */ 86 #define OCONF_PIPE_MASK (0x1<<18) 87 #define OCONF_PIPE_A (0x0<<18) 88 #define OCONF_PIPE_B (0x1<<18) 89 #define OCONF_GAMMA2_ENABLE (0x1<<16) 90 #define OCONF_CSC_MODE_BT601 (0x0<<5) 91 #define OCONF_CSC_MODE_BT709 (0x1<<5) 92 #define OCONF_CSC_BYPASS (0x1<<4) 93 #define OCONF_CC_OUT_8BIT (0x1<<3) 94 #define OCONF_TEST_MODE (0x1<<2) 95 #define OCONF_THREE_LINE_BUFFER (0x1<<0) 96 #define OCONF_TWO_LINE_BUFFER (0x0<<0) 97 98 /* DCLRKM (dst-key) register */ 99 #define DST_KEY_ENABLE (0x1<<31) 100 #define CLK_RGB24_MASK 0x0 101 #define CLK_RGB16_MASK 0x070307 102 #define CLK_RGB15_MASK 0x070707 103 #define CLK_RGB8I_MASK 0xffffff 104 105 #define RGB16_TO_COLORKEY(c) \ 106 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3)) 107 #define RGB15_TO_COLORKEY(c) \ 108 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3)) 109 110 /* overlay flip addr flag */ 111 #define OFC_UPDATE 0x1 112 113 /* polyphase filter coefficients */ 114 #define N_HORIZ_Y_TAPS 5 115 #define N_VERT_Y_TAPS 3 116 #define N_HORIZ_UV_TAPS 3 117 #define N_VERT_UV_TAPS 3 118 #define N_PHASES 17 119 #define MAX_TAPS 5 120 121 /* memory bufferd overlay registers */ 122 struct overlay_registers { 123 u32 OBUF_0Y; 124 u32 OBUF_1Y; 125 u32 OBUF_0U; 126 u32 OBUF_0V; 127 u32 OBUF_1U; 128 u32 OBUF_1V; 129 u32 OSTRIDE; 130 u32 YRGB_VPH; 131 u32 UV_VPH; 132 u32 HORZ_PH; 133 u32 INIT_PHS; 134 u32 DWINPOS; 135 u32 DWINSZ; 136 u32 SWIDTH; 137 u32 SWIDTHSW; 138 u32 SHEIGHT; 139 u32 YRGBSCALE; 140 u32 UVSCALE; 141 u32 OCLRC0; 142 u32 OCLRC1; 143 u32 DCLRKV; 144 u32 DCLRKM; 145 u32 SCLRKVH; 146 u32 SCLRKVL; 147 u32 SCLRKEN; 148 u32 OCONFIG; 149 u32 OCMD; 150 u32 RESERVED1; /* 0x6C */ 151 u32 OSTART_0Y; 152 u32 OSTART_1Y; 153 u32 OSTART_0U; 154 u32 OSTART_0V; 155 u32 OSTART_1U; 156 u32 OSTART_1V; 157 u32 OTILEOFF_0Y; 158 u32 OTILEOFF_1Y; 159 u32 OTILEOFF_0U; 160 u32 OTILEOFF_0V; 161 u32 OTILEOFF_1U; 162 u32 OTILEOFF_1V; 163 u32 FASTHSCALE; /* 0xA0 */ 164 u32 UVSCALEV; /* 0xA4 */ 165 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 166 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 167 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 168 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 169 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 170 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 171 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 172 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 173 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 174 }; 175 176 struct intel_overlay { 177 struct drm_i915_private *i915; 178 struct intel_crtc *crtc; 179 struct i915_vma *vma; 180 struct i915_vma *old_vma; 181 bool active; 182 bool pfit_active; 183 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 184 u32 color_key:24; 185 u32 color_key_enabled:1; 186 u32 brightness, contrast, saturation; 187 u32 old_xscale, old_yscale; 188 /* register access */ 189 struct drm_i915_gem_object *reg_bo; 190 struct overlay_registers __iomem *regs; 191 u32 flip_addr; 192 /* flip handling */ 193 struct i915_active_request last_flip; 194 }; 195 196 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, 197 bool enable) 198 { 199 struct pci_dev *pdev = dev_priv->drm.pdev; 200 u8 val; 201 202 /* WA_OVERLAY_CLKGATE:alm */ 203 if (enable) 204 I915_WRITE(DSPCLK_GATE_D, 0); 205 else 206 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 207 208 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 209 pci_bus_read_config_byte(pdev->bus, 210 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); 211 if (enable) 212 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; 213 else 214 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 215 pci_bus_write_config_byte(pdev->bus, 216 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 217 } 218 219 static void intel_overlay_submit_request(struct intel_overlay *overlay, 220 struct i915_request *rq, 221 i915_active_retire_fn retire) 222 { 223 GEM_BUG_ON(i915_active_request_peek(&overlay->last_flip, 224 &overlay->i915->drm.struct_mutex)); 225 i915_active_request_set_retire_fn(&overlay->last_flip, retire, 226 &overlay->i915->drm.struct_mutex); 227 __i915_active_request_set(&overlay->last_flip, rq); 228 i915_request_add(rq); 229 } 230 231 static int intel_overlay_do_wait_request(struct intel_overlay *overlay, 232 struct i915_request *rq, 233 i915_active_retire_fn retire) 234 { 235 intel_overlay_submit_request(overlay, rq, retire); 236 return i915_active_request_retire(&overlay->last_flip, 237 &overlay->i915->drm.struct_mutex); 238 } 239 240 static struct i915_request *alloc_request(struct intel_overlay *overlay) 241 { 242 struct intel_engine_cs *engine = overlay->i915->engine[RCS0]; 243 244 return i915_request_create(engine->kernel_context); 245 } 246 247 /* overlay needs to be disable in OCMD reg */ 248 static int intel_overlay_on(struct intel_overlay *overlay) 249 { 250 struct drm_i915_private *dev_priv = overlay->i915; 251 struct i915_request *rq; 252 u32 *cs; 253 254 WARN_ON(overlay->active); 255 256 rq = alloc_request(overlay); 257 if (IS_ERR(rq)) 258 return PTR_ERR(rq); 259 260 cs = intel_ring_begin(rq, 4); 261 if (IS_ERR(cs)) { 262 i915_request_add(rq); 263 return PTR_ERR(cs); 264 } 265 266 overlay->active = true; 267 268 if (IS_I830(dev_priv)) 269 i830_overlay_clock_gating(dev_priv, false); 270 271 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 272 *cs++ = overlay->flip_addr | OFC_UPDATE; 273 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 274 *cs++ = MI_NOOP; 275 intel_ring_advance(rq, cs); 276 277 return intel_overlay_do_wait_request(overlay, rq, NULL); 278 } 279 280 static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 281 struct i915_vma *vma) 282 { 283 enum pipe pipe = overlay->crtc->pipe; 284 285 WARN_ON(overlay->old_vma); 286 287 i915_gem_track_fb(overlay->vma ? overlay->vma->obj : NULL, 288 vma ? vma->obj : NULL, 289 INTEL_FRONTBUFFER_OVERLAY(pipe)); 290 291 intel_frontbuffer_flip_prepare(overlay->i915, 292 INTEL_FRONTBUFFER_OVERLAY(pipe)); 293 294 overlay->old_vma = overlay->vma; 295 if (vma) 296 overlay->vma = i915_vma_get(vma); 297 else 298 overlay->vma = NULL; 299 } 300 301 /* overlay needs to be enabled in OCMD reg */ 302 static int intel_overlay_continue(struct intel_overlay *overlay, 303 struct i915_vma *vma, 304 bool load_polyphase_filter) 305 { 306 struct drm_i915_private *dev_priv = overlay->i915; 307 struct i915_request *rq; 308 u32 flip_addr = overlay->flip_addr; 309 u32 tmp, *cs; 310 311 WARN_ON(!overlay->active); 312 313 if (load_polyphase_filter) 314 flip_addr |= OFC_UPDATE; 315 316 /* check for underruns */ 317 tmp = I915_READ(DOVSTA); 318 if (tmp & (1 << 17)) 319 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp); 320 321 rq = alloc_request(overlay); 322 if (IS_ERR(rq)) 323 return PTR_ERR(rq); 324 325 cs = intel_ring_begin(rq, 2); 326 if (IS_ERR(cs)) { 327 i915_request_add(rq); 328 return PTR_ERR(cs); 329 } 330 331 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 332 *cs++ = flip_addr; 333 intel_ring_advance(rq, cs); 334 335 intel_overlay_flip_prepare(overlay, vma); 336 337 intel_overlay_submit_request(overlay, rq, NULL); 338 339 return 0; 340 } 341 342 static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 343 { 344 struct i915_vma *vma; 345 346 vma = fetch_and_zero(&overlay->old_vma); 347 if (WARN_ON(!vma)) 348 return; 349 350 intel_frontbuffer_flip_complete(overlay->i915, 351 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 352 353 i915_gem_object_unpin_from_display_plane(vma); 354 i915_vma_put(vma); 355 } 356 357 static void 358 intel_overlay_release_old_vid_tail(struct i915_active_request *active, 359 struct i915_request *rq) 360 { 361 struct intel_overlay *overlay = 362 container_of(active, typeof(*overlay), last_flip); 363 364 intel_overlay_release_old_vma(overlay); 365 } 366 367 static void intel_overlay_off_tail(struct i915_active_request *active, 368 struct i915_request *rq) 369 { 370 struct intel_overlay *overlay = 371 container_of(active, typeof(*overlay), last_flip); 372 struct drm_i915_private *dev_priv = overlay->i915; 373 374 intel_overlay_release_old_vma(overlay); 375 376 overlay->crtc->overlay = NULL; 377 overlay->crtc = NULL; 378 overlay->active = false; 379 380 if (IS_I830(dev_priv)) 381 i830_overlay_clock_gating(dev_priv, true); 382 } 383 384 /* overlay needs to be disabled in OCMD reg */ 385 static int intel_overlay_off(struct intel_overlay *overlay) 386 { 387 struct i915_request *rq; 388 u32 *cs, flip_addr = overlay->flip_addr; 389 390 WARN_ON(!overlay->active); 391 392 /* According to intel docs the overlay hw may hang (when switching 393 * off) without loading the filter coeffs. It is however unclear whether 394 * this applies to the disabling of the overlay or to the switching off 395 * of the hw. Do it in both cases */ 396 flip_addr |= OFC_UPDATE; 397 398 rq = alloc_request(overlay); 399 if (IS_ERR(rq)) 400 return PTR_ERR(rq); 401 402 cs = intel_ring_begin(rq, 6); 403 if (IS_ERR(cs)) { 404 i915_request_add(rq); 405 return PTR_ERR(cs); 406 } 407 408 /* wait for overlay to go idle */ 409 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 410 *cs++ = flip_addr; 411 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 412 413 /* turn overlay off */ 414 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; 415 *cs++ = flip_addr; 416 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 417 418 intel_ring_advance(rq, cs); 419 420 intel_overlay_flip_prepare(overlay, NULL); 421 422 return intel_overlay_do_wait_request(overlay, rq, 423 intel_overlay_off_tail); 424 } 425 426 /* recover from an interruption due to a signal 427 * We have to be careful not to repeat work forever an make forward progess. */ 428 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) 429 { 430 return i915_active_request_retire(&overlay->last_flip, 431 &overlay->i915->drm.struct_mutex); 432 } 433 434 /* Wait for pending overlay flip and release old frame. 435 * Needs to be called before the overlay register are changed 436 * via intel_overlay_(un)map_regs 437 */ 438 static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 439 { 440 struct drm_i915_private *dev_priv = overlay->i915; 441 u32 *cs; 442 int ret; 443 444 lockdep_assert_held(&dev_priv->drm.struct_mutex); 445 446 /* Only wait if there is actually an old frame to release to 447 * guarantee forward progress. 448 */ 449 if (!overlay->old_vma) 450 return 0; 451 452 if (I915_READ(GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) { 453 /* synchronous slowpath */ 454 struct i915_request *rq; 455 456 rq = alloc_request(overlay); 457 if (IS_ERR(rq)) 458 return PTR_ERR(rq); 459 460 cs = intel_ring_begin(rq, 2); 461 if (IS_ERR(cs)) { 462 i915_request_add(rq); 463 return PTR_ERR(cs); 464 } 465 466 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 467 *cs++ = MI_NOOP; 468 intel_ring_advance(rq, cs); 469 470 ret = intel_overlay_do_wait_request(overlay, rq, 471 intel_overlay_release_old_vid_tail); 472 if (ret) 473 return ret; 474 } else 475 intel_overlay_release_old_vid_tail(&overlay->last_flip, NULL); 476 477 return 0; 478 } 479 480 void intel_overlay_reset(struct drm_i915_private *dev_priv) 481 { 482 struct intel_overlay *overlay = dev_priv->overlay; 483 484 if (!overlay) 485 return; 486 487 overlay->old_xscale = 0; 488 overlay->old_yscale = 0; 489 overlay->crtc = NULL; 490 overlay->active = false; 491 } 492 493 static int packed_depth_bytes(u32 format) 494 { 495 switch (format & I915_OVERLAY_DEPTH_MASK) { 496 case I915_OVERLAY_YUV422: 497 return 4; 498 case I915_OVERLAY_YUV411: 499 /* return 6; not implemented */ 500 default: 501 return -EINVAL; 502 } 503 } 504 505 static int packed_width_bytes(u32 format, short width) 506 { 507 switch (format & I915_OVERLAY_DEPTH_MASK) { 508 case I915_OVERLAY_YUV422: 509 return width << 1; 510 default: 511 return -EINVAL; 512 } 513 } 514 515 static int uv_hsubsampling(u32 format) 516 { 517 switch (format & I915_OVERLAY_DEPTH_MASK) { 518 case I915_OVERLAY_YUV422: 519 case I915_OVERLAY_YUV420: 520 return 2; 521 case I915_OVERLAY_YUV411: 522 case I915_OVERLAY_YUV410: 523 return 4; 524 default: 525 return -EINVAL; 526 } 527 } 528 529 static int uv_vsubsampling(u32 format) 530 { 531 switch (format & I915_OVERLAY_DEPTH_MASK) { 532 case I915_OVERLAY_YUV420: 533 case I915_OVERLAY_YUV410: 534 return 2; 535 case I915_OVERLAY_YUV422: 536 case I915_OVERLAY_YUV411: 537 return 1; 538 default: 539 return -EINVAL; 540 } 541 } 542 543 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) 544 { 545 u32 sw; 546 547 if (IS_GEN(dev_priv, 2)) 548 sw = ALIGN((offset & 31) + width, 32); 549 else 550 sw = ALIGN((offset & 63) + width, 64); 551 552 if (sw == 0) 553 return 0; 554 555 return (sw - 32) >> 3; 556 } 557 558 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 559 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 560 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 561 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 562 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 563 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 564 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 565 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 566 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 567 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 568 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 569 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 570 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 571 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 572 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 573 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 574 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 575 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 576 }; 577 578 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 579 [ 0] = { 0x3000, 0x1800, 0x1800, }, 580 [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 581 [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 582 [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 583 [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 584 [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 585 [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 586 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 587 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 588 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 589 [10] = { 0xb100, 0x1eb8, 0x3620, }, 590 [11] = { 0xb100, 0x1f18, 0x34a0, }, 591 [12] = { 0xb100, 0x1f68, 0x3360, }, 592 [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 593 [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 594 [15] = { 0xb060, 0x1ff0, 0x30a0, }, 595 [16] = { 0x3000, 0x0800, 0x3000, }, 596 }; 597 598 static void update_polyphase_filter(struct overlay_registers __iomem *regs) 599 { 600 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 601 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 602 sizeof(uv_static_hcoeffs)); 603 } 604 605 static bool update_scaling_factors(struct intel_overlay *overlay, 606 struct overlay_registers __iomem *regs, 607 struct drm_intel_overlay_put_image *params) 608 { 609 /* fixed point with a 12 bit shift */ 610 u32 xscale, yscale, xscale_UV, yscale_UV; 611 #define FP_SHIFT 12 612 #define FRACT_MASK 0xfff 613 bool scale_changed = false; 614 int uv_hscale = uv_hsubsampling(params->flags); 615 int uv_vscale = uv_vsubsampling(params->flags); 616 617 if (params->dst_width > 1) 618 xscale = ((params->src_scan_width - 1) << FP_SHIFT) / 619 params->dst_width; 620 else 621 xscale = 1 << FP_SHIFT; 622 623 if (params->dst_height > 1) 624 yscale = ((params->src_scan_height - 1) << FP_SHIFT) / 625 params->dst_height; 626 else 627 yscale = 1 << FP_SHIFT; 628 629 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 630 xscale_UV = xscale/uv_hscale; 631 yscale_UV = yscale/uv_vscale; 632 /* make the Y scale to UV scale ratio an exact multiply */ 633 xscale = xscale_UV * uv_hscale; 634 yscale = yscale_UV * uv_vscale; 635 /*} else { 636 xscale_UV = 0; 637 yscale_UV = 0; 638 }*/ 639 640 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 641 scale_changed = true; 642 overlay->old_xscale = xscale; 643 overlay->old_yscale = yscale; 644 645 iowrite32(((yscale & FRACT_MASK) << 20) | 646 ((xscale >> FP_SHIFT) << 16) | 647 ((xscale & FRACT_MASK) << 3), 648 ®s->YRGBSCALE); 649 650 iowrite32(((yscale_UV & FRACT_MASK) << 20) | 651 ((xscale_UV >> FP_SHIFT) << 16) | 652 ((xscale_UV & FRACT_MASK) << 3), 653 ®s->UVSCALE); 654 655 iowrite32((((yscale >> FP_SHIFT) << 16) | 656 ((yscale_UV >> FP_SHIFT) << 0)), 657 ®s->UVSCALEV); 658 659 if (scale_changed) 660 update_polyphase_filter(regs); 661 662 return scale_changed; 663 } 664 665 static void update_colorkey(struct intel_overlay *overlay, 666 struct overlay_registers __iomem *regs) 667 { 668 const struct intel_plane_state *state = 669 to_intel_plane_state(overlay->crtc->base.primary->state); 670 u32 key = overlay->color_key; 671 u32 format = 0; 672 u32 flags = 0; 673 674 if (overlay->color_key_enabled) 675 flags |= DST_KEY_ENABLE; 676 677 if (state->base.visible) 678 format = state->base.fb->format->format; 679 680 switch (format) { 681 case DRM_FORMAT_C8: 682 key = 0; 683 flags |= CLK_RGB8I_MASK; 684 break; 685 case DRM_FORMAT_XRGB1555: 686 key = RGB15_TO_COLORKEY(key); 687 flags |= CLK_RGB15_MASK; 688 break; 689 case DRM_FORMAT_RGB565: 690 key = RGB16_TO_COLORKEY(key); 691 flags |= CLK_RGB16_MASK; 692 break; 693 default: 694 flags |= CLK_RGB24_MASK; 695 break; 696 } 697 698 iowrite32(key, ®s->DCLRKV); 699 iowrite32(flags, ®s->DCLRKM); 700 } 701 702 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) 703 { 704 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 705 706 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 707 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 708 case I915_OVERLAY_YUV422: 709 cmd |= OCMD_YUV_422_PLANAR; 710 break; 711 case I915_OVERLAY_YUV420: 712 cmd |= OCMD_YUV_420_PLANAR; 713 break; 714 case I915_OVERLAY_YUV411: 715 case I915_OVERLAY_YUV410: 716 cmd |= OCMD_YUV_410_PLANAR; 717 break; 718 } 719 } else { /* YUV packed */ 720 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 721 case I915_OVERLAY_YUV422: 722 cmd |= OCMD_YUV_422_PACKED; 723 break; 724 case I915_OVERLAY_YUV411: 725 cmd |= OCMD_YUV_411_PACKED; 726 break; 727 } 728 729 switch (params->flags & I915_OVERLAY_SWAP_MASK) { 730 case I915_OVERLAY_NO_SWAP: 731 break; 732 case I915_OVERLAY_UV_SWAP: 733 cmd |= OCMD_UV_SWAP; 734 break; 735 case I915_OVERLAY_Y_SWAP: 736 cmd |= OCMD_Y_SWAP; 737 break; 738 case I915_OVERLAY_Y_AND_UV_SWAP: 739 cmd |= OCMD_Y_AND_UV_SWAP; 740 break; 741 } 742 } 743 744 return cmd; 745 } 746 747 static int intel_overlay_do_put_image(struct intel_overlay *overlay, 748 struct drm_i915_gem_object *new_bo, 749 struct drm_intel_overlay_put_image *params) 750 { 751 struct overlay_registers __iomem *regs = overlay->regs; 752 struct drm_i915_private *dev_priv = overlay->i915; 753 u32 swidth, swidthsw, sheight, ostride; 754 enum pipe pipe = overlay->crtc->pipe; 755 bool scale_changed = false; 756 struct i915_vma *vma; 757 int ret, tmp_width; 758 759 lockdep_assert_held(&dev_priv->drm.struct_mutex); 760 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 761 762 ret = intel_overlay_release_old_vid(overlay); 763 if (ret != 0) 764 return ret; 765 766 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 767 768 i915_gem_object_lock(new_bo); 769 vma = i915_gem_object_pin_to_display_plane(new_bo, 770 0, NULL, PIN_MAPPABLE); 771 i915_gem_object_unlock(new_bo); 772 if (IS_ERR(vma)) { 773 ret = PTR_ERR(vma); 774 goto out_pin_section; 775 } 776 intel_fb_obj_flush(new_bo, ORIGIN_DIRTYFB); 777 778 ret = i915_vma_put_fence(vma); 779 if (ret) 780 goto out_unpin; 781 782 if (!overlay->active) { 783 u32 oconfig; 784 785 oconfig = OCONF_CC_OUT_8BIT; 786 if (IS_GEN(dev_priv, 4)) 787 oconfig |= OCONF_CSC_MODE_BT709; 788 oconfig |= pipe == 0 ? 789 OCONF_PIPE_A : OCONF_PIPE_B; 790 iowrite32(oconfig, ®s->OCONFIG); 791 792 ret = intel_overlay_on(overlay); 793 if (ret != 0) 794 goto out_unpin; 795 } 796 797 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS); 798 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ); 799 800 if (params->flags & I915_OVERLAY_YUV_PACKED) 801 tmp_width = packed_width_bytes(params->flags, 802 params->src_width); 803 else 804 tmp_width = params->src_width; 805 806 swidth = params->src_width; 807 swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width); 808 sheight = params->src_height; 809 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); 810 ostride = params->stride_Y; 811 812 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 813 int uv_hscale = uv_hsubsampling(params->flags); 814 int uv_vscale = uv_vsubsampling(params->flags); 815 u32 tmp_U, tmp_V; 816 817 swidth |= (params->src_width / uv_hscale) << 16; 818 sheight |= (params->src_height / uv_vscale) << 16; 819 820 tmp_U = calc_swidthsw(dev_priv, params->offset_U, 821 params->src_width / uv_hscale); 822 tmp_V = calc_swidthsw(dev_priv, params->offset_V, 823 params->src_width / uv_hscale); 824 swidthsw |= max(tmp_U, tmp_V) << 16; 825 826 iowrite32(i915_ggtt_offset(vma) + params->offset_U, 827 ®s->OBUF_0U); 828 iowrite32(i915_ggtt_offset(vma) + params->offset_V, 829 ®s->OBUF_0V); 830 831 ostride |= params->stride_UV << 16; 832 } 833 834 iowrite32(swidth, ®s->SWIDTH); 835 iowrite32(swidthsw, ®s->SWIDTHSW); 836 iowrite32(sheight, ®s->SHEIGHT); 837 iowrite32(ostride, ®s->OSTRIDE); 838 839 scale_changed = update_scaling_factors(overlay, regs, params); 840 841 update_colorkey(overlay, regs); 842 843 iowrite32(overlay_cmd_reg(params), ®s->OCMD); 844 845 ret = intel_overlay_continue(overlay, vma, scale_changed); 846 if (ret) 847 goto out_unpin; 848 849 return 0; 850 851 out_unpin: 852 i915_gem_object_unpin_from_display_plane(vma); 853 out_pin_section: 854 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 855 856 return ret; 857 } 858 859 int intel_overlay_switch_off(struct intel_overlay *overlay) 860 { 861 struct drm_i915_private *dev_priv = overlay->i915; 862 int ret; 863 864 lockdep_assert_held(&dev_priv->drm.struct_mutex); 865 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 866 867 ret = intel_overlay_recover_from_interrupt(overlay); 868 if (ret != 0) 869 return ret; 870 871 if (!overlay->active) 872 return 0; 873 874 ret = intel_overlay_release_old_vid(overlay); 875 if (ret != 0) 876 return ret; 877 878 iowrite32(0, &overlay->regs->OCMD); 879 880 return intel_overlay_off(overlay); 881 } 882 883 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 884 struct intel_crtc *crtc) 885 { 886 if (!crtc->active) 887 return -EINVAL; 888 889 /* can't use the overlay with double wide pipe */ 890 if (crtc->config->double_wide) 891 return -EINVAL; 892 893 return 0; 894 } 895 896 static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 897 { 898 struct drm_i915_private *dev_priv = overlay->i915; 899 u32 pfit_control = I915_READ(PFIT_CONTROL); 900 u32 ratio; 901 902 /* XXX: This is not the same logic as in the xorg driver, but more in 903 * line with the intel documentation for the i965 904 */ 905 if (INTEL_GEN(dev_priv) >= 4) { 906 /* on i965 use the PGM reg to read out the autoscaler values */ 907 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; 908 } else { 909 if (pfit_control & VERT_AUTO_SCALE) 910 ratio = I915_READ(PFIT_AUTO_RATIOS); 911 else 912 ratio = I915_READ(PFIT_PGM_RATIOS); 913 ratio >>= PFIT_VERT_SCALE_SHIFT; 914 } 915 916 overlay->pfit_vscale_ratio = ratio; 917 } 918 919 static int check_overlay_dst(struct intel_overlay *overlay, 920 struct drm_intel_overlay_put_image *rec) 921 { 922 const struct intel_crtc_state *pipe_config = 923 overlay->crtc->config; 924 925 if (rec->dst_x < pipe_config->pipe_src_w && 926 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && 927 rec->dst_y < pipe_config->pipe_src_h && 928 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) 929 return 0; 930 else 931 return -EINVAL; 932 } 933 934 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) 935 { 936 u32 tmp; 937 938 /* downscaling limit is 8.0 */ 939 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16; 940 if (tmp > 7) 941 return -EINVAL; 942 943 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16; 944 if (tmp > 7) 945 return -EINVAL; 946 947 return 0; 948 } 949 950 static int check_overlay_src(struct drm_i915_private *dev_priv, 951 struct drm_intel_overlay_put_image *rec, 952 struct drm_i915_gem_object *new_bo) 953 { 954 int uv_hscale = uv_hsubsampling(rec->flags); 955 int uv_vscale = uv_vsubsampling(rec->flags); 956 u32 stride_mask; 957 int depth; 958 u32 tmp; 959 960 /* check src dimensions */ 961 if (IS_I845G(dev_priv) || IS_I830(dev_priv)) { 962 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 963 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 964 return -EINVAL; 965 } else { 966 if (rec->src_height > IMAGE_MAX_HEIGHT || 967 rec->src_width > IMAGE_MAX_WIDTH) 968 return -EINVAL; 969 } 970 971 /* better safe than sorry, use 4 as the maximal subsampling ratio */ 972 if (rec->src_height < N_VERT_Y_TAPS*4 || 973 rec->src_width < N_HORIZ_Y_TAPS*4) 974 return -EINVAL; 975 976 /* check alignment constraints */ 977 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 978 case I915_OVERLAY_RGB: 979 /* not implemented */ 980 return -EINVAL; 981 982 case I915_OVERLAY_YUV_PACKED: 983 if (uv_vscale != 1) 984 return -EINVAL; 985 986 depth = packed_depth_bytes(rec->flags); 987 if (depth < 0) 988 return depth; 989 990 /* ignore UV planes */ 991 rec->stride_UV = 0; 992 rec->offset_U = 0; 993 rec->offset_V = 0; 994 /* check pixel alignment */ 995 if (rec->offset_Y % depth) 996 return -EINVAL; 997 break; 998 999 case I915_OVERLAY_YUV_PLANAR: 1000 if (uv_vscale < 0 || uv_hscale < 0) 1001 return -EINVAL; 1002 /* no offset restrictions for planar formats */ 1003 break; 1004 1005 default: 1006 return -EINVAL; 1007 } 1008 1009 if (rec->src_width % uv_hscale) 1010 return -EINVAL; 1011 1012 /* stride checking */ 1013 if (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1014 stride_mask = 255; 1015 else 1016 stride_mask = 63; 1017 1018 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1019 return -EINVAL; 1020 if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512) 1021 return -EINVAL; 1022 1023 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1024 4096 : 8192; 1025 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 1026 return -EINVAL; 1027 1028 /* check buffer dimensions */ 1029 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1030 case I915_OVERLAY_RGB: 1031 case I915_OVERLAY_YUV_PACKED: 1032 /* always 4 Y values per depth pixels */ 1033 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 1034 return -EINVAL; 1035 1036 tmp = rec->stride_Y*rec->src_height; 1037 if (rec->offset_Y + tmp > new_bo->base.size) 1038 return -EINVAL; 1039 break; 1040 1041 case I915_OVERLAY_YUV_PLANAR: 1042 if (rec->src_width > rec->stride_Y) 1043 return -EINVAL; 1044 if (rec->src_width/uv_hscale > rec->stride_UV) 1045 return -EINVAL; 1046 1047 tmp = rec->stride_Y * rec->src_height; 1048 if (rec->offset_Y + tmp > new_bo->base.size) 1049 return -EINVAL; 1050 1051 tmp = rec->stride_UV * (rec->src_height / uv_vscale); 1052 if (rec->offset_U + tmp > new_bo->base.size || 1053 rec->offset_V + tmp > new_bo->base.size) 1054 return -EINVAL; 1055 break; 1056 } 1057 1058 return 0; 1059 } 1060 1061 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1062 struct drm_file *file_priv) 1063 { 1064 struct drm_intel_overlay_put_image *params = data; 1065 struct drm_i915_private *dev_priv = to_i915(dev); 1066 struct intel_overlay *overlay; 1067 struct drm_crtc *drmmode_crtc; 1068 struct intel_crtc *crtc; 1069 struct drm_i915_gem_object *new_bo; 1070 int ret; 1071 1072 overlay = dev_priv->overlay; 1073 if (!overlay) { 1074 DRM_DEBUG("userspace bug: no overlay\n"); 1075 return -ENODEV; 1076 } 1077 1078 if (!(params->flags & I915_OVERLAY_ENABLE)) { 1079 drm_modeset_lock_all(dev); 1080 mutex_lock(&dev->struct_mutex); 1081 1082 ret = intel_overlay_switch_off(overlay); 1083 1084 mutex_unlock(&dev->struct_mutex); 1085 drm_modeset_unlock_all(dev); 1086 1087 return ret; 1088 } 1089 1090 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id); 1091 if (!drmmode_crtc) 1092 return -ENOENT; 1093 crtc = to_intel_crtc(drmmode_crtc); 1094 1095 new_bo = i915_gem_object_lookup(file_priv, params->bo_handle); 1096 if (!new_bo) 1097 return -ENOENT; 1098 1099 drm_modeset_lock_all(dev); 1100 mutex_lock(&dev->struct_mutex); 1101 1102 if (i915_gem_object_is_tiled(new_bo)) { 1103 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n"); 1104 ret = -EINVAL; 1105 goto out_unlock; 1106 } 1107 1108 ret = intel_overlay_recover_from_interrupt(overlay); 1109 if (ret != 0) 1110 goto out_unlock; 1111 1112 if (overlay->crtc != crtc) { 1113 ret = intel_overlay_switch_off(overlay); 1114 if (ret != 0) 1115 goto out_unlock; 1116 1117 ret = check_overlay_possible_on_crtc(overlay, crtc); 1118 if (ret != 0) 1119 goto out_unlock; 1120 1121 overlay->crtc = crtc; 1122 crtc->overlay = overlay; 1123 1124 /* line too wide, i.e. one-line-mode */ 1125 if (crtc->config->pipe_src_w > 1024 && 1126 crtc->config->gmch_pfit.control & PFIT_ENABLE) { 1127 overlay->pfit_active = true; 1128 update_pfit_vscale_ratio(overlay); 1129 } else 1130 overlay->pfit_active = false; 1131 } 1132 1133 ret = check_overlay_dst(overlay, params); 1134 if (ret != 0) 1135 goto out_unlock; 1136 1137 if (overlay->pfit_active) { 1138 params->dst_y = (((u32)params->dst_y << 12) / 1139 overlay->pfit_vscale_ratio); 1140 /* shifting right rounds downwards, so add 1 */ 1141 params->dst_height = (((u32)params->dst_height << 12) / 1142 overlay->pfit_vscale_ratio) + 1; 1143 } 1144 1145 if (params->src_scan_height > params->src_height || 1146 params->src_scan_width > params->src_width) { 1147 ret = -EINVAL; 1148 goto out_unlock; 1149 } 1150 1151 ret = check_overlay_src(dev_priv, params, new_bo); 1152 if (ret != 0) 1153 goto out_unlock; 1154 1155 /* Check scaling after src size to prevent a divide-by-zero. */ 1156 ret = check_overlay_scaling(params); 1157 if (ret != 0) 1158 goto out_unlock; 1159 1160 ret = intel_overlay_do_put_image(overlay, new_bo, params); 1161 if (ret != 0) 1162 goto out_unlock; 1163 1164 mutex_unlock(&dev->struct_mutex); 1165 drm_modeset_unlock_all(dev); 1166 i915_gem_object_put(new_bo); 1167 1168 return 0; 1169 1170 out_unlock: 1171 mutex_unlock(&dev->struct_mutex); 1172 drm_modeset_unlock_all(dev); 1173 i915_gem_object_put(new_bo); 1174 1175 return ret; 1176 } 1177 1178 static void update_reg_attrs(struct intel_overlay *overlay, 1179 struct overlay_registers __iomem *regs) 1180 { 1181 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 1182 ®s->OCLRC0); 1183 iowrite32(overlay->saturation, ®s->OCLRC1); 1184 } 1185 1186 static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 1187 { 1188 int i; 1189 1190 if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 1191 return false; 1192 1193 for (i = 0; i < 3; i++) { 1194 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 1195 return false; 1196 } 1197 1198 return true; 1199 } 1200 1201 static bool check_gamma5_errata(u32 gamma5) 1202 { 1203 int i; 1204 1205 for (i = 0; i < 3; i++) { 1206 if (((gamma5 >> i*8) & 0xff) == 0x80) 1207 return false; 1208 } 1209 1210 return true; 1211 } 1212 1213 static int check_gamma(struct drm_intel_overlay_attrs *attrs) 1214 { 1215 if (!check_gamma_bounds(0, attrs->gamma0) || 1216 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 1217 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 1218 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 1219 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 1220 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 1221 !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 1222 return -EINVAL; 1223 1224 if (!check_gamma5_errata(attrs->gamma5)) 1225 return -EINVAL; 1226 1227 return 0; 1228 } 1229 1230 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1231 struct drm_file *file_priv) 1232 { 1233 struct drm_intel_overlay_attrs *attrs = data; 1234 struct drm_i915_private *dev_priv = to_i915(dev); 1235 struct intel_overlay *overlay; 1236 int ret; 1237 1238 overlay = dev_priv->overlay; 1239 if (!overlay) { 1240 DRM_DEBUG("userspace bug: no overlay\n"); 1241 return -ENODEV; 1242 } 1243 1244 drm_modeset_lock_all(dev); 1245 mutex_lock(&dev->struct_mutex); 1246 1247 ret = -EINVAL; 1248 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 1249 attrs->color_key = overlay->color_key; 1250 attrs->brightness = overlay->brightness; 1251 attrs->contrast = overlay->contrast; 1252 attrs->saturation = overlay->saturation; 1253 1254 if (!IS_GEN(dev_priv, 2)) { 1255 attrs->gamma0 = I915_READ(OGAMC0); 1256 attrs->gamma1 = I915_READ(OGAMC1); 1257 attrs->gamma2 = I915_READ(OGAMC2); 1258 attrs->gamma3 = I915_READ(OGAMC3); 1259 attrs->gamma4 = I915_READ(OGAMC4); 1260 attrs->gamma5 = I915_READ(OGAMC5); 1261 } 1262 } else { 1263 if (attrs->brightness < -128 || attrs->brightness > 127) 1264 goto out_unlock; 1265 if (attrs->contrast > 255) 1266 goto out_unlock; 1267 if (attrs->saturation > 1023) 1268 goto out_unlock; 1269 1270 overlay->color_key = attrs->color_key; 1271 overlay->brightness = attrs->brightness; 1272 overlay->contrast = attrs->contrast; 1273 overlay->saturation = attrs->saturation; 1274 1275 update_reg_attrs(overlay, overlay->regs); 1276 1277 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1278 if (IS_GEN(dev_priv, 2)) 1279 goto out_unlock; 1280 1281 if (overlay->active) { 1282 ret = -EBUSY; 1283 goto out_unlock; 1284 } 1285 1286 ret = check_gamma(attrs); 1287 if (ret) 1288 goto out_unlock; 1289 1290 I915_WRITE(OGAMC0, attrs->gamma0); 1291 I915_WRITE(OGAMC1, attrs->gamma1); 1292 I915_WRITE(OGAMC2, attrs->gamma2); 1293 I915_WRITE(OGAMC3, attrs->gamma3); 1294 I915_WRITE(OGAMC4, attrs->gamma4); 1295 I915_WRITE(OGAMC5, attrs->gamma5); 1296 } 1297 } 1298 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1299 1300 ret = 0; 1301 out_unlock: 1302 mutex_unlock(&dev->struct_mutex); 1303 drm_modeset_unlock_all(dev); 1304 1305 return ret; 1306 } 1307 1308 static int get_registers(struct intel_overlay *overlay, bool use_phys) 1309 { 1310 struct drm_i915_private *i915 = overlay->i915; 1311 struct drm_i915_gem_object *obj; 1312 struct i915_vma *vma; 1313 int err; 1314 1315 mutex_lock(&i915->drm.struct_mutex); 1316 1317 obj = i915_gem_object_create_stolen(i915, PAGE_SIZE); 1318 if (obj == NULL) 1319 obj = i915_gem_object_create_internal(i915, PAGE_SIZE); 1320 if (IS_ERR(obj)) { 1321 err = PTR_ERR(obj); 1322 goto err_unlock; 1323 } 1324 1325 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); 1326 if (IS_ERR(vma)) { 1327 err = PTR_ERR(vma); 1328 goto err_put_bo; 1329 } 1330 1331 if (use_phys) 1332 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl); 1333 else 1334 overlay->flip_addr = i915_ggtt_offset(vma); 1335 overlay->regs = i915_vma_pin_iomap(vma); 1336 i915_vma_unpin(vma); 1337 1338 if (IS_ERR(overlay->regs)) { 1339 err = PTR_ERR(overlay->regs); 1340 goto err_put_bo; 1341 } 1342 1343 overlay->reg_bo = obj; 1344 mutex_unlock(&i915->drm.struct_mutex); 1345 return 0; 1346 1347 err_put_bo: 1348 i915_gem_object_put(obj); 1349 err_unlock: 1350 mutex_unlock(&i915->drm.struct_mutex); 1351 return err; 1352 } 1353 1354 void intel_overlay_setup(struct drm_i915_private *dev_priv) 1355 { 1356 struct intel_overlay *overlay; 1357 int ret; 1358 1359 if (!HAS_OVERLAY(dev_priv)) 1360 return; 1361 1362 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 1363 if (!overlay) 1364 return; 1365 1366 overlay->i915 = dev_priv; 1367 1368 overlay->color_key = 0x0101fe; 1369 overlay->color_key_enabled = true; 1370 overlay->brightness = -19; 1371 overlay->contrast = 75; 1372 overlay->saturation = 146; 1373 1374 INIT_ACTIVE_REQUEST(&overlay->last_flip); 1375 1376 ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv)); 1377 if (ret) 1378 goto out_free; 1379 1380 memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1381 update_polyphase_filter(overlay->regs); 1382 update_reg_attrs(overlay, overlay->regs); 1383 1384 dev_priv->overlay = overlay; 1385 DRM_INFO("Initialized overlay support.\n"); 1386 return; 1387 1388 out_free: 1389 kfree(overlay); 1390 } 1391 1392 void intel_overlay_cleanup(struct drm_i915_private *dev_priv) 1393 { 1394 struct intel_overlay *overlay; 1395 1396 overlay = fetch_and_zero(&dev_priv->overlay); 1397 if (!overlay) 1398 return; 1399 1400 /* 1401 * The bo's should be free'd by the generic code already. 1402 * Furthermore modesetting teardown happens beforehand so the 1403 * hardware should be off already. 1404 */ 1405 WARN_ON(overlay->active); 1406 1407 i915_gem_object_put(overlay->reg_bo); 1408 1409 kfree(overlay); 1410 } 1411 1412 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1413 1414 struct intel_overlay_error_state { 1415 struct overlay_registers regs; 1416 unsigned long base; 1417 u32 dovsta; 1418 u32 isr; 1419 }; 1420 1421 struct intel_overlay_error_state * 1422 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) 1423 { 1424 struct intel_overlay *overlay = dev_priv->overlay; 1425 struct intel_overlay_error_state *error; 1426 1427 if (!overlay || !overlay->active) 1428 return NULL; 1429 1430 error = kmalloc(sizeof(*error), GFP_ATOMIC); 1431 if (error == NULL) 1432 return NULL; 1433 1434 error->dovsta = I915_READ(DOVSTA); 1435 error->isr = I915_READ(GEN2_ISR); 1436 error->base = overlay->flip_addr; 1437 1438 memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs)); 1439 1440 return error; 1441 } 1442 1443 void 1444 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m, 1445 struct intel_overlay_error_state *error) 1446 { 1447 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1448 error->dovsta, error->isr); 1449 i915_error_printf(m, " Register file at 0x%08lx:\n", 1450 error->base); 1451 1452 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) 1453 P(OBUF_0Y); 1454 P(OBUF_1Y); 1455 P(OBUF_0U); 1456 P(OBUF_0V); 1457 P(OBUF_1U); 1458 P(OBUF_1V); 1459 P(OSTRIDE); 1460 P(YRGB_VPH); 1461 P(UV_VPH); 1462 P(HORZ_PH); 1463 P(INIT_PHS); 1464 P(DWINPOS); 1465 P(DWINSZ); 1466 P(SWIDTH); 1467 P(SWIDTHSW); 1468 P(SHEIGHT); 1469 P(YRGBSCALE); 1470 P(UVSCALE); 1471 P(OCLRC0); 1472 P(OCLRC1); 1473 P(DCLRKV); 1474 P(DCLRKM); 1475 P(SCLRKVH); 1476 P(SCLRKVL); 1477 P(SCLRKEN); 1478 P(OCONFIG); 1479 P(OCMD); 1480 P(OSTART_0Y); 1481 P(OSTART_1Y); 1482 P(OSTART_0U); 1483 P(OSTART_0V); 1484 P(OSTART_1U); 1485 P(OSTART_1V); 1486 P(OTILEOFF_0Y); 1487 P(OTILEOFF_1Y); 1488 P(OTILEOFF_0U); 1489 P(OTILEOFF_0V); 1490 P(OTILEOFF_1U); 1491 P(OTILEOFF_1V); 1492 P(FASTHSCALE); 1493 P(UVSCALEV); 1494 #undef P 1495 } 1496 1497 #endif 1498