1 /* 2 * Copyright © 2009 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel@ffwll.ch> 25 * 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27 */ 28 29 #include <drm/drm_fourcc.h> 30 #include <drm/i915_drm.h> 31 32 #include "gem/i915_gem_pm.h" 33 34 #include "i915_drv.h" 35 #include "i915_reg.h" 36 #include "intel_drv.h" 37 #include "intel_frontbuffer.h" 38 #include "intel_overlay.h" 39 40 /* Limits for overlay size. According to intel doc, the real limits are: 41 * Y width: 4095, UV width (planar): 2047, Y height: 2047, 42 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 43 * the mininum of both. */ 44 #define IMAGE_MAX_WIDTH 2048 45 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 46 /* on 830 and 845 these large limits result in the card hanging */ 47 #define IMAGE_MAX_WIDTH_LEGACY 1024 48 #define IMAGE_MAX_HEIGHT_LEGACY 1088 49 50 /* overlay register definitions */ 51 /* OCMD register */ 52 #define OCMD_TILED_SURFACE (0x1<<19) 53 #define OCMD_MIRROR_MASK (0x3<<17) 54 #define OCMD_MIRROR_MODE (0x3<<17) 55 #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 56 #define OCMD_MIRROR_VERTICAL (0x2<<17) 57 #define OCMD_MIRROR_BOTH (0x3<<17) 58 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 59 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 60 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 61 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 62 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 63 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 64 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 65 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 66 #define OCMD_YUV_422_PACKED (0x8<<10) 67 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 68 #define OCMD_YUV_420_PLANAR (0xc<<10) 69 #define OCMD_YUV_422_PLANAR (0xd<<10) 70 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 71 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 72 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 73 #define OCMD_BUF_TYPE_MASK (0x1<<5) 74 #define OCMD_BUF_TYPE_FRAME (0x0<<5) 75 #define OCMD_BUF_TYPE_FIELD (0x1<<5) 76 #define OCMD_TEST_MODE (0x1<<4) 77 #define OCMD_BUFFER_SELECT (0x3<<2) 78 #define OCMD_BUFFER0 (0x0<<2) 79 #define OCMD_BUFFER1 (0x1<<2) 80 #define OCMD_FIELD_SELECT (0x1<<2) 81 #define OCMD_FIELD0 (0x0<<1) 82 #define OCMD_FIELD1 (0x1<<1) 83 #define OCMD_ENABLE (0x1<<0) 84 85 /* OCONFIG register */ 86 #define OCONF_PIPE_MASK (0x1<<18) 87 #define OCONF_PIPE_A (0x0<<18) 88 #define OCONF_PIPE_B (0x1<<18) 89 #define OCONF_GAMMA2_ENABLE (0x1<<16) 90 #define OCONF_CSC_MODE_BT601 (0x0<<5) 91 #define OCONF_CSC_MODE_BT709 (0x1<<5) 92 #define OCONF_CSC_BYPASS (0x1<<4) 93 #define OCONF_CC_OUT_8BIT (0x1<<3) 94 #define OCONF_TEST_MODE (0x1<<2) 95 #define OCONF_THREE_LINE_BUFFER (0x1<<0) 96 #define OCONF_TWO_LINE_BUFFER (0x0<<0) 97 98 /* DCLRKM (dst-key) register */ 99 #define DST_KEY_ENABLE (0x1<<31) 100 #define CLK_RGB24_MASK 0x0 101 #define CLK_RGB16_MASK 0x070307 102 #define CLK_RGB15_MASK 0x070707 103 #define CLK_RGB8I_MASK 0xffffff 104 105 #define RGB16_TO_COLORKEY(c) \ 106 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3)) 107 #define RGB15_TO_COLORKEY(c) \ 108 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3)) 109 110 /* overlay flip addr flag */ 111 #define OFC_UPDATE 0x1 112 113 /* polyphase filter coefficients */ 114 #define N_HORIZ_Y_TAPS 5 115 #define N_VERT_Y_TAPS 3 116 #define N_HORIZ_UV_TAPS 3 117 #define N_VERT_UV_TAPS 3 118 #define N_PHASES 17 119 #define MAX_TAPS 5 120 121 /* memory bufferd overlay registers */ 122 struct overlay_registers { 123 u32 OBUF_0Y; 124 u32 OBUF_1Y; 125 u32 OBUF_0U; 126 u32 OBUF_0V; 127 u32 OBUF_1U; 128 u32 OBUF_1V; 129 u32 OSTRIDE; 130 u32 YRGB_VPH; 131 u32 UV_VPH; 132 u32 HORZ_PH; 133 u32 INIT_PHS; 134 u32 DWINPOS; 135 u32 DWINSZ; 136 u32 SWIDTH; 137 u32 SWIDTHSW; 138 u32 SHEIGHT; 139 u32 YRGBSCALE; 140 u32 UVSCALE; 141 u32 OCLRC0; 142 u32 OCLRC1; 143 u32 DCLRKV; 144 u32 DCLRKM; 145 u32 SCLRKVH; 146 u32 SCLRKVL; 147 u32 SCLRKEN; 148 u32 OCONFIG; 149 u32 OCMD; 150 u32 RESERVED1; /* 0x6C */ 151 u32 OSTART_0Y; 152 u32 OSTART_1Y; 153 u32 OSTART_0U; 154 u32 OSTART_0V; 155 u32 OSTART_1U; 156 u32 OSTART_1V; 157 u32 OTILEOFF_0Y; 158 u32 OTILEOFF_1Y; 159 u32 OTILEOFF_0U; 160 u32 OTILEOFF_0V; 161 u32 OTILEOFF_1U; 162 u32 OTILEOFF_1V; 163 u32 FASTHSCALE; /* 0xA0 */ 164 u32 UVSCALEV; /* 0xA4 */ 165 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 166 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 167 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 168 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 169 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 170 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 171 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 172 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 173 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 174 }; 175 176 struct intel_overlay { 177 struct drm_i915_private *i915; 178 struct intel_context *context; 179 struct intel_crtc *crtc; 180 struct i915_vma *vma; 181 struct i915_vma *old_vma; 182 bool active; 183 bool pfit_active; 184 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 185 u32 color_key:24; 186 u32 color_key_enabled:1; 187 u32 brightness, contrast, saturation; 188 u32 old_xscale, old_yscale; 189 /* register access */ 190 struct drm_i915_gem_object *reg_bo; 191 struct overlay_registers __iomem *regs; 192 u32 flip_addr; 193 /* flip handling */ 194 struct i915_active_request last_flip; 195 }; 196 197 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, 198 bool enable) 199 { 200 struct pci_dev *pdev = dev_priv->drm.pdev; 201 u8 val; 202 203 /* WA_OVERLAY_CLKGATE:alm */ 204 if (enable) 205 I915_WRITE(DSPCLK_GATE_D, 0); 206 else 207 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 208 209 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 210 pci_bus_read_config_byte(pdev->bus, 211 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); 212 if (enable) 213 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; 214 else 215 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 216 pci_bus_write_config_byte(pdev->bus, 217 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 218 } 219 220 static void intel_overlay_submit_request(struct intel_overlay *overlay, 221 struct i915_request *rq, 222 i915_active_retire_fn retire) 223 { 224 GEM_BUG_ON(i915_active_request_peek(&overlay->last_flip, 225 &overlay->i915->drm.struct_mutex)); 226 i915_active_request_set_retire_fn(&overlay->last_flip, retire, 227 &overlay->i915->drm.struct_mutex); 228 __i915_active_request_set(&overlay->last_flip, rq); 229 i915_request_add(rq); 230 } 231 232 static int intel_overlay_do_wait_request(struct intel_overlay *overlay, 233 struct i915_request *rq, 234 i915_active_retire_fn retire) 235 { 236 intel_overlay_submit_request(overlay, rq, retire); 237 return i915_active_request_retire(&overlay->last_flip, 238 &overlay->i915->drm.struct_mutex); 239 } 240 241 static struct i915_request *alloc_request(struct intel_overlay *overlay) 242 { 243 return i915_request_create(overlay->context); 244 } 245 246 /* overlay needs to be disable in OCMD reg */ 247 static int intel_overlay_on(struct intel_overlay *overlay) 248 { 249 struct drm_i915_private *dev_priv = overlay->i915; 250 struct i915_request *rq; 251 u32 *cs; 252 253 WARN_ON(overlay->active); 254 255 rq = alloc_request(overlay); 256 if (IS_ERR(rq)) 257 return PTR_ERR(rq); 258 259 cs = intel_ring_begin(rq, 4); 260 if (IS_ERR(cs)) { 261 i915_request_add(rq); 262 return PTR_ERR(cs); 263 } 264 265 overlay->active = true; 266 267 if (IS_I830(dev_priv)) 268 i830_overlay_clock_gating(dev_priv, false); 269 270 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 271 *cs++ = overlay->flip_addr | OFC_UPDATE; 272 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 273 *cs++ = MI_NOOP; 274 intel_ring_advance(rq, cs); 275 276 return intel_overlay_do_wait_request(overlay, rq, NULL); 277 } 278 279 static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 280 struct i915_vma *vma) 281 { 282 enum pipe pipe = overlay->crtc->pipe; 283 284 WARN_ON(overlay->old_vma); 285 286 i915_gem_track_fb(overlay->vma ? overlay->vma->obj : NULL, 287 vma ? vma->obj : NULL, 288 INTEL_FRONTBUFFER_OVERLAY(pipe)); 289 290 intel_frontbuffer_flip_prepare(overlay->i915, 291 INTEL_FRONTBUFFER_OVERLAY(pipe)); 292 293 overlay->old_vma = overlay->vma; 294 if (vma) 295 overlay->vma = i915_vma_get(vma); 296 else 297 overlay->vma = NULL; 298 } 299 300 /* overlay needs to be enabled in OCMD reg */ 301 static int intel_overlay_continue(struct intel_overlay *overlay, 302 struct i915_vma *vma, 303 bool load_polyphase_filter) 304 { 305 struct drm_i915_private *dev_priv = overlay->i915; 306 struct i915_request *rq; 307 u32 flip_addr = overlay->flip_addr; 308 u32 tmp, *cs; 309 310 WARN_ON(!overlay->active); 311 312 if (load_polyphase_filter) 313 flip_addr |= OFC_UPDATE; 314 315 /* check for underruns */ 316 tmp = I915_READ(DOVSTA); 317 if (tmp & (1 << 17)) 318 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp); 319 320 rq = alloc_request(overlay); 321 if (IS_ERR(rq)) 322 return PTR_ERR(rq); 323 324 cs = intel_ring_begin(rq, 2); 325 if (IS_ERR(cs)) { 326 i915_request_add(rq); 327 return PTR_ERR(cs); 328 } 329 330 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 331 *cs++ = flip_addr; 332 intel_ring_advance(rq, cs); 333 334 intel_overlay_flip_prepare(overlay, vma); 335 336 intel_overlay_submit_request(overlay, rq, NULL); 337 338 return 0; 339 } 340 341 static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 342 { 343 struct i915_vma *vma; 344 345 vma = fetch_and_zero(&overlay->old_vma); 346 if (WARN_ON(!vma)) 347 return; 348 349 intel_frontbuffer_flip_complete(overlay->i915, 350 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 351 352 i915_gem_object_unpin_from_display_plane(vma); 353 i915_vma_put(vma); 354 } 355 356 static void 357 intel_overlay_release_old_vid_tail(struct i915_active_request *active, 358 struct i915_request *rq) 359 { 360 struct intel_overlay *overlay = 361 container_of(active, typeof(*overlay), last_flip); 362 363 intel_overlay_release_old_vma(overlay); 364 } 365 366 static void intel_overlay_off_tail(struct i915_active_request *active, 367 struct i915_request *rq) 368 { 369 struct intel_overlay *overlay = 370 container_of(active, typeof(*overlay), last_flip); 371 struct drm_i915_private *dev_priv = overlay->i915; 372 373 intel_overlay_release_old_vma(overlay); 374 375 overlay->crtc->overlay = NULL; 376 overlay->crtc = NULL; 377 overlay->active = false; 378 379 if (IS_I830(dev_priv)) 380 i830_overlay_clock_gating(dev_priv, true); 381 } 382 383 /* overlay needs to be disabled in OCMD reg */ 384 static int intel_overlay_off(struct intel_overlay *overlay) 385 { 386 struct i915_request *rq; 387 u32 *cs, flip_addr = overlay->flip_addr; 388 389 WARN_ON(!overlay->active); 390 391 /* According to intel docs the overlay hw may hang (when switching 392 * off) without loading the filter coeffs. It is however unclear whether 393 * this applies to the disabling of the overlay or to the switching off 394 * of the hw. Do it in both cases */ 395 flip_addr |= OFC_UPDATE; 396 397 rq = alloc_request(overlay); 398 if (IS_ERR(rq)) 399 return PTR_ERR(rq); 400 401 cs = intel_ring_begin(rq, 6); 402 if (IS_ERR(cs)) { 403 i915_request_add(rq); 404 return PTR_ERR(cs); 405 } 406 407 /* wait for overlay to go idle */ 408 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 409 *cs++ = flip_addr; 410 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 411 412 /* turn overlay off */ 413 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; 414 *cs++ = flip_addr; 415 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 416 417 intel_ring_advance(rq, cs); 418 419 intel_overlay_flip_prepare(overlay, NULL); 420 421 return intel_overlay_do_wait_request(overlay, rq, 422 intel_overlay_off_tail); 423 } 424 425 /* recover from an interruption due to a signal 426 * We have to be careful not to repeat work forever an make forward progess. */ 427 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) 428 { 429 return i915_active_request_retire(&overlay->last_flip, 430 &overlay->i915->drm.struct_mutex); 431 } 432 433 /* Wait for pending overlay flip and release old frame. 434 * Needs to be called before the overlay register are changed 435 * via intel_overlay_(un)map_regs 436 */ 437 static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 438 { 439 struct drm_i915_private *dev_priv = overlay->i915; 440 u32 *cs; 441 int ret; 442 443 lockdep_assert_held(&dev_priv->drm.struct_mutex); 444 445 /* Only wait if there is actually an old frame to release to 446 * guarantee forward progress. 447 */ 448 if (!overlay->old_vma) 449 return 0; 450 451 if (I915_READ(GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) { 452 /* synchronous slowpath */ 453 struct i915_request *rq; 454 455 rq = alloc_request(overlay); 456 if (IS_ERR(rq)) 457 return PTR_ERR(rq); 458 459 cs = intel_ring_begin(rq, 2); 460 if (IS_ERR(cs)) { 461 i915_request_add(rq); 462 return PTR_ERR(cs); 463 } 464 465 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 466 *cs++ = MI_NOOP; 467 intel_ring_advance(rq, cs); 468 469 ret = intel_overlay_do_wait_request(overlay, rq, 470 intel_overlay_release_old_vid_tail); 471 if (ret) 472 return ret; 473 } else 474 intel_overlay_release_old_vid_tail(&overlay->last_flip, NULL); 475 476 return 0; 477 } 478 479 void intel_overlay_reset(struct drm_i915_private *dev_priv) 480 { 481 struct intel_overlay *overlay = dev_priv->overlay; 482 483 if (!overlay) 484 return; 485 486 overlay->old_xscale = 0; 487 overlay->old_yscale = 0; 488 overlay->crtc = NULL; 489 overlay->active = false; 490 } 491 492 static int packed_depth_bytes(u32 format) 493 { 494 switch (format & I915_OVERLAY_DEPTH_MASK) { 495 case I915_OVERLAY_YUV422: 496 return 4; 497 case I915_OVERLAY_YUV411: 498 /* return 6; not implemented */ 499 default: 500 return -EINVAL; 501 } 502 } 503 504 static int packed_width_bytes(u32 format, short width) 505 { 506 switch (format & I915_OVERLAY_DEPTH_MASK) { 507 case I915_OVERLAY_YUV422: 508 return width << 1; 509 default: 510 return -EINVAL; 511 } 512 } 513 514 static int uv_hsubsampling(u32 format) 515 { 516 switch (format & I915_OVERLAY_DEPTH_MASK) { 517 case I915_OVERLAY_YUV422: 518 case I915_OVERLAY_YUV420: 519 return 2; 520 case I915_OVERLAY_YUV411: 521 case I915_OVERLAY_YUV410: 522 return 4; 523 default: 524 return -EINVAL; 525 } 526 } 527 528 static int uv_vsubsampling(u32 format) 529 { 530 switch (format & I915_OVERLAY_DEPTH_MASK) { 531 case I915_OVERLAY_YUV420: 532 case I915_OVERLAY_YUV410: 533 return 2; 534 case I915_OVERLAY_YUV422: 535 case I915_OVERLAY_YUV411: 536 return 1; 537 default: 538 return -EINVAL; 539 } 540 } 541 542 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) 543 { 544 u32 sw; 545 546 if (IS_GEN(dev_priv, 2)) 547 sw = ALIGN((offset & 31) + width, 32); 548 else 549 sw = ALIGN((offset & 63) + width, 64); 550 551 if (sw == 0) 552 return 0; 553 554 return (sw - 32) >> 3; 555 } 556 557 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 558 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 559 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 560 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 561 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 562 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 563 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 564 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 565 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 566 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 567 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 568 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 569 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 570 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 571 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 572 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 573 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 574 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 575 }; 576 577 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 578 [ 0] = { 0x3000, 0x1800, 0x1800, }, 579 [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 580 [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 581 [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 582 [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 583 [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 584 [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 585 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 586 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 587 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 588 [10] = { 0xb100, 0x1eb8, 0x3620, }, 589 [11] = { 0xb100, 0x1f18, 0x34a0, }, 590 [12] = { 0xb100, 0x1f68, 0x3360, }, 591 [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 592 [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 593 [15] = { 0xb060, 0x1ff0, 0x30a0, }, 594 [16] = { 0x3000, 0x0800, 0x3000, }, 595 }; 596 597 static void update_polyphase_filter(struct overlay_registers __iomem *regs) 598 { 599 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 600 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 601 sizeof(uv_static_hcoeffs)); 602 } 603 604 static bool update_scaling_factors(struct intel_overlay *overlay, 605 struct overlay_registers __iomem *regs, 606 struct drm_intel_overlay_put_image *params) 607 { 608 /* fixed point with a 12 bit shift */ 609 u32 xscale, yscale, xscale_UV, yscale_UV; 610 #define FP_SHIFT 12 611 #define FRACT_MASK 0xfff 612 bool scale_changed = false; 613 int uv_hscale = uv_hsubsampling(params->flags); 614 int uv_vscale = uv_vsubsampling(params->flags); 615 616 if (params->dst_width > 1) 617 xscale = ((params->src_scan_width - 1) << FP_SHIFT) / 618 params->dst_width; 619 else 620 xscale = 1 << FP_SHIFT; 621 622 if (params->dst_height > 1) 623 yscale = ((params->src_scan_height - 1) << FP_SHIFT) / 624 params->dst_height; 625 else 626 yscale = 1 << FP_SHIFT; 627 628 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 629 xscale_UV = xscale/uv_hscale; 630 yscale_UV = yscale/uv_vscale; 631 /* make the Y scale to UV scale ratio an exact multiply */ 632 xscale = xscale_UV * uv_hscale; 633 yscale = yscale_UV * uv_vscale; 634 /*} else { 635 xscale_UV = 0; 636 yscale_UV = 0; 637 }*/ 638 639 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 640 scale_changed = true; 641 overlay->old_xscale = xscale; 642 overlay->old_yscale = yscale; 643 644 iowrite32(((yscale & FRACT_MASK) << 20) | 645 ((xscale >> FP_SHIFT) << 16) | 646 ((xscale & FRACT_MASK) << 3), 647 ®s->YRGBSCALE); 648 649 iowrite32(((yscale_UV & FRACT_MASK) << 20) | 650 ((xscale_UV >> FP_SHIFT) << 16) | 651 ((xscale_UV & FRACT_MASK) << 3), 652 ®s->UVSCALE); 653 654 iowrite32((((yscale >> FP_SHIFT) << 16) | 655 ((yscale_UV >> FP_SHIFT) << 0)), 656 ®s->UVSCALEV); 657 658 if (scale_changed) 659 update_polyphase_filter(regs); 660 661 return scale_changed; 662 } 663 664 static void update_colorkey(struct intel_overlay *overlay, 665 struct overlay_registers __iomem *regs) 666 { 667 const struct intel_plane_state *state = 668 to_intel_plane_state(overlay->crtc->base.primary->state); 669 u32 key = overlay->color_key; 670 u32 format = 0; 671 u32 flags = 0; 672 673 if (overlay->color_key_enabled) 674 flags |= DST_KEY_ENABLE; 675 676 if (state->base.visible) 677 format = state->base.fb->format->format; 678 679 switch (format) { 680 case DRM_FORMAT_C8: 681 key = 0; 682 flags |= CLK_RGB8I_MASK; 683 break; 684 case DRM_FORMAT_XRGB1555: 685 key = RGB15_TO_COLORKEY(key); 686 flags |= CLK_RGB15_MASK; 687 break; 688 case DRM_FORMAT_RGB565: 689 key = RGB16_TO_COLORKEY(key); 690 flags |= CLK_RGB16_MASK; 691 break; 692 default: 693 flags |= CLK_RGB24_MASK; 694 break; 695 } 696 697 iowrite32(key, ®s->DCLRKV); 698 iowrite32(flags, ®s->DCLRKM); 699 } 700 701 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) 702 { 703 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 704 705 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 706 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 707 case I915_OVERLAY_YUV422: 708 cmd |= OCMD_YUV_422_PLANAR; 709 break; 710 case I915_OVERLAY_YUV420: 711 cmd |= OCMD_YUV_420_PLANAR; 712 break; 713 case I915_OVERLAY_YUV411: 714 case I915_OVERLAY_YUV410: 715 cmd |= OCMD_YUV_410_PLANAR; 716 break; 717 } 718 } else { /* YUV packed */ 719 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 720 case I915_OVERLAY_YUV422: 721 cmd |= OCMD_YUV_422_PACKED; 722 break; 723 case I915_OVERLAY_YUV411: 724 cmd |= OCMD_YUV_411_PACKED; 725 break; 726 } 727 728 switch (params->flags & I915_OVERLAY_SWAP_MASK) { 729 case I915_OVERLAY_NO_SWAP: 730 break; 731 case I915_OVERLAY_UV_SWAP: 732 cmd |= OCMD_UV_SWAP; 733 break; 734 case I915_OVERLAY_Y_SWAP: 735 cmd |= OCMD_Y_SWAP; 736 break; 737 case I915_OVERLAY_Y_AND_UV_SWAP: 738 cmd |= OCMD_Y_AND_UV_SWAP; 739 break; 740 } 741 } 742 743 return cmd; 744 } 745 746 static int intel_overlay_do_put_image(struct intel_overlay *overlay, 747 struct drm_i915_gem_object *new_bo, 748 struct drm_intel_overlay_put_image *params) 749 { 750 struct overlay_registers __iomem *regs = overlay->regs; 751 struct drm_i915_private *dev_priv = overlay->i915; 752 u32 swidth, swidthsw, sheight, ostride; 753 enum pipe pipe = overlay->crtc->pipe; 754 bool scale_changed = false; 755 struct i915_vma *vma; 756 int ret, tmp_width; 757 758 lockdep_assert_held(&dev_priv->drm.struct_mutex); 759 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 760 761 ret = intel_overlay_release_old_vid(overlay); 762 if (ret != 0) 763 return ret; 764 765 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 766 767 i915_gem_object_lock(new_bo); 768 vma = i915_gem_object_pin_to_display_plane(new_bo, 769 0, NULL, PIN_MAPPABLE); 770 i915_gem_object_unlock(new_bo); 771 if (IS_ERR(vma)) { 772 ret = PTR_ERR(vma); 773 goto out_pin_section; 774 } 775 intel_fb_obj_flush(new_bo, ORIGIN_DIRTYFB); 776 777 ret = i915_vma_put_fence(vma); 778 if (ret) 779 goto out_unpin; 780 781 if (!overlay->active) { 782 u32 oconfig; 783 784 oconfig = OCONF_CC_OUT_8BIT; 785 if (IS_GEN(dev_priv, 4)) 786 oconfig |= OCONF_CSC_MODE_BT709; 787 oconfig |= pipe == 0 ? 788 OCONF_PIPE_A : OCONF_PIPE_B; 789 iowrite32(oconfig, ®s->OCONFIG); 790 791 ret = intel_overlay_on(overlay); 792 if (ret != 0) 793 goto out_unpin; 794 } 795 796 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS); 797 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ); 798 799 if (params->flags & I915_OVERLAY_YUV_PACKED) 800 tmp_width = packed_width_bytes(params->flags, 801 params->src_width); 802 else 803 tmp_width = params->src_width; 804 805 swidth = params->src_width; 806 swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width); 807 sheight = params->src_height; 808 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); 809 ostride = params->stride_Y; 810 811 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 812 int uv_hscale = uv_hsubsampling(params->flags); 813 int uv_vscale = uv_vsubsampling(params->flags); 814 u32 tmp_U, tmp_V; 815 816 swidth |= (params->src_width / uv_hscale) << 16; 817 sheight |= (params->src_height / uv_vscale) << 16; 818 819 tmp_U = calc_swidthsw(dev_priv, params->offset_U, 820 params->src_width / uv_hscale); 821 tmp_V = calc_swidthsw(dev_priv, params->offset_V, 822 params->src_width / uv_hscale); 823 swidthsw |= max(tmp_U, tmp_V) << 16; 824 825 iowrite32(i915_ggtt_offset(vma) + params->offset_U, 826 ®s->OBUF_0U); 827 iowrite32(i915_ggtt_offset(vma) + params->offset_V, 828 ®s->OBUF_0V); 829 830 ostride |= params->stride_UV << 16; 831 } 832 833 iowrite32(swidth, ®s->SWIDTH); 834 iowrite32(swidthsw, ®s->SWIDTHSW); 835 iowrite32(sheight, ®s->SHEIGHT); 836 iowrite32(ostride, ®s->OSTRIDE); 837 838 scale_changed = update_scaling_factors(overlay, regs, params); 839 840 update_colorkey(overlay, regs); 841 842 iowrite32(overlay_cmd_reg(params), ®s->OCMD); 843 844 ret = intel_overlay_continue(overlay, vma, scale_changed); 845 if (ret) 846 goto out_unpin; 847 848 return 0; 849 850 out_unpin: 851 i915_gem_object_unpin_from_display_plane(vma); 852 out_pin_section: 853 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 854 855 return ret; 856 } 857 858 int intel_overlay_switch_off(struct intel_overlay *overlay) 859 { 860 struct drm_i915_private *dev_priv = overlay->i915; 861 int ret; 862 863 lockdep_assert_held(&dev_priv->drm.struct_mutex); 864 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 865 866 ret = intel_overlay_recover_from_interrupt(overlay); 867 if (ret != 0) 868 return ret; 869 870 if (!overlay->active) 871 return 0; 872 873 ret = intel_overlay_release_old_vid(overlay); 874 if (ret != 0) 875 return ret; 876 877 iowrite32(0, &overlay->regs->OCMD); 878 879 return intel_overlay_off(overlay); 880 } 881 882 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 883 struct intel_crtc *crtc) 884 { 885 if (!crtc->active) 886 return -EINVAL; 887 888 /* can't use the overlay with double wide pipe */ 889 if (crtc->config->double_wide) 890 return -EINVAL; 891 892 return 0; 893 } 894 895 static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 896 { 897 struct drm_i915_private *dev_priv = overlay->i915; 898 u32 pfit_control = I915_READ(PFIT_CONTROL); 899 u32 ratio; 900 901 /* XXX: This is not the same logic as in the xorg driver, but more in 902 * line with the intel documentation for the i965 903 */ 904 if (INTEL_GEN(dev_priv) >= 4) { 905 /* on i965 use the PGM reg to read out the autoscaler values */ 906 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; 907 } else { 908 if (pfit_control & VERT_AUTO_SCALE) 909 ratio = I915_READ(PFIT_AUTO_RATIOS); 910 else 911 ratio = I915_READ(PFIT_PGM_RATIOS); 912 ratio >>= PFIT_VERT_SCALE_SHIFT; 913 } 914 915 overlay->pfit_vscale_ratio = ratio; 916 } 917 918 static int check_overlay_dst(struct intel_overlay *overlay, 919 struct drm_intel_overlay_put_image *rec) 920 { 921 const struct intel_crtc_state *pipe_config = 922 overlay->crtc->config; 923 924 if (rec->dst_x < pipe_config->pipe_src_w && 925 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && 926 rec->dst_y < pipe_config->pipe_src_h && 927 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) 928 return 0; 929 else 930 return -EINVAL; 931 } 932 933 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) 934 { 935 u32 tmp; 936 937 /* downscaling limit is 8.0 */ 938 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16; 939 if (tmp > 7) 940 return -EINVAL; 941 942 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16; 943 if (tmp > 7) 944 return -EINVAL; 945 946 return 0; 947 } 948 949 static int check_overlay_src(struct drm_i915_private *dev_priv, 950 struct drm_intel_overlay_put_image *rec, 951 struct drm_i915_gem_object *new_bo) 952 { 953 int uv_hscale = uv_hsubsampling(rec->flags); 954 int uv_vscale = uv_vsubsampling(rec->flags); 955 u32 stride_mask; 956 int depth; 957 u32 tmp; 958 959 /* check src dimensions */ 960 if (IS_I845G(dev_priv) || IS_I830(dev_priv)) { 961 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 962 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 963 return -EINVAL; 964 } else { 965 if (rec->src_height > IMAGE_MAX_HEIGHT || 966 rec->src_width > IMAGE_MAX_WIDTH) 967 return -EINVAL; 968 } 969 970 /* better safe than sorry, use 4 as the maximal subsampling ratio */ 971 if (rec->src_height < N_VERT_Y_TAPS*4 || 972 rec->src_width < N_HORIZ_Y_TAPS*4) 973 return -EINVAL; 974 975 /* check alignment constraints */ 976 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 977 case I915_OVERLAY_RGB: 978 /* not implemented */ 979 return -EINVAL; 980 981 case I915_OVERLAY_YUV_PACKED: 982 if (uv_vscale != 1) 983 return -EINVAL; 984 985 depth = packed_depth_bytes(rec->flags); 986 if (depth < 0) 987 return depth; 988 989 /* ignore UV planes */ 990 rec->stride_UV = 0; 991 rec->offset_U = 0; 992 rec->offset_V = 0; 993 /* check pixel alignment */ 994 if (rec->offset_Y % depth) 995 return -EINVAL; 996 break; 997 998 case I915_OVERLAY_YUV_PLANAR: 999 if (uv_vscale < 0 || uv_hscale < 0) 1000 return -EINVAL; 1001 /* no offset restrictions for planar formats */ 1002 break; 1003 1004 default: 1005 return -EINVAL; 1006 } 1007 1008 if (rec->src_width % uv_hscale) 1009 return -EINVAL; 1010 1011 /* stride checking */ 1012 if (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1013 stride_mask = 255; 1014 else 1015 stride_mask = 63; 1016 1017 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1018 return -EINVAL; 1019 if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512) 1020 return -EINVAL; 1021 1022 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1023 4096 : 8192; 1024 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 1025 return -EINVAL; 1026 1027 /* check buffer dimensions */ 1028 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1029 case I915_OVERLAY_RGB: 1030 case I915_OVERLAY_YUV_PACKED: 1031 /* always 4 Y values per depth pixels */ 1032 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 1033 return -EINVAL; 1034 1035 tmp = rec->stride_Y*rec->src_height; 1036 if (rec->offset_Y + tmp > new_bo->base.size) 1037 return -EINVAL; 1038 break; 1039 1040 case I915_OVERLAY_YUV_PLANAR: 1041 if (rec->src_width > rec->stride_Y) 1042 return -EINVAL; 1043 if (rec->src_width/uv_hscale > rec->stride_UV) 1044 return -EINVAL; 1045 1046 tmp = rec->stride_Y * rec->src_height; 1047 if (rec->offset_Y + tmp > new_bo->base.size) 1048 return -EINVAL; 1049 1050 tmp = rec->stride_UV * (rec->src_height / uv_vscale); 1051 if (rec->offset_U + tmp > new_bo->base.size || 1052 rec->offset_V + tmp > new_bo->base.size) 1053 return -EINVAL; 1054 break; 1055 } 1056 1057 return 0; 1058 } 1059 1060 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1061 struct drm_file *file_priv) 1062 { 1063 struct drm_intel_overlay_put_image *params = data; 1064 struct drm_i915_private *dev_priv = to_i915(dev); 1065 struct intel_overlay *overlay; 1066 struct drm_crtc *drmmode_crtc; 1067 struct intel_crtc *crtc; 1068 struct drm_i915_gem_object *new_bo; 1069 int ret; 1070 1071 overlay = dev_priv->overlay; 1072 if (!overlay) { 1073 DRM_DEBUG("userspace bug: no overlay\n"); 1074 return -ENODEV; 1075 } 1076 1077 if (!(params->flags & I915_OVERLAY_ENABLE)) { 1078 drm_modeset_lock_all(dev); 1079 mutex_lock(&dev->struct_mutex); 1080 1081 ret = intel_overlay_switch_off(overlay); 1082 1083 mutex_unlock(&dev->struct_mutex); 1084 drm_modeset_unlock_all(dev); 1085 1086 return ret; 1087 } 1088 1089 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id); 1090 if (!drmmode_crtc) 1091 return -ENOENT; 1092 crtc = to_intel_crtc(drmmode_crtc); 1093 1094 new_bo = i915_gem_object_lookup(file_priv, params->bo_handle); 1095 if (!new_bo) 1096 return -ENOENT; 1097 1098 drm_modeset_lock_all(dev); 1099 mutex_lock(&dev->struct_mutex); 1100 1101 if (i915_gem_object_is_tiled(new_bo)) { 1102 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n"); 1103 ret = -EINVAL; 1104 goto out_unlock; 1105 } 1106 1107 ret = intel_overlay_recover_from_interrupt(overlay); 1108 if (ret != 0) 1109 goto out_unlock; 1110 1111 if (overlay->crtc != crtc) { 1112 ret = intel_overlay_switch_off(overlay); 1113 if (ret != 0) 1114 goto out_unlock; 1115 1116 ret = check_overlay_possible_on_crtc(overlay, crtc); 1117 if (ret != 0) 1118 goto out_unlock; 1119 1120 overlay->crtc = crtc; 1121 crtc->overlay = overlay; 1122 1123 /* line too wide, i.e. one-line-mode */ 1124 if (crtc->config->pipe_src_w > 1024 && 1125 crtc->config->gmch_pfit.control & PFIT_ENABLE) { 1126 overlay->pfit_active = true; 1127 update_pfit_vscale_ratio(overlay); 1128 } else 1129 overlay->pfit_active = false; 1130 } 1131 1132 ret = check_overlay_dst(overlay, params); 1133 if (ret != 0) 1134 goto out_unlock; 1135 1136 if (overlay->pfit_active) { 1137 params->dst_y = (((u32)params->dst_y << 12) / 1138 overlay->pfit_vscale_ratio); 1139 /* shifting right rounds downwards, so add 1 */ 1140 params->dst_height = (((u32)params->dst_height << 12) / 1141 overlay->pfit_vscale_ratio) + 1; 1142 } 1143 1144 if (params->src_scan_height > params->src_height || 1145 params->src_scan_width > params->src_width) { 1146 ret = -EINVAL; 1147 goto out_unlock; 1148 } 1149 1150 ret = check_overlay_src(dev_priv, params, new_bo); 1151 if (ret != 0) 1152 goto out_unlock; 1153 1154 /* Check scaling after src size to prevent a divide-by-zero. */ 1155 ret = check_overlay_scaling(params); 1156 if (ret != 0) 1157 goto out_unlock; 1158 1159 ret = intel_overlay_do_put_image(overlay, new_bo, params); 1160 if (ret != 0) 1161 goto out_unlock; 1162 1163 mutex_unlock(&dev->struct_mutex); 1164 drm_modeset_unlock_all(dev); 1165 i915_gem_object_put(new_bo); 1166 1167 return 0; 1168 1169 out_unlock: 1170 mutex_unlock(&dev->struct_mutex); 1171 drm_modeset_unlock_all(dev); 1172 i915_gem_object_put(new_bo); 1173 1174 return ret; 1175 } 1176 1177 static void update_reg_attrs(struct intel_overlay *overlay, 1178 struct overlay_registers __iomem *regs) 1179 { 1180 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 1181 ®s->OCLRC0); 1182 iowrite32(overlay->saturation, ®s->OCLRC1); 1183 } 1184 1185 static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 1186 { 1187 int i; 1188 1189 if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 1190 return false; 1191 1192 for (i = 0; i < 3; i++) { 1193 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 1194 return false; 1195 } 1196 1197 return true; 1198 } 1199 1200 static bool check_gamma5_errata(u32 gamma5) 1201 { 1202 int i; 1203 1204 for (i = 0; i < 3; i++) { 1205 if (((gamma5 >> i*8) & 0xff) == 0x80) 1206 return false; 1207 } 1208 1209 return true; 1210 } 1211 1212 static int check_gamma(struct drm_intel_overlay_attrs *attrs) 1213 { 1214 if (!check_gamma_bounds(0, attrs->gamma0) || 1215 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 1216 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 1217 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 1218 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 1219 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 1220 !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 1221 return -EINVAL; 1222 1223 if (!check_gamma5_errata(attrs->gamma5)) 1224 return -EINVAL; 1225 1226 return 0; 1227 } 1228 1229 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1230 struct drm_file *file_priv) 1231 { 1232 struct drm_intel_overlay_attrs *attrs = data; 1233 struct drm_i915_private *dev_priv = to_i915(dev); 1234 struct intel_overlay *overlay; 1235 int ret; 1236 1237 overlay = dev_priv->overlay; 1238 if (!overlay) { 1239 DRM_DEBUG("userspace bug: no overlay\n"); 1240 return -ENODEV; 1241 } 1242 1243 drm_modeset_lock_all(dev); 1244 mutex_lock(&dev->struct_mutex); 1245 1246 ret = -EINVAL; 1247 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 1248 attrs->color_key = overlay->color_key; 1249 attrs->brightness = overlay->brightness; 1250 attrs->contrast = overlay->contrast; 1251 attrs->saturation = overlay->saturation; 1252 1253 if (!IS_GEN(dev_priv, 2)) { 1254 attrs->gamma0 = I915_READ(OGAMC0); 1255 attrs->gamma1 = I915_READ(OGAMC1); 1256 attrs->gamma2 = I915_READ(OGAMC2); 1257 attrs->gamma3 = I915_READ(OGAMC3); 1258 attrs->gamma4 = I915_READ(OGAMC4); 1259 attrs->gamma5 = I915_READ(OGAMC5); 1260 } 1261 } else { 1262 if (attrs->brightness < -128 || attrs->brightness > 127) 1263 goto out_unlock; 1264 if (attrs->contrast > 255) 1265 goto out_unlock; 1266 if (attrs->saturation > 1023) 1267 goto out_unlock; 1268 1269 overlay->color_key = attrs->color_key; 1270 overlay->brightness = attrs->brightness; 1271 overlay->contrast = attrs->contrast; 1272 overlay->saturation = attrs->saturation; 1273 1274 update_reg_attrs(overlay, overlay->regs); 1275 1276 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1277 if (IS_GEN(dev_priv, 2)) 1278 goto out_unlock; 1279 1280 if (overlay->active) { 1281 ret = -EBUSY; 1282 goto out_unlock; 1283 } 1284 1285 ret = check_gamma(attrs); 1286 if (ret) 1287 goto out_unlock; 1288 1289 I915_WRITE(OGAMC0, attrs->gamma0); 1290 I915_WRITE(OGAMC1, attrs->gamma1); 1291 I915_WRITE(OGAMC2, attrs->gamma2); 1292 I915_WRITE(OGAMC3, attrs->gamma3); 1293 I915_WRITE(OGAMC4, attrs->gamma4); 1294 I915_WRITE(OGAMC5, attrs->gamma5); 1295 } 1296 } 1297 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1298 1299 ret = 0; 1300 out_unlock: 1301 mutex_unlock(&dev->struct_mutex); 1302 drm_modeset_unlock_all(dev); 1303 1304 return ret; 1305 } 1306 1307 static int get_registers(struct intel_overlay *overlay, bool use_phys) 1308 { 1309 struct drm_i915_private *i915 = overlay->i915; 1310 struct drm_i915_gem_object *obj; 1311 struct i915_vma *vma; 1312 int err; 1313 1314 mutex_lock(&i915->drm.struct_mutex); 1315 1316 obj = i915_gem_object_create_stolen(i915, PAGE_SIZE); 1317 if (obj == NULL) 1318 obj = i915_gem_object_create_internal(i915, PAGE_SIZE); 1319 if (IS_ERR(obj)) { 1320 err = PTR_ERR(obj); 1321 goto err_unlock; 1322 } 1323 1324 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); 1325 if (IS_ERR(vma)) { 1326 err = PTR_ERR(vma); 1327 goto err_put_bo; 1328 } 1329 1330 if (use_phys) 1331 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl); 1332 else 1333 overlay->flip_addr = i915_ggtt_offset(vma); 1334 overlay->regs = i915_vma_pin_iomap(vma); 1335 i915_vma_unpin(vma); 1336 1337 if (IS_ERR(overlay->regs)) { 1338 err = PTR_ERR(overlay->regs); 1339 goto err_put_bo; 1340 } 1341 1342 overlay->reg_bo = obj; 1343 mutex_unlock(&i915->drm.struct_mutex); 1344 return 0; 1345 1346 err_put_bo: 1347 i915_gem_object_put(obj); 1348 err_unlock: 1349 mutex_unlock(&i915->drm.struct_mutex); 1350 return err; 1351 } 1352 1353 void intel_overlay_setup(struct drm_i915_private *dev_priv) 1354 { 1355 struct intel_overlay *overlay; 1356 int ret; 1357 1358 if (!HAS_OVERLAY(dev_priv)) 1359 return; 1360 1361 if (!HAS_ENGINE(dev_priv, RCS0)) 1362 return; 1363 1364 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 1365 if (!overlay) 1366 return; 1367 1368 overlay->i915 = dev_priv; 1369 overlay->context = dev_priv->engine[RCS0]->kernel_context; 1370 GEM_BUG_ON(!overlay->context); 1371 1372 overlay->color_key = 0x0101fe; 1373 overlay->color_key_enabled = true; 1374 overlay->brightness = -19; 1375 overlay->contrast = 75; 1376 overlay->saturation = 146; 1377 1378 INIT_ACTIVE_REQUEST(&overlay->last_flip); 1379 1380 ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv)); 1381 if (ret) 1382 goto out_free; 1383 1384 memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1385 update_polyphase_filter(overlay->regs); 1386 update_reg_attrs(overlay, overlay->regs); 1387 1388 dev_priv->overlay = overlay; 1389 DRM_INFO("Initialized overlay support.\n"); 1390 return; 1391 1392 out_free: 1393 kfree(overlay); 1394 } 1395 1396 void intel_overlay_cleanup(struct drm_i915_private *dev_priv) 1397 { 1398 struct intel_overlay *overlay; 1399 1400 overlay = fetch_and_zero(&dev_priv->overlay); 1401 if (!overlay) 1402 return; 1403 1404 /* 1405 * The bo's should be free'd by the generic code already. 1406 * Furthermore modesetting teardown happens beforehand so the 1407 * hardware should be off already. 1408 */ 1409 WARN_ON(overlay->active); 1410 1411 i915_gem_object_put(overlay->reg_bo); 1412 1413 kfree(overlay); 1414 } 1415 1416 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1417 1418 struct intel_overlay_error_state { 1419 struct overlay_registers regs; 1420 unsigned long base; 1421 u32 dovsta; 1422 u32 isr; 1423 }; 1424 1425 struct intel_overlay_error_state * 1426 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) 1427 { 1428 struct intel_overlay *overlay = dev_priv->overlay; 1429 struct intel_overlay_error_state *error; 1430 1431 if (!overlay || !overlay->active) 1432 return NULL; 1433 1434 error = kmalloc(sizeof(*error), GFP_ATOMIC); 1435 if (error == NULL) 1436 return NULL; 1437 1438 error->dovsta = I915_READ(DOVSTA); 1439 error->isr = I915_READ(GEN2_ISR); 1440 error->base = overlay->flip_addr; 1441 1442 memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs)); 1443 1444 return error; 1445 } 1446 1447 void 1448 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m, 1449 struct intel_overlay_error_state *error) 1450 { 1451 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1452 error->dovsta, error->isr); 1453 i915_error_printf(m, " Register file at 0x%08lx:\n", 1454 error->base); 1455 1456 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) 1457 P(OBUF_0Y); 1458 P(OBUF_1Y); 1459 P(OBUF_0U); 1460 P(OBUF_0V); 1461 P(OBUF_1U); 1462 P(OBUF_1V); 1463 P(OSTRIDE); 1464 P(YRGB_VPH); 1465 P(UV_VPH); 1466 P(HORZ_PH); 1467 P(INIT_PHS); 1468 P(DWINPOS); 1469 P(DWINSZ); 1470 P(SWIDTH); 1471 P(SWIDTHSW); 1472 P(SHEIGHT); 1473 P(YRGBSCALE); 1474 P(UVSCALE); 1475 P(OCLRC0); 1476 P(OCLRC1); 1477 P(DCLRKV); 1478 P(DCLRKM); 1479 P(SCLRKVH); 1480 P(SCLRKVL); 1481 P(SCLRKEN); 1482 P(OCONFIG); 1483 P(OCMD); 1484 P(OSTART_0Y); 1485 P(OSTART_1Y); 1486 P(OSTART_0U); 1487 P(OSTART_0V); 1488 P(OSTART_1U); 1489 P(OSTART_1V); 1490 P(OTILEOFF_0Y); 1491 P(OTILEOFF_1Y); 1492 P(OTILEOFF_0U); 1493 P(OTILEOFF_0V); 1494 P(OTILEOFF_1U); 1495 P(OTILEOFF_1V); 1496 P(FASTHSCALE); 1497 P(UVSCALEV); 1498 #undef P 1499 } 1500 1501 #endif 1502