1 /* 2 * Copyright © 2009 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel@ffwll.ch> 25 * 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27 */ 28 29 #include <drm/drm_fourcc.h> 30 31 #include "gem/i915_gem_pm.h" 32 #include "gt/intel_gpu_commands.h" 33 #include "gt/intel_ring.h" 34 35 #include "i915_drv.h" 36 #include "i915_reg.h" 37 #include "intel_display_types.h" 38 #include "intel_frontbuffer.h" 39 #include "intel_overlay.h" 40 41 /* Limits for overlay size. According to intel doc, the real limits are: 42 * Y width: 4095, UV width (planar): 2047, Y height: 2047, 43 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 44 * the mininum of both. */ 45 #define IMAGE_MAX_WIDTH 2048 46 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 47 /* on 830 and 845 these large limits result in the card hanging */ 48 #define IMAGE_MAX_WIDTH_LEGACY 1024 49 #define IMAGE_MAX_HEIGHT_LEGACY 1088 50 51 /* overlay register definitions */ 52 /* OCMD register */ 53 #define OCMD_TILED_SURFACE (0x1<<19) 54 #define OCMD_MIRROR_MASK (0x3<<17) 55 #define OCMD_MIRROR_MODE (0x3<<17) 56 #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 57 #define OCMD_MIRROR_VERTICAL (0x2<<17) 58 #define OCMD_MIRROR_BOTH (0x3<<17) 59 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 60 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 61 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 62 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 63 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 64 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 65 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 66 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 67 #define OCMD_YUV_422_PACKED (0x8<<10) 68 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 69 #define OCMD_YUV_420_PLANAR (0xc<<10) 70 #define OCMD_YUV_422_PLANAR (0xd<<10) 71 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 72 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 73 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 74 #define OCMD_BUF_TYPE_MASK (0x1<<5) 75 #define OCMD_BUF_TYPE_FRAME (0x0<<5) 76 #define OCMD_BUF_TYPE_FIELD (0x1<<5) 77 #define OCMD_TEST_MODE (0x1<<4) 78 #define OCMD_BUFFER_SELECT (0x3<<2) 79 #define OCMD_BUFFER0 (0x0<<2) 80 #define OCMD_BUFFER1 (0x1<<2) 81 #define OCMD_FIELD_SELECT (0x1<<2) 82 #define OCMD_FIELD0 (0x0<<1) 83 #define OCMD_FIELD1 (0x1<<1) 84 #define OCMD_ENABLE (0x1<<0) 85 86 /* OCONFIG register */ 87 #define OCONF_PIPE_MASK (0x1<<18) 88 #define OCONF_PIPE_A (0x0<<18) 89 #define OCONF_PIPE_B (0x1<<18) 90 #define OCONF_GAMMA2_ENABLE (0x1<<16) 91 #define OCONF_CSC_MODE_BT601 (0x0<<5) 92 #define OCONF_CSC_MODE_BT709 (0x1<<5) 93 #define OCONF_CSC_BYPASS (0x1<<4) 94 #define OCONF_CC_OUT_8BIT (0x1<<3) 95 #define OCONF_TEST_MODE (0x1<<2) 96 #define OCONF_THREE_LINE_BUFFER (0x1<<0) 97 #define OCONF_TWO_LINE_BUFFER (0x0<<0) 98 99 /* DCLRKM (dst-key) register */ 100 #define DST_KEY_ENABLE (0x1<<31) 101 #define CLK_RGB24_MASK 0x0 102 #define CLK_RGB16_MASK 0x070307 103 #define CLK_RGB15_MASK 0x070707 104 105 #define RGB30_TO_COLORKEY(c) \ 106 ((((c) & 0x3fc00000) >> 6) | (((c) & 0x000ff000) >> 4) | (((c) & 0x000003fc) >> 2)) 107 #define RGB16_TO_COLORKEY(c) \ 108 ((((c) & 0xf800) << 8) | (((c) & 0x07e0) << 5) | (((c) & 0x001f) << 3)) 109 #define RGB15_TO_COLORKEY(c) \ 110 ((((c) & 0x7c00) << 9) | (((c) & 0x03e0) << 6) | (((c) & 0x001f) << 3)) 111 #define RGB8I_TO_COLORKEY(c) \ 112 ((((c) & 0xff) << 16) | (((c) & 0xff) << 8) | (((c) & 0xff) << 0)) 113 114 /* overlay flip addr flag */ 115 #define OFC_UPDATE 0x1 116 117 /* polyphase filter coefficients */ 118 #define N_HORIZ_Y_TAPS 5 119 #define N_VERT_Y_TAPS 3 120 #define N_HORIZ_UV_TAPS 3 121 #define N_VERT_UV_TAPS 3 122 #define N_PHASES 17 123 #define MAX_TAPS 5 124 125 /* memory bufferd overlay registers */ 126 struct overlay_registers { 127 u32 OBUF_0Y; 128 u32 OBUF_1Y; 129 u32 OBUF_0U; 130 u32 OBUF_0V; 131 u32 OBUF_1U; 132 u32 OBUF_1V; 133 u32 OSTRIDE; 134 u32 YRGB_VPH; 135 u32 UV_VPH; 136 u32 HORZ_PH; 137 u32 INIT_PHS; 138 u32 DWINPOS; 139 u32 DWINSZ; 140 u32 SWIDTH; 141 u32 SWIDTHSW; 142 u32 SHEIGHT; 143 u32 YRGBSCALE; 144 u32 UVSCALE; 145 u32 OCLRC0; 146 u32 OCLRC1; 147 u32 DCLRKV; 148 u32 DCLRKM; 149 u32 SCLRKVH; 150 u32 SCLRKVL; 151 u32 SCLRKEN; 152 u32 OCONFIG; 153 u32 OCMD; 154 u32 RESERVED1; /* 0x6C */ 155 u32 OSTART_0Y; 156 u32 OSTART_1Y; 157 u32 OSTART_0U; 158 u32 OSTART_0V; 159 u32 OSTART_1U; 160 u32 OSTART_1V; 161 u32 OTILEOFF_0Y; 162 u32 OTILEOFF_1Y; 163 u32 OTILEOFF_0U; 164 u32 OTILEOFF_0V; 165 u32 OTILEOFF_1U; 166 u32 OTILEOFF_1V; 167 u32 FASTHSCALE; /* 0xA0 */ 168 u32 UVSCALEV; /* 0xA4 */ 169 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 170 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 171 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 172 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 173 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 174 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 175 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 176 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 177 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 178 }; 179 180 struct intel_overlay { 181 struct drm_i915_private *i915; 182 struct intel_context *context; 183 struct intel_crtc *crtc; 184 struct i915_vma *vma; 185 struct i915_vma *old_vma; 186 struct intel_frontbuffer *frontbuffer; 187 bool active; 188 bool pfit_active; 189 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 190 u32 color_key:24; 191 u32 color_key_enabled:1; 192 u32 brightness, contrast, saturation; 193 u32 old_xscale, old_yscale; 194 /* register access */ 195 struct drm_i915_gem_object *reg_bo; 196 struct overlay_registers __iomem *regs; 197 u32 flip_addr; 198 /* flip handling */ 199 struct i915_active last_flip; 200 void (*flip_complete)(struct intel_overlay *ovl); 201 }; 202 203 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, 204 bool enable) 205 { 206 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 207 u8 val; 208 209 /* WA_OVERLAY_CLKGATE:alm */ 210 if (enable) 211 intel_de_write(dev_priv, DSPCLK_GATE_D, 0); 212 else 213 intel_de_write(dev_priv, DSPCLK_GATE_D, 214 OVRUNIT_CLOCK_GATE_DISABLE); 215 216 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 217 pci_bus_read_config_byte(pdev->bus, 218 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); 219 if (enable) 220 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; 221 else 222 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 223 pci_bus_write_config_byte(pdev->bus, 224 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 225 } 226 227 static struct i915_request * 228 alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *)) 229 { 230 struct i915_request *rq; 231 int err; 232 233 overlay->flip_complete = fn; 234 235 rq = i915_request_create(overlay->context); 236 if (IS_ERR(rq)) 237 return rq; 238 239 err = i915_active_add_request(&overlay->last_flip, rq); 240 if (err) { 241 i915_request_add(rq); 242 return ERR_PTR(err); 243 } 244 245 return rq; 246 } 247 248 /* overlay needs to be disable in OCMD reg */ 249 static int intel_overlay_on(struct intel_overlay *overlay) 250 { 251 struct drm_i915_private *dev_priv = overlay->i915; 252 struct i915_request *rq; 253 u32 *cs; 254 255 drm_WARN_ON(&dev_priv->drm, overlay->active); 256 257 rq = alloc_request(overlay, NULL); 258 if (IS_ERR(rq)) 259 return PTR_ERR(rq); 260 261 cs = intel_ring_begin(rq, 4); 262 if (IS_ERR(cs)) { 263 i915_request_add(rq); 264 return PTR_ERR(cs); 265 } 266 267 overlay->active = true; 268 269 if (IS_I830(dev_priv)) 270 i830_overlay_clock_gating(dev_priv, false); 271 272 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 273 *cs++ = overlay->flip_addr | OFC_UPDATE; 274 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 275 *cs++ = MI_NOOP; 276 intel_ring_advance(rq, cs); 277 278 i915_request_add(rq); 279 280 return i915_active_wait(&overlay->last_flip); 281 } 282 283 static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 284 struct i915_vma *vma) 285 { 286 enum pipe pipe = overlay->crtc->pipe; 287 struct intel_frontbuffer *frontbuffer = NULL; 288 289 drm_WARN_ON(&overlay->i915->drm, overlay->old_vma); 290 291 if (vma) 292 frontbuffer = intel_frontbuffer_get(vma->obj); 293 294 intel_frontbuffer_track(overlay->frontbuffer, frontbuffer, 295 INTEL_FRONTBUFFER_OVERLAY(pipe)); 296 297 if (overlay->frontbuffer) 298 intel_frontbuffer_put(overlay->frontbuffer); 299 overlay->frontbuffer = frontbuffer; 300 301 intel_frontbuffer_flip_prepare(overlay->i915, 302 INTEL_FRONTBUFFER_OVERLAY(pipe)); 303 304 overlay->old_vma = overlay->vma; 305 if (vma) 306 overlay->vma = i915_vma_get(vma); 307 else 308 overlay->vma = NULL; 309 } 310 311 /* overlay needs to be enabled in OCMD reg */ 312 static int intel_overlay_continue(struct intel_overlay *overlay, 313 struct i915_vma *vma, 314 bool load_polyphase_filter) 315 { 316 struct drm_i915_private *dev_priv = overlay->i915; 317 struct i915_request *rq; 318 u32 flip_addr = overlay->flip_addr; 319 u32 tmp, *cs; 320 321 drm_WARN_ON(&dev_priv->drm, !overlay->active); 322 323 if (load_polyphase_filter) 324 flip_addr |= OFC_UPDATE; 325 326 /* check for underruns */ 327 tmp = intel_de_read(dev_priv, DOVSTA); 328 if (tmp & (1 << 17)) 329 drm_dbg(&dev_priv->drm, "overlay underrun, DOVSTA: %x\n", tmp); 330 331 rq = alloc_request(overlay, NULL); 332 if (IS_ERR(rq)) 333 return PTR_ERR(rq); 334 335 cs = intel_ring_begin(rq, 2); 336 if (IS_ERR(cs)) { 337 i915_request_add(rq); 338 return PTR_ERR(cs); 339 } 340 341 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 342 *cs++ = flip_addr; 343 intel_ring_advance(rq, cs); 344 345 intel_overlay_flip_prepare(overlay, vma); 346 i915_request_add(rq); 347 348 return 0; 349 } 350 351 static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 352 { 353 struct i915_vma *vma; 354 355 vma = fetch_and_zero(&overlay->old_vma); 356 if (drm_WARN_ON(&overlay->i915->drm, !vma)) 357 return; 358 359 intel_frontbuffer_flip_complete(overlay->i915, 360 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 361 362 i915_vma_unpin(vma); 363 i915_vma_put(vma); 364 } 365 366 static void 367 intel_overlay_release_old_vid_tail(struct intel_overlay *overlay) 368 { 369 intel_overlay_release_old_vma(overlay); 370 } 371 372 static void intel_overlay_off_tail(struct intel_overlay *overlay) 373 { 374 struct drm_i915_private *dev_priv = overlay->i915; 375 376 intel_overlay_release_old_vma(overlay); 377 378 overlay->crtc->overlay = NULL; 379 overlay->crtc = NULL; 380 overlay->active = false; 381 382 if (IS_I830(dev_priv)) 383 i830_overlay_clock_gating(dev_priv, true); 384 } 385 386 static void 387 intel_overlay_last_flip_retire(struct i915_active *active) 388 { 389 struct intel_overlay *overlay = 390 container_of(active, typeof(*overlay), last_flip); 391 392 if (overlay->flip_complete) 393 overlay->flip_complete(overlay); 394 } 395 396 /* overlay needs to be disabled in OCMD reg */ 397 static int intel_overlay_off(struct intel_overlay *overlay) 398 { 399 struct i915_request *rq; 400 u32 *cs, flip_addr = overlay->flip_addr; 401 402 drm_WARN_ON(&overlay->i915->drm, !overlay->active); 403 404 /* According to intel docs the overlay hw may hang (when switching 405 * off) without loading the filter coeffs. It is however unclear whether 406 * this applies to the disabling of the overlay or to the switching off 407 * of the hw. Do it in both cases */ 408 flip_addr |= OFC_UPDATE; 409 410 rq = alloc_request(overlay, intel_overlay_off_tail); 411 if (IS_ERR(rq)) 412 return PTR_ERR(rq); 413 414 cs = intel_ring_begin(rq, 6); 415 if (IS_ERR(cs)) { 416 i915_request_add(rq); 417 return PTR_ERR(cs); 418 } 419 420 /* wait for overlay to go idle */ 421 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 422 *cs++ = flip_addr; 423 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 424 425 /* turn overlay off */ 426 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; 427 *cs++ = flip_addr; 428 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 429 430 intel_ring_advance(rq, cs); 431 432 intel_overlay_flip_prepare(overlay, NULL); 433 i915_request_add(rq); 434 435 return i915_active_wait(&overlay->last_flip); 436 } 437 438 /* recover from an interruption due to a signal 439 * We have to be careful not to repeat work forever an make forward progess. */ 440 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) 441 { 442 return i915_active_wait(&overlay->last_flip); 443 } 444 445 /* Wait for pending overlay flip and release old frame. 446 * Needs to be called before the overlay register are changed 447 * via intel_overlay_(un)map_regs 448 */ 449 static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 450 { 451 struct drm_i915_private *dev_priv = overlay->i915; 452 struct i915_request *rq; 453 u32 *cs; 454 455 /* 456 * Only wait if there is actually an old frame to release to 457 * guarantee forward progress. 458 */ 459 if (!overlay->old_vma) 460 return 0; 461 462 if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { 463 intel_overlay_release_old_vid_tail(overlay); 464 return 0; 465 } 466 467 rq = alloc_request(overlay, intel_overlay_release_old_vid_tail); 468 if (IS_ERR(rq)) 469 return PTR_ERR(rq); 470 471 cs = intel_ring_begin(rq, 2); 472 if (IS_ERR(cs)) { 473 i915_request_add(rq); 474 return PTR_ERR(cs); 475 } 476 477 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 478 *cs++ = MI_NOOP; 479 intel_ring_advance(rq, cs); 480 481 i915_request_add(rq); 482 483 return i915_active_wait(&overlay->last_flip); 484 } 485 486 void intel_overlay_reset(struct drm_i915_private *dev_priv) 487 { 488 struct intel_overlay *overlay = dev_priv->overlay; 489 490 if (!overlay) 491 return; 492 493 overlay->old_xscale = 0; 494 overlay->old_yscale = 0; 495 overlay->crtc = NULL; 496 overlay->active = false; 497 } 498 499 static int packed_depth_bytes(u32 format) 500 { 501 switch (format & I915_OVERLAY_DEPTH_MASK) { 502 case I915_OVERLAY_YUV422: 503 return 4; 504 case I915_OVERLAY_YUV411: 505 /* return 6; not implemented */ 506 default: 507 return -EINVAL; 508 } 509 } 510 511 static int packed_width_bytes(u32 format, short width) 512 { 513 switch (format & I915_OVERLAY_DEPTH_MASK) { 514 case I915_OVERLAY_YUV422: 515 return width << 1; 516 default: 517 return -EINVAL; 518 } 519 } 520 521 static int uv_hsubsampling(u32 format) 522 { 523 switch (format & I915_OVERLAY_DEPTH_MASK) { 524 case I915_OVERLAY_YUV422: 525 case I915_OVERLAY_YUV420: 526 return 2; 527 case I915_OVERLAY_YUV411: 528 case I915_OVERLAY_YUV410: 529 return 4; 530 default: 531 return -EINVAL; 532 } 533 } 534 535 static int uv_vsubsampling(u32 format) 536 { 537 switch (format & I915_OVERLAY_DEPTH_MASK) { 538 case I915_OVERLAY_YUV420: 539 case I915_OVERLAY_YUV410: 540 return 2; 541 case I915_OVERLAY_YUV422: 542 case I915_OVERLAY_YUV411: 543 return 1; 544 default: 545 return -EINVAL; 546 } 547 } 548 549 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) 550 { 551 u32 sw; 552 553 if (DISPLAY_VER(dev_priv) == 2) 554 sw = ALIGN((offset & 31) + width, 32); 555 else 556 sw = ALIGN((offset & 63) + width, 64); 557 558 if (sw == 0) 559 return 0; 560 561 return (sw - 32) >> 3; 562 } 563 564 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 565 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 566 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 567 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 568 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 569 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 570 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 571 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 572 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 573 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 574 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 575 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 576 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 577 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 578 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 579 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 580 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 581 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 582 }; 583 584 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 585 [ 0] = { 0x3000, 0x1800, 0x1800, }, 586 [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 587 [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 588 [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 589 [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 590 [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 591 [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 592 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 593 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 594 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 595 [10] = { 0xb100, 0x1eb8, 0x3620, }, 596 [11] = { 0xb100, 0x1f18, 0x34a0, }, 597 [12] = { 0xb100, 0x1f68, 0x3360, }, 598 [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 599 [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 600 [15] = { 0xb060, 0x1ff0, 0x30a0, }, 601 [16] = { 0x3000, 0x0800, 0x3000, }, 602 }; 603 604 static void update_polyphase_filter(struct overlay_registers __iomem *regs) 605 { 606 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 607 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 608 sizeof(uv_static_hcoeffs)); 609 } 610 611 static bool update_scaling_factors(struct intel_overlay *overlay, 612 struct overlay_registers __iomem *regs, 613 struct drm_intel_overlay_put_image *params) 614 { 615 /* fixed point with a 12 bit shift */ 616 u32 xscale, yscale, xscale_UV, yscale_UV; 617 #define FP_SHIFT 12 618 #define FRACT_MASK 0xfff 619 bool scale_changed = false; 620 int uv_hscale = uv_hsubsampling(params->flags); 621 int uv_vscale = uv_vsubsampling(params->flags); 622 623 if (params->dst_width > 1) 624 xscale = ((params->src_scan_width - 1) << FP_SHIFT) / 625 params->dst_width; 626 else 627 xscale = 1 << FP_SHIFT; 628 629 if (params->dst_height > 1) 630 yscale = ((params->src_scan_height - 1) << FP_SHIFT) / 631 params->dst_height; 632 else 633 yscale = 1 << FP_SHIFT; 634 635 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 636 xscale_UV = xscale/uv_hscale; 637 yscale_UV = yscale/uv_vscale; 638 /* make the Y scale to UV scale ratio an exact multiply */ 639 xscale = xscale_UV * uv_hscale; 640 yscale = yscale_UV * uv_vscale; 641 /*} else { 642 xscale_UV = 0; 643 yscale_UV = 0; 644 }*/ 645 646 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 647 scale_changed = true; 648 overlay->old_xscale = xscale; 649 overlay->old_yscale = yscale; 650 651 iowrite32(((yscale & FRACT_MASK) << 20) | 652 ((xscale >> FP_SHIFT) << 16) | 653 ((xscale & FRACT_MASK) << 3), 654 ®s->YRGBSCALE); 655 656 iowrite32(((yscale_UV & FRACT_MASK) << 20) | 657 ((xscale_UV >> FP_SHIFT) << 16) | 658 ((xscale_UV & FRACT_MASK) << 3), 659 ®s->UVSCALE); 660 661 iowrite32((((yscale >> FP_SHIFT) << 16) | 662 ((yscale_UV >> FP_SHIFT) << 0)), 663 ®s->UVSCALEV); 664 665 if (scale_changed) 666 update_polyphase_filter(regs); 667 668 return scale_changed; 669 } 670 671 static void update_colorkey(struct intel_overlay *overlay, 672 struct overlay_registers __iomem *regs) 673 { 674 const struct intel_plane_state *state = 675 to_intel_plane_state(overlay->crtc->base.primary->state); 676 u32 key = overlay->color_key; 677 u32 format = 0; 678 u32 flags = 0; 679 680 if (overlay->color_key_enabled) 681 flags |= DST_KEY_ENABLE; 682 683 if (state->uapi.visible) 684 format = state->hw.fb->format->format; 685 686 switch (format) { 687 case DRM_FORMAT_C8: 688 key = RGB8I_TO_COLORKEY(key); 689 flags |= CLK_RGB24_MASK; 690 break; 691 case DRM_FORMAT_XRGB1555: 692 key = RGB15_TO_COLORKEY(key); 693 flags |= CLK_RGB15_MASK; 694 break; 695 case DRM_FORMAT_RGB565: 696 key = RGB16_TO_COLORKEY(key); 697 flags |= CLK_RGB16_MASK; 698 break; 699 case DRM_FORMAT_XRGB2101010: 700 case DRM_FORMAT_XBGR2101010: 701 key = RGB30_TO_COLORKEY(key); 702 flags |= CLK_RGB24_MASK; 703 break; 704 default: 705 flags |= CLK_RGB24_MASK; 706 break; 707 } 708 709 iowrite32(key, ®s->DCLRKV); 710 iowrite32(flags, ®s->DCLRKM); 711 } 712 713 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) 714 { 715 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 716 717 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 718 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 719 case I915_OVERLAY_YUV422: 720 cmd |= OCMD_YUV_422_PLANAR; 721 break; 722 case I915_OVERLAY_YUV420: 723 cmd |= OCMD_YUV_420_PLANAR; 724 break; 725 case I915_OVERLAY_YUV411: 726 case I915_OVERLAY_YUV410: 727 cmd |= OCMD_YUV_410_PLANAR; 728 break; 729 } 730 } else { /* YUV packed */ 731 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 732 case I915_OVERLAY_YUV422: 733 cmd |= OCMD_YUV_422_PACKED; 734 break; 735 case I915_OVERLAY_YUV411: 736 cmd |= OCMD_YUV_411_PACKED; 737 break; 738 } 739 740 switch (params->flags & I915_OVERLAY_SWAP_MASK) { 741 case I915_OVERLAY_NO_SWAP: 742 break; 743 case I915_OVERLAY_UV_SWAP: 744 cmd |= OCMD_UV_SWAP; 745 break; 746 case I915_OVERLAY_Y_SWAP: 747 cmd |= OCMD_Y_SWAP; 748 break; 749 case I915_OVERLAY_Y_AND_UV_SWAP: 750 cmd |= OCMD_Y_AND_UV_SWAP; 751 break; 752 } 753 } 754 755 return cmd; 756 } 757 758 static struct i915_vma *intel_overlay_pin_fb(struct drm_i915_gem_object *new_bo) 759 { 760 struct i915_gem_ww_ctx ww; 761 struct i915_vma *vma; 762 int ret; 763 764 i915_gem_ww_ctx_init(&ww, true); 765 retry: 766 ret = i915_gem_object_lock(new_bo, &ww); 767 if (!ret) { 768 vma = i915_gem_object_pin_to_display_plane(new_bo, &ww, 0, 769 NULL, PIN_MAPPABLE); 770 ret = PTR_ERR_OR_ZERO(vma); 771 } 772 if (ret == -EDEADLK) { 773 ret = i915_gem_ww_ctx_backoff(&ww); 774 if (!ret) 775 goto retry; 776 } 777 i915_gem_ww_ctx_fini(&ww); 778 if (ret) 779 return ERR_PTR(ret); 780 781 return vma; 782 } 783 784 static int intel_overlay_do_put_image(struct intel_overlay *overlay, 785 struct drm_i915_gem_object *new_bo, 786 struct drm_intel_overlay_put_image *params) 787 { 788 struct overlay_registers __iomem *regs = overlay->regs; 789 struct drm_i915_private *dev_priv = overlay->i915; 790 u32 swidth, swidthsw, sheight, ostride; 791 enum pipe pipe = overlay->crtc->pipe; 792 bool scale_changed = false; 793 struct i915_vma *vma; 794 int ret, tmp_width; 795 796 drm_WARN_ON(&dev_priv->drm, 797 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 798 799 ret = intel_overlay_release_old_vid(overlay); 800 if (ret != 0) 801 return ret; 802 803 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 804 805 vma = intel_overlay_pin_fb(new_bo); 806 if (IS_ERR(vma)) 807 goto out_pin_section; 808 809 i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB); 810 811 if (!overlay->active) { 812 const struct intel_crtc_state *crtc_state = 813 overlay->crtc->config; 814 u32 oconfig = 0; 815 816 if (crtc_state->gamma_enable && 817 crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 818 oconfig |= OCONF_CC_OUT_8BIT; 819 if (crtc_state->gamma_enable) 820 oconfig |= OCONF_GAMMA2_ENABLE; 821 if (DISPLAY_VER(dev_priv) == 4) 822 oconfig |= OCONF_CSC_MODE_BT709; 823 oconfig |= pipe == 0 ? 824 OCONF_PIPE_A : OCONF_PIPE_B; 825 iowrite32(oconfig, ®s->OCONFIG); 826 827 ret = intel_overlay_on(overlay); 828 if (ret != 0) 829 goto out_unpin; 830 } 831 832 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS); 833 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ); 834 835 if (params->flags & I915_OVERLAY_YUV_PACKED) 836 tmp_width = packed_width_bytes(params->flags, 837 params->src_width); 838 else 839 tmp_width = params->src_width; 840 841 swidth = params->src_width; 842 swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width); 843 sheight = params->src_height; 844 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); 845 ostride = params->stride_Y; 846 847 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 848 int uv_hscale = uv_hsubsampling(params->flags); 849 int uv_vscale = uv_vsubsampling(params->flags); 850 u32 tmp_U, tmp_V; 851 852 swidth |= (params->src_width / uv_hscale) << 16; 853 sheight |= (params->src_height / uv_vscale) << 16; 854 855 tmp_U = calc_swidthsw(dev_priv, params->offset_U, 856 params->src_width / uv_hscale); 857 tmp_V = calc_swidthsw(dev_priv, params->offset_V, 858 params->src_width / uv_hscale); 859 swidthsw |= max(tmp_U, tmp_V) << 16; 860 861 iowrite32(i915_ggtt_offset(vma) + params->offset_U, 862 ®s->OBUF_0U); 863 iowrite32(i915_ggtt_offset(vma) + params->offset_V, 864 ®s->OBUF_0V); 865 866 ostride |= params->stride_UV << 16; 867 } 868 869 iowrite32(swidth, ®s->SWIDTH); 870 iowrite32(swidthsw, ®s->SWIDTHSW); 871 iowrite32(sheight, ®s->SHEIGHT); 872 iowrite32(ostride, ®s->OSTRIDE); 873 874 scale_changed = update_scaling_factors(overlay, regs, params); 875 876 update_colorkey(overlay, regs); 877 878 iowrite32(overlay_cmd_reg(params), ®s->OCMD); 879 880 ret = intel_overlay_continue(overlay, vma, scale_changed); 881 if (ret) 882 goto out_unpin; 883 884 return 0; 885 886 out_unpin: 887 i915_vma_unpin(vma); 888 out_pin_section: 889 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 890 891 return ret; 892 } 893 894 int intel_overlay_switch_off(struct intel_overlay *overlay) 895 { 896 struct drm_i915_private *dev_priv = overlay->i915; 897 int ret; 898 899 drm_WARN_ON(&dev_priv->drm, 900 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 901 902 ret = intel_overlay_recover_from_interrupt(overlay); 903 if (ret != 0) 904 return ret; 905 906 if (!overlay->active) 907 return 0; 908 909 ret = intel_overlay_release_old_vid(overlay); 910 if (ret != 0) 911 return ret; 912 913 iowrite32(0, &overlay->regs->OCMD); 914 915 return intel_overlay_off(overlay); 916 } 917 918 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 919 struct intel_crtc *crtc) 920 { 921 if (!crtc->active) 922 return -EINVAL; 923 924 /* can't use the overlay with double wide pipe */ 925 if (crtc->config->double_wide) 926 return -EINVAL; 927 928 return 0; 929 } 930 931 static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 932 { 933 struct drm_i915_private *dev_priv = overlay->i915; 934 u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL); 935 u32 ratio; 936 937 /* XXX: This is not the same logic as in the xorg driver, but more in 938 * line with the intel documentation for the i965 939 */ 940 if (DISPLAY_VER(dev_priv) >= 4) { 941 /* on i965 use the PGM reg to read out the autoscaler values */ 942 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; 943 } else { 944 if (pfit_control & VERT_AUTO_SCALE) 945 ratio = intel_de_read(dev_priv, PFIT_AUTO_RATIOS); 946 else 947 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS); 948 ratio >>= PFIT_VERT_SCALE_SHIFT; 949 } 950 951 overlay->pfit_vscale_ratio = ratio; 952 } 953 954 static int check_overlay_dst(struct intel_overlay *overlay, 955 struct drm_intel_overlay_put_image *rec) 956 { 957 const struct intel_crtc_state *pipe_config = 958 overlay->crtc->config; 959 960 if (rec->dst_x < pipe_config->pipe_src_w && 961 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && 962 rec->dst_y < pipe_config->pipe_src_h && 963 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) 964 return 0; 965 else 966 return -EINVAL; 967 } 968 969 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) 970 { 971 u32 tmp; 972 973 /* downscaling limit is 8.0 */ 974 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16; 975 if (tmp > 7) 976 return -EINVAL; 977 978 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16; 979 if (tmp > 7) 980 return -EINVAL; 981 982 return 0; 983 } 984 985 static int check_overlay_src(struct drm_i915_private *dev_priv, 986 struct drm_intel_overlay_put_image *rec, 987 struct drm_i915_gem_object *new_bo) 988 { 989 int uv_hscale = uv_hsubsampling(rec->flags); 990 int uv_vscale = uv_vsubsampling(rec->flags); 991 u32 stride_mask; 992 int depth; 993 u32 tmp; 994 995 /* check src dimensions */ 996 if (IS_I845G(dev_priv) || IS_I830(dev_priv)) { 997 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 998 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 999 return -EINVAL; 1000 } else { 1001 if (rec->src_height > IMAGE_MAX_HEIGHT || 1002 rec->src_width > IMAGE_MAX_WIDTH) 1003 return -EINVAL; 1004 } 1005 1006 /* better safe than sorry, use 4 as the maximal subsampling ratio */ 1007 if (rec->src_height < N_VERT_Y_TAPS*4 || 1008 rec->src_width < N_HORIZ_Y_TAPS*4) 1009 return -EINVAL; 1010 1011 /* check alignment constraints */ 1012 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1013 case I915_OVERLAY_RGB: 1014 /* not implemented */ 1015 return -EINVAL; 1016 1017 case I915_OVERLAY_YUV_PACKED: 1018 if (uv_vscale != 1) 1019 return -EINVAL; 1020 1021 depth = packed_depth_bytes(rec->flags); 1022 if (depth < 0) 1023 return depth; 1024 1025 /* ignore UV planes */ 1026 rec->stride_UV = 0; 1027 rec->offset_U = 0; 1028 rec->offset_V = 0; 1029 /* check pixel alignment */ 1030 if (rec->offset_Y % depth) 1031 return -EINVAL; 1032 break; 1033 1034 case I915_OVERLAY_YUV_PLANAR: 1035 if (uv_vscale < 0 || uv_hscale < 0) 1036 return -EINVAL; 1037 /* no offset restrictions for planar formats */ 1038 break; 1039 1040 default: 1041 return -EINVAL; 1042 } 1043 1044 if (rec->src_width % uv_hscale) 1045 return -EINVAL; 1046 1047 /* stride checking */ 1048 if (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1049 stride_mask = 255; 1050 else 1051 stride_mask = 63; 1052 1053 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1054 return -EINVAL; 1055 if (DISPLAY_VER(dev_priv) == 4 && rec->stride_Y < 512) 1056 return -EINVAL; 1057 1058 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1059 4096 : 8192; 1060 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 1061 return -EINVAL; 1062 1063 /* check buffer dimensions */ 1064 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1065 case I915_OVERLAY_RGB: 1066 case I915_OVERLAY_YUV_PACKED: 1067 /* always 4 Y values per depth pixels */ 1068 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 1069 return -EINVAL; 1070 1071 tmp = rec->stride_Y*rec->src_height; 1072 if (rec->offset_Y + tmp > new_bo->base.size) 1073 return -EINVAL; 1074 break; 1075 1076 case I915_OVERLAY_YUV_PLANAR: 1077 if (rec->src_width > rec->stride_Y) 1078 return -EINVAL; 1079 if (rec->src_width/uv_hscale > rec->stride_UV) 1080 return -EINVAL; 1081 1082 tmp = rec->stride_Y * rec->src_height; 1083 if (rec->offset_Y + tmp > new_bo->base.size) 1084 return -EINVAL; 1085 1086 tmp = rec->stride_UV * (rec->src_height / uv_vscale); 1087 if (rec->offset_U + tmp > new_bo->base.size || 1088 rec->offset_V + tmp > new_bo->base.size) 1089 return -EINVAL; 1090 break; 1091 } 1092 1093 return 0; 1094 } 1095 1096 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1097 struct drm_file *file_priv) 1098 { 1099 struct drm_intel_overlay_put_image *params = data; 1100 struct drm_i915_private *dev_priv = to_i915(dev); 1101 struct intel_overlay *overlay; 1102 struct drm_crtc *drmmode_crtc; 1103 struct intel_crtc *crtc; 1104 struct drm_i915_gem_object *new_bo; 1105 int ret; 1106 1107 overlay = dev_priv->overlay; 1108 if (!overlay) { 1109 drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n"); 1110 return -ENODEV; 1111 } 1112 1113 if (!(params->flags & I915_OVERLAY_ENABLE)) { 1114 drm_modeset_lock_all(dev); 1115 ret = intel_overlay_switch_off(overlay); 1116 drm_modeset_unlock_all(dev); 1117 1118 return ret; 1119 } 1120 1121 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id); 1122 if (!drmmode_crtc) 1123 return -ENOENT; 1124 crtc = to_intel_crtc(drmmode_crtc); 1125 1126 new_bo = i915_gem_object_lookup(file_priv, params->bo_handle); 1127 if (!new_bo) 1128 return -ENOENT; 1129 1130 drm_modeset_lock_all(dev); 1131 1132 if (i915_gem_object_is_tiled(new_bo)) { 1133 drm_dbg_kms(&dev_priv->drm, 1134 "buffer used for overlay image can not be tiled\n"); 1135 ret = -EINVAL; 1136 goto out_unlock; 1137 } 1138 1139 ret = intel_overlay_recover_from_interrupt(overlay); 1140 if (ret != 0) 1141 goto out_unlock; 1142 1143 if (overlay->crtc != crtc) { 1144 ret = intel_overlay_switch_off(overlay); 1145 if (ret != 0) 1146 goto out_unlock; 1147 1148 ret = check_overlay_possible_on_crtc(overlay, crtc); 1149 if (ret != 0) 1150 goto out_unlock; 1151 1152 overlay->crtc = crtc; 1153 crtc->overlay = overlay; 1154 1155 /* line too wide, i.e. one-line-mode */ 1156 if (crtc->config->pipe_src_w > 1024 && 1157 crtc->config->gmch_pfit.control & PFIT_ENABLE) { 1158 overlay->pfit_active = true; 1159 update_pfit_vscale_ratio(overlay); 1160 } else 1161 overlay->pfit_active = false; 1162 } 1163 1164 ret = check_overlay_dst(overlay, params); 1165 if (ret != 0) 1166 goto out_unlock; 1167 1168 if (overlay->pfit_active) { 1169 params->dst_y = (((u32)params->dst_y << 12) / 1170 overlay->pfit_vscale_ratio); 1171 /* shifting right rounds downwards, so add 1 */ 1172 params->dst_height = (((u32)params->dst_height << 12) / 1173 overlay->pfit_vscale_ratio) + 1; 1174 } 1175 1176 if (params->src_scan_height > params->src_height || 1177 params->src_scan_width > params->src_width) { 1178 ret = -EINVAL; 1179 goto out_unlock; 1180 } 1181 1182 ret = check_overlay_src(dev_priv, params, new_bo); 1183 if (ret != 0) 1184 goto out_unlock; 1185 1186 /* Check scaling after src size to prevent a divide-by-zero. */ 1187 ret = check_overlay_scaling(params); 1188 if (ret != 0) 1189 goto out_unlock; 1190 1191 ret = intel_overlay_do_put_image(overlay, new_bo, params); 1192 if (ret != 0) 1193 goto out_unlock; 1194 1195 drm_modeset_unlock_all(dev); 1196 i915_gem_object_put(new_bo); 1197 1198 return 0; 1199 1200 out_unlock: 1201 drm_modeset_unlock_all(dev); 1202 i915_gem_object_put(new_bo); 1203 1204 return ret; 1205 } 1206 1207 static void update_reg_attrs(struct intel_overlay *overlay, 1208 struct overlay_registers __iomem *regs) 1209 { 1210 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 1211 ®s->OCLRC0); 1212 iowrite32(overlay->saturation, ®s->OCLRC1); 1213 } 1214 1215 static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 1216 { 1217 int i; 1218 1219 if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 1220 return false; 1221 1222 for (i = 0; i < 3; i++) { 1223 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 1224 return false; 1225 } 1226 1227 return true; 1228 } 1229 1230 static bool check_gamma5_errata(u32 gamma5) 1231 { 1232 int i; 1233 1234 for (i = 0; i < 3; i++) { 1235 if (((gamma5 >> i*8) & 0xff) == 0x80) 1236 return false; 1237 } 1238 1239 return true; 1240 } 1241 1242 static int check_gamma(struct drm_intel_overlay_attrs *attrs) 1243 { 1244 if (!check_gamma_bounds(0, attrs->gamma0) || 1245 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 1246 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 1247 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 1248 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 1249 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 1250 !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 1251 return -EINVAL; 1252 1253 if (!check_gamma5_errata(attrs->gamma5)) 1254 return -EINVAL; 1255 1256 return 0; 1257 } 1258 1259 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1260 struct drm_file *file_priv) 1261 { 1262 struct drm_intel_overlay_attrs *attrs = data; 1263 struct drm_i915_private *dev_priv = to_i915(dev); 1264 struct intel_overlay *overlay; 1265 int ret; 1266 1267 overlay = dev_priv->overlay; 1268 if (!overlay) { 1269 drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n"); 1270 return -ENODEV; 1271 } 1272 1273 drm_modeset_lock_all(dev); 1274 1275 ret = -EINVAL; 1276 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 1277 attrs->color_key = overlay->color_key; 1278 attrs->brightness = overlay->brightness; 1279 attrs->contrast = overlay->contrast; 1280 attrs->saturation = overlay->saturation; 1281 1282 if (DISPLAY_VER(dev_priv) != 2) { 1283 attrs->gamma0 = intel_de_read(dev_priv, OGAMC0); 1284 attrs->gamma1 = intel_de_read(dev_priv, OGAMC1); 1285 attrs->gamma2 = intel_de_read(dev_priv, OGAMC2); 1286 attrs->gamma3 = intel_de_read(dev_priv, OGAMC3); 1287 attrs->gamma4 = intel_de_read(dev_priv, OGAMC4); 1288 attrs->gamma5 = intel_de_read(dev_priv, OGAMC5); 1289 } 1290 } else { 1291 if (attrs->brightness < -128 || attrs->brightness > 127) 1292 goto out_unlock; 1293 if (attrs->contrast > 255) 1294 goto out_unlock; 1295 if (attrs->saturation > 1023) 1296 goto out_unlock; 1297 1298 overlay->color_key = attrs->color_key; 1299 overlay->brightness = attrs->brightness; 1300 overlay->contrast = attrs->contrast; 1301 overlay->saturation = attrs->saturation; 1302 1303 update_reg_attrs(overlay, overlay->regs); 1304 1305 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1306 if (DISPLAY_VER(dev_priv) == 2) 1307 goto out_unlock; 1308 1309 if (overlay->active) { 1310 ret = -EBUSY; 1311 goto out_unlock; 1312 } 1313 1314 ret = check_gamma(attrs); 1315 if (ret) 1316 goto out_unlock; 1317 1318 intel_de_write(dev_priv, OGAMC0, attrs->gamma0); 1319 intel_de_write(dev_priv, OGAMC1, attrs->gamma1); 1320 intel_de_write(dev_priv, OGAMC2, attrs->gamma2); 1321 intel_de_write(dev_priv, OGAMC3, attrs->gamma3); 1322 intel_de_write(dev_priv, OGAMC4, attrs->gamma4); 1323 intel_de_write(dev_priv, OGAMC5, attrs->gamma5); 1324 } 1325 } 1326 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1327 1328 ret = 0; 1329 out_unlock: 1330 drm_modeset_unlock_all(dev); 1331 1332 return ret; 1333 } 1334 1335 static int get_registers(struct intel_overlay *overlay, bool use_phys) 1336 { 1337 struct drm_i915_private *i915 = overlay->i915; 1338 struct drm_i915_gem_object *obj; 1339 struct i915_vma *vma; 1340 int err; 1341 1342 obj = i915_gem_object_create_stolen(i915, PAGE_SIZE); 1343 if (IS_ERR(obj)) 1344 obj = i915_gem_object_create_internal(i915, PAGE_SIZE); 1345 if (IS_ERR(obj)) 1346 return PTR_ERR(obj); 1347 1348 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); 1349 if (IS_ERR(vma)) { 1350 err = PTR_ERR(vma); 1351 goto err_put_bo; 1352 } 1353 1354 if (use_phys) 1355 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl); 1356 else 1357 overlay->flip_addr = i915_ggtt_offset(vma); 1358 overlay->regs = i915_vma_pin_iomap(vma); 1359 i915_vma_unpin(vma); 1360 1361 if (IS_ERR(overlay->regs)) { 1362 err = PTR_ERR(overlay->regs); 1363 goto err_put_bo; 1364 } 1365 1366 overlay->reg_bo = obj; 1367 return 0; 1368 1369 err_put_bo: 1370 i915_gem_object_put(obj); 1371 return err; 1372 } 1373 1374 void intel_overlay_setup(struct drm_i915_private *dev_priv) 1375 { 1376 struct intel_overlay *overlay; 1377 struct intel_engine_cs *engine; 1378 int ret; 1379 1380 if (!HAS_OVERLAY(dev_priv)) 1381 return; 1382 1383 engine = dev_priv->gt.engine[RCS0]; 1384 if (!engine || !engine->kernel_context) 1385 return; 1386 1387 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 1388 if (!overlay) 1389 return; 1390 1391 overlay->i915 = dev_priv; 1392 overlay->context = engine->kernel_context; 1393 GEM_BUG_ON(!overlay->context); 1394 1395 overlay->color_key = 0x0101fe; 1396 overlay->color_key_enabled = true; 1397 overlay->brightness = -19; 1398 overlay->contrast = 75; 1399 overlay->saturation = 146; 1400 1401 i915_active_init(&overlay->last_flip, 1402 NULL, intel_overlay_last_flip_retire); 1403 1404 ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv)); 1405 if (ret) 1406 goto out_free; 1407 1408 memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1409 update_polyphase_filter(overlay->regs); 1410 update_reg_attrs(overlay, overlay->regs); 1411 1412 dev_priv->overlay = overlay; 1413 drm_info(&dev_priv->drm, "Initialized overlay support.\n"); 1414 return; 1415 1416 out_free: 1417 kfree(overlay); 1418 } 1419 1420 void intel_overlay_cleanup(struct drm_i915_private *dev_priv) 1421 { 1422 struct intel_overlay *overlay; 1423 1424 overlay = fetch_and_zero(&dev_priv->overlay); 1425 if (!overlay) 1426 return; 1427 1428 /* 1429 * The bo's should be free'd by the generic code already. 1430 * Furthermore modesetting teardown happens beforehand so the 1431 * hardware should be off already. 1432 */ 1433 drm_WARN_ON(&dev_priv->drm, overlay->active); 1434 1435 i915_gem_object_put(overlay->reg_bo); 1436 i915_active_fini(&overlay->last_flip); 1437 1438 kfree(overlay); 1439 } 1440 1441 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1442 1443 struct intel_overlay_error_state { 1444 struct overlay_registers regs; 1445 unsigned long base; 1446 u32 dovsta; 1447 u32 isr; 1448 }; 1449 1450 struct intel_overlay_error_state * 1451 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) 1452 { 1453 struct intel_overlay *overlay = dev_priv->overlay; 1454 struct intel_overlay_error_state *error; 1455 1456 if (!overlay || !overlay->active) 1457 return NULL; 1458 1459 error = kmalloc(sizeof(*error), GFP_ATOMIC); 1460 if (error == NULL) 1461 return NULL; 1462 1463 error->dovsta = intel_de_read(dev_priv, DOVSTA); 1464 error->isr = intel_de_read(dev_priv, GEN2_ISR); 1465 error->base = overlay->flip_addr; 1466 1467 memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs)); 1468 1469 return error; 1470 } 1471 1472 void 1473 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m, 1474 struct intel_overlay_error_state *error) 1475 { 1476 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1477 error->dovsta, error->isr); 1478 i915_error_printf(m, " Register file at 0x%08lx:\n", 1479 error->base); 1480 1481 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) 1482 P(OBUF_0Y); 1483 P(OBUF_1Y); 1484 P(OBUF_0U); 1485 P(OBUF_0V); 1486 P(OBUF_1U); 1487 P(OBUF_1V); 1488 P(OSTRIDE); 1489 P(YRGB_VPH); 1490 P(UV_VPH); 1491 P(HORZ_PH); 1492 P(INIT_PHS); 1493 P(DWINPOS); 1494 P(DWINSZ); 1495 P(SWIDTH); 1496 P(SWIDTHSW); 1497 P(SHEIGHT); 1498 P(YRGBSCALE); 1499 P(UVSCALE); 1500 P(OCLRC0); 1501 P(OCLRC1); 1502 P(DCLRKV); 1503 P(DCLRKM); 1504 P(SCLRKVH); 1505 P(SCLRKVL); 1506 P(SCLRKEN); 1507 P(OCONFIG); 1508 P(OCMD); 1509 P(OSTART_0Y); 1510 P(OSTART_1Y); 1511 P(OSTART_0U); 1512 P(OSTART_0V); 1513 P(OSTART_1U); 1514 P(OSTART_1V); 1515 P(OTILEOFF_0Y); 1516 P(OTILEOFF_1Y); 1517 P(OTILEOFF_0U); 1518 P(OTILEOFF_0V); 1519 P(OTILEOFF_1U); 1520 P(OTILEOFF_1V); 1521 P(FASTHSCALE); 1522 P(UVSCALEV); 1523 #undef P 1524 } 1525 1526 #endif 1527