1 /* 2 * Copyright © 2009 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel@ffwll.ch> 25 * 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27 */ 28 29 #include <drm/drm_fourcc.h> 30 #include <drm/i915_drm.h> 31 32 #include "gem/i915_gem_pm.h" 33 34 #include "i915_drv.h" 35 #include "i915_reg.h" 36 #include "intel_display_types.h" 37 #include "intel_frontbuffer.h" 38 #include "intel_overlay.h" 39 40 /* Limits for overlay size. According to intel doc, the real limits are: 41 * Y width: 4095, UV width (planar): 2047, Y height: 2047, 42 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 43 * the mininum of both. */ 44 #define IMAGE_MAX_WIDTH 2048 45 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 46 /* on 830 and 845 these large limits result in the card hanging */ 47 #define IMAGE_MAX_WIDTH_LEGACY 1024 48 #define IMAGE_MAX_HEIGHT_LEGACY 1088 49 50 /* overlay register definitions */ 51 /* OCMD register */ 52 #define OCMD_TILED_SURFACE (0x1<<19) 53 #define OCMD_MIRROR_MASK (0x3<<17) 54 #define OCMD_MIRROR_MODE (0x3<<17) 55 #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 56 #define OCMD_MIRROR_VERTICAL (0x2<<17) 57 #define OCMD_MIRROR_BOTH (0x3<<17) 58 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 59 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 60 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 61 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 62 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 63 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 64 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 65 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 66 #define OCMD_YUV_422_PACKED (0x8<<10) 67 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 68 #define OCMD_YUV_420_PLANAR (0xc<<10) 69 #define OCMD_YUV_422_PLANAR (0xd<<10) 70 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 71 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 72 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 73 #define OCMD_BUF_TYPE_MASK (0x1<<5) 74 #define OCMD_BUF_TYPE_FRAME (0x0<<5) 75 #define OCMD_BUF_TYPE_FIELD (0x1<<5) 76 #define OCMD_TEST_MODE (0x1<<4) 77 #define OCMD_BUFFER_SELECT (0x3<<2) 78 #define OCMD_BUFFER0 (0x0<<2) 79 #define OCMD_BUFFER1 (0x1<<2) 80 #define OCMD_FIELD_SELECT (0x1<<2) 81 #define OCMD_FIELD0 (0x0<<1) 82 #define OCMD_FIELD1 (0x1<<1) 83 #define OCMD_ENABLE (0x1<<0) 84 85 /* OCONFIG register */ 86 #define OCONF_PIPE_MASK (0x1<<18) 87 #define OCONF_PIPE_A (0x0<<18) 88 #define OCONF_PIPE_B (0x1<<18) 89 #define OCONF_GAMMA2_ENABLE (0x1<<16) 90 #define OCONF_CSC_MODE_BT601 (0x0<<5) 91 #define OCONF_CSC_MODE_BT709 (0x1<<5) 92 #define OCONF_CSC_BYPASS (0x1<<4) 93 #define OCONF_CC_OUT_8BIT (0x1<<3) 94 #define OCONF_TEST_MODE (0x1<<2) 95 #define OCONF_THREE_LINE_BUFFER (0x1<<0) 96 #define OCONF_TWO_LINE_BUFFER (0x0<<0) 97 98 /* DCLRKM (dst-key) register */ 99 #define DST_KEY_ENABLE (0x1<<31) 100 #define CLK_RGB24_MASK 0x0 101 #define CLK_RGB16_MASK 0x070307 102 #define CLK_RGB15_MASK 0x070707 103 #define CLK_RGB8I_MASK 0xffffff 104 105 #define RGB16_TO_COLORKEY(c) \ 106 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3)) 107 #define RGB15_TO_COLORKEY(c) \ 108 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3)) 109 110 /* overlay flip addr flag */ 111 #define OFC_UPDATE 0x1 112 113 /* polyphase filter coefficients */ 114 #define N_HORIZ_Y_TAPS 5 115 #define N_VERT_Y_TAPS 3 116 #define N_HORIZ_UV_TAPS 3 117 #define N_VERT_UV_TAPS 3 118 #define N_PHASES 17 119 #define MAX_TAPS 5 120 121 /* memory bufferd overlay registers */ 122 struct overlay_registers { 123 u32 OBUF_0Y; 124 u32 OBUF_1Y; 125 u32 OBUF_0U; 126 u32 OBUF_0V; 127 u32 OBUF_1U; 128 u32 OBUF_1V; 129 u32 OSTRIDE; 130 u32 YRGB_VPH; 131 u32 UV_VPH; 132 u32 HORZ_PH; 133 u32 INIT_PHS; 134 u32 DWINPOS; 135 u32 DWINSZ; 136 u32 SWIDTH; 137 u32 SWIDTHSW; 138 u32 SHEIGHT; 139 u32 YRGBSCALE; 140 u32 UVSCALE; 141 u32 OCLRC0; 142 u32 OCLRC1; 143 u32 DCLRKV; 144 u32 DCLRKM; 145 u32 SCLRKVH; 146 u32 SCLRKVL; 147 u32 SCLRKEN; 148 u32 OCONFIG; 149 u32 OCMD; 150 u32 RESERVED1; /* 0x6C */ 151 u32 OSTART_0Y; 152 u32 OSTART_1Y; 153 u32 OSTART_0U; 154 u32 OSTART_0V; 155 u32 OSTART_1U; 156 u32 OSTART_1V; 157 u32 OTILEOFF_0Y; 158 u32 OTILEOFF_1Y; 159 u32 OTILEOFF_0U; 160 u32 OTILEOFF_0V; 161 u32 OTILEOFF_1U; 162 u32 OTILEOFF_1V; 163 u32 FASTHSCALE; /* 0xA0 */ 164 u32 UVSCALEV; /* 0xA4 */ 165 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 166 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 167 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 168 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 169 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 170 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 171 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 172 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 173 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 174 }; 175 176 struct intel_overlay { 177 struct drm_i915_private *i915; 178 struct intel_context *context; 179 struct intel_crtc *crtc; 180 struct i915_vma *vma; 181 struct i915_vma *old_vma; 182 bool active; 183 bool pfit_active; 184 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 185 u32 color_key:24; 186 u32 color_key_enabled:1; 187 u32 brightness, contrast, saturation; 188 u32 old_xscale, old_yscale; 189 /* register access */ 190 struct drm_i915_gem_object *reg_bo; 191 struct overlay_registers __iomem *regs; 192 u32 flip_addr; 193 /* flip handling */ 194 struct i915_active last_flip; 195 void (*flip_complete)(struct intel_overlay *ovl); 196 }; 197 198 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, 199 bool enable) 200 { 201 struct pci_dev *pdev = dev_priv->drm.pdev; 202 u8 val; 203 204 /* WA_OVERLAY_CLKGATE:alm */ 205 if (enable) 206 I915_WRITE(DSPCLK_GATE_D, 0); 207 else 208 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 209 210 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 211 pci_bus_read_config_byte(pdev->bus, 212 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); 213 if (enable) 214 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; 215 else 216 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 217 pci_bus_write_config_byte(pdev->bus, 218 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 219 } 220 221 static struct i915_request * 222 alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *)) 223 { 224 struct i915_request *rq; 225 int err; 226 227 overlay->flip_complete = fn; 228 229 rq = i915_request_create(overlay->context); 230 if (IS_ERR(rq)) 231 return rq; 232 233 err = i915_active_add_request(&overlay->last_flip, rq); 234 if (err) { 235 i915_request_add(rq); 236 return ERR_PTR(err); 237 } 238 239 return rq; 240 } 241 242 /* overlay needs to be disable in OCMD reg */ 243 static int intel_overlay_on(struct intel_overlay *overlay) 244 { 245 struct drm_i915_private *dev_priv = overlay->i915; 246 struct i915_request *rq; 247 u32 *cs; 248 249 WARN_ON(overlay->active); 250 251 rq = alloc_request(overlay, NULL); 252 if (IS_ERR(rq)) 253 return PTR_ERR(rq); 254 255 cs = intel_ring_begin(rq, 4); 256 if (IS_ERR(cs)) { 257 i915_request_add(rq); 258 return PTR_ERR(cs); 259 } 260 261 overlay->active = true; 262 263 if (IS_I830(dev_priv)) 264 i830_overlay_clock_gating(dev_priv, false); 265 266 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 267 *cs++ = overlay->flip_addr | OFC_UPDATE; 268 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 269 *cs++ = MI_NOOP; 270 intel_ring_advance(rq, cs); 271 272 i915_request_add(rq); 273 274 return i915_active_wait(&overlay->last_flip); 275 } 276 277 static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 278 struct i915_vma *vma) 279 { 280 enum pipe pipe = overlay->crtc->pipe; 281 282 WARN_ON(overlay->old_vma); 283 284 intel_frontbuffer_track(overlay->vma ? overlay->vma->obj->frontbuffer : NULL, 285 vma ? vma->obj->frontbuffer : NULL, 286 INTEL_FRONTBUFFER_OVERLAY(pipe)); 287 288 intel_frontbuffer_flip_prepare(overlay->i915, 289 INTEL_FRONTBUFFER_OVERLAY(pipe)); 290 291 overlay->old_vma = overlay->vma; 292 if (vma) 293 overlay->vma = i915_vma_get(vma); 294 else 295 overlay->vma = NULL; 296 } 297 298 /* overlay needs to be enabled in OCMD reg */ 299 static int intel_overlay_continue(struct intel_overlay *overlay, 300 struct i915_vma *vma, 301 bool load_polyphase_filter) 302 { 303 struct drm_i915_private *dev_priv = overlay->i915; 304 struct i915_request *rq; 305 u32 flip_addr = overlay->flip_addr; 306 u32 tmp, *cs; 307 308 WARN_ON(!overlay->active); 309 310 if (load_polyphase_filter) 311 flip_addr |= OFC_UPDATE; 312 313 /* check for underruns */ 314 tmp = I915_READ(DOVSTA); 315 if (tmp & (1 << 17)) 316 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp); 317 318 rq = alloc_request(overlay, NULL); 319 if (IS_ERR(rq)) 320 return PTR_ERR(rq); 321 322 cs = intel_ring_begin(rq, 2); 323 if (IS_ERR(cs)) { 324 i915_request_add(rq); 325 return PTR_ERR(cs); 326 } 327 328 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 329 *cs++ = flip_addr; 330 intel_ring_advance(rq, cs); 331 332 intel_overlay_flip_prepare(overlay, vma); 333 i915_request_add(rq); 334 335 return 0; 336 } 337 338 static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 339 { 340 struct i915_vma *vma; 341 342 vma = fetch_and_zero(&overlay->old_vma); 343 if (WARN_ON(!vma)) 344 return; 345 346 intel_frontbuffer_flip_complete(overlay->i915, 347 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 348 349 i915_gem_object_unpin_from_display_plane(vma); 350 i915_vma_put(vma); 351 } 352 353 static void 354 intel_overlay_release_old_vid_tail(struct intel_overlay *overlay) 355 { 356 intel_overlay_release_old_vma(overlay); 357 } 358 359 static void intel_overlay_off_tail(struct intel_overlay *overlay) 360 { 361 struct drm_i915_private *dev_priv = overlay->i915; 362 363 intel_overlay_release_old_vma(overlay); 364 365 overlay->crtc->overlay = NULL; 366 overlay->crtc = NULL; 367 overlay->active = false; 368 369 if (IS_I830(dev_priv)) 370 i830_overlay_clock_gating(dev_priv, true); 371 } 372 373 static void 374 intel_overlay_last_flip_retire(struct i915_active *active) 375 { 376 struct intel_overlay *overlay = 377 container_of(active, typeof(*overlay), last_flip); 378 379 if (overlay->flip_complete) 380 overlay->flip_complete(overlay); 381 } 382 383 /* overlay needs to be disabled in OCMD reg */ 384 static int intel_overlay_off(struct intel_overlay *overlay) 385 { 386 struct i915_request *rq; 387 u32 *cs, flip_addr = overlay->flip_addr; 388 389 WARN_ON(!overlay->active); 390 391 /* According to intel docs the overlay hw may hang (when switching 392 * off) without loading the filter coeffs. It is however unclear whether 393 * this applies to the disabling of the overlay or to the switching off 394 * of the hw. Do it in both cases */ 395 flip_addr |= OFC_UPDATE; 396 397 rq = alloc_request(overlay, intel_overlay_off_tail); 398 if (IS_ERR(rq)) 399 return PTR_ERR(rq); 400 401 cs = intel_ring_begin(rq, 6); 402 if (IS_ERR(cs)) { 403 i915_request_add(rq); 404 return PTR_ERR(cs); 405 } 406 407 /* wait for overlay to go idle */ 408 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 409 *cs++ = flip_addr; 410 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 411 412 /* turn overlay off */ 413 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; 414 *cs++ = flip_addr; 415 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 416 417 intel_ring_advance(rq, cs); 418 419 intel_overlay_flip_prepare(overlay, NULL); 420 i915_request_add(rq); 421 422 return i915_active_wait(&overlay->last_flip); 423 } 424 425 /* recover from an interruption due to a signal 426 * We have to be careful not to repeat work forever an make forward progess. */ 427 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) 428 { 429 return i915_active_wait(&overlay->last_flip); 430 } 431 432 /* Wait for pending overlay flip and release old frame. 433 * Needs to be called before the overlay register are changed 434 * via intel_overlay_(un)map_regs 435 */ 436 static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 437 { 438 struct drm_i915_private *dev_priv = overlay->i915; 439 struct i915_request *rq; 440 u32 *cs; 441 442 /* 443 * Only wait if there is actually an old frame to release to 444 * guarantee forward progress. 445 */ 446 if (!overlay->old_vma) 447 return 0; 448 449 if (!(I915_READ(GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { 450 intel_overlay_release_old_vid_tail(overlay); 451 return 0; 452 } 453 454 rq = alloc_request(overlay, intel_overlay_release_old_vid_tail); 455 if (IS_ERR(rq)) 456 return PTR_ERR(rq); 457 458 cs = intel_ring_begin(rq, 2); 459 if (IS_ERR(cs)) { 460 i915_request_add(rq); 461 return PTR_ERR(cs); 462 } 463 464 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 465 *cs++ = MI_NOOP; 466 intel_ring_advance(rq, cs); 467 468 i915_request_add(rq); 469 470 return i915_active_wait(&overlay->last_flip); 471 } 472 473 void intel_overlay_reset(struct drm_i915_private *dev_priv) 474 { 475 struct intel_overlay *overlay = dev_priv->overlay; 476 477 if (!overlay) 478 return; 479 480 overlay->old_xscale = 0; 481 overlay->old_yscale = 0; 482 overlay->crtc = NULL; 483 overlay->active = false; 484 } 485 486 static int packed_depth_bytes(u32 format) 487 { 488 switch (format & I915_OVERLAY_DEPTH_MASK) { 489 case I915_OVERLAY_YUV422: 490 return 4; 491 case I915_OVERLAY_YUV411: 492 /* return 6; not implemented */ 493 default: 494 return -EINVAL; 495 } 496 } 497 498 static int packed_width_bytes(u32 format, short width) 499 { 500 switch (format & I915_OVERLAY_DEPTH_MASK) { 501 case I915_OVERLAY_YUV422: 502 return width << 1; 503 default: 504 return -EINVAL; 505 } 506 } 507 508 static int uv_hsubsampling(u32 format) 509 { 510 switch (format & I915_OVERLAY_DEPTH_MASK) { 511 case I915_OVERLAY_YUV422: 512 case I915_OVERLAY_YUV420: 513 return 2; 514 case I915_OVERLAY_YUV411: 515 case I915_OVERLAY_YUV410: 516 return 4; 517 default: 518 return -EINVAL; 519 } 520 } 521 522 static int uv_vsubsampling(u32 format) 523 { 524 switch (format & I915_OVERLAY_DEPTH_MASK) { 525 case I915_OVERLAY_YUV420: 526 case I915_OVERLAY_YUV410: 527 return 2; 528 case I915_OVERLAY_YUV422: 529 case I915_OVERLAY_YUV411: 530 return 1; 531 default: 532 return -EINVAL; 533 } 534 } 535 536 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) 537 { 538 u32 sw; 539 540 if (IS_GEN(dev_priv, 2)) 541 sw = ALIGN((offset & 31) + width, 32); 542 else 543 sw = ALIGN((offset & 63) + width, 64); 544 545 if (sw == 0) 546 return 0; 547 548 return (sw - 32) >> 3; 549 } 550 551 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 552 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 553 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 554 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 555 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 556 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 557 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 558 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 559 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 560 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 561 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 562 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 563 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 564 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 565 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 566 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 567 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 568 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 569 }; 570 571 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 572 [ 0] = { 0x3000, 0x1800, 0x1800, }, 573 [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 574 [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 575 [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 576 [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 577 [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 578 [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 579 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 580 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 581 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 582 [10] = { 0xb100, 0x1eb8, 0x3620, }, 583 [11] = { 0xb100, 0x1f18, 0x34a0, }, 584 [12] = { 0xb100, 0x1f68, 0x3360, }, 585 [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 586 [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 587 [15] = { 0xb060, 0x1ff0, 0x30a0, }, 588 [16] = { 0x3000, 0x0800, 0x3000, }, 589 }; 590 591 static void update_polyphase_filter(struct overlay_registers __iomem *regs) 592 { 593 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 594 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 595 sizeof(uv_static_hcoeffs)); 596 } 597 598 static bool update_scaling_factors(struct intel_overlay *overlay, 599 struct overlay_registers __iomem *regs, 600 struct drm_intel_overlay_put_image *params) 601 { 602 /* fixed point with a 12 bit shift */ 603 u32 xscale, yscale, xscale_UV, yscale_UV; 604 #define FP_SHIFT 12 605 #define FRACT_MASK 0xfff 606 bool scale_changed = false; 607 int uv_hscale = uv_hsubsampling(params->flags); 608 int uv_vscale = uv_vsubsampling(params->flags); 609 610 if (params->dst_width > 1) 611 xscale = ((params->src_scan_width - 1) << FP_SHIFT) / 612 params->dst_width; 613 else 614 xscale = 1 << FP_SHIFT; 615 616 if (params->dst_height > 1) 617 yscale = ((params->src_scan_height - 1) << FP_SHIFT) / 618 params->dst_height; 619 else 620 yscale = 1 << FP_SHIFT; 621 622 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 623 xscale_UV = xscale/uv_hscale; 624 yscale_UV = yscale/uv_vscale; 625 /* make the Y scale to UV scale ratio an exact multiply */ 626 xscale = xscale_UV * uv_hscale; 627 yscale = yscale_UV * uv_vscale; 628 /*} else { 629 xscale_UV = 0; 630 yscale_UV = 0; 631 }*/ 632 633 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 634 scale_changed = true; 635 overlay->old_xscale = xscale; 636 overlay->old_yscale = yscale; 637 638 iowrite32(((yscale & FRACT_MASK) << 20) | 639 ((xscale >> FP_SHIFT) << 16) | 640 ((xscale & FRACT_MASK) << 3), 641 ®s->YRGBSCALE); 642 643 iowrite32(((yscale_UV & FRACT_MASK) << 20) | 644 ((xscale_UV >> FP_SHIFT) << 16) | 645 ((xscale_UV & FRACT_MASK) << 3), 646 ®s->UVSCALE); 647 648 iowrite32((((yscale >> FP_SHIFT) << 16) | 649 ((yscale_UV >> FP_SHIFT) << 0)), 650 ®s->UVSCALEV); 651 652 if (scale_changed) 653 update_polyphase_filter(regs); 654 655 return scale_changed; 656 } 657 658 static void update_colorkey(struct intel_overlay *overlay, 659 struct overlay_registers __iomem *regs) 660 { 661 const struct intel_plane_state *state = 662 to_intel_plane_state(overlay->crtc->base.primary->state); 663 u32 key = overlay->color_key; 664 u32 format = 0; 665 u32 flags = 0; 666 667 if (overlay->color_key_enabled) 668 flags |= DST_KEY_ENABLE; 669 670 if (state->base.visible) 671 format = state->base.fb->format->format; 672 673 switch (format) { 674 case DRM_FORMAT_C8: 675 key = 0; 676 flags |= CLK_RGB8I_MASK; 677 break; 678 case DRM_FORMAT_XRGB1555: 679 key = RGB15_TO_COLORKEY(key); 680 flags |= CLK_RGB15_MASK; 681 break; 682 case DRM_FORMAT_RGB565: 683 key = RGB16_TO_COLORKEY(key); 684 flags |= CLK_RGB16_MASK; 685 break; 686 default: 687 flags |= CLK_RGB24_MASK; 688 break; 689 } 690 691 iowrite32(key, ®s->DCLRKV); 692 iowrite32(flags, ®s->DCLRKM); 693 } 694 695 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) 696 { 697 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 698 699 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 700 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 701 case I915_OVERLAY_YUV422: 702 cmd |= OCMD_YUV_422_PLANAR; 703 break; 704 case I915_OVERLAY_YUV420: 705 cmd |= OCMD_YUV_420_PLANAR; 706 break; 707 case I915_OVERLAY_YUV411: 708 case I915_OVERLAY_YUV410: 709 cmd |= OCMD_YUV_410_PLANAR; 710 break; 711 } 712 } else { /* YUV packed */ 713 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 714 case I915_OVERLAY_YUV422: 715 cmd |= OCMD_YUV_422_PACKED; 716 break; 717 case I915_OVERLAY_YUV411: 718 cmd |= OCMD_YUV_411_PACKED; 719 break; 720 } 721 722 switch (params->flags & I915_OVERLAY_SWAP_MASK) { 723 case I915_OVERLAY_NO_SWAP: 724 break; 725 case I915_OVERLAY_UV_SWAP: 726 cmd |= OCMD_UV_SWAP; 727 break; 728 case I915_OVERLAY_Y_SWAP: 729 cmd |= OCMD_Y_SWAP; 730 break; 731 case I915_OVERLAY_Y_AND_UV_SWAP: 732 cmd |= OCMD_Y_AND_UV_SWAP; 733 break; 734 } 735 } 736 737 return cmd; 738 } 739 740 static int intel_overlay_do_put_image(struct intel_overlay *overlay, 741 struct drm_i915_gem_object *new_bo, 742 struct drm_intel_overlay_put_image *params) 743 { 744 struct overlay_registers __iomem *regs = overlay->regs; 745 struct drm_i915_private *dev_priv = overlay->i915; 746 u32 swidth, swidthsw, sheight, ostride; 747 enum pipe pipe = overlay->crtc->pipe; 748 bool scale_changed = false; 749 struct i915_vma *vma; 750 int ret, tmp_width; 751 752 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 753 754 ret = intel_overlay_release_old_vid(overlay); 755 if (ret != 0) 756 return ret; 757 758 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 759 760 i915_gem_object_lock(new_bo); 761 vma = i915_gem_object_pin_to_display_plane(new_bo, 762 0, NULL, PIN_MAPPABLE); 763 i915_gem_object_unlock(new_bo); 764 if (IS_ERR(vma)) { 765 ret = PTR_ERR(vma); 766 goto out_pin_section; 767 } 768 intel_frontbuffer_flush(new_bo->frontbuffer, ORIGIN_DIRTYFB); 769 770 if (!overlay->active) { 771 u32 oconfig; 772 773 oconfig = OCONF_CC_OUT_8BIT; 774 if (IS_GEN(dev_priv, 4)) 775 oconfig |= OCONF_CSC_MODE_BT709; 776 oconfig |= pipe == 0 ? 777 OCONF_PIPE_A : OCONF_PIPE_B; 778 iowrite32(oconfig, ®s->OCONFIG); 779 780 ret = intel_overlay_on(overlay); 781 if (ret != 0) 782 goto out_unpin; 783 } 784 785 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS); 786 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ); 787 788 if (params->flags & I915_OVERLAY_YUV_PACKED) 789 tmp_width = packed_width_bytes(params->flags, 790 params->src_width); 791 else 792 tmp_width = params->src_width; 793 794 swidth = params->src_width; 795 swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width); 796 sheight = params->src_height; 797 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); 798 ostride = params->stride_Y; 799 800 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 801 int uv_hscale = uv_hsubsampling(params->flags); 802 int uv_vscale = uv_vsubsampling(params->flags); 803 u32 tmp_U, tmp_V; 804 805 swidth |= (params->src_width / uv_hscale) << 16; 806 sheight |= (params->src_height / uv_vscale) << 16; 807 808 tmp_U = calc_swidthsw(dev_priv, params->offset_U, 809 params->src_width / uv_hscale); 810 tmp_V = calc_swidthsw(dev_priv, params->offset_V, 811 params->src_width / uv_hscale); 812 swidthsw |= max(tmp_U, tmp_V) << 16; 813 814 iowrite32(i915_ggtt_offset(vma) + params->offset_U, 815 ®s->OBUF_0U); 816 iowrite32(i915_ggtt_offset(vma) + params->offset_V, 817 ®s->OBUF_0V); 818 819 ostride |= params->stride_UV << 16; 820 } 821 822 iowrite32(swidth, ®s->SWIDTH); 823 iowrite32(swidthsw, ®s->SWIDTHSW); 824 iowrite32(sheight, ®s->SHEIGHT); 825 iowrite32(ostride, ®s->OSTRIDE); 826 827 scale_changed = update_scaling_factors(overlay, regs, params); 828 829 update_colorkey(overlay, regs); 830 831 iowrite32(overlay_cmd_reg(params), ®s->OCMD); 832 833 ret = intel_overlay_continue(overlay, vma, scale_changed); 834 if (ret) 835 goto out_unpin; 836 837 return 0; 838 839 out_unpin: 840 i915_gem_object_unpin_from_display_plane(vma); 841 out_pin_section: 842 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 843 844 return ret; 845 } 846 847 int intel_overlay_switch_off(struct intel_overlay *overlay) 848 { 849 struct drm_i915_private *dev_priv = overlay->i915; 850 int ret; 851 852 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 853 854 ret = intel_overlay_recover_from_interrupt(overlay); 855 if (ret != 0) 856 return ret; 857 858 if (!overlay->active) 859 return 0; 860 861 ret = intel_overlay_release_old_vid(overlay); 862 if (ret != 0) 863 return ret; 864 865 iowrite32(0, &overlay->regs->OCMD); 866 867 return intel_overlay_off(overlay); 868 } 869 870 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 871 struct intel_crtc *crtc) 872 { 873 if (!crtc->active) 874 return -EINVAL; 875 876 /* can't use the overlay with double wide pipe */ 877 if (crtc->config->double_wide) 878 return -EINVAL; 879 880 return 0; 881 } 882 883 static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 884 { 885 struct drm_i915_private *dev_priv = overlay->i915; 886 u32 pfit_control = I915_READ(PFIT_CONTROL); 887 u32 ratio; 888 889 /* XXX: This is not the same logic as in the xorg driver, but more in 890 * line with the intel documentation for the i965 891 */ 892 if (INTEL_GEN(dev_priv) >= 4) { 893 /* on i965 use the PGM reg to read out the autoscaler values */ 894 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; 895 } else { 896 if (pfit_control & VERT_AUTO_SCALE) 897 ratio = I915_READ(PFIT_AUTO_RATIOS); 898 else 899 ratio = I915_READ(PFIT_PGM_RATIOS); 900 ratio >>= PFIT_VERT_SCALE_SHIFT; 901 } 902 903 overlay->pfit_vscale_ratio = ratio; 904 } 905 906 static int check_overlay_dst(struct intel_overlay *overlay, 907 struct drm_intel_overlay_put_image *rec) 908 { 909 const struct intel_crtc_state *pipe_config = 910 overlay->crtc->config; 911 912 if (rec->dst_x < pipe_config->pipe_src_w && 913 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && 914 rec->dst_y < pipe_config->pipe_src_h && 915 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) 916 return 0; 917 else 918 return -EINVAL; 919 } 920 921 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) 922 { 923 u32 tmp; 924 925 /* downscaling limit is 8.0 */ 926 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16; 927 if (tmp > 7) 928 return -EINVAL; 929 930 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16; 931 if (tmp > 7) 932 return -EINVAL; 933 934 return 0; 935 } 936 937 static int check_overlay_src(struct drm_i915_private *dev_priv, 938 struct drm_intel_overlay_put_image *rec, 939 struct drm_i915_gem_object *new_bo) 940 { 941 int uv_hscale = uv_hsubsampling(rec->flags); 942 int uv_vscale = uv_vsubsampling(rec->flags); 943 u32 stride_mask; 944 int depth; 945 u32 tmp; 946 947 /* check src dimensions */ 948 if (IS_I845G(dev_priv) || IS_I830(dev_priv)) { 949 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 950 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 951 return -EINVAL; 952 } else { 953 if (rec->src_height > IMAGE_MAX_HEIGHT || 954 rec->src_width > IMAGE_MAX_WIDTH) 955 return -EINVAL; 956 } 957 958 /* better safe than sorry, use 4 as the maximal subsampling ratio */ 959 if (rec->src_height < N_VERT_Y_TAPS*4 || 960 rec->src_width < N_HORIZ_Y_TAPS*4) 961 return -EINVAL; 962 963 /* check alignment constraints */ 964 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 965 case I915_OVERLAY_RGB: 966 /* not implemented */ 967 return -EINVAL; 968 969 case I915_OVERLAY_YUV_PACKED: 970 if (uv_vscale != 1) 971 return -EINVAL; 972 973 depth = packed_depth_bytes(rec->flags); 974 if (depth < 0) 975 return depth; 976 977 /* ignore UV planes */ 978 rec->stride_UV = 0; 979 rec->offset_U = 0; 980 rec->offset_V = 0; 981 /* check pixel alignment */ 982 if (rec->offset_Y % depth) 983 return -EINVAL; 984 break; 985 986 case I915_OVERLAY_YUV_PLANAR: 987 if (uv_vscale < 0 || uv_hscale < 0) 988 return -EINVAL; 989 /* no offset restrictions for planar formats */ 990 break; 991 992 default: 993 return -EINVAL; 994 } 995 996 if (rec->src_width % uv_hscale) 997 return -EINVAL; 998 999 /* stride checking */ 1000 if (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1001 stride_mask = 255; 1002 else 1003 stride_mask = 63; 1004 1005 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1006 return -EINVAL; 1007 if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512) 1008 return -EINVAL; 1009 1010 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1011 4096 : 8192; 1012 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 1013 return -EINVAL; 1014 1015 /* check buffer dimensions */ 1016 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1017 case I915_OVERLAY_RGB: 1018 case I915_OVERLAY_YUV_PACKED: 1019 /* always 4 Y values per depth pixels */ 1020 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 1021 return -EINVAL; 1022 1023 tmp = rec->stride_Y*rec->src_height; 1024 if (rec->offset_Y + tmp > new_bo->base.size) 1025 return -EINVAL; 1026 break; 1027 1028 case I915_OVERLAY_YUV_PLANAR: 1029 if (rec->src_width > rec->stride_Y) 1030 return -EINVAL; 1031 if (rec->src_width/uv_hscale > rec->stride_UV) 1032 return -EINVAL; 1033 1034 tmp = rec->stride_Y * rec->src_height; 1035 if (rec->offset_Y + tmp > new_bo->base.size) 1036 return -EINVAL; 1037 1038 tmp = rec->stride_UV * (rec->src_height / uv_vscale); 1039 if (rec->offset_U + tmp > new_bo->base.size || 1040 rec->offset_V + tmp > new_bo->base.size) 1041 return -EINVAL; 1042 break; 1043 } 1044 1045 return 0; 1046 } 1047 1048 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1049 struct drm_file *file_priv) 1050 { 1051 struct drm_intel_overlay_put_image *params = data; 1052 struct drm_i915_private *dev_priv = to_i915(dev); 1053 struct intel_overlay *overlay; 1054 struct drm_crtc *drmmode_crtc; 1055 struct intel_crtc *crtc; 1056 struct drm_i915_gem_object *new_bo; 1057 int ret; 1058 1059 overlay = dev_priv->overlay; 1060 if (!overlay) { 1061 DRM_DEBUG("userspace bug: no overlay\n"); 1062 return -ENODEV; 1063 } 1064 1065 if (!(params->flags & I915_OVERLAY_ENABLE)) { 1066 drm_modeset_lock_all(dev); 1067 ret = intel_overlay_switch_off(overlay); 1068 drm_modeset_unlock_all(dev); 1069 1070 return ret; 1071 } 1072 1073 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id); 1074 if (!drmmode_crtc) 1075 return -ENOENT; 1076 crtc = to_intel_crtc(drmmode_crtc); 1077 1078 new_bo = i915_gem_object_lookup(file_priv, params->bo_handle); 1079 if (!new_bo) 1080 return -ENOENT; 1081 1082 drm_modeset_lock_all(dev); 1083 1084 if (i915_gem_object_is_tiled(new_bo)) { 1085 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n"); 1086 ret = -EINVAL; 1087 goto out_unlock; 1088 } 1089 1090 ret = intel_overlay_recover_from_interrupt(overlay); 1091 if (ret != 0) 1092 goto out_unlock; 1093 1094 if (overlay->crtc != crtc) { 1095 ret = intel_overlay_switch_off(overlay); 1096 if (ret != 0) 1097 goto out_unlock; 1098 1099 ret = check_overlay_possible_on_crtc(overlay, crtc); 1100 if (ret != 0) 1101 goto out_unlock; 1102 1103 overlay->crtc = crtc; 1104 crtc->overlay = overlay; 1105 1106 /* line too wide, i.e. one-line-mode */ 1107 if (crtc->config->pipe_src_w > 1024 && 1108 crtc->config->gmch_pfit.control & PFIT_ENABLE) { 1109 overlay->pfit_active = true; 1110 update_pfit_vscale_ratio(overlay); 1111 } else 1112 overlay->pfit_active = false; 1113 } 1114 1115 ret = check_overlay_dst(overlay, params); 1116 if (ret != 0) 1117 goto out_unlock; 1118 1119 if (overlay->pfit_active) { 1120 params->dst_y = (((u32)params->dst_y << 12) / 1121 overlay->pfit_vscale_ratio); 1122 /* shifting right rounds downwards, so add 1 */ 1123 params->dst_height = (((u32)params->dst_height << 12) / 1124 overlay->pfit_vscale_ratio) + 1; 1125 } 1126 1127 if (params->src_scan_height > params->src_height || 1128 params->src_scan_width > params->src_width) { 1129 ret = -EINVAL; 1130 goto out_unlock; 1131 } 1132 1133 ret = check_overlay_src(dev_priv, params, new_bo); 1134 if (ret != 0) 1135 goto out_unlock; 1136 1137 /* Check scaling after src size to prevent a divide-by-zero. */ 1138 ret = check_overlay_scaling(params); 1139 if (ret != 0) 1140 goto out_unlock; 1141 1142 ret = intel_overlay_do_put_image(overlay, new_bo, params); 1143 if (ret != 0) 1144 goto out_unlock; 1145 1146 drm_modeset_unlock_all(dev); 1147 i915_gem_object_put(new_bo); 1148 1149 return 0; 1150 1151 out_unlock: 1152 drm_modeset_unlock_all(dev); 1153 i915_gem_object_put(new_bo); 1154 1155 return ret; 1156 } 1157 1158 static void update_reg_attrs(struct intel_overlay *overlay, 1159 struct overlay_registers __iomem *regs) 1160 { 1161 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 1162 ®s->OCLRC0); 1163 iowrite32(overlay->saturation, ®s->OCLRC1); 1164 } 1165 1166 static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 1167 { 1168 int i; 1169 1170 if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 1171 return false; 1172 1173 for (i = 0; i < 3; i++) { 1174 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 1175 return false; 1176 } 1177 1178 return true; 1179 } 1180 1181 static bool check_gamma5_errata(u32 gamma5) 1182 { 1183 int i; 1184 1185 for (i = 0; i < 3; i++) { 1186 if (((gamma5 >> i*8) & 0xff) == 0x80) 1187 return false; 1188 } 1189 1190 return true; 1191 } 1192 1193 static int check_gamma(struct drm_intel_overlay_attrs *attrs) 1194 { 1195 if (!check_gamma_bounds(0, attrs->gamma0) || 1196 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 1197 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 1198 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 1199 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 1200 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 1201 !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 1202 return -EINVAL; 1203 1204 if (!check_gamma5_errata(attrs->gamma5)) 1205 return -EINVAL; 1206 1207 return 0; 1208 } 1209 1210 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1211 struct drm_file *file_priv) 1212 { 1213 struct drm_intel_overlay_attrs *attrs = data; 1214 struct drm_i915_private *dev_priv = to_i915(dev); 1215 struct intel_overlay *overlay; 1216 int ret; 1217 1218 overlay = dev_priv->overlay; 1219 if (!overlay) { 1220 DRM_DEBUG("userspace bug: no overlay\n"); 1221 return -ENODEV; 1222 } 1223 1224 drm_modeset_lock_all(dev); 1225 1226 ret = -EINVAL; 1227 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 1228 attrs->color_key = overlay->color_key; 1229 attrs->brightness = overlay->brightness; 1230 attrs->contrast = overlay->contrast; 1231 attrs->saturation = overlay->saturation; 1232 1233 if (!IS_GEN(dev_priv, 2)) { 1234 attrs->gamma0 = I915_READ(OGAMC0); 1235 attrs->gamma1 = I915_READ(OGAMC1); 1236 attrs->gamma2 = I915_READ(OGAMC2); 1237 attrs->gamma3 = I915_READ(OGAMC3); 1238 attrs->gamma4 = I915_READ(OGAMC4); 1239 attrs->gamma5 = I915_READ(OGAMC5); 1240 } 1241 } else { 1242 if (attrs->brightness < -128 || attrs->brightness > 127) 1243 goto out_unlock; 1244 if (attrs->contrast > 255) 1245 goto out_unlock; 1246 if (attrs->saturation > 1023) 1247 goto out_unlock; 1248 1249 overlay->color_key = attrs->color_key; 1250 overlay->brightness = attrs->brightness; 1251 overlay->contrast = attrs->contrast; 1252 overlay->saturation = attrs->saturation; 1253 1254 update_reg_attrs(overlay, overlay->regs); 1255 1256 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1257 if (IS_GEN(dev_priv, 2)) 1258 goto out_unlock; 1259 1260 if (overlay->active) { 1261 ret = -EBUSY; 1262 goto out_unlock; 1263 } 1264 1265 ret = check_gamma(attrs); 1266 if (ret) 1267 goto out_unlock; 1268 1269 I915_WRITE(OGAMC0, attrs->gamma0); 1270 I915_WRITE(OGAMC1, attrs->gamma1); 1271 I915_WRITE(OGAMC2, attrs->gamma2); 1272 I915_WRITE(OGAMC3, attrs->gamma3); 1273 I915_WRITE(OGAMC4, attrs->gamma4); 1274 I915_WRITE(OGAMC5, attrs->gamma5); 1275 } 1276 } 1277 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1278 1279 ret = 0; 1280 out_unlock: 1281 drm_modeset_unlock_all(dev); 1282 1283 return ret; 1284 } 1285 1286 static int get_registers(struct intel_overlay *overlay, bool use_phys) 1287 { 1288 struct drm_i915_private *i915 = overlay->i915; 1289 struct drm_i915_gem_object *obj; 1290 struct i915_vma *vma; 1291 int err; 1292 1293 obj = i915_gem_object_create_stolen(i915, PAGE_SIZE); 1294 if (IS_ERR(obj)) 1295 obj = i915_gem_object_create_internal(i915, PAGE_SIZE); 1296 if (IS_ERR(obj)) 1297 return PTR_ERR(obj); 1298 1299 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); 1300 if (IS_ERR(vma)) { 1301 err = PTR_ERR(vma); 1302 goto err_put_bo; 1303 } 1304 1305 if (use_phys) 1306 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl); 1307 else 1308 overlay->flip_addr = i915_ggtt_offset(vma); 1309 overlay->regs = i915_vma_pin_iomap(vma); 1310 i915_vma_unpin(vma); 1311 1312 if (IS_ERR(overlay->regs)) { 1313 err = PTR_ERR(overlay->regs); 1314 goto err_put_bo; 1315 } 1316 1317 overlay->reg_bo = obj; 1318 return 0; 1319 1320 err_put_bo: 1321 i915_gem_object_put(obj); 1322 return err; 1323 } 1324 1325 void intel_overlay_setup(struct drm_i915_private *dev_priv) 1326 { 1327 struct intel_overlay *overlay; 1328 int ret; 1329 1330 if (!HAS_OVERLAY(dev_priv)) 1331 return; 1332 1333 if (!HAS_ENGINE(dev_priv, RCS0)) 1334 return; 1335 1336 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 1337 if (!overlay) 1338 return; 1339 1340 overlay->i915 = dev_priv; 1341 overlay->context = dev_priv->engine[RCS0]->kernel_context; 1342 GEM_BUG_ON(!overlay->context); 1343 1344 overlay->color_key = 0x0101fe; 1345 overlay->color_key_enabled = true; 1346 overlay->brightness = -19; 1347 overlay->contrast = 75; 1348 overlay->saturation = 146; 1349 1350 i915_active_init(&overlay->last_flip, 1351 NULL, intel_overlay_last_flip_retire); 1352 1353 ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv)); 1354 if (ret) 1355 goto out_free; 1356 1357 memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1358 update_polyphase_filter(overlay->regs); 1359 update_reg_attrs(overlay, overlay->regs); 1360 1361 dev_priv->overlay = overlay; 1362 DRM_INFO("Initialized overlay support.\n"); 1363 return; 1364 1365 out_free: 1366 kfree(overlay); 1367 } 1368 1369 void intel_overlay_cleanup(struct drm_i915_private *dev_priv) 1370 { 1371 struct intel_overlay *overlay; 1372 1373 overlay = fetch_and_zero(&dev_priv->overlay); 1374 if (!overlay) 1375 return; 1376 1377 /* 1378 * The bo's should be free'd by the generic code already. 1379 * Furthermore modesetting teardown happens beforehand so the 1380 * hardware should be off already. 1381 */ 1382 WARN_ON(overlay->active); 1383 1384 i915_gem_object_put(overlay->reg_bo); 1385 i915_active_fini(&overlay->last_flip); 1386 1387 kfree(overlay); 1388 } 1389 1390 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1391 1392 struct intel_overlay_error_state { 1393 struct overlay_registers regs; 1394 unsigned long base; 1395 u32 dovsta; 1396 u32 isr; 1397 }; 1398 1399 struct intel_overlay_error_state * 1400 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) 1401 { 1402 struct intel_overlay *overlay = dev_priv->overlay; 1403 struct intel_overlay_error_state *error; 1404 1405 if (!overlay || !overlay->active) 1406 return NULL; 1407 1408 error = kmalloc(sizeof(*error), GFP_ATOMIC); 1409 if (error == NULL) 1410 return NULL; 1411 1412 error->dovsta = I915_READ(DOVSTA); 1413 error->isr = I915_READ(GEN2_ISR); 1414 error->base = overlay->flip_addr; 1415 1416 memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs)); 1417 1418 return error; 1419 } 1420 1421 void 1422 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m, 1423 struct intel_overlay_error_state *error) 1424 { 1425 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1426 error->dovsta, error->isr); 1427 i915_error_printf(m, " Register file at 0x%08lx:\n", 1428 error->base); 1429 1430 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) 1431 P(OBUF_0Y); 1432 P(OBUF_1Y); 1433 P(OBUF_0U); 1434 P(OBUF_0V); 1435 P(OBUF_1U); 1436 P(OBUF_1V); 1437 P(OSTRIDE); 1438 P(YRGB_VPH); 1439 P(UV_VPH); 1440 P(HORZ_PH); 1441 P(INIT_PHS); 1442 P(DWINPOS); 1443 P(DWINSZ); 1444 P(SWIDTH); 1445 P(SWIDTHSW); 1446 P(SHEIGHT); 1447 P(YRGBSCALE); 1448 P(UVSCALE); 1449 P(OCLRC0); 1450 P(OCLRC1); 1451 P(DCLRKV); 1452 P(DCLRKM); 1453 P(SCLRKVH); 1454 P(SCLRKVL); 1455 P(SCLRKEN); 1456 P(OCONFIG); 1457 P(OCMD); 1458 P(OSTART_0Y); 1459 P(OSTART_1Y); 1460 P(OSTART_0U); 1461 P(OSTART_0V); 1462 P(OSTART_1U); 1463 P(OSTART_1V); 1464 P(OTILEOFF_0Y); 1465 P(OTILEOFF_1Y); 1466 P(OTILEOFF_0U); 1467 P(OTILEOFF_0V); 1468 P(OTILEOFF_1U); 1469 P(OTILEOFF_1V); 1470 P(FASTHSCALE); 1471 P(UVSCALEV); 1472 #undef P 1473 } 1474 1475 #endif 1476