1 /* 2 * Copyright © 2009 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel@ffwll.ch> 25 * 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27 */ 28 29 #include <drm/drm_fourcc.h> 30 31 #include "gem/i915_gem_pm.h" 32 #include "gt/intel_gpu_commands.h" 33 #include "gt/intel_ring.h" 34 35 #include "i915_drv.h" 36 #include "i915_reg.h" 37 #include "intel_de.h" 38 #include "intel_display_types.h" 39 #include "intel_frontbuffer.h" 40 #include "intel_overlay.h" 41 #include "intel_pci_config.h" 42 43 /* Limits for overlay size. According to intel doc, the real limits are: 44 * Y width: 4095, UV width (planar): 2047, Y height: 2047, 45 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 46 * the mininum of both. */ 47 #define IMAGE_MAX_WIDTH 2048 48 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 49 /* on 830 and 845 these large limits result in the card hanging */ 50 #define IMAGE_MAX_WIDTH_LEGACY 1024 51 #define IMAGE_MAX_HEIGHT_LEGACY 1088 52 53 /* overlay register definitions */ 54 /* OCMD register */ 55 #define OCMD_TILED_SURFACE (0x1<<19) 56 #define OCMD_MIRROR_MASK (0x3<<17) 57 #define OCMD_MIRROR_MODE (0x3<<17) 58 #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 59 #define OCMD_MIRROR_VERTICAL (0x2<<17) 60 #define OCMD_MIRROR_BOTH (0x3<<17) 61 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 62 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 63 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 64 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 65 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 66 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 67 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 68 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 69 #define OCMD_YUV_422_PACKED (0x8<<10) 70 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 71 #define OCMD_YUV_420_PLANAR (0xc<<10) 72 #define OCMD_YUV_422_PLANAR (0xd<<10) 73 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 74 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 75 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 76 #define OCMD_BUF_TYPE_MASK (0x1<<5) 77 #define OCMD_BUF_TYPE_FRAME (0x0<<5) 78 #define OCMD_BUF_TYPE_FIELD (0x1<<5) 79 #define OCMD_TEST_MODE (0x1<<4) 80 #define OCMD_BUFFER_SELECT (0x3<<2) 81 #define OCMD_BUFFER0 (0x0<<2) 82 #define OCMD_BUFFER1 (0x1<<2) 83 #define OCMD_FIELD_SELECT (0x1<<2) 84 #define OCMD_FIELD0 (0x0<<1) 85 #define OCMD_FIELD1 (0x1<<1) 86 #define OCMD_ENABLE (0x1<<0) 87 88 /* OCONFIG register */ 89 #define OCONF_PIPE_MASK (0x1<<18) 90 #define OCONF_PIPE_A (0x0<<18) 91 #define OCONF_PIPE_B (0x1<<18) 92 #define OCONF_GAMMA2_ENABLE (0x1<<16) 93 #define OCONF_CSC_MODE_BT601 (0x0<<5) 94 #define OCONF_CSC_MODE_BT709 (0x1<<5) 95 #define OCONF_CSC_BYPASS (0x1<<4) 96 #define OCONF_CC_OUT_8BIT (0x1<<3) 97 #define OCONF_TEST_MODE (0x1<<2) 98 #define OCONF_THREE_LINE_BUFFER (0x1<<0) 99 #define OCONF_TWO_LINE_BUFFER (0x0<<0) 100 101 /* DCLRKM (dst-key) register */ 102 #define DST_KEY_ENABLE (0x1<<31) 103 #define CLK_RGB24_MASK 0x0 104 #define CLK_RGB16_MASK 0x070307 105 #define CLK_RGB15_MASK 0x070707 106 107 #define RGB30_TO_COLORKEY(c) \ 108 ((((c) & 0x3fc00000) >> 6) | (((c) & 0x000ff000) >> 4) | (((c) & 0x000003fc) >> 2)) 109 #define RGB16_TO_COLORKEY(c) \ 110 ((((c) & 0xf800) << 8) | (((c) & 0x07e0) << 5) | (((c) & 0x001f) << 3)) 111 #define RGB15_TO_COLORKEY(c) \ 112 ((((c) & 0x7c00) << 9) | (((c) & 0x03e0) << 6) | (((c) & 0x001f) << 3)) 113 #define RGB8I_TO_COLORKEY(c) \ 114 ((((c) & 0xff) << 16) | (((c) & 0xff) << 8) | (((c) & 0xff) << 0)) 115 116 /* overlay flip addr flag */ 117 #define OFC_UPDATE 0x1 118 119 /* polyphase filter coefficients */ 120 #define N_HORIZ_Y_TAPS 5 121 #define N_VERT_Y_TAPS 3 122 #define N_HORIZ_UV_TAPS 3 123 #define N_VERT_UV_TAPS 3 124 #define N_PHASES 17 125 #define MAX_TAPS 5 126 127 /* memory bufferd overlay registers */ 128 struct overlay_registers { 129 u32 OBUF_0Y; 130 u32 OBUF_1Y; 131 u32 OBUF_0U; 132 u32 OBUF_0V; 133 u32 OBUF_1U; 134 u32 OBUF_1V; 135 u32 OSTRIDE; 136 u32 YRGB_VPH; 137 u32 UV_VPH; 138 u32 HORZ_PH; 139 u32 INIT_PHS; 140 u32 DWINPOS; 141 u32 DWINSZ; 142 u32 SWIDTH; 143 u32 SWIDTHSW; 144 u32 SHEIGHT; 145 u32 YRGBSCALE; 146 u32 UVSCALE; 147 u32 OCLRC0; 148 u32 OCLRC1; 149 u32 DCLRKV; 150 u32 DCLRKM; 151 u32 SCLRKVH; 152 u32 SCLRKVL; 153 u32 SCLRKEN; 154 u32 OCONFIG; 155 u32 OCMD; 156 u32 RESERVED1; /* 0x6C */ 157 u32 OSTART_0Y; 158 u32 OSTART_1Y; 159 u32 OSTART_0U; 160 u32 OSTART_0V; 161 u32 OSTART_1U; 162 u32 OSTART_1V; 163 u32 OTILEOFF_0Y; 164 u32 OTILEOFF_1Y; 165 u32 OTILEOFF_0U; 166 u32 OTILEOFF_0V; 167 u32 OTILEOFF_1U; 168 u32 OTILEOFF_1V; 169 u32 FASTHSCALE; /* 0xA0 */ 170 u32 UVSCALEV; /* 0xA4 */ 171 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 172 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 173 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 174 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 175 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 176 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 177 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 178 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 179 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 180 }; 181 182 struct intel_overlay { 183 struct drm_i915_private *i915; 184 struct intel_context *context; 185 struct intel_crtc *crtc; 186 struct i915_vma *vma; 187 struct i915_vma *old_vma; 188 struct intel_frontbuffer *frontbuffer; 189 bool active; 190 bool pfit_active; 191 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 192 u32 color_key:24; 193 u32 color_key_enabled:1; 194 u32 brightness, contrast, saturation; 195 u32 old_xscale, old_yscale; 196 /* register access */ 197 struct drm_i915_gem_object *reg_bo; 198 struct overlay_registers __iomem *regs; 199 u32 flip_addr; 200 /* flip handling */ 201 struct i915_active last_flip; 202 void (*flip_complete)(struct intel_overlay *ovl); 203 }; 204 205 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, 206 bool enable) 207 { 208 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 209 u8 val; 210 211 /* WA_OVERLAY_CLKGATE:alm */ 212 if (enable) 213 intel_de_write(dev_priv, DSPCLK_GATE_D, 0); 214 else 215 intel_de_write(dev_priv, DSPCLK_GATE_D, 216 OVRUNIT_CLOCK_GATE_DISABLE); 217 218 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 219 pci_bus_read_config_byte(pdev->bus, 220 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); 221 if (enable) 222 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; 223 else 224 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 225 pci_bus_write_config_byte(pdev->bus, 226 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 227 } 228 229 static struct i915_request * 230 alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *)) 231 { 232 struct i915_request *rq; 233 int err; 234 235 overlay->flip_complete = fn; 236 237 rq = i915_request_create(overlay->context); 238 if (IS_ERR(rq)) 239 return rq; 240 241 err = i915_active_add_request(&overlay->last_flip, rq); 242 if (err) { 243 i915_request_add(rq); 244 return ERR_PTR(err); 245 } 246 247 return rq; 248 } 249 250 /* overlay needs to be disable in OCMD reg */ 251 static int intel_overlay_on(struct intel_overlay *overlay) 252 { 253 struct drm_i915_private *dev_priv = overlay->i915; 254 struct i915_request *rq; 255 u32 *cs; 256 257 drm_WARN_ON(&dev_priv->drm, overlay->active); 258 259 rq = alloc_request(overlay, NULL); 260 if (IS_ERR(rq)) 261 return PTR_ERR(rq); 262 263 cs = intel_ring_begin(rq, 4); 264 if (IS_ERR(cs)) { 265 i915_request_add(rq); 266 return PTR_ERR(cs); 267 } 268 269 overlay->active = true; 270 271 if (IS_I830(dev_priv)) 272 i830_overlay_clock_gating(dev_priv, false); 273 274 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 275 *cs++ = overlay->flip_addr | OFC_UPDATE; 276 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 277 *cs++ = MI_NOOP; 278 intel_ring_advance(rq, cs); 279 280 i915_request_add(rq); 281 282 return i915_active_wait(&overlay->last_flip); 283 } 284 285 static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 286 struct i915_vma *vma) 287 { 288 enum pipe pipe = overlay->crtc->pipe; 289 struct intel_frontbuffer *frontbuffer = NULL; 290 291 drm_WARN_ON(&overlay->i915->drm, overlay->old_vma); 292 293 if (vma) 294 frontbuffer = intel_frontbuffer_get(vma->obj); 295 296 intel_frontbuffer_track(overlay->frontbuffer, frontbuffer, 297 INTEL_FRONTBUFFER_OVERLAY(pipe)); 298 299 if (overlay->frontbuffer) 300 intel_frontbuffer_put(overlay->frontbuffer); 301 overlay->frontbuffer = frontbuffer; 302 303 intel_frontbuffer_flip_prepare(overlay->i915, 304 INTEL_FRONTBUFFER_OVERLAY(pipe)); 305 306 overlay->old_vma = overlay->vma; 307 if (vma) 308 overlay->vma = i915_vma_get(vma); 309 else 310 overlay->vma = NULL; 311 } 312 313 /* overlay needs to be enabled in OCMD reg */ 314 static int intel_overlay_continue(struct intel_overlay *overlay, 315 struct i915_vma *vma, 316 bool load_polyphase_filter) 317 { 318 struct drm_i915_private *dev_priv = overlay->i915; 319 struct i915_request *rq; 320 u32 flip_addr = overlay->flip_addr; 321 u32 tmp, *cs; 322 323 drm_WARN_ON(&dev_priv->drm, !overlay->active); 324 325 if (load_polyphase_filter) 326 flip_addr |= OFC_UPDATE; 327 328 /* check for underruns */ 329 tmp = intel_de_read(dev_priv, DOVSTA); 330 if (tmp & (1 << 17)) 331 drm_dbg(&dev_priv->drm, "overlay underrun, DOVSTA: %x\n", tmp); 332 333 rq = alloc_request(overlay, NULL); 334 if (IS_ERR(rq)) 335 return PTR_ERR(rq); 336 337 cs = intel_ring_begin(rq, 2); 338 if (IS_ERR(cs)) { 339 i915_request_add(rq); 340 return PTR_ERR(cs); 341 } 342 343 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 344 *cs++ = flip_addr; 345 intel_ring_advance(rq, cs); 346 347 intel_overlay_flip_prepare(overlay, vma); 348 i915_request_add(rq); 349 350 return 0; 351 } 352 353 static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 354 { 355 struct i915_vma *vma; 356 357 vma = fetch_and_zero(&overlay->old_vma); 358 if (drm_WARN_ON(&overlay->i915->drm, !vma)) 359 return; 360 361 intel_frontbuffer_flip_complete(overlay->i915, 362 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 363 364 i915_vma_unpin(vma); 365 i915_vma_put(vma); 366 } 367 368 static void 369 intel_overlay_release_old_vid_tail(struct intel_overlay *overlay) 370 { 371 intel_overlay_release_old_vma(overlay); 372 } 373 374 static void intel_overlay_off_tail(struct intel_overlay *overlay) 375 { 376 struct drm_i915_private *dev_priv = overlay->i915; 377 378 intel_overlay_release_old_vma(overlay); 379 380 overlay->crtc->overlay = NULL; 381 overlay->crtc = NULL; 382 overlay->active = false; 383 384 if (IS_I830(dev_priv)) 385 i830_overlay_clock_gating(dev_priv, true); 386 } 387 388 static void intel_overlay_last_flip_retire(struct i915_active *active) 389 { 390 struct intel_overlay *overlay = 391 container_of(active, typeof(*overlay), last_flip); 392 393 if (overlay->flip_complete) 394 overlay->flip_complete(overlay); 395 } 396 397 /* overlay needs to be disabled in OCMD reg */ 398 static int intel_overlay_off(struct intel_overlay *overlay) 399 { 400 struct i915_request *rq; 401 u32 *cs, flip_addr = overlay->flip_addr; 402 403 drm_WARN_ON(&overlay->i915->drm, !overlay->active); 404 405 /* According to intel docs the overlay hw may hang (when switching 406 * off) without loading the filter coeffs. It is however unclear whether 407 * this applies to the disabling of the overlay or to the switching off 408 * of the hw. Do it in both cases */ 409 flip_addr |= OFC_UPDATE; 410 411 rq = alloc_request(overlay, intel_overlay_off_tail); 412 if (IS_ERR(rq)) 413 return PTR_ERR(rq); 414 415 cs = intel_ring_begin(rq, 6); 416 if (IS_ERR(cs)) { 417 i915_request_add(rq); 418 return PTR_ERR(cs); 419 } 420 421 /* wait for overlay to go idle */ 422 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 423 *cs++ = flip_addr; 424 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 425 426 /* turn overlay off */ 427 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; 428 *cs++ = flip_addr; 429 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 430 431 intel_ring_advance(rq, cs); 432 433 intel_overlay_flip_prepare(overlay, NULL); 434 i915_request_add(rq); 435 436 return i915_active_wait(&overlay->last_flip); 437 } 438 439 /* recover from an interruption due to a signal 440 * We have to be careful not to repeat work forever an make forward progess. */ 441 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) 442 { 443 return i915_active_wait(&overlay->last_flip); 444 } 445 446 /* Wait for pending overlay flip and release old frame. 447 * Needs to be called before the overlay register are changed 448 * via intel_overlay_(un)map_regs 449 */ 450 static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 451 { 452 struct drm_i915_private *dev_priv = overlay->i915; 453 struct i915_request *rq; 454 u32 *cs; 455 456 /* 457 * Only wait if there is actually an old frame to release to 458 * guarantee forward progress. 459 */ 460 if (!overlay->old_vma) 461 return 0; 462 463 if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { 464 intel_overlay_release_old_vid_tail(overlay); 465 return 0; 466 } 467 468 rq = alloc_request(overlay, intel_overlay_release_old_vid_tail); 469 if (IS_ERR(rq)) 470 return PTR_ERR(rq); 471 472 cs = intel_ring_begin(rq, 2); 473 if (IS_ERR(cs)) { 474 i915_request_add(rq); 475 return PTR_ERR(cs); 476 } 477 478 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 479 *cs++ = MI_NOOP; 480 intel_ring_advance(rq, cs); 481 482 i915_request_add(rq); 483 484 return i915_active_wait(&overlay->last_flip); 485 } 486 487 void intel_overlay_reset(struct drm_i915_private *dev_priv) 488 { 489 struct intel_overlay *overlay = dev_priv->overlay; 490 491 if (!overlay) 492 return; 493 494 overlay->old_xscale = 0; 495 overlay->old_yscale = 0; 496 overlay->crtc = NULL; 497 overlay->active = false; 498 } 499 500 static int packed_depth_bytes(u32 format) 501 { 502 switch (format & I915_OVERLAY_DEPTH_MASK) { 503 case I915_OVERLAY_YUV422: 504 return 4; 505 case I915_OVERLAY_YUV411: 506 /* return 6; not implemented */ 507 default: 508 return -EINVAL; 509 } 510 } 511 512 static int packed_width_bytes(u32 format, short width) 513 { 514 switch (format & I915_OVERLAY_DEPTH_MASK) { 515 case I915_OVERLAY_YUV422: 516 return width << 1; 517 default: 518 return -EINVAL; 519 } 520 } 521 522 static int uv_hsubsampling(u32 format) 523 { 524 switch (format & I915_OVERLAY_DEPTH_MASK) { 525 case I915_OVERLAY_YUV422: 526 case I915_OVERLAY_YUV420: 527 return 2; 528 case I915_OVERLAY_YUV411: 529 case I915_OVERLAY_YUV410: 530 return 4; 531 default: 532 return -EINVAL; 533 } 534 } 535 536 static int uv_vsubsampling(u32 format) 537 { 538 switch (format & I915_OVERLAY_DEPTH_MASK) { 539 case I915_OVERLAY_YUV420: 540 case I915_OVERLAY_YUV410: 541 return 2; 542 case I915_OVERLAY_YUV422: 543 case I915_OVERLAY_YUV411: 544 return 1; 545 default: 546 return -EINVAL; 547 } 548 } 549 550 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) 551 { 552 u32 sw; 553 554 if (DISPLAY_VER(dev_priv) == 2) 555 sw = ALIGN((offset & 31) + width, 32); 556 else 557 sw = ALIGN((offset & 63) + width, 64); 558 559 if (sw == 0) 560 return 0; 561 562 return (sw - 32) >> 3; 563 } 564 565 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 566 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 567 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 568 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 569 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 570 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 571 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 572 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 573 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 574 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 575 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 576 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 577 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 578 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 579 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 580 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 581 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 582 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 583 }; 584 585 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 586 [ 0] = { 0x3000, 0x1800, 0x1800, }, 587 [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 588 [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 589 [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 590 [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 591 [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 592 [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 593 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 594 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 595 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 596 [10] = { 0xb100, 0x1eb8, 0x3620, }, 597 [11] = { 0xb100, 0x1f18, 0x34a0, }, 598 [12] = { 0xb100, 0x1f68, 0x3360, }, 599 [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 600 [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 601 [15] = { 0xb060, 0x1ff0, 0x30a0, }, 602 [16] = { 0x3000, 0x0800, 0x3000, }, 603 }; 604 605 static void update_polyphase_filter(struct overlay_registers __iomem *regs) 606 { 607 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 608 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 609 sizeof(uv_static_hcoeffs)); 610 } 611 612 static bool update_scaling_factors(struct intel_overlay *overlay, 613 struct overlay_registers __iomem *regs, 614 struct drm_intel_overlay_put_image *params) 615 { 616 /* fixed point with a 12 bit shift */ 617 u32 xscale, yscale, xscale_UV, yscale_UV; 618 #define FP_SHIFT 12 619 #define FRACT_MASK 0xfff 620 bool scale_changed = false; 621 int uv_hscale = uv_hsubsampling(params->flags); 622 int uv_vscale = uv_vsubsampling(params->flags); 623 624 if (params->dst_width > 1) 625 xscale = ((params->src_scan_width - 1) << FP_SHIFT) / 626 params->dst_width; 627 else 628 xscale = 1 << FP_SHIFT; 629 630 if (params->dst_height > 1) 631 yscale = ((params->src_scan_height - 1) << FP_SHIFT) / 632 params->dst_height; 633 else 634 yscale = 1 << FP_SHIFT; 635 636 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 637 xscale_UV = xscale/uv_hscale; 638 yscale_UV = yscale/uv_vscale; 639 /* make the Y scale to UV scale ratio an exact multiply */ 640 xscale = xscale_UV * uv_hscale; 641 yscale = yscale_UV * uv_vscale; 642 /*} else { 643 xscale_UV = 0; 644 yscale_UV = 0; 645 }*/ 646 647 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 648 scale_changed = true; 649 overlay->old_xscale = xscale; 650 overlay->old_yscale = yscale; 651 652 iowrite32(((yscale & FRACT_MASK) << 20) | 653 ((xscale >> FP_SHIFT) << 16) | 654 ((xscale & FRACT_MASK) << 3), 655 ®s->YRGBSCALE); 656 657 iowrite32(((yscale_UV & FRACT_MASK) << 20) | 658 ((xscale_UV >> FP_SHIFT) << 16) | 659 ((xscale_UV & FRACT_MASK) << 3), 660 ®s->UVSCALE); 661 662 iowrite32((((yscale >> FP_SHIFT) << 16) | 663 ((yscale_UV >> FP_SHIFT) << 0)), 664 ®s->UVSCALEV); 665 666 if (scale_changed) 667 update_polyphase_filter(regs); 668 669 return scale_changed; 670 } 671 672 static void update_colorkey(struct intel_overlay *overlay, 673 struct overlay_registers __iomem *regs) 674 { 675 const struct intel_plane_state *state = 676 to_intel_plane_state(overlay->crtc->base.primary->state); 677 u32 key = overlay->color_key; 678 u32 format = 0; 679 u32 flags = 0; 680 681 if (overlay->color_key_enabled) 682 flags |= DST_KEY_ENABLE; 683 684 if (state->uapi.visible) 685 format = state->hw.fb->format->format; 686 687 switch (format) { 688 case DRM_FORMAT_C8: 689 key = RGB8I_TO_COLORKEY(key); 690 flags |= CLK_RGB24_MASK; 691 break; 692 case DRM_FORMAT_XRGB1555: 693 key = RGB15_TO_COLORKEY(key); 694 flags |= CLK_RGB15_MASK; 695 break; 696 case DRM_FORMAT_RGB565: 697 key = RGB16_TO_COLORKEY(key); 698 flags |= CLK_RGB16_MASK; 699 break; 700 case DRM_FORMAT_XRGB2101010: 701 case DRM_FORMAT_XBGR2101010: 702 key = RGB30_TO_COLORKEY(key); 703 flags |= CLK_RGB24_MASK; 704 break; 705 default: 706 flags |= CLK_RGB24_MASK; 707 break; 708 } 709 710 iowrite32(key, ®s->DCLRKV); 711 iowrite32(flags, ®s->DCLRKM); 712 } 713 714 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) 715 { 716 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 717 718 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 719 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 720 case I915_OVERLAY_YUV422: 721 cmd |= OCMD_YUV_422_PLANAR; 722 break; 723 case I915_OVERLAY_YUV420: 724 cmd |= OCMD_YUV_420_PLANAR; 725 break; 726 case I915_OVERLAY_YUV411: 727 case I915_OVERLAY_YUV410: 728 cmd |= OCMD_YUV_410_PLANAR; 729 break; 730 } 731 } else { /* YUV packed */ 732 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 733 case I915_OVERLAY_YUV422: 734 cmd |= OCMD_YUV_422_PACKED; 735 break; 736 case I915_OVERLAY_YUV411: 737 cmd |= OCMD_YUV_411_PACKED; 738 break; 739 } 740 741 switch (params->flags & I915_OVERLAY_SWAP_MASK) { 742 case I915_OVERLAY_NO_SWAP: 743 break; 744 case I915_OVERLAY_UV_SWAP: 745 cmd |= OCMD_UV_SWAP; 746 break; 747 case I915_OVERLAY_Y_SWAP: 748 cmd |= OCMD_Y_SWAP; 749 break; 750 case I915_OVERLAY_Y_AND_UV_SWAP: 751 cmd |= OCMD_Y_AND_UV_SWAP; 752 break; 753 } 754 } 755 756 return cmd; 757 } 758 759 static struct i915_vma *intel_overlay_pin_fb(struct drm_i915_gem_object *new_bo) 760 { 761 struct i915_gem_ww_ctx ww; 762 struct i915_vma *vma; 763 int ret; 764 765 i915_gem_ww_ctx_init(&ww, true); 766 retry: 767 ret = i915_gem_object_lock(new_bo, &ww); 768 if (!ret) { 769 vma = i915_gem_object_pin_to_display_plane(new_bo, &ww, 0, 770 NULL, PIN_MAPPABLE); 771 ret = PTR_ERR_OR_ZERO(vma); 772 } 773 if (ret == -EDEADLK) { 774 ret = i915_gem_ww_ctx_backoff(&ww); 775 if (!ret) 776 goto retry; 777 } 778 i915_gem_ww_ctx_fini(&ww); 779 if (ret) 780 return ERR_PTR(ret); 781 782 return vma; 783 } 784 785 static int intel_overlay_do_put_image(struct intel_overlay *overlay, 786 struct drm_i915_gem_object *new_bo, 787 struct drm_intel_overlay_put_image *params) 788 { 789 struct overlay_registers __iomem *regs = overlay->regs; 790 struct drm_i915_private *dev_priv = overlay->i915; 791 u32 swidth, swidthsw, sheight, ostride; 792 enum pipe pipe = overlay->crtc->pipe; 793 bool scale_changed = false; 794 struct i915_vma *vma; 795 int ret, tmp_width; 796 797 drm_WARN_ON(&dev_priv->drm, 798 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 799 800 ret = intel_overlay_release_old_vid(overlay); 801 if (ret != 0) 802 return ret; 803 804 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 805 806 vma = intel_overlay_pin_fb(new_bo); 807 if (IS_ERR(vma)) { 808 ret = PTR_ERR(vma); 809 goto out_pin_section; 810 } 811 812 i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB); 813 814 if (!overlay->active) { 815 const struct intel_crtc_state *crtc_state = 816 overlay->crtc->config; 817 u32 oconfig = 0; 818 819 if (crtc_state->gamma_enable && 820 crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 821 oconfig |= OCONF_CC_OUT_8BIT; 822 if (crtc_state->gamma_enable) 823 oconfig |= OCONF_GAMMA2_ENABLE; 824 if (DISPLAY_VER(dev_priv) == 4) 825 oconfig |= OCONF_CSC_MODE_BT709; 826 oconfig |= pipe == 0 ? 827 OCONF_PIPE_A : OCONF_PIPE_B; 828 iowrite32(oconfig, ®s->OCONFIG); 829 830 ret = intel_overlay_on(overlay); 831 if (ret != 0) 832 goto out_unpin; 833 } 834 835 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS); 836 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ); 837 838 if (params->flags & I915_OVERLAY_YUV_PACKED) 839 tmp_width = packed_width_bytes(params->flags, 840 params->src_width); 841 else 842 tmp_width = params->src_width; 843 844 swidth = params->src_width; 845 swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width); 846 sheight = params->src_height; 847 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); 848 ostride = params->stride_Y; 849 850 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 851 int uv_hscale = uv_hsubsampling(params->flags); 852 int uv_vscale = uv_vsubsampling(params->flags); 853 u32 tmp_U, tmp_V; 854 855 swidth |= (params->src_width / uv_hscale) << 16; 856 sheight |= (params->src_height / uv_vscale) << 16; 857 858 tmp_U = calc_swidthsw(dev_priv, params->offset_U, 859 params->src_width / uv_hscale); 860 tmp_V = calc_swidthsw(dev_priv, params->offset_V, 861 params->src_width / uv_hscale); 862 swidthsw |= max(tmp_U, tmp_V) << 16; 863 864 iowrite32(i915_ggtt_offset(vma) + params->offset_U, 865 ®s->OBUF_0U); 866 iowrite32(i915_ggtt_offset(vma) + params->offset_V, 867 ®s->OBUF_0V); 868 869 ostride |= params->stride_UV << 16; 870 } 871 872 iowrite32(swidth, ®s->SWIDTH); 873 iowrite32(swidthsw, ®s->SWIDTHSW); 874 iowrite32(sheight, ®s->SHEIGHT); 875 iowrite32(ostride, ®s->OSTRIDE); 876 877 scale_changed = update_scaling_factors(overlay, regs, params); 878 879 update_colorkey(overlay, regs); 880 881 iowrite32(overlay_cmd_reg(params), ®s->OCMD); 882 883 ret = intel_overlay_continue(overlay, vma, scale_changed); 884 if (ret) 885 goto out_unpin; 886 887 return 0; 888 889 out_unpin: 890 i915_vma_unpin(vma); 891 out_pin_section: 892 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 893 894 return ret; 895 } 896 897 int intel_overlay_switch_off(struct intel_overlay *overlay) 898 { 899 struct drm_i915_private *dev_priv = overlay->i915; 900 int ret; 901 902 drm_WARN_ON(&dev_priv->drm, 903 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 904 905 ret = intel_overlay_recover_from_interrupt(overlay); 906 if (ret != 0) 907 return ret; 908 909 if (!overlay->active) 910 return 0; 911 912 ret = intel_overlay_release_old_vid(overlay); 913 if (ret != 0) 914 return ret; 915 916 iowrite32(0, &overlay->regs->OCMD); 917 918 return intel_overlay_off(overlay); 919 } 920 921 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 922 struct intel_crtc *crtc) 923 { 924 if (!crtc->active) 925 return -EINVAL; 926 927 /* can't use the overlay with double wide pipe */ 928 if (crtc->config->double_wide) 929 return -EINVAL; 930 931 return 0; 932 } 933 934 static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 935 { 936 struct drm_i915_private *dev_priv = overlay->i915; 937 u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL); 938 u32 ratio; 939 940 /* XXX: This is not the same logic as in the xorg driver, but more in 941 * line with the intel documentation for the i965 942 */ 943 if (DISPLAY_VER(dev_priv) >= 4) { 944 /* on i965 use the PGM reg to read out the autoscaler values */ 945 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; 946 } else { 947 if (pfit_control & VERT_AUTO_SCALE) 948 ratio = intel_de_read(dev_priv, PFIT_AUTO_RATIOS); 949 else 950 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS); 951 ratio >>= PFIT_VERT_SCALE_SHIFT; 952 } 953 954 overlay->pfit_vscale_ratio = ratio; 955 } 956 957 static int check_overlay_dst(struct intel_overlay *overlay, 958 struct drm_intel_overlay_put_image *rec) 959 { 960 const struct intel_crtc_state *pipe_config = 961 overlay->crtc->config; 962 963 if (rec->dst_x < pipe_config->pipe_src_w && 964 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && 965 rec->dst_y < pipe_config->pipe_src_h && 966 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) 967 return 0; 968 else 969 return -EINVAL; 970 } 971 972 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) 973 { 974 u32 tmp; 975 976 /* downscaling limit is 8.0 */ 977 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16; 978 if (tmp > 7) 979 return -EINVAL; 980 981 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16; 982 if (tmp > 7) 983 return -EINVAL; 984 985 return 0; 986 } 987 988 static int check_overlay_src(struct drm_i915_private *dev_priv, 989 struct drm_intel_overlay_put_image *rec, 990 struct drm_i915_gem_object *new_bo) 991 { 992 int uv_hscale = uv_hsubsampling(rec->flags); 993 int uv_vscale = uv_vsubsampling(rec->flags); 994 u32 stride_mask; 995 int depth; 996 u32 tmp; 997 998 /* check src dimensions */ 999 if (IS_I845G(dev_priv) || IS_I830(dev_priv)) { 1000 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 1001 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 1002 return -EINVAL; 1003 } else { 1004 if (rec->src_height > IMAGE_MAX_HEIGHT || 1005 rec->src_width > IMAGE_MAX_WIDTH) 1006 return -EINVAL; 1007 } 1008 1009 /* better safe than sorry, use 4 as the maximal subsampling ratio */ 1010 if (rec->src_height < N_VERT_Y_TAPS*4 || 1011 rec->src_width < N_HORIZ_Y_TAPS*4) 1012 return -EINVAL; 1013 1014 /* check alignment constraints */ 1015 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1016 case I915_OVERLAY_RGB: 1017 /* not implemented */ 1018 return -EINVAL; 1019 1020 case I915_OVERLAY_YUV_PACKED: 1021 if (uv_vscale != 1) 1022 return -EINVAL; 1023 1024 depth = packed_depth_bytes(rec->flags); 1025 if (depth < 0) 1026 return depth; 1027 1028 /* ignore UV planes */ 1029 rec->stride_UV = 0; 1030 rec->offset_U = 0; 1031 rec->offset_V = 0; 1032 /* check pixel alignment */ 1033 if (rec->offset_Y % depth) 1034 return -EINVAL; 1035 break; 1036 1037 case I915_OVERLAY_YUV_PLANAR: 1038 if (uv_vscale < 0 || uv_hscale < 0) 1039 return -EINVAL; 1040 /* no offset restrictions for planar formats */ 1041 break; 1042 1043 default: 1044 return -EINVAL; 1045 } 1046 1047 if (rec->src_width % uv_hscale) 1048 return -EINVAL; 1049 1050 /* stride checking */ 1051 if (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1052 stride_mask = 255; 1053 else 1054 stride_mask = 63; 1055 1056 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1057 return -EINVAL; 1058 if (DISPLAY_VER(dev_priv) == 4 && rec->stride_Y < 512) 1059 return -EINVAL; 1060 1061 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1062 4096 : 8192; 1063 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 1064 return -EINVAL; 1065 1066 /* check buffer dimensions */ 1067 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1068 case I915_OVERLAY_RGB: 1069 case I915_OVERLAY_YUV_PACKED: 1070 /* always 4 Y values per depth pixels */ 1071 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 1072 return -EINVAL; 1073 1074 tmp = rec->stride_Y*rec->src_height; 1075 if (rec->offset_Y + tmp > new_bo->base.size) 1076 return -EINVAL; 1077 break; 1078 1079 case I915_OVERLAY_YUV_PLANAR: 1080 if (rec->src_width > rec->stride_Y) 1081 return -EINVAL; 1082 if (rec->src_width/uv_hscale > rec->stride_UV) 1083 return -EINVAL; 1084 1085 tmp = rec->stride_Y * rec->src_height; 1086 if (rec->offset_Y + tmp > new_bo->base.size) 1087 return -EINVAL; 1088 1089 tmp = rec->stride_UV * (rec->src_height / uv_vscale); 1090 if (rec->offset_U + tmp > new_bo->base.size || 1091 rec->offset_V + tmp > new_bo->base.size) 1092 return -EINVAL; 1093 break; 1094 } 1095 1096 return 0; 1097 } 1098 1099 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1100 struct drm_file *file_priv) 1101 { 1102 struct drm_intel_overlay_put_image *params = data; 1103 struct drm_i915_private *dev_priv = to_i915(dev); 1104 struct intel_overlay *overlay; 1105 struct drm_crtc *drmmode_crtc; 1106 struct intel_crtc *crtc; 1107 struct drm_i915_gem_object *new_bo; 1108 int ret; 1109 1110 overlay = dev_priv->overlay; 1111 if (!overlay) { 1112 drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n"); 1113 return -ENODEV; 1114 } 1115 1116 if (!(params->flags & I915_OVERLAY_ENABLE)) { 1117 drm_modeset_lock_all(dev); 1118 ret = intel_overlay_switch_off(overlay); 1119 drm_modeset_unlock_all(dev); 1120 1121 return ret; 1122 } 1123 1124 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id); 1125 if (!drmmode_crtc) 1126 return -ENOENT; 1127 crtc = to_intel_crtc(drmmode_crtc); 1128 1129 new_bo = i915_gem_object_lookup(file_priv, params->bo_handle); 1130 if (!new_bo) 1131 return -ENOENT; 1132 1133 drm_modeset_lock_all(dev); 1134 1135 if (i915_gem_object_is_tiled(new_bo)) { 1136 drm_dbg_kms(&dev_priv->drm, 1137 "buffer used for overlay image can not be tiled\n"); 1138 ret = -EINVAL; 1139 goto out_unlock; 1140 } 1141 1142 ret = intel_overlay_recover_from_interrupt(overlay); 1143 if (ret != 0) 1144 goto out_unlock; 1145 1146 if (overlay->crtc != crtc) { 1147 ret = intel_overlay_switch_off(overlay); 1148 if (ret != 0) 1149 goto out_unlock; 1150 1151 ret = check_overlay_possible_on_crtc(overlay, crtc); 1152 if (ret != 0) 1153 goto out_unlock; 1154 1155 overlay->crtc = crtc; 1156 crtc->overlay = overlay; 1157 1158 /* line too wide, i.e. one-line-mode */ 1159 if (crtc->config->pipe_src_w > 1024 && 1160 crtc->config->gmch_pfit.control & PFIT_ENABLE) { 1161 overlay->pfit_active = true; 1162 update_pfit_vscale_ratio(overlay); 1163 } else 1164 overlay->pfit_active = false; 1165 } 1166 1167 ret = check_overlay_dst(overlay, params); 1168 if (ret != 0) 1169 goto out_unlock; 1170 1171 if (overlay->pfit_active) { 1172 params->dst_y = (((u32)params->dst_y << 12) / 1173 overlay->pfit_vscale_ratio); 1174 /* shifting right rounds downwards, so add 1 */ 1175 params->dst_height = (((u32)params->dst_height << 12) / 1176 overlay->pfit_vscale_ratio) + 1; 1177 } 1178 1179 if (params->src_scan_height > params->src_height || 1180 params->src_scan_width > params->src_width) { 1181 ret = -EINVAL; 1182 goto out_unlock; 1183 } 1184 1185 ret = check_overlay_src(dev_priv, params, new_bo); 1186 if (ret != 0) 1187 goto out_unlock; 1188 1189 /* Check scaling after src size to prevent a divide-by-zero. */ 1190 ret = check_overlay_scaling(params); 1191 if (ret != 0) 1192 goto out_unlock; 1193 1194 ret = intel_overlay_do_put_image(overlay, new_bo, params); 1195 if (ret != 0) 1196 goto out_unlock; 1197 1198 drm_modeset_unlock_all(dev); 1199 i915_gem_object_put(new_bo); 1200 1201 return 0; 1202 1203 out_unlock: 1204 drm_modeset_unlock_all(dev); 1205 i915_gem_object_put(new_bo); 1206 1207 return ret; 1208 } 1209 1210 static void update_reg_attrs(struct intel_overlay *overlay, 1211 struct overlay_registers __iomem *regs) 1212 { 1213 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 1214 ®s->OCLRC0); 1215 iowrite32(overlay->saturation, ®s->OCLRC1); 1216 } 1217 1218 static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 1219 { 1220 int i; 1221 1222 if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 1223 return false; 1224 1225 for (i = 0; i < 3; i++) { 1226 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 1227 return false; 1228 } 1229 1230 return true; 1231 } 1232 1233 static bool check_gamma5_errata(u32 gamma5) 1234 { 1235 int i; 1236 1237 for (i = 0; i < 3; i++) { 1238 if (((gamma5 >> i*8) & 0xff) == 0x80) 1239 return false; 1240 } 1241 1242 return true; 1243 } 1244 1245 static int check_gamma(struct drm_intel_overlay_attrs *attrs) 1246 { 1247 if (!check_gamma_bounds(0, attrs->gamma0) || 1248 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 1249 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 1250 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 1251 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 1252 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 1253 !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 1254 return -EINVAL; 1255 1256 if (!check_gamma5_errata(attrs->gamma5)) 1257 return -EINVAL; 1258 1259 return 0; 1260 } 1261 1262 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1263 struct drm_file *file_priv) 1264 { 1265 struct drm_intel_overlay_attrs *attrs = data; 1266 struct drm_i915_private *dev_priv = to_i915(dev); 1267 struct intel_overlay *overlay; 1268 int ret; 1269 1270 overlay = dev_priv->overlay; 1271 if (!overlay) { 1272 drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n"); 1273 return -ENODEV; 1274 } 1275 1276 drm_modeset_lock_all(dev); 1277 1278 ret = -EINVAL; 1279 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 1280 attrs->color_key = overlay->color_key; 1281 attrs->brightness = overlay->brightness; 1282 attrs->contrast = overlay->contrast; 1283 attrs->saturation = overlay->saturation; 1284 1285 if (DISPLAY_VER(dev_priv) != 2) { 1286 attrs->gamma0 = intel_de_read(dev_priv, OGAMC0); 1287 attrs->gamma1 = intel_de_read(dev_priv, OGAMC1); 1288 attrs->gamma2 = intel_de_read(dev_priv, OGAMC2); 1289 attrs->gamma3 = intel_de_read(dev_priv, OGAMC3); 1290 attrs->gamma4 = intel_de_read(dev_priv, OGAMC4); 1291 attrs->gamma5 = intel_de_read(dev_priv, OGAMC5); 1292 } 1293 } else { 1294 if (attrs->brightness < -128 || attrs->brightness > 127) 1295 goto out_unlock; 1296 if (attrs->contrast > 255) 1297 goto out_unlock; 1298 if (attrs->saturation > 1023) 1299 goto out_unlock; 1300 1301 overlay->color_key = attrs->color_key; 1302 overlay->brightness = attrs->brightness; 1303 overlay->contrast = attrs->contrast; 1304 overlay->saturation = attrs->saturation; 1305 1306 update_reg_attrs(overlay, overlay->regs); 1307 1308 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1309 if (DISPLAY_VER(dev_priv) == 2) 1310 goto out_unlock; 1311 1312 if (overlay->active) { 1313 ret = -EBUSY; 1314 goto out_unlock; 1315 } 1316 1317 ret = check_gamma(attrs); 1318 if (ret) 1319 goto out_unlock; 1320 1321 intel_de_write(dev_priv, OGAMC0, attrs->gamma0); 1322 intel_de_write(dev_priv, OGAMC1, attrs->gamma1); 1323 intel_de_write(dev_priv, OGAMC2, attrs->gamma2); 1324 intel_de_write(dev_priv, OGAMC3, attrs->gamma3); 1325 intel_de_write(dev_priv, OGAMC4, attrs->gamma4); 1326 intel_de_write(dev_priv, OGAMC5, attrs->gamma5); 1327 } 1328 } 1329 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1330 1331 ret = 0; 1332 out_unlock: 1333 drm_modeset_unlock_all(dev); 1334 1335 return ret; 1336 } 1337 1338 static int get_registers(struct intel_overlay *overlay, bool use_phys) 1339 { 1340 struct drm_i915_private *i915 = overlay->i915; 1341 struct drm_i915_gem_object *obj; 1342 struct i915_vma *vma; 1343 int err; 1344 1345 obj = i915_gem_object_create_stolen(i915, PAGE_SIZE); 1346 if (IS_ERR(obj)) 1347 obj = i915_gem_object_create_internal(i915, PAGE_SIZE); 1348 if (IS_ERR(obj)) 1349 return PTR_ERR(obj); 1350 1351 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); 1352 if (IS_ERR(vma)) { 1353 err = PTR_ERR(vma); 1354 goto err_put_bo; 1355 } 1356 1357 if (use_phys) 1358 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl); 1359 else 1360 overlay->flip_addr = i915_ggtt_offset(vma); 1361 overlay->regs = i915_vma_pin_iomap(vma); 1362 i915_vma_unpin(vma); 1363 1364 if (IS_ERR(overlay->regs)) { 1365 err = PTR_ERR(overlay->regs); 1366 goto err_put_bo; 1367 } 1368 1369 overlay->reg_bo = obj; 1370 return 0; 1371 1372 err_put_bo: 1373 i915_gem_object_put(obj); 1374 return err; 1375 } 1376 1377 void intel_overlay_setup(struct drm_i915_private *dev_priv) 1378 { 1379 struct intel_overlay *overlay; 1380 struct intel_engine_cs *engine; 1381 int ret; 1382 1383 if (!HAS_OVERLAY(dev_priv)) 1384 return; 1385 1386 engine = dev_priv->gt.engine[RCS0]; 1387 if (!engine || !engine->kernel_context) 1388 return; 1389 1390 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 1391 if (!overlay) 1392 return; 1393 1394 overlay->i915 = dev_priv; 1395 overlay->context = engine->kernel_context; 1396 GEM_BUG_ON(!overlay->context); 1397 1398 overlay->color_key = 0x0101fe; 1399 overlay->color_key_enabled = true; 1400 overlay->brightness = -19; 1401 overlay->contrast = 75; 1402 overlay->saturation = 146; 1403 1404 i915_active_init(&overlay->last_flip, 1405 NULL, intel_overlay_last_flip_retire, 0); 1406 1407 ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv)); 1408 if (ret) 1409 goto out_free; 1410 1411 memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1412 update_polyphase_filter(overlay->regs); 1413 update_reg_attrs(overlay, overlay->regs); 1414 1415 dev_priv->overlay = overlay; 1416 drm_info(&dev_priv->drm, "Initialized overlay support.\n"); 1417 return; 1418 1419 out_free: 1420 kfree(overlay); 1421 } 1422 1423 void intel_overlay_cleanup(struct drm_i915_private *dev_priv) 1424 { 1425 struct intel_overlay *overlay; 1426 1427 overlay = fetch_and_zero(&dev_priv->overlay); 1428 if (!overlay) 1429 return; 1430 1431 /* 1432 * The bo's should be free'd by the generic code already. 1433 * Furthermore modesetting teardown happens beforehand so the 1434 * hardware should be off already. 1435 */ 1436 drm_WARN_ON(&dev_priv->drm, overlay->active); 1437 1438 i915_gem_object_put(overlay->reg_bo); 1439 i915_active_fini(&overlay->last_flip); 1440 1441 kfree(overlay); 1442 } 1443 1444 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1445 1446 struct intel_overlay_error_state { 1447 struct overlay_registers regs; 1448 unsigned long base; 1449 u32 dovsta; 1450 u32 isr; 1451 }; 1452 1453 struct intel_overlay_error_state * 1454 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) 1455 { 1456 struct intel_overlay *overlay = dev_priv->overlay; 1457 struct intel_overlay_error_state *error; 1458 1459 if (!overlay || !overlay->active) 1460 return NULL; 1461 1462 error = kmalloc(sizeof(*error), GFP_ATOMIC); 1463 if (error == NULL) 1464 return NULL; 1465 1466 error->dovsta = intel_de_read(dev_priv, DOVSTA); 1467 error->isr = intel_de_read(dev_priv, GEN2_ISR); 1468 error->base = overlay->flip_addr; 1469 1470 memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs)); 1471 1472 return error; 1473 } 1474 1475 void 1476 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m, 1477 struct intel_overlay_error_state *error) 1478 { 1479 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1480 error->dovsta, error->isr); 1481 i915_error_printf(m, " Register file at 0x%08lx:\n", 1482 error->base); 1483 1484 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) 1485 P(OBUF_0Y); 1486 P(OBUF_1Y); 1487 P(OBUF_0U); 1488 P(OBUF_0V); 1489 P(OBUF_1U); 1490 P(OBUF_1V); 1491 P(OSTRIDE); 1492 P(YRGB_VPH); 1493 P(UV_VPH); 1494 P(HORZ_PH); 1495 P(INIT_PHS); 1496 P(DWINPOS); 1497 P(DWINSZ); 1498 P(SWIDTH); 1499 P(SWIDTHSW); 1500 P(SHEIGHT); 1501 P(YRGBSCALE); 1502 P(UVSCALE); 1503 P(OCLRC0); 1504 P(OCLRC1); 1505 P(DCLRKV); 1506 P(DCLRKM); 1507 P(SCLRKVH); 1508 P(SCLRKVL); 1509 P(SCLRKEN); 1510 P(OCONFIG); 1511 P(OCMD); 1512 P(OSTART_0Y); 1513 P(OSTART_1Y); 1514 P(OSTART_0U); 1515 P(OSTART_0V); 1516 P(OSTART_1U); 1517 P(OSTART_1V); 1518 P(OTILEOFF_0Y); 1519 P(OTILEOFF_1Y); 1520 P(OTILEOFF_0U); 1521 P(OTILEOFF_0V); 1522 P(OTILEOFF_1U); 1523 P(OTILEOFF_1V); 1524 P(FASTHSCALE); 1525 P(UVSCALEV); 1526 #undef P 1527 } 1528 1529 #endif 1530