1 /* 2 * Copyright © 2009 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel@ffwll.ch> 25 * 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27 */ 28 29 #include <drm/drm_fourcc.h> 30 31 #include "gem/i915_gem_pm.h" 32 #include "gt/intel_gpu_commands.h" 33 #include "gt/intel_ring.h" 34 35 #include "i915_drv.h" 36 #include "i915_reg.h" 37 #include "intel_display_types.h" 38 #include "intel_frontbuffer.h" 39 #include "intel_overlay.h" 40 41 /* Limits for overlay size. According to intel doc, the real limits are: 42 * Y width: 4095, UV width (planar): 2047, Y height: 2047, 43 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 44 * the mininum of both. */ 45 #define IMAGE_MAX_WIDTH 2048 46 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 47 /* on 830 and 845 these large limits result in the card hanging */ 48 #define IMAGE_MAX_WIDTH_LEGACY 1024 49 #define IMAGE_MAX_HEIGHT_LEGACY 1088 50 51 /* overlay register definitions */ 52 /* OCMD register */ 53 #define OCMD_TILED_SURFACE (0x1<<19) 54 #define OCMD_MIRROR_MASK (0x3<<17) 55 #define OCMD_MIRROR_MODE (0x3<<17) 56 #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 57 #define OCMD_MIRROR_VERTICAL (0x2<<17) 58 #define OCMD_MIRROR_BOTH (0x3<<17) 59 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 60 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 61 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 62 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 63 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 64 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 65 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 66 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 67 #define OCMD_YUV_422_PACKED (0x8<<10) 68 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 69 #define OCMD_YUV_420_PLANAR (0xc<<10) 70 #define OCMD_YUV_422_PLANAR (0xd<<10) 71 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 72 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 73 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 74 #define OCMD_BUF_TYPE_MASK (0x1<<5) 75 #define OCMD_BUF_TYPE_FRAME (0x0<<5) 76 #define OCMD_BUF_TYPE_FIELD (0x1<<5) 77 #define OCMD_TEST_MODE (0x1<<4) 78 #define OCMD_BUFFER_SELECT (0x3<<2) 79 #define OCMD_BUFFER0 (0x0<<2) 80 #define OCMD_BUFFER1 (0x1<<2) 81 #define OCMD_FIELD_SELECT (0x1<<2) 82 #define OCMD_FIELD0 (0x0<<1) 83 #define OCMD_FIELD1 (0x1<<1) 84 #define OCMD_ENABLE (0x1<<0) 85 86 /* OCONFIG register */ 87 #define OCONF_PIPE_MASK (0x1<<18) 88 #define OCONF_PIPE_A (0x0<<18) 89 #define OCONF_PIPE_B (0x1<<18) 90 #define OCONF_GAMMA2_ENABLE (0x1<<16) 91 #define OCONF_CSC_MODE_BT601 (0x0<<5) 92 #define OCONF_CSC_MODE_BT709 (0x1<<5) 93 #define OCONF_CSC_BYPASS (0x1<<4) 94 #define OCONF_CC_OUT_8BIT (0x1<<3) 95 #define OCONF_TEST_MODE (0x1<<2) 96 #define OCONF_THREE_LINE_BUFFER (0x1<<0) 97 #define OCONF_TWO_LINE_BUFFER (0x0<<0) 98 99 /* DCLRKM (dst-key) register */ 100 #define DST_KEY_ENABLE (0x1<<31) 101 #define CLK_RGB24_MASK 0x0 102 #define CLK_RGB16_MASK 0x070307 103 #define CLK_RGB15_MASK 0x070707 104 105 #define RGB30_TO_COLORKEY(c) \ 106 ((((c) & 0x3fc00000) >> 6) | (((c) & 0x000ff000) >> 4) | (((c) & 0x000003fc) >> 2)) 107 #define RGB16_TO_COLORKEY(c) \ 108 ((((c) & 0xf800) << 8) | (((c) & 0x07e0) << 5) | (((c) & 0x001f) << 3)) 109 #define RGB15_TO_COLORKEY(c) \ 110 ((((c) & 0x7c00) << 9) | (((c) & 0x03e0) << 6) | (((c) & 0x001f) << 3)) 111 #define RGB8I_TO_COLORKEY(c) \ 112 ((((c) & 0xff) << 16) | (((c) & 0xff) << 8) | (((c) & 0xff) << 0)) 113 114 /* overlay flip addr flag */ 115 #define OFC_UPDATE 0x1 116 117 /* polyphase filter coefficients */ 118 #define N_HORIZ_Y_TAPS 5 119 #define N_VERT_Y_TAPS 3 120 #define N_HORIZ_UV_TAPS 3 121 #define N_VERT_UV_TAPS 3 122 #define N_PHASES 17 123 #define MAX_TAPS 5 124 125 /* memory bufferd overlay registers */ 126 struct overlay_registers { 127 u32 OBUF_0Y; 128 u32 OBUF_1Y; 129 u32 OBUF_0U; 130 u32 OBUF_0V; 131 u32 OBUF_1U; 132 u32 OBUF_1V; 133 u32 OSTRIDE; 134 u32 YRGB_VPH; 135 u32 UV_VPH; 136 u32 HORZ_PH; 137 u32 INIT_PHS; 138 u32 DWINPOS; 139 u32 DWINSZ; 140 u32 SWIDTH; 141 u32 SWIDTHSW; 142 u32 SHEIGHT; 143 u32 YRGBSCALE; 144 u32 UVSCALE; 145 u32 OCLRC0; 146 u32 OCLRC1; 147 u32 DCLRKV; 148 u32 DCLRKM; 149 u32 SCLRKVH; 150 u32 SCLRKVL; 151 u32 SCLRKEN; 152 u32 OCONFIG; 153 u32 OCMD; 154 u32 RESERVED1; /* 0x6C */ 155 u32 OSTART_0Y; 156 u32 OSTART_1Y; 157 u32 OSTART_0U; 158 u32 OSTART_0V; 159 u32 OSTART_1U; 160 u32 OSTART_1V; 161 u32 OTILEOFF_0Y; 162 u32 OTILEOFF_1Y; 163 u32 OTILEOFF_0U; 164 u32 OTILEOFF_0V; 165 u32 OTILEOFF_1U; 166 u32 OTILEOFF_1V; 167 u32 FASTHSCALE; /* 0xA0 */ 168 u32 UVSCALEV; /* 0xA4 */ 169 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 170 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 171 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 172 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 173 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 174 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 175 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 176 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 177 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 178 }; 179 180 struct intel_overlay { 181 struct drm_i915_private *i915; 182 struct intel_context *context; 183 struct intel_crtc *crtc; 184 struct i915_vma *vma; 185 struct i915_vma *old_vma; 186 bool active; 187 bool pfit_active; 188 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 189 u32 color_key:24; 190 u32 color_key_enabled:1; 191 u32 brightness, contrast, saturation; 192 u32 old_xscale, old_yscale; 193 /* register access */ 194 struct drm_i915_gem_object *reg_bo; 195 struct overlay_registers __iomem *regs; 196 u32 flip_addr; 197 /* flip handling */ 198 struct i915_active last_flip; 199 void (*flip_complete)(struct intel_overlay *ovl); 200 }; 201 202 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, 203 bool enable) 204 { 205 struct pci_dev *pdev = dev_priv->drm.pdev; 206 u8 val; 207 208 /* WA_OVERLAY_CLKGATE:alm */ 209 if (enable) 210 intel_de_write(dev_priv, DSPCLK_GATE_D, 0); 211 else 212 intel_de_write(dev_priv, DSPCLK_GATE_D, 213 OVRUNIT_CLOCK_GATE_DISABLE); 214 215 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 216 pci_bus_read_config_byte(pdev->bus, 217 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); 218 if (enable) 219 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; 220 else 221 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 222 pci_bus_write_config_byte(pdev->bus, 223 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 224 } 225 226 static struct i915_request * 227 alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *)) 228 { 229 struct i915_request *rq; 230 int err; 231 232 overlay->flip_complete = fn; 233 234 rq = i915_request_create(overlay->context); 235 if (IS_ERR(rq)) 236 return rq; 237 238 err = i915_active_add_request(&overlay->last_flip, rq); 239 if (err) { 240 i915_request_add(rq); 241 return ERR_PTR(err); 242 } 243 244 return rq; 245 } 246 247 /* overlay needs to be disable in OCMD reg */ 248 static int intel_overlay_on(struct intel_overlay *overlay) 249 { 250 struct drm_i915_private *dev_priv = overlay->i915; 251 struct i915_request *rq; 252 u32 *cs; 253 254 drm_WARN_ON(&dev_priv->drm, overlay->active); 255 256 rq = alloc_request(overlay, NULL); 257 if (IS_ERR(rq)) 258 return PTR_ERR(rq); 259 260 cs = intel_ring_begin(rq, 4); 261 if (IS_ERR(cs)) { 262 i915_request_add(rq); 263 return PTR_ERR(cs); 264 } 265 266 overlay->active = true; 267 268 if (IS_I830(dev_priv)) 269 i830_overlay_clock_gating(dev_priv, false); 270 271 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 272 *cs++ = overlay->flip_addr | OFC_UPDATE; 273 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 274 *cs++ = MI_NOOP; 275 intel_ring_advance(rq, cs); 276 277 i915_request_add(rq); 278 279 return i915_active_wait(&overlay->last_flip); 280 } 281 282 static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 283 struct i915_vma *vma) 284 { 285 enum pipe pipe = overlay->crtc->pipe; 286 struct intel_frontbuffer *from = NULL, *to = NULL; 287 288 drm_WARN_ON(&overlay->i915->drm, overlay->old_vma); 289 290 if (overlay->vma) 291 from = intel_frontbuffer_get(overlay->vma->obj); 292 if (vma) 293 to = intel_frontbuffer_get(vma->obj); 294 295 intel_frontbuffer_track(from, to, INTEL_FRONTBUFFER_OVERLAY(pipe)); 296 297 if (to) 298 intel_frontbuffer_put(to); 299 if (from) 300 intel_frontbuffer_put(from); 301 302 intel_frontbuffer_flip_prepare(overlay->i915, 303 INTEL_FRONTBUFFER_OVERLAY(pipe)); 304 305 overlay->old_vma = overlay->vma; 306 if (vma) 307 overlay->vma = i915_vma_get(vma); 308 else 309 overlay->vma = NULL; 310 } 311 312 /* overlay needs to be enabled in OCMD reg */ 313 static int intel_overlay_continue(struct intel_overlay *overlay, 314 struct i915_vma *vma, 315 bool load_polyphase_filter) 316 { 317 struct drm_i915_private *dev_priv = overlay->i915; 318 struct i915_request *rq; 319 u32 flip_addr = overlay->flip_addr; 320 u32 tmp, *cs; 321 322 drm_WARN_ON(&dev_priv->drm, !overlay->active); 323 324 if (load_polyphase_filter) 325 flip_addr |= OFC_UPDATE; 326 327 /* check for underruns */ 328 tmp = intel_de_read(dev_priv, DOVSTA); 329 if (tmp & (1 << 17)) 330 drm_dbg(&dev_priv->drm, "overlay underrun, DOVSTA: %x\n", tmp); 331 332 rq = alloc_request(overlay, NULL); 333 if (IS_ERR(rq)) 334 return PTR_ERR(rq); 335 336 cs = intel_ring_begin(rq, 2); 337 if (IS_ERR(cs)) { 338 i915_request_add(rq); 339 return PTR_ERR(cs); 340 } 341 342 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 343 *cs++ = flip_addr; 344 intel_ring_advance(rq, cs); 345 346 intel_overlay_flip_prepare(overlay, vma); 347 i915_request_add(rq); 348 349 return 0; 350 } 351 352 static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 353 { 354 struct i915_vma *vma; 355 356 vma = fetch_and_zero(&overlay->old_vma); 357 if (drm_WARN_ON(&overlay->i915->drm, !vma)) 358 return; 359 360 intel_frontbuffer_flip_complete(overlay->i915, 361 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 362 363 i915_vma_unpin(vma); 364 i915_vma_put(vma); 365 } 366 367 static void 368 intel_overlay_release_old_vid_tail(struct intel_overlay *overlay) 369 { 370 intel_overlay_release_old_vma(overlay); 371 } 372 373 static void intel_overlay_off_tail(struct intel_overlay *overlay) 374 { 375 struct drm_i915_private *dev_priv = overlay->i915; 376 377 intel_overlay_release_old_vma(overlay); 378 379 overlay->crtc->overlay = NULL; 380 overlay->crtc = NULL; 381 overlay->active = false; 382 383 if (IS_I830(dev_priv)) 384 i830_overlay_clock_gating(dev_priv, true); 385 } 386 387 static void 388 intel_overlay_last_flip_retire(struct i915_active *active) 389 { 390 struct intel_overlay *overlay = 391 container_of(active, typeof(*overlay), last_flip); 392 393 if (overlay->flip_complete) 394 overlay->flip_complete(overlay); 395 } 396 397 /* overlay needs to be disabled in OCMD reg */ 398 static int intel_overlay_off(struct intel_overlay *overlay) 399 { 400 struct i915_request *rq; 401 u32 *cs, flip_addr = overlay->flip_addr; 402 403 drm_WARN_ON(&overlay->i915->drm, !overlay->active); 404 405 /* According to intel docs the overlay hw may hang (when switching 406 * off) without loading the filter coeffs. It is however unclear whether 407 * this applies to the disabling of the overlay or to the switching off 408 * of the hw. Do it in both cases */ 409 flip_addr |= OFC_UPDATE; 410 411 rq = alloc_request(overlay, intel_overlay_off_tail); 412 if (IS_ERR(rq)) 413 return PTR_ERR(rq); 414 415 cs = intel_ring_begin(rq, 6); 416 if (IS_ERR(cs)) { 417 i915_request_add(rq); 418 return PTR_ERR(cs); 419 } 420 421 /* wait for overlay to go idle */ 422 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 423 *cs++ = flip_addr; 424 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 425 426 /* turn overlay off */ 427 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; 428 *cs++ = flip_addr; 429 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 430 431 intel_ring_advance(rq, cs); 432 433 intel_overlay_flip_prepare(overlay, NULL); 434 i915_request_add(rq); 435 436 return i915_active_wait(&overlay->last_flip); 437 } 438 439 /* recover from an interruption due to a signal 440 * We have to be careful not to repeat work forever an make forward progess. */ 441 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) 442 { 443 return i915_active_wait(&overlay->last_flip); 444 } 445 446 /* Wait for pending overlay flip and release old frame. 447 * Needs to be called before the overlay register are changed 448 * via intel_overlay_(un)map_regs 449 */ 450 static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 451 { 452 struct drm_i915_private *dev_priv = overlay->i915; 453 struct i915_request *rq; 454 u32 *cs; 455 456 /* 457 * Only wait if there is actually an old frame to release to 458 * guarantee forward progress. 459 */ 460 if (!overlay->old_vma) 461 return 0; 462 463 if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { 464 intel_overlay_release_old_vid_tail(overlay); 465 return 0; 466 } 467 468 rq = alloc_request(overlay, intel_overlay_release_old_vid_tail); 469 if (IS_ERR(rq)) 470 return PTR_ERR(rq); 471 472 cs = intel_ring_begin(rq, 2); 473 if (IS_ERR(cs)) { 474 i915_request_add(rq); 475 return PTR_ERR(cs); 476 } 477 478 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 479 *cs++ = MI_NOOP; 480 intel_ring_advance(rq, cs); 481 482 i915_request_add(rq); 483 484 return i915_active_wait(&overlay->last_flip); 485 } 486 487 void intel_overlay_reset(struct drm_i915_private *dev_priv) 488 { 489 struct intel_overlay *overlay = dev_priv->overlay; 490 491 if (!overlay) 492 return; 493 494 overlay->old_xscale = 0; 495 overlay->old_yscale = 0; 496 overlay->crtc = NULL; 497 overlay->active = false; 498 } 499 500 static int packed_depth_bytes(u32 format) 501 { 502 switch (format & I915_OVERLAY_DEPTH_MASK) { 503 case I915_OVERLAY_YUV422: 504 return 4; 505 case I915_OVERLAY_YUV411: 506 /* return 6; not implemented */ 507 default: 508 return -EINVAL; 509 } 510 } 511 512 static int packed_width_bytes(u32 format, short width) 513 { 514 switch (format & I915_OVERLAY_DEPTH_MASK) { 515 case I915_OVERLAY_YUV422: 516 return width << 1; 517 default: 518 return -EINVAL; 519 } 520 } 521 522 static int uv_hsubsampling(u32 format) 523 { 524 switch (format & I915_OVERLAY_DEPTH_MASK) { 525 case I915_OVERLAY_YUV422: 526 case I915_OVERLAY_YUV420: 527 return 2; 528 case I915_OVERLAY_YUV411: 529 case I915_OVERLAY_YUV410: 530 return 4; 531 default: 532 return -EINVAL; 533 } 534 } 535 536 static int uv_vsubsampling(u32 format) 537 { 538 switch (format & I915_OVERLAY_DEPTH_MASK) { 539 case I915_OVERLAY_YUV420: 540 case I915_OVERLAY_YUV410: 541 return 2; 542 case I915_OVERLAY_YUV422: 543 case I915_OVERLAY_YUV411: 544 return 1; 545 default: 546 return -EINVAL; 547 } 548 } 549 550 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) 551 { 552 u32 sw; 553 554 if (IS_GEN(dev_priv, 2)) 555 sw = ALIGN((offset & 31) + width, 32); 556 else 557 sw = ALIGN((offset & 63) + width, 64); 558 559 if (sw == 0) 560 return 0; 561 562 return (sw - 32) >> 3; 563 } 564 565 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 566 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 567 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 568 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 569 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 570 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 571 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 572 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 573 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 574 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 575 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 576 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 577 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 578 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 579 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 580 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 581 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 582 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 583 }; 584 585 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 586 [ 0] = { 0x3000, 0x1800, 0x1800, }, 587 [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 588 [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 589 [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 590 [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 591 [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 592 [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 593 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 594 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 595 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 596 [10] = { 0xb100, 0x1eb8, 0x3620, }, 597 [11] = { 0xb100, 0x1f18, 0x34a0, }, 598 [12] = { 0xb100, 0x1f68, 0x3360, }, 599 [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 600 [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 601 [15] = { 0xb060, 0x1ff0, 0x30a0, }, 602 [16] = { 0x3000, 0x0800, 0x3000, }, 603 }; 604 605 static void update_polyphase_filter(struct overlay_registers __iomem *regs) 606 { 607 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 608 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 609 sizeof(uv_static_hcoeffs)); 610 } 611 612 static bool update_scaling_factors(struct intel_overlay *overlay, 613 struct overlay_registers __iomem *regs, 614 struct drm_intel_overlay_put_image *params) 615 { 616 /* fixed point with a 12 bit shift */ 617 u32 xscale, yscale, xscale_UV, yscale_UV; 618 #define FP_SHIFT 12 619 #define FRACT_MASK 0xfff 620 bool scale_changed = false; 621 int uv_hscale = uv_hsubsampling(params->flags); 622 int uv_vscale = uv_vsubsampling(params->flags); 623 624 if (params->dst_width > 1) 625 xscale = ((params->src_scan_width - 1) << FP_SHIFT) / 626 params->dst_width; 627 else 628 xscale = 1 << FP_SHIFT; 629 630 if (params->dst_height > 1) 631 yscale = ((params->src_scan_height - 1) << FP_SHIFT) / 632 params->dst_height; 633 else 634 yscale = 1 << FP_SHIFT; 635 636 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 637 xscale_UV = xscale/uv_hscale; 638 yscale_UV = yscale/uv_vscale; 639 /* make the Y scale to UV scale ratio an exact multiply */ 640 xscale = xscale_UV * uv_hscale; 641 yscale = yscale_UV * uv_vscale; 642 /*} else { 643 xscale_UV = 0; 644 yscale_UV = 0; 645 }*/ 646 647 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 648 scale_changed = true; 649 overlay->old_xscale = xscale; 650 overlay->old_yscale = yscale; 651 652 iowrite32(((yscale & FRACT_MASK) << 20) | 653 ((xscale >> FP_SHIFT) << 16) | 654 ((xscale & FRACT_MASK) << 3), 655 ®s->YRGBSCALE); 656 657 iowrite32(((yscale_UV & FRACT_MASK) << 20) | 658 ((xscale_UV >> FP_SHIFT) << 16) | 659 ((xscale_UV & FRACT_MASK) << 3), 660 ®s->UVSCALE); 661 662 iowrite32((((yscale >> FP_SHIFT) << 16) | 663 ((yscale_UV >> FP_SHIFT) << 0)), 664 ®s->UVSCALEV); 665 666 if (scale_changed) 667 update_polyphase_filter(regs); 668 669 return scale_changed; 670 } 671 672 static void update_colorkey(struct intel_overlay *overlay, 673 struct overlay_registers __iomem *regs) 674 { 675 const struct intel_plane_state *state = 676 to_intel_plane_state(overlay->crtc->base.primary->state); 677 u32 key = overlay->color_key; 678 u32 format = 0; 679 u32 flags = 0; 680 681 if (overlay->color_key_enabled) 682 flags |= DST_KEY_ENABLE; 683 684 if (state->uapi.visible) 685 format = state->hw.fb->format->format; 686 687 switch (format) { 688 case DRM_FORMAT_C8: 689 key = RGB8I_TO_COLORKEY(key); 690 flags |= CLK_RGB24_MASK; 691 break; 692 case DRM_FORMAT_XRGB1555: 693 key = RGB15_TO_COLORKEY(key); 694 flags |= CLK_RGB15_MASK; 695 break; 696 case DRM_FORMAT_RGB565: 697 key = RGB16_TO_COLORKEY(key); 698 flags |= CLK_RGB16_MASK; 699 break; 700 case DRM_FORMAT_XRGB2101010: 701 case DRM_FORMAT_XBGR2101010: 702 key = RGB30_TO_COLORKEY(key); 703 flags |= CLK_RGB24_MASK; 704 break; 705 default: 706 flags |= CLK_RGB24_MASK; 707 break; 708 } 709 710 iowrite32(key, ®s->DCLRKV); 711 iowrite32(flags, ®s->DCLRKM); 712 } 713 714 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) 715 { 716 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 717 718 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 719 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 720 case I915_OVERLAY_YUV422: 721 cmd |= OCMD_YUV_422_PLANAR; 722 break; 723 case I915_OVERLAY_YUV420: 724 cmd |= OCMD_YUV_420_PLANAR; 725 break; 726 case I915_OVERLAY_YUV411: 727 case I915_OVERLAY_YUV410: 728 cmd |= OCMD_YUV_410_PLANAR; 729 break; 730 } 731 } else { /* YUV packed */ 732 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 733 case I915_OVERLAY_YUV422: 734 cmd |= OCMD_YUV_422_PACKED; 735 break; 736 case I915_OVERLAY_YUV411: 737 cmd |= OCMD_YUV_411_PACKED; 738 break; 739 } 740 741 switch (params->flags & I915_OVERLAY_SWAP_MASK) { 742 case I915_OVERLAY_NO_SWAP: 743 break; 744 case I915_OVERLAY_UV_SWAP: 745 cmd |= OCMD_UV_SWAP; 746 break; 747 case I915_OVERLAY_Y_SWAP: 748 cmd |= OCMD_Y_SWAP; 749 break; 750 case I915_OVERLAY_Y_AND_UV_SWAP: 751 cmd |= OCMD_Y_AND_UV_SWAP; 752 break; 753 } 754 } 755 756 return cmd; 757 } 758 759 static int intel_overlay_do_put_image(struct intel_overlay *overlay, 760 struct drm_i915_gem_object *new_bo, 761 struct drm_intel_overlay_put_image *params) 762 { 763 struct overlay_registers __iomem *regs = overlay->regs; 764 struct drm_i915_private *dev_priv = overlay->i915; 765 u32 swidth, swidthsw, sheight, ostride; 766 enum pipe pipe = overlay->crtc->pipe; 767 bool scale_changed = false; 768 struct i915_vma *vma; 769 int ret, tmp_width; 770 771 drm_WARN_ON(&dev_priv->drm, 772 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 773 774 ret = intel_overlay_release_old_vid(overlay); 775 if (ret != 0) 776 return ret; 777 778 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 779 780 vma = i915_gem_object_pin_to_display_plane(new_bo, 781 0, NULL, PIN_MAPPABLE); 782 if (IS_ERR(vma)) { 783 ret = PTR_ERR(vma); 784 goto out_pin_section; 785 } 786 i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB); 787 788 if (!overlay->active) { 789 const struct intel_crtc_state *crtc_state = 790 overlay->crtc->config; 791 u32 oconfig = 0; 792 793 if (crtc_state->gamma_enable && 794 crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 795 oconfig |= OCONF_CC_OUT_8BIT; 796 if (crtc_state->gamma_enable) 797 oconfig |= OCONF_GAMMA2_ENABLE; 798 if (IS_GEN(dev_priv, 4)) 799 oconfig |= OCONF_CSC_MODE_BT709; 800 oconfig |= pipe == 0 ? 801 OCONF_PIPE_A : OCONF_PIPE_B; 802 iowrite32(oconfig, ®s->OCONFIG); 803 804 ret = intel_overlay_on(overlay); 805 if (ret != 0) 806 goto out_unpin; 807 } 808 809 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS); 810 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ); 811 812 if (params->flags & I915_OVERLAY_YUV_PACKED) 813 tmp_width = packed_width_bytes(params->flags, 814 params->src_width); 815 else 816 tmp_width = params->src_width; 817 818 swidth = params->src_width; 819 swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width); 820 sheight = params->src_height; 821 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); 822 ostride = params->stride_Y; 823 824 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 825 int uv_hscale = uv_hsubsampling(params->flags); 826 int uv_vscale = uv_vsubsampling(params->flags); 827 u32 tmp_U, tmp_V; 828 829 swidth |= (params->src_width / uv_hscale) << 16; 830 sheight |= (params->src_height / uv_vscale) << 16; 831 832 tmp_U = calc_swidthsw(dev_priv, params->offset_U, 833 params->src_width / uv_hscale); 834 tmp_V = calc_swidthsw(dev_priv, params->offset_V, 835 params->src_width / uv_hscale); 836 swidthsw |= max(tmp_U, tmp_V) << 16; 837 838 iowrite32(i915_ggtt_offset(vma) + params->offset_U, 839 ®s->OBUF_0U); 840 iowrite32(i915_ggtt_offset(vma) + params->offset_V, 841 ®s->OBUF_0V); 842 843 ostride |= params->stride_UV << 16; 844 } 845 846 iowrite32(swidth, ®s->SWIDTH); 847 iowrite32(swidthsw, ®s->SWIDTHSW); 848 iowrite32(sheight, ®s->SHEIGHT); 849 iowrite32(ostride, ®s->OSTRIDE); 850 851 scale_changed = update_scaling_factors(overlay, regs, params); 852 853 update_colorkey(overlay, regs); 854 855 iowrite32(overlay_cmd_reg(params), ®s->OCMD); 856 857 ret = intel_overlay_continue(overlay, vma, scale_changed); 858 if (ret) 859 goto out_unpin; 860 861 return 0; 862 863 out_unpin: 864 i915_vma_unpin(vma); 865 out_pin_section: 866 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 867 868 return ret; 869 } 870 871 int intel_overlay_switch_off(struct intel_overlay *overlay) 872 { 873 struct drm_i915_private *dev_priv = overlay->i915; 874 int ret; 875 876 drm_WARN_ON(&dev_priv->drm, 877 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 878 879 ret = intel_overlay_recover_from_interrupt(overlay); 880 if (ret != 0) 881 return ret; 882 883 if (!overlay->active) 884 return 0; 885 886 ret = intel_overlay_release_old_vid(overlay); 887 if (ret != 0) 888 return ret; 889 890 iowrite32(0, &overlay->regs->OCMD); 891 892 return intel_overlay_off(overlay); 893 } 894 895 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 896 struct intel_crtc *crtc) 897 { 898 if (!crtc->active) 899 return -EINVAL; 900 901 /* can't use the overlay with double wide pipe */ 902 if (crtc->config->double_wide) 903 return -EINVAL; 904 905 return 0; 906 } 907 908 static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 909 { 910 struct drm_i915_private *dev_priv = overlay->i915; 911 u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL); 912 u32 ratio; 913 914 /* XXX: This is not the same logic as in the xorg driver, but more in 915 * line with the intel documentation for the i965 916 */ 917 if (INTEL_GEN(dev_priv) >= 4) { 918 /* on i965 use the PGM reg to read out the autoscaler values */ 919 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; 920 } else { 921 if (pfit_control & VERT_AUTO_SCALE) 922 ratio = intel_de_read(dev_priv, PFIT_AUTO_RATIOS); 923 else 924 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS); 925 ratio >>= PFIT_VERT_SCALE_SHIFT; 926 } 927 928 overlay->pfit_vscale_ratio = ratio; 929 } 930 931 static int check_overlay_dst(struct intel_overlay *overlay, 932 struct drm_intel_overlay_put_image *rec) 933 { 934 const struct intel_crtc_state *pipe_config = 935 overlay->crtc->config; 936 937 if (rec->dst_x < pipe_config->pipe_src_w && 938 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && 939 rec->dst_y < pipe_config->pipe_src_h && 940 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) 941 return 0; 942 else 943 return -EINVAL; 944 } 945 946 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) 947 { 948 u32 tmp; 949 950 /* downscaling limit is 8.0 */ 951 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16; 952 if (tmp > 7) 953 return -EINVAL; 954 955 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16; 956 if (tmp > 7) 957 return -EINVAL; 958 959 return 0; 960 } 961 962 static int check_overlay_src(struct drm_i915_private *dev_priv, 963 struct drm_intel_overlay_put_image *rec, 964 struct drm_i915_gem_object *new_bo) 965 { 966 int uv_hscale = uv_hsubsampling(rec->flags); 967 int uv_vscale = uv_vsubsampling(rec->flags); 968 u32 stride_mask; 969 int depth; 970 u32 tmp; 971 972 /* check src dimensions */ 973 if (IS_I845G(dev_priv) || IS_I830(dev_priv)) { 974 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 975 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 976 return -EINVAL; 977 } else { 978 if (rec->src_height > IMAGE_MAX_HEIGHT || 979 rec->src_width > IMAGE_MAX_WIDTH) 980 return -EINVAL; 981 } 982 983 /* better safe than sorry, use 4 as the maximal subsampling ratio */ 984 if (rec->src_height < N_VERT_Y_TAPS*4 || 985 rec->src_width < N_HORIZ_Y_TAPS*4) 986 return -EINVAL; 987 988 /* check alignment constraints */ 989 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 990 case I915_OVERLAY_RGB: 991 /* not implemented */ 992 return -EINVAL; 993 994 case I915_OVERLAY_YUV_PACKED: 995 if (uv_vscale != 1) 996 return -EINVAL; 997 998 depth = packed_depth_bytes(rec->flags); 999 if (depth < 0) 1000 return depth; 1001 1002 /* ignore UV planes */ 1003 rec->stride_UV = 0; 1004 rec->offset_U = 0; 1005 rec->offset_V = 0; 1006 /* check pixel alignment */ 1007 if (rec->offset_Y % depth) 1008 return -EINVAL; 1009 break; 1010 1011 case I915_OVERLAY_YUV_PLANAR: 1012 if (uv_vscale < 0 || uv_hscale < 0) 1013 return -EINVAL; 1014 /* no offset restrictions for planar formats */ 1015 break; 1016 1017 default: 1018 return -EINVAL; 1019 } 1020 1021 if (rec->src_width % uv_hscale) 1022 return -EINVAL; 1023 1024 /* stride checking */ 1025 if (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1026 stride_mask = 255; 1027 else 1028 stride_mask = 63; 1029 1030 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1031 return -EINVAL; 1032 if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512) 1033 return -EINVAL; 1034 1035 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1036 4096 : 8192; 1037 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 1038 return -EINVAL; 1039 1040 /* check buffer dimensions */ 1041 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1042 case I915_OVERLAY_RGB: 1043 case I915_OVERLAY_YUV_PACKED: 1044 /* always 4 Y values per depth pixels */ 1045 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 1046 return -EINVAL; 1047 1048 tmp = rec->stride_Y*rec->src_height; 1049 if (rec->offset_Y + tmp > new_bo->base.size) 1050 return -EINVAL; 1051 break; 1052 1053 case I915_OVERLAY_YUV_PLANAR: 1054 if (rec->src_width > rec->stride_Y) 1055 return -EINVAL; 1056 if (rec->src_width/uv_hscale > rec->stride_UV) 1057 return -EINVAL; 1058 1059 tmp = rec->stride_Y * rec->src_height; 1060 if (rec->offset_Y + tmp > new_bo->base.size) 1061 return -EINVAL; 1062 1063 tmp = rec->stride_UV * (rec->src_height / uv_vscale); 1064 if (rec->offset_U + tmp > new_bo->base.size || 1065 rec->offset_V + tmp > new_bo->base.size) 1066 return -EINVAL; 1067 break; 1068 } 1069 1070 return 0; 1071 } 1072 1073 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1074 struct drm_file *file_priv) 1075 { 1076 struct drm_intel_overlay_put_image *params = data; 1077 struct drm_i915_private *dev_priv = to_i915(dev); 1078 struct intel_overlay *overlay; 1079 struct drm_crtc *drmmode_crtc; 1080 struct intel_crtc *crtc; 1081 struct drm_i915_gem_object *new_bo; 1082 int ret; 1083 1084 overlay = dev_priv->overlay; 1085 if (!overlay) { 1086 drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n"); 1087 return -ENODEV; 1088 } 1089 1090 if (!(params->flags & I915_OVERLAY_ENABLE)) { 1091 drm_modeset_lock_all(dev); 1092 ret = intel_overlay_switch_off(overlay); 1093 drm_modeset_unlock_all(dev); 1094 1095 return ret; 1096 } 1097 1098 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id); 1099 if (!drmmode_crtc) 1100 return -ENOENT; 1101 crtc = to_intel_crtc(drmmode_crtc); 1102 1103 new_bo = i915_gem_object_lookup(file_priv, params->bo_handle); 1104 if (!new_bo) 1105 return -ENOENT; 1106 1107 drm_modeset_lock_all(dev); 1108 1109 if (i915_gem_object_is_tiled(new_bo)) { 1110 drm_dbg_kms(&dev_priv->drm, 1111 "buffer used for overlay image can not be tiled\n"); 1112 ret = -EINVAL; 1113 goto out_unlock; 1114 } 1115 1116 ret = intel_overlay_recover_from_interrupt(overlay); 1117 if (ret != 0) 1118 goto out_unlock; 1119 1120 if (overlay->crtc != crtc) { 1121 ret = intel_overlay_switch_off(overlay); 1122 if (ret != 0) 1123 goto out_unlock; 1124 1125 ret = check_overlay_possible_on_crtc(overlay, crtc); 1126 if (ret != 0) 1127 goto out_unlock; 1128 1129 overlay->crtc = crtc; 1130 crtc->overlay = overlay; 1131 1132 /* line too wide, i.e. one-line-mode */ 1133 if (crtc->config->pipe_src_w > 1024 && 1134 crtc->config->gmch_pfit.control & PFIT_ENABLE) { 1135 overlay->pfit_active = true; 1136 update_pfit_vscale_ratio(overlay); 1137 } else 1138 overlay->pfit_active = false; 1139 } 1140 1141 ret = check_overlay_dst(overlay, params); 1142 if (ret != 0) 1143 goto out_unlock; 1144 1145 if (overlay->pfit_active) { 1146 params->dst_y = (((u32)params->dst_y << 12) / 1147 overlay->pfit_vscale_ratio); 1148 /* shifting right rounds downwards, so add 1 */ 1149 params->dst_height = (((u32)params->dst_height << 12) / 1150 overlay->pfit_vscale_ratio) + 1; 1151 } 1152 1153 if (params->src_scan_height > params->src_height || 1154 params->src_scan_width > params->src_width) { 1155 ret = -EINVAL; 1156 goto out_unlock; 1157 } 1158 1159 ret = check_overlay_src(dev_priv, params, new_bo); 1160 if (ret != 0) 1161 goto out_unlock; 1162 1163 /* Check scaling after src size to prevent a divide-by-zero. */ 1164 ret = check_overlay_scaling(params); 1165 if (ret != 0) 1166 goto out_unlock; 1167 1168 ret = intel_overlay_do_put_image(overlay, new_bo, params); 1169 if (ret != 0) 1170 goto out_unlock; 1171 1172 drm_modeset_unlock_all(dev); 1173 i915_gem_object_put(new_bo); 1174 1175 return 0; 1176 1177 out_unlock: 1178 drm_modeset_unlock_all(dev); 1179 i915_gem_object_put(new_bo); 1180 1181 return ret; 1182 } 1183 1184 static void update_reg_attrs(struct intel_overlay *overlay, 1185 struct overlay_registers __iomem *regs) 1186 { 1187 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 1188 ®s->OCLRC0); 1189 iowrite32(overlay->saturation, ®s->OCLRC1); 1190 } 1191 1192 static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 1193 { 1194 int i; 1195 1196 if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 1197 return false; 1198 1199 for (i = 0; i < 3; i++) { 1200 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 1201 return false; 1202 } 1203 1204 return true; 1205 } 1206 1207 static bool check_gamma5_errata(u32 gamma5) 1208 { 1209 int i; 1210 1211 for (i = 0; i < 3; i++) { 1212 if (((gamma5 >> i*8) & 0xff) == 0x80) 1213 return false; 1214 } 1215 1216 return true; 1217 } 1218 1219 static int check_gamma(struct drm_intel_overlay_attrs *attrs) 1220 { 1221 if (!check_gamma_bounds(0, attrs->gamma0) || 1222 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 1223 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 1224 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 1225 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 1226 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 1227 !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 1228 return -EINVAL; 1229 1230 if (!check_gamma5_errata(attrs->gamma5)) 1231 return -EINVAL; 1232 1233 return 0; 1234 } 1235 1236 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1237 struct drm_file *file_priv) 1238 { 1239 struct drm_intel_overlay_attrs *attrs = data; 1240 struct drm_i915_private *dev_priv = to_i915(dev); 1241 struct intel_overlay *overlay; 1242 int ret; 1243 1244 overlay = dev_priv->overlay; 1245 if (!overlay) { 1246 drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n"); 1247 return -ENODEV; 1248 } 1249 1250 drm_modeset_lock_all(dev); 1251 1252 ret = -EINVAL; 1253 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 1254 attrs->color_key = overlay->color_key; 1255 attrs->brightness = overlay->brightness; 1256 attrs->contrast = overlay->contrast; 1257 attrs->saturation = overlay->saturation; 1258 1259 if (!IS_GEN(dev_priv, 2)) { 1260 attrs->gamma0 = intel_de_read(dev_priv, OGAMC0); 1261 attrs->gamma1 = intel_de_read(dev_priv, OGAMC1); 1262 attrs->gamma2 = intel_de_read(dev_priv, OGAMC2); 1263 attrs->gamma3 = intel_de_read(dev_priv, OGAMC3); 1264 attrs->gamma4 = intel_de_read(dev_priv, OGAMC4); 1265 attrs->gamma5 = intel_de_read(dev_priv, OGAMC5); 1266 } 1267 } else { 1268 if (attrs->brightness < -128 || attrs->brightness > 127) 1269 goto out_unlock; 1270 if (attrs->contrast > 255) 1271 goto out_unlock; 1272 if (attrs->saturation > 1023) 1273 goto out_unlock; 1274 1275 overlay->color_key = attrs->color_key; 1276 overlay->brightness = attrs->brightness; 1277 overlay->contrast = attrs->contrast; 1278 overlay->saturation = attrs->saturation; 1279 1280 update_reg_attrs(overlay, overlay->regs); 1281 1282 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1283 if (IS_GEN(dev_priv, 2)) 1284 goto out_unlock; 1285 1286 if (overlay->active) { 1287 ret = -EBUSY; 1288 goto out_unlock; 1289 } 1290 1291 ret = check_gamma(attrs); 1292 if (ret) 1293 goto out_unlock; 1294 1295 intel_de_write(dev_priv, OGAMC0, attrs->gamma0); 1296 intel_de_write(dev_priv, OGAMC1, attrs->gamma1); 1297 intel_de_write(dev_priv, OGAMC2, attrs->gamma2); 1298 intel_de_write(dev_priv, OGAMC3, attrs->gamma3); 1299 intel_de_write(dev_priv, OGAMC4, attrs->gamma4); 1300 intel_de_write(dev_priv, OGAMC5, attrs->gamma5); 1301 } 1302 } 1303 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1304 1305 ret = 0; 1306 out_unlock: 1307 drm_modeset_unlock_all(dev); 1308 1309 return ret; 1310 } 1311 1312 static int get_registers(struct intel_overlay *overlay, bool use_phys) 1313 { 1314 struct drm_i915_private *i915 = overlay->i915; 1315 struct drm_i915_gem_object *obj; 1316 struct i915_vma *vma; 1317 int err; 1318 1319 obj = i915_gem_object_create_stolen(i915, PAGE_SIZE); 1320 if (IS_ERR(obj)) 1321 obj = i915_gem_object_create_internal(i915, PAGE_SIZE); 1322 if (IS_ERR(obj)) 1323 return PTR_ERR(obj); 1324 1325 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); 1326 if (IS_ERR(vma)) { 1327 err = PTR_ERR(vma); 1328 goto err_put_bo; 1329 } 1330 1331 if (use_phys) 1332 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl); 1333 else 1334 overlay->flip_addr = i915_ggtt_offset(vma); 1335 overlay->regs = i915_vma_pin_iomap(vma); 1336 i915_vma_unpin(vma); 1337 1338 if (IS_ERR(overlay->regs)) { 1339 err = PTR_ERR(overlay->regs); 1340 goto err_put_bo; 1341 } 1342 1343 overlay->reg_bo = obj; 1344 return 0; 1345 1346 err_put_bo: 1347 i915_gem_object_put(obj); 1348 return err; 1349 } 1350 1351 void intel_overlay_setup(struct drm_i915_private *dev_priv) 1352 { 1353 struct intel_overlay *overlay; 1354 struct intel_engine_cs *engine; 1355 int ret; 1356 1357 if (!HAS_OVERLAY(dev_priv)) 1358 return; 1359 1360 engine = dev_priv->gt.engine[RCS0]; 1361 if (!engine || !engine->kernel_context) 1362 return; 1363 1364 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 1365 if (!overlay) 1366 return; 1367 1368 overlay->i915 = dev_priv; 1369 overlay->context = engine->kernel_context; 1370 GEM_BUG_ON(!overlay->context); 1371 1372 overlay->color_key = 0x0101fe; 1373 overlay->color_key_enabled = true; 1374 overlay->brightness = -19; 1375 overlay->contrast = 75; 1376 overlay->saturation = 146; 1377 1378 i915_active_init(&overlay->last_flip, 1379 NULL, intel_overlay_last_flip_retire); 1380 1381 ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv)); 1382 if (ret) 1383 goto out_free; 1384 1385 memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1386 update_polyphase_filter(overlay->regs); 1387 update_reg_attrs(overlay, overlay->regs); 1388 1389 dev_priv->overlay = overlay; 1390 drm_info(&dev_priv->drm, "Initialized overlay support.\n"); 1391 return; 1392 1393 out_free: 1394 kfree(overlay); 1395 } 1396 1397 void intel_overlay_cleanup(struct drm_i915_private *dev_priv) 1398 { 1399 struct intel_overlay *overlay; 1400 1401 overlay = fetch_and_zero(&dev_priv->overlay); 1402 if (!overlay) 1403 return; 1404 1405 /* 1406 * The bo's should be free'd by the generic code already. 1407 * Furthermore modesetting teardown happens beforehand so the 1408 * hardware should be off already. 1409 */ 1410 drm_WARN_ON(&dev_priv->drm, overlay->active); 1411 1412 i915_gem_object_put(overlay->reg_bo); 1413 i915_active_fini(&overlay->last_flip); 1414 1415 kfree(overlay); 1416 } 1417 1418 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1419 1420 struct intel_overlay_error_state { 1421 struct overlay_registers regs; 1422 unsigned long base; 1423 u32 dovsta; 1424 u32 isr; 1425 }; 1426 1427 struct intel_overlay_error_state * 1428 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) 1429 { 1430 struct intel_overlay *overlay = dev_priv->overlay; 1431 struct intel_overlay_error_state *error; 1432 1433 if (!overlay || !overlay->active) 1434 return NULL; 1435 1436 error = kmalloc(sizeof(*error), GFP_ATOMIC); 1437 if (error == NULL) 1438 return NULL; 1439 1440 error->dovsta = intel_de_read(dev_priv, DOVSTA); 1441 error->isr = intel_de_read(dev_priv, GEN2_ISR); 1442 error->base = overlay->flip_addr; 1443 1444 memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs)); 1445 1446 return error; 1447 } 1448 1449 void 1450 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m, 1451 struct intel_overlay_error_state *error) 1452 { 1453 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1454 error->dovsta, error->isr); 1455 i915_error_printf(m, " Register file at 0x%08lx:\n", 1456 error->base); 1457 1458 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) 1459 P(OBUF_0Y); 1460 P(OBUF_1Y); 1461 P(OBUF_0U); 1462 P(OBUF_0V); 1463 P(OBUF_1U); 1464 P(OBUF_1V); 1465 P(OSTRIDE); 1466 P(YRGB_VPH); 1467 P(UV_VPH); 1468 P(HORZ_PH); 1469 P(INIT_PHS); 1470 P(DWINPOS); 1471 P(DWINSZ); 1472 P(SWIDTH); 1473 P(SWIDTHSW); 1474 P(SHEIGHT); 1475 P(YRGBSCALE); 1476 P(UVSCALE); 1477 P(OCLRC0); 1478 P(OCLRC1); 1479 P(DCLRKV); 1480 P(DCLRKM); 1481 P(SCLRKVH); 1482 P(SCLRKVL); 1483 P(SCLRKEN); 1484 P(OCONFIG); 1485 P(OCMD); 1486 P(OSTART_0Y); 1487 P(OSTART_1Y); 1488 P(OSTART_0U); 1489 P(OSTART_0V); 1490 P(OSTART_1U); 1491 P(OSTART_1V); 1492 P(OTILEOFF_0Y); 1493 P(OTILEOFF_1Y); 1494 P(OTILEOFF_0U); 1495 P(OTILEOFF_0V); 1496 P(OTILEOFF_1U); 1497 P(OTILEOFF_1V); 1498 P(FASTHSCALE); 1499 P(UVSCALEV); 1500 #undef P 1501 } 1502 1503 #endif 1504