1df0566a6SJani Nikula /* 2df0566a6SJani Nikula * Copyright © 2009 3df0566a6SJani Nikula * 4df0566a6SJani Nikula * Permission is hereby granted, free of charge, to any person obtaining a 5df0566a6SJani Nikula * copy of this software and associated documentation files (the "Software"), 6df0566a6SJani Nikula * to deal in the Software without restriction, including without limitation 7df0566a6SJani Nikula * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8df0566a6SJani Nikula * and/or sell copies of the Software, and to permit persons to whom the 9df0566a6SJani Nikula * Software is furnished to do so, subject to the following conditions: 10df0566a6SJani Nikula * 11df0566a6SJani Nikula * The above copyright notice and this permission notice (including the next 12df0566a6SJani Nikula * paragraph) shall be included in all copies or substantial portions of the 13df0566a6SJani Nikula * Software. 14df0566a6SJani Nikula * 15df0566a6SJani Nikula * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16df0566a6SJani Nikula * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17df0566a6SJani Nikula * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18df0566a6SJani Nikula * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19df0566a6SJani Nikula * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20df0566a6SJani Nikula * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21df0566a6SJani Nikula * SOFTWARE. 22df0566a6SJani Nikula * 23df0566a6SJani Nikula * Authors: 24df0566a6SJani Nikula * Daniel Vetter <daniel@ffwll.ch> 25df0566a6SJani Nikula * 26df0566a6SJani Nikula * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27df0566a6SJani Nikula */ 28df0566a6SJani Nikula 29df0566a6SJani Nikula #include <drm/drm_fourcc.h> 30df0566a6SJani Nikula 31df0566a6SJani Nikula #include "gem/i915_gem_pm.h" 322871ea85SChris Wilson #include "gt/intel_ring.h" 33df0566a6SJani Nikula 34df0566a6SJani Nikula #include "i915_drv.h" 35df0566a6SJani Nikula #include "i915_reg.h" 361d455f8dSJani Nikula #include "intel_display_types.h" 37df0566a6SJani Nikula #include "intel_frontbuffer.h" 38df0566a6SJani Nikula #include "intel_overlay.h" 39df0566a6SJani Nikula 40df0566a6SJani Nikula /* Limits for overlay size. According to intel doc, the real limits are: 41df0566a6SJani Nikula * Y width: 4095, UV width (planar): 2047, Y height: 2047, 42df0566a6SJani Nikula * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 43df0566a6SJani Nikula * the mininum of both. */ 44df0566a6SJani Nikula #define IMAGE_MAX_WIDTH 2048 45df0566a6SJani Nikula #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 46df0566a6SJani Nikula /* on 830 and 845 these large limits result in the card hanging */ 47df0566a6SJani Nikula #define IMAGE_MAX_WIDTH_LEGACY 1024 48df0566a6SJani Nikula #define IMAGE_MAX_HEIGHT_LEGACY 1088 49df0566a6SJani Nikula 50df0566a6SJani Nikula /* overlay register definitions */ 51df0566a6SJani Nikula /* OCMD register */ 52df0566a6SJani Nikula #define OCMD_TILED_SURFACE (0x1<<19) 53df0566a6SJani Nikula #define OCMD_MIRROR_MASK (0x3<<17) 54df0566a6SJani Nikula #define OCMD_MIRROR_MODE (0x3<<17) 55df0566a6SJani Nikula #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 56df0566a6SJani Nikula #define OCMD_MIRROR_VERTICAL (0x2<<17) 57df0566a6SJani Nikula #define OCMD_MIRROR_BOTH (0x3<<17) 58df0566a6SJani Nikula #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 59df0566a6SJani Nikula #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 60df0566a6SJani Nikula #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 61df0566a6SJani Nikula #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 62df0566a6SJani Nikula #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 63df0566a6SJani Nikula #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 64df0566a6SJani Nikula #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 65df0566a6SJani Nikula #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 66df0566a6SJani Nikula #define OCMD_YUV_422_PACKED (0x8<<10) 67df0566a6SJani Nikula #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 68df0566a6SJani Nikula #define OCMD_YUV_420_PLANAR (0xc<<10) 69df0566a6SJani Nikula #define OCMD_YUV_422_PLANAR (0xd<<10) 70df0566a6SJani Nikula #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 71df0566a6SJani Nikula #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 72df0566a6SJani Nikula #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 73df0566a6SJani Nikula #define OCMD_BUF_TYPE_MASK (0x1<<5) 74df0566a6SJani Nikula #define OCMD_BUF_TYPE_FRAME (0x0<<5) 75df0566a6SJani Nikula #define OCMD_BUF_TYPE_FIELD (0x1<<5) 76df0566a6SJani Nikula #define OCMD_TEST_MODE (0x1<<4) 77df0566a6SJani Nikula #define OCMD_BUFFER_SELECT (0x3<<2) 78df0566a6SJani Nikula #define OCMD_BUFFER0 (0x0<<2) 79df0566a6SJani Nikula #define OCMD_BUFFER1 (0x1<<2) 80df0566a6SJani Nikula #define OCMD_FIELD_SELECT (0x1<<2) 81df0566a6SJani Nikula #define OCMD_FIELD0 (0x0<<1) 82df0566a6SJani Nikula #define OCMD_FIELD1 (0x1<<1) 83df0566a6SJani Nikula #define OCMD_ENABLE (0x1<<0) 84df0566a6SJani Nikula 85df0566a6SJani Nikula /* OCONFIG register */ 86df0566a6SJani Nikula #define OCONF_PIPE_MASK (0x1<<18) 87df0566a6SJani Nikula #define OCONF_PIPE_A (0x0<<18) 88df0566a6SJani Nikula #define OCONF_PIPE_B (0x1<<18) 89df0566a6SJani Nikula #define OCONF_GAMMA2_ENABLE (0x1<<16) 90df0566a6SJani Nikula #define OCONF_CSC_MODE_BT601 (0x0<<5) 91df0566a6SJani Nikula #define OCONF_CSC_MODE_BT709 (0x1<<5) 92df0566a6SJani Nikula #define OCONF_CSC_BYPASS (0x1<<4) 93df0566a6SJani Nikula #define OCONF_CC_OUT_8BIT (0x1<<3) 94df0566a6SJani Nikula #define OCONF_TEST_MODE (0x1<<2) 95df0566a6SJani Nikula #define OCONF_THREE_LINE_BUFFER (0x1<<0) 96df0566a6SJani Nikula #define OCONF_TWO_LINE_BUFFER (0x0<<0) 97df0566a6SJani Nikula 98df0566a6SJani Nikula /* DCLRKM (dst-key) register */ 99df0566a6SJani Nikula #define DST_KEY_ENABLE (0x1<<31) 100df0566a6SJani Nikula #define CLK_RGB24_MASK 0x0 101df0566a6SJani Nikula #define CLK_RGB16_MASK 0x070307 102df0566a6SJani Nikula #define CLK_RGB15_MASK 0x070707 103df0566a6SJani Nikula #define CLK_RGB8I_MASK 0xffffff 104df0566a6SJani Nikula 105df0566a6SJani Nikula #define RGB16_TO_COLORKEY(c) \ 106df0566a6SJani Nikula (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3)) 107df0566a6SJani Nikula #define RGB15_TO_COLORKEY(c) \ 108df0566a6SJani Nikula (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3)) 109df0566a6SJani Nikula 110df0566a6SJani Nikula /* overlay flip addr flag */ 111df0566a6SJani Nikula #define OFC_UPDATE 0x1 112df0566a6SJani Nikula 113df0566a6SJani Nikula /* polyphase filter coefficients */ 114df0566a6SJani Nikula #define N_HORIZ_Y_TAPS 5 115df0566a6SJani Nikula #define N_VERT_Y_TAPS 3 116df0566a6SJani Nikula #define N_HORIZ_UV_TAPS 3 117df0566a6SJani Nikula #define N_VERT_UV_TAPS 3 118df0566a6SJani Nikula #define N_PHASES 17 119df0566a6SJani Nikula #define MAX_TAPS 5 120df0566a6SJani Nikula 121df0566a6SJani Nikula /* memory bufferd overlay registers */ 122df0566a6SJani Nikula struct overlay_registers { 123df0566a6SJani Nikula u32 OBUF_0Y; 124df0566a6SJani Nikula u32 OBUF_1Y; 125df0566a6SJani Nikula u32 OBUF_0U; 126df0566a6SJani Nikula u32 OBUF_0V; 127df0566a6SJani Nikula u32 OBUF_1U; 128df0566a6SJani Nikula u32 OBUF_1V; 129df0566a6SJani Nikula u32 OSTRIDE; 130df0566a6SJani Nikula u32 YRGB_VPH; 131df0566a6SJani Nikula u32 UV_VPH; 132df0566a6SJani Nikula u32 HORZ_PH; 133df0566a6SJani Nikula u32 INIT_PHS; 134df0566a6SJani Nikula u32 DWINPOS; 135df0566a6SJani Nikula u32 DWINSZ; 136df0566a6SJani Nikula u32 SWIDTH; 137df0566a6SJani Nikula u32 SWIDTHSW; 138df0566a6SJani Nikula u32 SHEIGHT; 139df0566a6SJani Nikula u32 YRGBSCALE; 140df0566a6SJani Nikula u32 UVSCALE; 141df0566a6SJani Nikula u32 OCLRC0; 142df0566a6SJani Nikula u32 OCLRC1; 143df0566a6SJani Nikula u32 DCLRKV; 144df0566a6SJani Nikula u32 DCLRKM; 145df0566a6SJani Nikula u32 SCLRKVH; 146df0566a6SJani Nikula u32 SCLRKVL; 147df0566a6SJani Nikula u32 SCLRKEN; 148df0566a6SJani Nikula u32 OCONFIG; 149df0566a6SJani Nikula u32 OCMD; 150df0566a6SJani Nikula u32 RESERVED1; /* 0x6C */ 151df0566a6SJani Nikula u32 OSTART_0Y; 152df0566a6SJani Nikula u32 OSTART_1Y; 153df0566a6SJani Nikula u32 OSTART_0U; 154df0566a6SJani Nikula u32 OSTART_0V; 155df0566a6SJani Nikula u32 OSTART_1U; 156df0566a6SJani Nikula u32 OSTART_1V; 157df0566a6SJani Nikula u32 OTILEOFF_0Y; 158df0566a6SJani Nikula u32 OTILEOFF_1Y; 159df0566a6SJani Nikula u32 OTILEOFF_0U; 160df0566a6SJani Nikula u32 OTILEOFF_0V; 161df0566a6SJani Nikula u32 OTILEOFF_1U; 162df0566a6SJani Nikula u32 OTILEOFF_1V; 163df0566a6SJani Nikula u32 FASTHSCALE; /* 0xA0 */ 164df0566a6SJani Nikula u32 UVSCALEV; /* 0xA4 */ 165df0566a6SJani Nikula u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 166df0566a6SJani Nikula u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 167df0566a6SJani Nikula u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 168df0566a6SJani Nikula u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 169df0566a6SJani Nikula u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 170df0566a6SJani Nikula u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 171df0566a6SJani Nikula u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 172df0566a6SJani Nikula u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 173df0566a6SJani Nikula u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 174df0566a6SJani Nikula }; 175df0566a6SJani Nikula 176df0566a6SJani Nikula struct intel_overlay { 177df0566a6SJani Nikula struct drm_i915_private *i915; 178ec22f256SChris Wilson struct intel_context *context; 179df0566a6SJani Nikula struct intel_crtc *crtc; 180df0566a6SJani Nikula struct i915_vma *vma; 181df0566a6SJani Nikula struct i915_vma *old_vma; 182df0566a6SJani Nikula bool active; 183df0566a6SJani Nikula bool pfit_active; 184df0566a6SJani Nikula u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 185df0566a6SJani Nikula u32 color_key:24; 186df0566a6SJani Nikula u32 color_key_enabled:1; 187df0566a6SJani Nikula u32 brightness, contrast, saturation; 188df0566a6SJani Nikula u32 old_xscale, old_yscale; 189df0566a6SJani Nikula /* register access */ 190df0566a6SJani Nikula struct drm_i915_gem_object *reg_bo; 191df0566a6SJani Nikula struct overlay_registers __iomem *regs; 192df0566a6SJani Nikula u32 flip_addr; 193df0566a6SJani Nikula /* flip handling */ 194a21ce8adSChris Wilson struct i915_active last_flip; 195a21ce8adSChris Wilson void (*flip_complete)(struct intel_overlay *ovl); 196df0566a6SJani Nikula }; 197df0566a6SJani Nikula 198df0566a6SJani Nikula static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, 199df0566a6SJani Nikula bool enable) 200df0566a6SJani Nikula { 201df0566a6SJani Nikula struct pci_dev *pdev = dev_priv->drm.pdev; 202df0566a6SJani Nikula u8 val; 203df0566a6SJani Nikula 204df0566a6SJani Nikula /* WA_OVERLAY_CLKGATE:alm */ 205df0566a6SJani Nikula if (enable) 20682e1b12eSJani Nikula intel_de_write(dev_priv, DSPCLK_GATE_D, 0); 207df0566a6SJani Nikula else 20882e1b12eSJani Nikula intel_de_write(dev_priv, DSPCLK_GATE_D, 20982e1b12eSJani Nikula OVRUNIT_CLOCK_GATE_DISABLE); 210df0566a6SJani Nikula 211df0566a6SJani Nikula /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 212df0566a6SJani Nikula pci_bus_read_config_byte(pdev->bus, 213df0566a6SJani Nikula PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); 214df0566a6SJani Nikula if (enable) 215df0566a6SJani Nikula val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; 216df0566a6SJani Nikula else 217df0566a6SJani Nikula val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 218df0566a6SJani Nikula pci_bus_write_config_byte(pdev->bus, 219df0566a6SJani Nikula PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 220df0566a6SJani Nikula } 221df0566a6SJani Nikula 222a21ce8adSChris Wilson static struct i915_request * 223a21ce8adSChris Wilson alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *)) 224df0566a6SJani Nikula { 225a21ce8adSChris Wilson struct i915_request *rq; 226a21ce8adSChris Wilson int err; 227a21ce8adSChris Wilson 228a21ce8adSChris Wilson overlay->flip_complete = fn; 229a21ce8adSChris Wilson 230a21ce8adSChris Wilson rq = i915_request_create(overlay->context); 231a21ce8adSChris Wilson if (IS_ERR(rq)) 232a21ce8adSChris Wilson return rq; 233a21ce8adSChris Wilson 234d19d71fcSChris Wilson err = i915_active_add_request(&overlay->last_flip, rq); 235a21ce8adSChris Wilson if (err) { 236df0566a6SJani Nikula i915_request_add(rq); 237a21ce8adSChris Wilson return ERR_PTR(err); 238df0566a6SJani Nikula } 239df0566a6SJani Nikula 240a21ce8adSChris Wilson return rq; 241df0566a6SJani Nikula } 242df0566a6SJani Nikula 243df0566a6SJani Nikula /* overlay needs to be disable in OCMD reg */ 244df0566a6SJani Nikula static int intel_overlay_on(struct intel_overlay *overlay) 245df0566a6SJani Nikula { 246df0566a6SJani Nikula struct drm_i915_private *dev_priv = overlay->i915; 247df0566a6SJani Nikula struct i915_request *rq; 248df0566a6SJani Nikula u32 *cs; 249df0566a6SJani Nikula 250b0b2ed0cSPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, overlay->active); 251df0566a6SJani Nikula 252a21ce8adSChris Wilson rq = alloc_request(overlay, NULL); 253df0566a6SJani Nikula if (IS_ERR(rq)) 254df0566a6SJani Nikula return PTR_ERR(rq); 255df0566a6SJani Nikula 256df0566a6SJani Nikula cs = intel_ring_begin(rq, 4); 257df0566a6SJani Nikula if (IS_ERR(cs)) { 258df0566a6SJani Nikula i915_request_add(rq); 259df0566a6SJani Nikula return PTR_ERR(cs); 260df0566a6SJani Nikula } 261df0566a6SJani Nikula 262df0566a6SJani Nikula overlay->active = true; 263df0566a6SJani Nikula 264df0566a6SJani Nikula if (IS_I830(dev_priv)) 265df0566a6SJani Nikula i830_overlay_clock_gating(dev_priv, false); 266df0566a6SJani Nikula 267df0566a6SJani Nikula *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 268df0566a6SJani Nikula *cs++ = overlay->flip_addr | OFC_UPDATE; 269df0566a6SJani Nikula *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 270df0566a6SJani Nikula *cs++ = MI_NOOP; 271df0566a6SJani Nikula intel_ring_advance(rq, cs); 272df0566a6SJani Nikula 273a21ce8adSChris Wilson i915_request_add(rq); 274a21ce8adSChris Wilson 275a21ce8adSChris Wilson return i915_active_wait(&overlay->last_flip); 276df0566a6SJani Nikula } 277df0566a6SJani Nikula 278df0566a6SJani Nikula static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 279df0566a6SJani Nikula struct i915_vma *vma) 280df0566a6SJani Nikula { 281df0566a6SJani Nikula enum pipe pipe = overlay->crtc->pipe; 282e1f0fbdaSColin Ian King struct intel_frontbuffer *from = NULL, *to = NULL; 283df0566a6SJani Nikula 284e278f076SPankaj Bharadiya drm_WARN_ON(&overlay->i915->drm, overlay->old_vma); 285df0566a6SJani Nikula 286da42104fSChris Wilson if (overlay->vma) 287da42104fSChris Wilson from = intel_frontbuffer_get(overlay->vma->obj); 288da42104fSChris Wilson if (vma) 289da42104fSChris Wilson to = intel_frontbuffer_get(vma->obj); 290da42104fSChris Wilson 291da42104fSChris Wilson intel_frontbuffer_track(from, to, INTEL_FRONTBUFFER_OVERLAY(pipe)); 292da42104fSChris Wilson 293da42104fSChris Wilson if (to) 294da42104fSChris Wilson intel_frontbuffer_put(to); 295da42104fSChris Wilson if (from) 296da42104fSChris Wilson intel_frontbuffer_put(from); 297df0566a6SJani Nikula 298df0566a6SJani Nikula intel_frontbuffer_flip_prepare(overlay->i915, 299df0566a6SJani Nikula INTEL_FRONTBUFFER_OVERLAY(pipe)); 300df0566a6SJani Nikula 301df0566a6SJani Nikula overlay->old_vma = overlay->vma; 302df0566a6SJani Nikula if (vma) 303df0566a6SJani Nikula overlay->vma = i915_vma_get(vma); 304df0566a6SJani Nikula else 305df0566a6SJani Nikula overlay->vma = NULL; 306df0566a6SJani Nikula } 307df0566a6SJani Nikula 308df0566a6SJani Nikula /* overlay needs to be enabled in OCMD reg */ 309df0566a6SJani Nikula static int intel_overlay_continue(struct intel_overlay *overlay, 310df0566a6SJani Nikula struct i915_vma *vma, 311df0566a6SJani Nikula bool load_polyphase_filter) 312df0566a6SJani Nikula { 313df0566a6SJani Nikula struct drm_i915_private *dev_priv = overlay->i915; 314df0566a6SJani Nikula struct i915_request *rq; 315df0566a6SJani Nikula u32 flip_addr = overlay->flip_addr; 316df0566a6SJani Nikula u32 tmp, *cs; 317df0566a6SJani Nikula 318b0b2ed0cSPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, !overlay->active); 319df0566a6SJani Nikula 320df0566a6SJani Nikula if (load_polyphase_filter) 321df0566a6SJani Nikula flip_addr |= OFC_UPDATE; 322df0566a6SJani Nikula 323df0566a6SJani Nikula /* check for underruns */ 32482e1b12eSJani Nikula tmp = intel_de_read(dev_priv, DOVSTA); 325df0566a6SJani Nikula if (tmp & (1 << 17)) 3263c4e93e9SWambui Karuga drm_dbg(&dev_priv->drm, "overlay underrun, DOVSTA: %x\n", tmp); 327df0566a6SJani Nikula 328a21ce8adSChris Wilson rq = alloc_request(overlay, NULL); 329df0566a6SJani Nikula if (IS_ERR(rq)) 330df0566a6SJani Nikula return PTR_ERR(rq); 331df0566a6SJani Nikula 332df0566a6SJani Nikula cs = intel_ring_begin(rq, 2); 333df0566a6SJani Nikula if (IS_ERR(cs)) { 334df0566a6SJani Nikula i915_request_add(rq); 335df0566a6SJani Nikula return PTR_ERR(cs); 336df0566a6SJani Nikula } 337df0566a6SJani Nikula 338df0566a6SJani Nikula *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 339df0566a6SJani Nikula *cs++ = flip_addr; 340df0566a6SJani Nikula intel_ring_advance(rq, cs); 341df0566a6SJani Nikula 342df0566a6SJani Nikula intel_overlay_flip_prepare(overlay, vma); 343a21ce8adSChris Wilson i915_request_add(rq); 344df0566a6SJani Nikula 345df0566a6SJani Nikula return 0; 346df0566a6SJani Nikula } 347df0566a6SJani Nikula 348df0566a6SJani Nikula static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 349df0566a6SJani Nikula { 350df0566a6SJani Nikula struct i915_vma *vma; 351df0566a6SJani Nikula 352df0566a6SJani Nikula vma = fetch_and_zero(&overlay->old_vma); 353e278f076SPankaj Bharadiya if (drm_WARN_ON(&overlay->i915->drm, !vma)) 354df0566a6SJani Nikula return; 355df0566a6SJani Nikula 356df0566a6SJani Nikula intel_frontbuffer_flip_complete(overlay->i915, 357df0566a6SJani Nikula INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 358df0566a6SJani Nikula 359df0566a6SJani Nikula i915_gem_object_unpin_from_display_plane(vma); 360df0566a6SJani Nikula i915_vma_put(vma); 361df0566a6SJani Nikula } 362df0566a6SJani Nikula 363df0566a6SJani Nikula static void 364a21ce8adSChris Wilson intel_overlay_release_old_vid_tail(struct intel_overlay *overlay) 365df0566a6SJani Nikula { 366df0566a6SJani Nikula intel_overlay_release_old_vma(overlay); 367df0566a6SJani Nikula } 368df0566a6SJani Nikula 369a21ce8adSChris Wilson static void intel_overlay_off_tail(struct intel_overlay *overlay) 370df0566a6SJani Nikula { 371df0566a6SJani Nikula struct drm_i915_private *dev_priv = overlay->i915; 372df0566a6SJani Nikula 373df0566a6SJani Nikula intel_overlay_release_old_vma(overlay); 374df0566a6SJani Nikula 375df0566a6SJani Nikula overlay->crtc->overlay = NULL; 376df0566a6SJani Nikula overlay->crtc = NULL; 377df0566a6SJani Nikula overlay->active = false; 378df0566a6SJani Nikula 379df0566a6SJani Nikula if (IS_I830(dev_priv)) 380df0566a6SJani Nikula i830_overlay_clock_gating(dev_priv, true); 381df0566a6SJani Nikula } 382df0566a6SJani Nikula 383a21ce8adSChris Wilson static void 384a21ce8adSChris Wilson intel_overlay_last_flip_retire(struct i915_active *active) 385a21ce8adSChris Wilson { 386a21ce8adSChris Wilson struct intel_overlay *overlay = 387a21ce8adSChris Wilson container_of(active, typeof(*overlay), last_flip); 388a21ce8adSChris Wilson 389a21ce8adSChris Wilson if (overlay->flip_complete) 390a21ce8adSChris Wilson overlay->flip_complete(overlay); 391a21ce8adSChris Wilson } 392a21ce8adSChris Wilson 393df0566a6SJani Nikula /* overlay needs to be disabled in OCMD reg */ 394df0566a6SJani Nikula static int intel_overlay_off(struct intel_overlay *overlay) 395df0566a6SJani Nikula { 396df0566a6SJani Nikula struct i915_request *rq; 397df0566a6SJani Nikula u32 *cs, flip_addr = overlay->flip_addr; 398df0566a6SJani Nikula 399e278f076SPankaj Bharadiya drm_WARN_ON(&overlay->i915->drm, !overlay->active); 400df0566a6SJani Nikula 401df0566a6SJani Nikula /* According to intel docs the overlay hw may hang (when switching 402df0566a6SJani Nikula * off) without loading the filter coeffs. It is however unclear whether 403df0566a6SJani Nikula * this applies to the disabling of the overlay or to the switching off 404df0566a6SJani Nikula * of the hw. Do it in both cases */ 405df0566a6SJani Nikula flip_addr |= OFC_UPDATE; 406df0566a6SJani Nikula 407a21ce8adSChris Wilson rq = alloc_request(overlay, intel_overlay_off_tail); 408df0566a6SJani Nikula if (IS_ERR(rq)) 409df0566a6SJani Nikula return PTR_ERR(rq); 410df0566a6SJani Nikula 411df0566a6SJani Nikula cs = intel_ring_begin(rq, 6); 412df0566a6SJani Nikula if (IS_ERR(cs)) { 413df0566a6SJani Nikula i915_request_add(rq); 414df0566a6SJani Nikula return PTR_ERR(cs); 415df0566a6SJani Nikula } 416df0566a6SJani Nikula 417df0566a6SJani Nikula /* wait for overlay to go idle */ 418df0566a6SJani Nikula *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 419df0566a6SJani Nikula *cs++ = flip_addr; 420df0566a6SJani Nikula *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 421df0566a6SJani Nikula 422df0566a6SJani Nikula /* turn overlay off */ 423df0566a6SJani Nikula *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; 424df0566a6SJani Nikula *cs++ = flip_addr; 425df0566a6SJani Nikula *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 426df0566a6SJani Nikula 427df0566a6SJani Nikula intel_ring_advance(rq, cs); 428df0566a6SJani Nikula 429df0566a6SJani Nikula intel_overlay_flip_prepare(overlay, NULL); 430a21ce8adSChris Wilson i915_request_add(rq); 431df0566a6SJani Nikula 432a21ce8adSChris Wilson return i915_active_wait(&overlay->last_flip); 433df0566a6SJani Nikula } 434df0566a6SJani Nikula 435df0566a6SJani Nikula /* recover from an interruption due to a signal 436df0566a6SJani Nikula * We have to be careful not to repeat work forever an make forward progess. */ 437df0566a6SJani Nikula static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) 438df0566a6SJani Nikula { 439a21ce8adSChris Wilson return i915_active_wait(&overlay->last_flip); 440df0566a6SJani Nikula } 441df0566a6SJani Nikula 442df0566a6SJani Nikula /* Wait for pending overlay flip and release old frame. 443df0566a6SJani Nikula * Needs to be called before the overlay register are changed 444df0566a6SJani Nikula * via intel_overlay_(un)map_regs 445df0566a6SJani Nikula */ 446df0566a6SJani Nikula static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 447df0566a6SJani Nikula { 448df0566a6SJani Nikula struct drm_i915_private *dev_priv = overlay->i915; 449a21ce8adSChris Wilson struct i915_request *rq; 450df0566a6SJani Nikula u32 *cs; 451df0566a6SJani Nikula 452a21ce8adSChris Wilson /* 453a21ce8adSChris Wilson * Only wait if there is actually an old frame to release to 454df0566a6SJani Nikula * guarantee forward progress. 455df0566a6SJani Nikula */ 456df0566a6SJani Nikula if (!overlay->old_vma) 457df0566a6SJani Nikula return 0; 458df0566a6SJani Nikula 45982e1b12eSJani Nikula if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { 460a21ce8adSChris Wilson intel_overlay_release_old_vid_tail(overlay); 461a21ce8adSChris Wilson return 0; 462a21ce8adSChris Wilson } 463df0566a6SJani Nikula 464a21ce8adSChris Wilson rq = alloc_request(overlay, intel_overlay_release_old_vid_tail); 465df0566a6SJani Nikula if (IS_ERR(rq)) 466df0566a6SJani Nikula return PTR_ERR(rq); 467df0566a6SJani Nikula 468df0566a6SJani Nikula cs = intel_ring_begin(rq, 2); 469df0566a6SJani Nikula if (IS_ERR(cs)) { 470df0566a6SJani Nikula i915_request_add(rq); 471df0566a6SJani Nikula return PTR_ERR(cs); 472df0566a6SJani Nikula } 473df0566a6SJani Nikula 474df0566a6SJani Nikula *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 475df0566a6SJani Nikula *cs++ = MI_NOOP; 476df0566a6SJani Nikula intel_ring_advance(rq, cs); 477df0566a6SJani Nikula 478a21ce8adSChris Wilson i915_request_add(rq); 479df0566a6SJani Nikula 480a21ce8adSChris Wilson return i915_active_wait(&overlay->last_flip); 481df0566a6SJani Nikula } 482df0566a6SJani Nikula 483df0566a6SJani Nikula void intel_overlay_reset(struct drm_i915_private *dev_priv) 484df0566a6SJani Nikula { 485df0566a6SJani Nikula struct intel_overlay *overlay = dev_priv->overlay; 486df0566a6SJani Nikula 487df0566a6SJani Nikula if (!overlay) 488df0566a6SJani Nikula return; 489df0566a6SJani Nikula 490df0566a6SJani Nikula overlay->old_xscale = 0; 491df0566a6SJani Nikula overlay->old_yscale = 0; 492df0566a6SJani Nikula overlay->crtc = NULL; 493df0566a6SJani Nikula overlay->active = false; 494df0566a6SJani Nikula } 495df0566a6SJani Nikula 496df0566a6SJani Nikula static int packed_depth_bytes(u32 format) 497df0566a6SJani Nikula { 498df0566a6SJani Nikula switch (format & I915_OVERLAY_DEPTH_MASK) { 499df0566a6SJani Nikula case I915_OVERLAY_YUV422: 500df0566a6SJani Nikula return 4; 501df0566a6SJani Nikula case I915_OVERLAY_YUV411: 502df0566a6SJani Nikula /* return 6; not implemented */ 503df0566a6SJani Nikula default: 504df0566a6SJani Nikula return -EINVAL; 505df0566a6SJani Nikula } 506df0566a6SJani Nikula } 507df0566a6SJani Nikula 508df0566a6SJani Nikula static int packed_width_bytes(u32 format, short width) 509df0566a6SJani Nikula { 510df0566a6SJani Nikula switch (format & I915_OVERLAY_DEPTH_MASK) { 511df0566a6SJani Nikula case I915_OVERLAY_YUV422: 512df0566a6SJani Nikula return width << 1; 513df0566a6SJani Nikula default: 514df0566a6SJani Nikula return -EINVAL; 515df0566a6SJani Nikula } 516df0566a6SJani Nikula } 517df0566a6SJani Nikula 518df0566a6SJani Nikula static int uv_hsubsampling(u32 format) 519df0566a6SJani Nikula { 520df0566a6SJani Nikula switch (format & I915_OVERLAY_DEPTH_MASK) { 521df0566a6SJani Nikula case I915_OVERLAY_YUV422: 522df0566a6SJani Nikula case I915_OVERLAY_YUV420: 523df0566a6SJani Nikula return 2; 524df0566a6SJani Nikula case I915_OVERLAY_YUV411: 525df0566a6SJani Nikula case I915_OVERLAY_YUV410: 526df0566a6SJani Nikula return 4; 527df0566a6SJani Nikula default: 528df0566a6SJani Nikula return -EINVAL; 529df0566a6SJani Nikula } 530df0566a6SJani Nikula } 531df0566a6SJani Nikula 532df0566a6SJani Nikula static int uv_vsubsampling(u32 format) 533df0566a6SJani Nikula { 534df0566a6SJani Nikula switch (format & I915_OVERLAY_DEPTH_MASK) { 535df0566a6SJani Nikula case I915_OVERLAY_YUV420: 536df0566a6SJani Nikula case I915_OVERLAY_YUV410: 537df0566a6SJani Nikula return 2; 538df0566a6SJani Nikula case I915_OVERLAY_YUV422: 539df0566a6SJani Nikula case I915_OVERLAY_YUV411: 540df0566a6SJani Nikula return 1; 541df0566a6SJani Nikula default: 542df0566a6SJani Nikula return -EINVAL; 543df0566a6SJani Nikula } 544df0566a6SJani Nikula } 545df0566a6SJani Nikula 546df0566a6SJani Nikula static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) 547df0566a6SJani Nikula { 548df0566a6SJani Nikula u32 sw; 549df0566a6SJani Nikula 550df0566a6SJani Nikula if (IS_GEN(dev_priv, 2)) 551df0566a6SJani Nikula sw = ALIGN((offset & 31) + width, 32); 552df0566a6SJani Nikula else 553df0566a6SJani Nikula sw = ALIGN((offset & 63) + width, 64); 554df0566a6SJani Nikula 555df0566a6SJani Nikula if (sw == 0) 556df0566a6SJani Nikula return 0; 557df0566a6SJani Nikula 558df0566a6SJani Nikula return (sw - 32) >> 3; 559df0566a6SJani Nikula } 560df0566a6SJani Nikula 561df0566a6SJani Nikula static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 562df0566a6SJani Nikula [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 563df0566a6SJani Nikula [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 564df0566a6SJani Nikula [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 565df0566a6SJani Nikula [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 566df0566a6SJani Nikula [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 567df0566a6SJani Nikula [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 568df0566a6SJani Nikula [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 569df0566a6SJani Nikula [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 570df0566a6SJani Nikula [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 571df0566a6SJani Nikula [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 572df0566a6SJani Nikula [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 573df0566a6SJani Nikula [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 574df0566a6SJani Nikula [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 575df0566a6SJani Nikula [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 576df0566a6SJani Nikula [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 577df0566a6SJani Nikula [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 578df0566a6SJani Nikula [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 579df0566a6SJani Nikula }; 580df0566a6SJani Nikula 581df0566a6SJani Nikula static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 582df0566a6SJani Nikula [ 0] = { 0x3000, 0x1800, 0x1800, }, 583df0566a6SJani Nikula [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 584df0566a6SJani Nikula [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 585df0566a6SJani Nikula [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 586df0566a6SJani Nikula [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 587df0566a6SJani Nikula [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 588df0566a6SJani Nikula [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 589df0566a6SJani Nikula [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 590df0566a6SJani Nikula [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 591df0566a6SJani Nikula [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 592df0566a6SJani Nikula [10] = { 0xb100, 0x1eb8, 0x3620, }, 593df0566a6SJani Nikula [11] = { 0xb100, 0x1f18, 0x34a0, }, 594df0566a6SJani Nikula [12] = { 0xb100, 0x1f68, 0x3360, }, 595df0566a6SJani Nikula [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 596df0566a6SJani Nikula [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 597df0566a6SJani Nikula [15] = { 0xb060, 0x1ff0, 0x30a0, }, 598df0566a6SJani Nikula [16] = { 0x3000, 0x0800, 0x3000, }, 599df0566a6SJani Nikula }; 600df0566a6SJani Nikula 601df0566a6SJani Nikula static void update_polyphase_filter(struct overlay_registers __iomem *regs) 602df0566a6SJani Nikula { 603df0566a6SJani Nikula memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 604df0566a6SJani Nikula memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 605df0566a6SJani Nikula sizeof(uv_static_hcoeffs)); 606df0566a6SJani Nikula } 607df0566a6SJani Nikula 608df0566a6SJani Nikula static bool update_scaling_factors(struct intel_overlay *overlay, 609df0566a6SJani Nikula struct overlay_registers __iomem *regs, 610df0566a6SJani Nikula struct drm_intel_overlay_put_image *params) 611df0566a6SJani Nikula { 612df0566a6SJani Nikula /* fixed point with a 12 bit shift */ 613df0566a6SJani Nikula u32 xscale, yscale, xscale_UV, yscale_UV; 614df0566a6SJani Nikula #define FP_SHIFT 12 615df0566a6SJani Nikula #define FRACT_MASK 0xfff 616df0566a6SJani Nikula bool scale_changed = false; 617df0566a6SJani Nikula int uv_hscale = uv_hsubsampling(params->flags); 618df0566a6SJani Nikula int uv_vscale = uv_vsubsampling(params->flags); 619df0566a6SJani Nikula 620df0566a6SJani Nikula if (params->dst_width > 1) 621df0566a6SJani Nikula xscale = ((params->src_scan_width - 1) << FP_SHIFT) / 622df0566a6SJani Nikula params->dst_width; 623df0566a6SJani Nikula else 624df0566a6SJani Nikula xscale = 1 << FP_SHIFT; 625df0566a6SJani Nikula 626df0566a6SJani Nikula if (params->dst_height > 1) 627df0566a6SJani Nikula yscale = ((params->src_scan_height - 1) << FP_SHIFT) / 628df0566a6SJani Nikula params->dst_height; 629df0566a6SJani Nikula else 630df0566a6SJani Nikula yscale = 1 << FP_SHIFT; 631df0566a6SJani Nikula 632df0566a6SJani Nikula /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 633df0566a6SJani Nikula xscale_UV = xscale/uv_hscale; 634df0566a6SJani Nikula yscale_UV = yscale/uv_vscale; 635df0566a6SJani Nikula /* make the Y scale to UV scale ratio an exact multiply */ 636df0566a6SJani Nikula xscale = xscale_UV * uv_hscale; 637df0566a6SJani Nikula yscale = yscale_UV * uv_vscale; 638df0566a6SJani Nikula /*} else { 639df0566a6SJani Nikula xscale_UV = 0; 640df0566a6SJani Nikula yscale_UV = 0; 641df0566a6SJani Nikula }*/ 642df0566a6SJani Nikula 643df0566a6SJani Nikula if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 644df0566a6SJani Nikula scale_changed = true; 645df0566a6SJani Nikula overlay->old_xscale = xscale; 646df0566a6SJani Nikula overlay->old_yscale = yscale; 647df0566a6SJani Nikula 648df0566a6SJani Nikula iowrite32(((yscale & FRACT_MASK) << 20) | 649df0566a6SJani Nikula ((xscale >> FP_SHIFT) << 16) | 650df0566a6SJani Nikula ((xscale & FRACT_MASK) << 3), 651df0566a6SJani Nikula ®s->YRGBSCALE); 652df0566a6SJani Nikula 653df0566a6SJani Nikula iowrite32(((yscale_UV & FRACT_MASK) << 20) | 654df0566a6SJani Nikula ((xscale_UV >> FP_SHIFT) << 16) | 655df0566a6SJani Nikula ((xscale_UV & FRACT_MASK) << 3), 656df0566a6SJani Nikula ®s->UVSCALE); 657df0566a6SJani Nikula 658df0566a6SJani Nikula iowrite32((((yscale >> FP_SHIFT) << 16) | 659df0566a6SJani Nikula ((yscale_UV >> FP_SHIFT) << 0)), 660df0566a6SJani Nikula ®s->UVSCALEV); 661df0566a6SJani Nikula 662df0566a6SJani Nikula if (scale_changed) 663df0566a6SJani Nikula update_polyphase_filter(regs); 664df0566a6SJani Nikula 665df0566a6SJani Nikula return scale_changed; 666df0566a6SJani Nikula } 667df0566a6SJani Nikula 668df0566a6SJani Nikula static void update_colorkey(struct intel_overlay *overlay, 669df0566a6SJani Nikula struct overlay_registers __iomem *regs) 670df0566a6SJani Nikula { 671df0566a6SJani Nikula const struct intel_plane_state *state = 672df0566a6SJani Nikula to_intel_plane_state(overlay->crtc->base.primary->state); 673df0566a6SJani Nikula u32 key = overlay->color_key; 674df0566a6SJani Nikula u32 format = 0; 675df0566a6SJani Nikula u32 flags = 0; 676df0566a6SJani Nikula 677df0566a6SJani Nikula if (overlay->color_key_enabled) 678df0566a6SJani Nikula flags |= DST_KEY_ENABLE; 679df0566a6SJani Nikula 680f90a85e7SMaarten Lankhorst if (state->uapi.visible) 6817b3cb17aSMaarten Lankhorst format = state->hw.fb->format->format; 682df0566a6SJani Nikula 683df0566a6SJani Nikula switch (format) { 684df0566a6SJani Nikula case DRM_FORMAT_C8: 685df0566a6SJani Nikula key = 0; 686df0566a6SJani Nikula flags |= CLK_RGB8I_MASK; 687df0566a6SJani Nikula break; 688df0566a6SJani Nikula case DRM_FORMAT_XRGB1555: 689df0566a6SJani Nikula key = RGB15_TO_COLORKEY(key); 690df0566a6SJani Nikula flags |= CLK_RGB15_MASK; 691df0566a6SJani Nikula break; 692df0566a6SJani Nikula case DRM_FORMAT_RGB565: 693df0566a6SJani Nikula key = RGB16_TO_COLORKEY(key); 694df0566a6SJani Nikula flags |= CLK_RGB16_MASK; 695df0566a6SJani Nikula break; 696df0566a6SJani Nikula default: 697df0566a6SJani Nikula flags |= CLK_RGB24_MASK; 698df0566a6SJani Nikula break; 699df0566a6SJani Nikula } 700df0566a6SJani Nikula 701df0566a6SJani Nikula iowrite32(key, ®s->DCLRKV); 702df0566a6SJani Nikula iowrite32(flags, ®s->DCLRKM); 703df0566a6SJani Nikula } 704df0566a6SJani Nikula 705df0566a6SJani Nikula static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) 706df0566a6SJani Nikula { 707df0566a6SJani Nikula u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 708df0566a6SJani Nikula 709df0566a6SJani Nikula if (params->flags & I915_OVERLAY_YUV_PLANAR) { 710df0566a6SJani Nikula switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 711df0566a6SJani Nikula case I915_OVERLAY_YUV422: 712df0566a6SJani Nikula cmd |= OCMD_YUV_422_PLANAR; 713df0566a6SJani Nikula break; 714df0566a6SJani Nikula case I915_OVERLAY_YUV420: 715df0566a6SJani Nikula cmd |= OCMD_YUV_420_PLANAR; 716df0566a6SJani Nikula break; 717df0566a6SJani Nikula case I915_OVERLAY_YUV411: 718df0566a6SJani Nikula case I915_OVERLAY_YUV410: 719df0566a6SJani Nikula cmd |= OCMD_YUV_410_PLANAR; 720df0566a6SJani Nikula break; 721df0566a6SJani Nikula } 722df0566a6SJani Nikula } else { /* YUV packed */ 723df0566a6SJani Nikula switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 724df0566a6SJani Nikula case I915_OVERLAY_YUV422: 725df0566a6SJani Nikula cmd |= OCMD_YUV_422_PACKED; 726df0566a6SJani Nikula break; 727df0566a6SJani Nikula case I915_OVERLAY_YUV411: 728df0566a6SJani Nikula cmd |= OCMD_YUV_411_PACKED; 729df0566a6SJani Nikula break; 730df0566a6SJani Nikula } 731df0566a6SJani Nikula 732df0566a6SJani Nikula switch (params->flags & I915_OVERLAY_SWAP_MASK) { 733df0566a6SJani Nikula case I915_OVERLAY_NO_SWAP: 734df0566a6SJani Nikula break; 735df0566a6SJani Nikula case I915_OVERLAY_UV_SWAP: 736df0566a6SJani Nikula cmd |= OCMD_UV_SWAP; 737df0566a6SJani Nikula break; 738df0566a6SJani Nikula case I915_OVERLAY_Y_SWAP: 739df0566a6SJani Nikula cmd |= OCMD_Y_SWAP; 740df0566a6SJani Nikula break; 741df0566a6SJani Nikula case I915_OVERLAY_Y_AND_UV_SWAP: 742df0566a6SJani Nikula cmd |= OCMD_Y_AND_UV_SWAP; 743df0566a6SJani Nikula break; 744df0566a6SJani Nikula } 745df0566a6SJani Nikula } 746df0566a6SJani Nikula 747df0566a6SJani Nikula return cmd; 748df0566a6SJani Nikula } 749df0566a6SJani Nikula 750df0566a6SJani Nikula static int intel_overlay_do_put_image(struct intel_overlay *overlay, 751df0566a6SJani Nikula struct drm_i915_gem_object *new_bo, 752df0566a6SJani Nikula struct drm_intel_overlay_put_image *params) 753df0566a6SJani Nikula { 754df0566a6SJani Nikula struct overlay_registers __iomem *regs = overlay->regs; 755df0566a6SJani Nikula struct drm_i915_private *dev_priv = overlay->i915; 756df0566a6SJani Nikula u32 swidth, swidthsw, sheight, ostride; 757df0566a6SJani Nikula enum pipe pipe = overlay->crtc->pipe; 758df0566a6SJani Nikula bool scale_changed = false; 759df0566a6SJani Nikula struct i915_vma *vma; 760df0566a6SJani Nikula int ret, tmp_width; 761df0566a6SJani Nikula 762b0b2ed0cSPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, 763b0b2ed0cSPankaj Bharadiya !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 764df0566a6SJani Nikula 765df0566a6SJani Nikula ret = intel_overlay_release_old_vid(overlay); 766df0566a6SJani Nikula if (ret != 0) 767df0566a6SJani Nikula return ret; 768df0566a6SJani Nikula 769df0566a6SJani Nikula atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 770df0566a6SJani Nikula 771df0566a6SJani Nikula vma = i915_gem_object_pin_to_display_plane(new_bo, 772df0566a6SJani Nikula 0, NULL, PIN_MAPPABLE); 773df0566a6SJani Nikula if (IS_ERR(vma)) { 774df0566a6SJani Nikula ret = PTR_ERR(vma); 775df0566a6SJani Nikula goto out_pin_section; 776df0566a6SJani Nikula } 777da42104fSChris Wilson i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB); 778df0566a6SJani Nikula 779df0566a6SJani Nikula if (!overlay->active) { 780df0566a6SJani Nikula u32 oconfig; 781df0566a6SJani Nikula 782df0566a6SJani Nikula oconfig = OCONF_CC_OUT_8BIT; 783df0566a6SJani Nikula if (IS_GEN(dev_priv, 4)) 784df0566a6SJani Nikula oconfig |= OCONF_CSC_MODE_BT709; 785df0566a6SJani Nikula oconfig |= pipe == 0 ? 786df0566a6SJani Nikula OCONF_PIPE_A : OCONF_PIPE_B; 787df0566a6SJani Nikula iowrite32(oconfig, ®s->OCONFIG); 788df0566a6SJani Nikula 789df0566a6SJani Nikula ret = intel_overlay_on(overlay); 790df0566a6SJani Nikula if (ret != 0) 791df0566a6SJani Nikula goto out_unpin; 792df0566a6SJani Nikula } 793df0566a6SJani Nikula 794df0566a6SJani Nikula iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS); 795df0566a6SJani Nikula iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ); 796df0566a6SJani Nikula 797df0566a6SJani Nikula if (params->flags & I915_OVERLAY_YUV_PACKED) 798df0566a6SJani Nikula tmp_width = packed_width_bytes(params->flags, 799df0566a6SJani Nikula params->src_width); 800df0566a6SJani Nikula else 801df0566a6SJani Nikula tmp_width = params->src_width; 802df0566a6SJani Nikula 803df0566a6SJani Nikula swidth = params->src_width; 804df0566a6SJani Nikula swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width); 805df0566a6SJani Nikula sheight = params->src_height; 806df0566a6SJani Nikula iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); 807df0566a6SJani Nikula ostride = params->stride_Y; 808df0566a6SJani Nikula 809df0566a6SJani Nikula if (params->flags & I915_OVERLAY_YUV_PLANAR) { 810df0566a6SJani Nikula int uv_hscale = uv_hsubsampling(params->flags); 811df0566a6SJani Nikula int uv_vscale = uv_vsubsampling(params->flags); 812df0566a6SJani Nikula u32 tmp_U, tmp_V; 813df0566a6SJani Nikula 814df0566a6SJani Nikula swidth |= (params->src_width / uv_hscale) << 16; 815df0566a6SJani Nikula sheight |= (params->src_height / uv_vscale) << 16; 816df0566a6SJani Nikula 817df0566a6SJani Nikula tmp_U = calc_swidthsw(dev_priv, params->offset_U, 818df0566a6SJani Nikula params->src_width / uv_hscale); 819df0566a6SJani Nikula tmp_V = calc_swidthsw(dev_priv, params->offset_V, 820df0566a6SJani Nikula params->src_width / uv_hscale); 821df0566a6SJani Nikula swidthsw |= max(tmp_U, tmp_V) << 16; 822df0566a6SJani Nikula 823df0566a6SJani Nikula iowrite32(i915_ggtt_offset(vma) + params->offset_U, 824df0566a6SJani Nikula ®s->OBUF_0U); 825df0566a6SJani Nikula iowrite32(i915_ggtt_offset(vma) + params->offset_V, 826df0566a6SJani Nikula ®s->OBUF_0V); 827df0566a6SJani Nikula 828df0566a6SJani Nikula ostride |= params->stride_UV << 16; 829df0566a6SJani Nikula } 830df0566a6SJani Nikula 831df0566a6SJani Nikula iowrite32(swidth, ®s->SWIDTH); 832df0566a6SJani Nikula iowrite32(swidthsw, ®s->SWIDTHSW); 833df0566a6SJani Nikula iowrite32(sheight, ®s->SHEIGHT); 834df0566a6SJani Nikula iowrite32(ostride, ®s->OSTRIDE); 835df0566a6SJani Nikula 836df0566a6SJani Nikula scale_changed = update_scaling_factors(overlay, regs, params); 837df0566a6SJani Nikula 838df0566a6SJani Nikula update_colorkey(overlay, regs); 839df0566a6SJani Nikula 840df0566a6SJani Nikula iowrite32(overlay_cmd_reg(params), ®s->OCMD); 841df0566a6SJani Nikula 842df0566a6SJani Nikula ret = intel_overlay_continue(overlay, vma, scale_changed); 843df0566a6SJani Nikula if (ret) 844df0566a6SJani Nikula goto out_unpin; 845df0566a6SJani Nikula 846df0566a6SJani Nikula return 0; 847df0566a6SJani Nikula 848df0566a6SJani Nikula out_unpin: 849df0566a6SJani Nikula i915_gem_object_unpin_from_display_plane(vma); 850df0566a6SJani Nikula out_pin_section: 851df0566a6SJani Nikula atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 852df0566a6SJani Nikula 853df0566a6SJani Nikula return ret; 854df0566a6SJani Nikula } 855df0566a6SJani Nikula 856df0566a6SJani Nikula int intel_overlay_switch_off(struct intel_overlay *overlay) 857df0566a6SJani Nikula { 858df0566a6SJani Nikula struct drm_i915_private *dev_priv = overlay->i915; 859df0566a6SJani Nikula int ret; 860df0566a6SJani Nikula 861b0b2ed0cSPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, 862b0b2ed0cSPankaj Bharadiya !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 863df0566a6SJani Nikula 864df0566a6SJani Nikula ret = intel_overlay_recover_from_interrupt(overlay); 865df0566a6SJani Nikula if (ret != 0) 866df0566a6SJani Nikula return ret; 867df0566a6SJani Nikula 868df0566a6SJani Nikula if (!overlay->active) 869df0566a6SJani Nikula return 0; 870df0566a6SJani Nikula 871df0566a6SJani Nikula ret = intel_overlay_release_old_vid(overlay); 872df0566a6SJani Nikula if (ret != 0) 873df0566a6SJani Nikula return ret; 874df0566a6SJani Nikula 875df0566a6SJani Nikula iowrite32(0, &overlay->regs->OCMD); 876df0566a6SJani Nikula 877df0566a6SJani Nikula return intel_overlay_off(overlay); 878df0566a6SJani Nikula } 879df0566a6SJani Nikula 880df0566a6SJani Nikula static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 881df0566a6SJani Nikula struct intel_crtc *crtc) 882df0566a6SJani Nikula { 883df0566a6SJani Nikula if (!crtc->active) 884df0566a6SJani Nikula return -EINVAL; 885df0566a6SJani Nikula 886df0566a6SJani Nikula /* can't use the overlay with double wide pipe */ 887df0566a6SJani Nikula if (crtc->config->double_wide) 888df0566a6SJani Nikula return -EINVAL; 889df0566a6SJani Nikula 890df0566a6SJani Nikula return 0; 891df0566a6SJani Nikula } 892df0566a6SJani Nikula 893df0566a6SJani Nikula static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 894df0566a6SJani Nikula { 895df0566a6SJani Nikula struct drm_i915_private *dev_priv = overlay->i915; 89682e1b12eSJani Nikula u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL); 897df0566a6SJani Nikula u32 ratio; 898df0566a6SJani Nikula 899df0566a6SJani Nikula /* XXX: This is not the same logic as in the xorg driver, but more in 900df0566a6SJani Nikula * line with the intel documentation for the i965 901df0566a6SJani Nikula */ 902df0566a6SJani Nikula if (INTEL_GEN(dev_priv) >= 4) { 903df0566a6SJani Nikula /* on i965 use the PGM reg to read out the autoscaler values */ 90482e1b12eSJani Nikula ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; 905df0566a6SJani Nikula } else { 906df0566a6SJani Nikula if (pfit_control & VERT_AUTO_SCALE) 90782e1b12eSJani Nikula ratio = intel_de_read(dev_priv, PFIT_AUTO_RATIOS); 908df0566a6SJani Nikula else 90982e1b12eSJani Nikula ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS); 910df0566a6SJani Nikula ratio >>= PFIT_VERT_SCALE_SHIFT; 911df0566a6SJani Nikula } 912df0566a6SJani Nikula 913df0566a6SJani Nikula overlay->pfit_vscale_ratio = ratio; 914df0566a6SJani Nikula } 915df0566a6SJani Nikula 916df0566a6SJani Nikula static int check_overlay_dst(struct intel_overlay *overlay, 917df0566a6SJani Nikula struct drm_intel_overlay_put_image *rec) 918df0566a6SJani Nikula { 919df0566a6SJani Nikula const struct intel_crtc_state *pipe_config = 920df0566a6SJani Nikula overlay->crtc->config; 921df0566a6SJani Nikula 922df0566a6SJani Nikula if (rec->dst_x < pipe_config->pipe_src_w && 923df0566a6SJani Nikula rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && 924df0566a6SJani Nikula rec->dst_y < pipe_config->pipe_src_h && 925df0566a6SJani Nikula rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) 926df0566a6SJani Nikula return 0; 927df0566a6SJani Nikula else 928df0566a6SJani Nikula return -EINVAL; 929df0566a6SJani Nikula } 930df0566a6SJani Nikula 931df0566a6SJani Nikula static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) 932df0566a6SJani Nikula { 933df0566a6SJani Nikula u32 tmp; 934df0566a6SJani Nikula 935df0566a6SJani Nikula /* downscaling limit is 8.0 */ 936df0566a6SJani Nikula tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16; 937df0566a6SJani Nikula if (tmp > 7) 938df0566a6SJani Nikula return -EINVAL; 939df0566a6SJani Nikula 940df0566a6SJani Nikula tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16; 941df0566a6SJani Nikula if (tmp > 7) 942df0566a6SJani Nikula return -EINVAL; 943df0566a6SJani Nikula 944df0566a6SJani Nikula return 0; 945df0566a6SJani Nikula } 946df0566a6SJani Nikula 947df0566a6SJani Nikula static int check_overlay_src(struct drm_i915_private *dev_priv, 948df0566a6SJani Nikula struct drm_intel_overlay_put_image *rec, 949df0566a6SJani Nikula struct drm_i915_gem_object *new_bo) 950df0566a6SJani Nikula { 951df0566a6SJani Nikula int uv_hscale = uv_hsubsampling(rec->flags); 952df0566a6SJani Nikula int uv_vscale = uv_vsubsampling(rec->flags); 953df0566a6SJani Nikula u32 stride_mask; 954df0566a6SJani Nikula int depth; 955df0566a6SJani Nikula u32 tmp; 956df0566a6SJani Nikula 957df0566a6SJani Nikula /* check src dimensions */ 958df0566a6SJani Nikula if (IS_I845G(dev_priv) || IS_I830(dev_priv)) { 959df0566a6SJani Nikula if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 960df0566a6SJani Nikula rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 961df0566a6SJani Nikula return -EINVAL; 962df0566a6SJani Nikula } else { 963df0566a6SJani Nikula if (rec->src_height > IMAGE_MAX_HEIGHT || 964df0566a6SJani Nikula rec->src_width > IMAGE_MAX_WIDTH) 965df0566a6SJani Nikula return -EINVAL; 966df0566a6SJani Nikula } 967df0566a6SJani Nikula 968df0566a6SJani Nikula /* better safe than sorry, use 4 as the maximal subsampling ratio */ 969df0566a6SJani Nikula if (rec->src_height < N_VERT_Y_TAPS*4 || 970df0566a6SJani Nikula rec->src_width < N_HORIZ_Y_TAPS*4) 971df0566a6SJani Nikula return -EINVAL; 972df0566a6SJani Nikula 973df0566a6SJani Nikula /* check alignment constraints */ 974df0566a6SJani Nikula switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 975df0566a6SJani Nikula case I915_OVERLAY_RGB: 976df0566a6SJani Nikula /* not implemented */ 977df0566a6SJani Nikula return -EINVAL; 978df0566a6SJani Nikula 979df0566a6SJani Nikula case I915_OVERLAY_YUV_PACKED: 980df0566a6SJani Nikula if (uv_vscale != 1) 981df0566a6SJani Nikula return -EINVAL; 982df0566a6SJani Nikula 983df0566a6SJani Nikula depth = packed_depth_bytes(rec->flags); 984df0566a6SJani Nikula if (depth < 0) 985df0566a6SJani Nikula return depth; 986df0566a6SJani Nikula 987df0566a6SJani Nikula /* ignore UV planes */ 988df0566a6SJani Nikula rec->stride_UV = 0; 989df0566a6SJani Nikula rec->offset_U = 0; 990df0566a6SJani Nikula rec->offset_V = 0; 991df0566a6SJani Nikula /* check pixel alignment */ 992df0566a6SJani Nikula if (rec->offset_Y % depth) 993df0566a6SJani Nikula return -EINVAL; 994df0566a6SJani Nikula break; 995df0566a6SJani Nikula 996df0566a6SJani Nikula case I915_OVERLAY_YUV_PLANAR: 997df0566a6SJani Nikula if (uv_vscale < 0 || uv_hscale < 0) 998df0566a6SJani Nikula return -EINVAL; 999df0566a6SJani Nikula /* no offset restrictions for planar formats */ 1000df0566a6SJani Nikula break; 1001df0566a6SJani Nikula 1002df0566a6SJani Nikula default: 1003df0566a6SJani Nikula return -EINVAL; 1004df0566a6SJani Nikula } 1005df0566a6SJani Nikula 1006df0566a6SJani Nikula if (rec->src_width % uv_hscale) 1007df0566a6SJani Nikula return -EINVAL; 1008df0566a6SJani Nikula 1009df0566a6SJani Nikula /* stride checking */ 1010df0566a6SJani Nikula if (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1011df0566a6SJani Nikula stride_mask = 255; 1012df0566a6SJani Nikula else 1013df0566a6SJani Nikula stride_mask = 63; 1014df0566a6SJani Nikula 1015df0566a6SJani Nikula if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1016df0566a6SJani Nikula return -EINVAL; 1017df0566a6SJani Nikula if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512) 1018df0566a6SJani Nikula return -EINVAL; 1019df0566a6SJani Nikula 1020df0566a6SJani Nikula tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1021df0566a6SJani Nikula 4096 : 8192; 1022df0566a6SJani Nikula if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 1023df0566a6SJani Nikula return -EINVAL; 1024df0566a6SJani Nikula 1025df0566a6SJani Nikula /* check buffer dimensions */ 1026df0566a6SJani Nikula switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1027df0566a6SJani Nikula case I915_OVERLAY_RGB: 1028df0566a6SJani Nikula case I915_OVERLAY_YUV_PACKED: 1029df0566a6SJani Nikula /* always 4 Y values per depth pixels */ 1030df0566a6SJani Nikula if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 1031df0566a6SJani Nikula return -EINVAL; 1032df0566a6SJani Nikula 1033df0566a6SJani Nikula tmp = rec->stride_Y*rec->src_height; 1034df0566a6SJani Nikula if (rec->offset_Y + tmp > new_bo->base.size) 1035df0566a6SJani Nikula return -EINVAL; 1036df0566a6SJani Nikula break; 1037df0566a6SJani Nikula 1038df0566a6SJani Nikula case I915_OVERLAY_YUV_PLANAR: 1039df0566a6SJani Nikula if (rec->src_width > rec->stride_Y) 1040df0566a6SJani Nikula return -EINVAL; 1041df0566a6SJani Nikula if (rec->src_width/uv_hscale > rec->stride_UV) 1042df0566a6SJani Nikula return -EINVAL; 1043df0566a6SJani Nikula 1044df0566a6SJani Nikula tmp = rec->stride_Y * rec->src_height; 1045df0566a6SJani Nikula if (rec->offset_Y + tmp > new_bo->base.size) 1046df0566a6SJani Nikula return -EINVAL; 1047df0566a6SJani Nikula 1048df0566a6SJani Nikula tmp = rec->stride_UV * (rec->src_height / uv_vscale); 1049df0566a6SJani Nikula if (rec->offset_U + tmp > new_bo->base.size || 1050df0566a6SJani Nikula rec->offset_V + tmp > new_bo->base.size) 1051df0566a6SJani Nikula return -EINVAL; 1052df0566a6SJani Nikula break; 1053df0566a6SJani Nikula } 1054df0566a6SJani Nikula 1055df0566a6SJani Nikula return 0; 1056df0566a6SJani Nikula } 1057df0566a6SJani Nikula 1058df0566a6SJani Nikula int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1059df0566a6SJani Nikula struct drm_file *file_priv) 1060df0566a6SJani Nikula { 1061df0566a6SJani Nikula struct drm_intel_overlay_put_image *params = data; 1062df0566a6SJani Nikula struct drm_i915_private *dev_priv = to_i915(dev); 1063df0566a6SJani Nikula struct intel_overlay *overlay; 1064df0566a6SJani Nikula struct drm_crtc *drmmode_crtc; 1065df0566a6SJani Nikula struct intel_crtc *crtc; 1066df0566a6SJani Nikula struct drm_i915_gem_object *new_bo; 1067df0566a6SJani Nikula int ret; 1068df0566a6SJani Nikula 1069df0566a6SJani Nikula overlay = dev_priv->overlay; 1070df0566a6SJani Nikula if (!overlay) { 10713c4e93e9SWambui Karuga drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n"); 1072df0566a6SJani Nikula return -ENODEV; 1073df0566a6SJani Nikula } 1074df0566a6SJani Nikula 1075df0566a6SJani Nikula if (!(params->flags & I915_OVERLAY_ENABLE)) { 1076df0566a6SJani Nikula drm_modeset_lock_all(dev); 1077df0566a6SJani Nikula ret = intel_overlay_switch_off(overlay); 1078df0566a6SJani Nikula drm_modeset_unlock_all(dev); 1079df0566a6SJani Nikula 1080df0566a6SJani Nikula return ret; 1081df0566a6SJani Nikula } 1082df0566a6SJani Nikula 1083df0566a6SJani Nikula drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id); 1084df0566a6SJani Nikula if (!drmmode_crtc) 1085df0566a6SJani Nikula return -ENOENT; 1086df0566a6SJani Nikula crtc = to_intel_crtc(drmmode_crtc); 1087df0566a6SJani Nikula 1088df0566a6SJani Nikula new_bo = i915_gem_object_lookup(file_priv, params->bo_handle); 1089df0566a6SJani Nikula if (!new_bo) 1090df0566a6SJani Nikula return -ENOENT; 1091df0566a6SJani Nikula 1092df0566a6SJani Nikula drm_modeset_lock_all(dev); 1093df0566a6SJani Nikula 1094df0566a6SJani Nikula if (i915_gem_object_is_tiled(new_bo)) { 10953c4e93e9SWambui Karuga drm_dbg_kms(&dev_priv->drm, 10963c4e93e9SWambui Karuga "buffer used for overlay image can not be tiled\n"); 1097df0566a6SJani Nikula ret = -EINVAL; 1098df0566a6SJani Nikula goto out_unlock; 1099df0566a6SJani Nikula } 1100df0566a6SJani Nikula 1101df0566a6SJani Nikula ret = intel_overlay_recover_from_interrupt(overlay); 1102df0566a6SJani Nikula if (ret != 0) 1103df0566a6SJani Nikula goto out_unlock; 1104df0566a6SJani Nikula 1105df0566a6SJani Nikula if (overlay->crtc != crtc) { 1106df0566a6SJani Nikula ret = intel_overlay_switch_off(overlay); 1107df0566a6SJani Nikula if (ret != 0) 1108df0566a6SJani Nikula goto out_unlock; 1109df0566a6SJani Nikula 1110df0566a6SJani Nikula ret = check_overlay_possible_on_crtc(overlay, crtc); 1111df0566a6SJani Nikula if (ret != 0) 1112df0566a6SJani Nikula goto out_unlock; 1113df0566a6SJani Nikula 1114df0566a6SJani Nikula overlay->crtc = crtc; 1115df0566a6SJani Nikula crtc->overlay = overlay; 1116df0566a6SJani Nikula 1117df0566a6SJani Nikula /* line too wide, i.e. one-line-mode */ 1118df0566a6SJani Nikula if (crtc->config->pipe_src_w > 1024 && 1119df0566a6SJani Nikula crtc->config->gmch_pfit.control & PFIT_ENABLE) { 1120df0566a6SJani Nikula overlay->pfit_active = true; 1121df0566a6SJani Nikula update_pfit_vscale_ratio(overlay); 1122df0566a6SJani Nikula } else 1123df0566a6SJani Nikula overlay->pfit_active = false; 1124df0566a6SJani Nikula } 1125df0566a6SJani Nikula 1126df0566a6SJani Nikula ret = check_overlay_dst(overlay, params); 1127df0566a6SJani Nikula if (ret != 0) 1128df0566a6SJani Nikula goto out_unlock; 1129df0566a6SJani Nikula 1130df0566a6SJani Nikula if (overlay->pfit_active) { 1131df0566a6SJani Nikula params->dst_y = (((u32)params->dst_y << 12) / 1132df0566a6SJani Nikula overlay->pfit_vscale_ratio); 1133df0566a6SJani Nikula /* shifting right rounds downwards, so add 1 */ 1134df0566a6SJani Nikula params->dst_height = (((u32)params->dst_height << 12) / 1135df0566a6SJani Nikula overlay->pfit_vscale_ratio) + 1; 1136df0566a6SJani Nikula } 1137df0566a6SJani Nikula 1138df0566a6SJani Nikula if (params->src_scan_height > params->src_height || 1139df0566a6SJani Nikula params->src_scan_width > params->src_width) { 1140df0566a6SJani Nikula ret = -EINVAL; 1141df0566a6SJani Nikula goto out_unlock; 1142df0566a6SJani Nikula } 1143df0566a6SJani Nikula 1144df0566a6SJani Nikula ret = check_overlay_src(dev_priv, params, new_bo); 1145df0566a6SJani Nikula if (ret != 0) 1146df0566a6SJani Nikula goto out_unlock; 1147df0566a6SJani Nikula 1148df0566a6SJani Nikula /* Check scaling after src size to prevent a divide-by-zero. */ 1149df0566a6SJani Nikula ret = check_overlay_scaling(params); 1150df0566a6SJani Nikula if (ret != 0) 1151df0566a6SJani Nikula goto out_unlock; 1152df0566a6SJani Nikula 1153df0566a6SJani Nikula ret = intel_overlay_do_put_image(overlay, new_bo, params); 1154df0566a6SJani Nikula if (ret != 0) 1155df0566a6SJani Nikula goto out_unlock; 1156df0566a6SJani Nikula 1157df0566a6SJani Nikula drm_modeset_unlock_all(dev); 1158df0566a6SJani Nikula i915_gem_object_put(new_bo); 1159df0566a6SJani Nikula 1160df0566a6SJani Nikula return 0; 1161df0566a6SJani Nikula 1162df0566a6SJani Nikula out_unlock: 1163df0566a6SJani Nikula drm_modeset_unlock_all(dev); 1164df0566a6SJani Nikula i915_gem_object_put(new_bo); 1165df0566a6SJani Nikula 1166df0566a6SJani Nikula return ret; 1167df0566a6SJani Nikula } 1168df0566a6SJani Nikula 1169df0566a6SJani Nikula static void update_reg_attrs(struct intel_overlay *overlay, 1170df0566a6SJani Nikula struct overlay_registers __iomem *regs) 1171df0566a6SJani Nikula { 1172df0566a6SJani Nikula iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 1173df0566a6SJani Nikula ®s->OCLRC0); 1174df0566a6SJani Nikula iowrite32(overlay->saturation, ®s->OCLRC1); 1175df0566a6SJani Nikula } 1176df0566a6SJani Nikula 1177df0566a6SJani Nikula static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 1178df0566a6SJani Nikula { 1179df0566a6SJani Nikula int i; 1180df0566a6SJani Nikula 1181df0566a6SJani Nikula if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 1182df0566a6SJani Nikula return false; 1183df0566a6SJani Nikula 1184df0566a6SJani Nikula for (i = 0; i < 3; i++) { 1185df0566a6SJani Nikula if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 1186df0566a6SJani Nikula return false; 1187df0566a6SJani Nikula } 1188df0566a6SJani Nikula 1189df0566a6SJani Nikula return true; 1190df0566a6SJani Nikula } 1191df0566a6SJani Nikula 1192df0566a6SJani Nikula static bool check_gamma5_errata(u32 gamma5) 1193df0566a6SJani Nikula { 1194df0566a6SJani Nikula int i; 1195df0566a6SJani Nikula 1196df0566a6SJani Nikula for (i = 0; i < 3; i++) { 1197df0566a6SJani Nikula if (((gamma5 >> i*8) & 0xff) == 0x80) 1198df0566a6SJani Nikula return false; 1199df0566a6SJani Nikula } 1200df0566a6SJani Nikula 1201df0566a6SJani Nikula return true; 1202df0566a6SJani Nikula } 1203df0566a6SJani Nikula 1204df0566a6SJani Nikula static int check_gamma(struct drm_intel_overlay_attrs *attrs) 1205df0566a6SJani Nikula { 1206df0566a6SJani Nikula if (!check_gamma_bounds(0, attrs->gamma0) || 1207df0566a6SJani Nikula !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 1208df0566a6SJani Nikula !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 1209df0566a6SJani Nikula !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 1210df0566a6SJani Nikula !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 1211df0566a6SJani Nikula !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 1212df0566a6SJani Nikula !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 1213df0566a6SJani Nikula return -EINVAL; 1214df0566a6SJani Nikula 1215df0566a6SJani Nikula if (!check_gamma5_errata(attrs->gamma5)) 1216df0566a6SJani Nikula return -EINVAL; 1217df0566a6SJani Nikula 1218df0566a6SJani Nikula return 0; 1219df0566a6SJani Nikula } 1220df0566a6SJani Nikula 1221df0566a6SJani Nikula int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1222df0566a6SJani Nikula struct drm_file *file_priv) 1223df0566a6SJani Nikula { 1224df0566a6SJani Nikula struct drm_intel_overlay_attrs *attrs = data; 1225df0566a6SJani Nikula struct drm_i915_private *dev_priv = to_i915(dev); 1226df0566a6SJani Nikula struct intel_overlay *overlay; 1227df0566a6SJani Nikula int ret; 1228df0566a6SJani Nikula 1229df0566a6SJani Nikula overlay = dev_priv->overlay; 1230df0566a6SJani Nikula if (!overlay) { 12313c4e93e9SWambui Karuga drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n"); 1232df0566a6SJani Nikula return -ENODEV; 1233df0566a6SJani Nikula } 1234df0566a6SJani Nikula 1235df0566a6SJani Nikula drm_modeset_lock_all(dev); 1236df0566a6SJani Nikula 1237df0566a6SJani Nikula ret = -EINVAL; 1238df0566a6SJani Nikula if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 1239df0566a6SJani Nikula attrs->color_key = overlay->color_key; 1240df0566a6SJani Nikula attrs->brightness = overlay->brightness; 1241df0566a6SJani Nikula attrs->contrast = overlay->contrast; 1242df0566a6SJani Nikula attrs->saturation = overlay->saturation; 1243df0566a6SJani Nikula 1244df0566a6SJani Nikula if (!IS_GEN(dev_priv, 2)) { 124582e1b12eSJani Nikula attrs->gamma0 = intel_de_read(dev_priv, OGAMC0); 124682e1b12eSJani Nikula attrs->gamma1 = intel_de_read(dev_priv, OGAMC1); 124782e1b12eSJani Nikula attrs->gamma2 = intel_de_read(dev_priv, OGAMC2); 124882e1b12eSJani Nikula attrs->gamma3 = intel_de_read(dev_priv, OGAMC3); 124982e1b12eSJani Nikula attrs->gamma4 = intel_de_read(dev_priv, OGAMC4); 125082e1b12eSJani Nikula attrs->gamma5 = intel_de_read(dev_priv, OGAMC5); 1251df0566a6SJani Nikula } 1252df0566a6SJani Nikula } else { 1253df0566a6SJani Nikula if (attrs->brightness < -128 || attrs->brightness > 127) 1254df0566a6SJani Nikula goto out_unlock; 1255df0566a6SJani Nikula if (attrs->contrast > 255) 1256df0566a6SJani Nikula goto out_unlock; 1257df0566a6SJani Nikula if (attrs->saturation > 1023) 1258df0566a6SJani Nikula goto out_unlock; 1259df0566a6SJani Nikula 1260df0566a6SJani Nikula overlay->color_key = attrs->color_key; 1261df0566a6SJani Nikula overlay->brightness = attrs->brightness; 1262df0566a6SJani Nikula overlay->contrast = attrs->contrast; 1263df0566a6SJani Nikula overlay->saturation = attrs->saturation; 1264df0566a6SJani Nikula 1265df0566a6SJani Nikula update_reg_attrs(overlay, overlay->regs); 1266df0566a6SJani Nikula 1267df0566a6SJani Nikula if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1268df0566a6SJani Nikula if (IS_GEN(dev_priv, 2)) 1269df0566a6SJani Nikula goto out_unlock; 1270df0566a6SJani Nikula 1271df0566a6SJani Nikula if (overlay->active) { 1272df0566a6SJani Nikula ret = -EBUSY; 1273df0566a6SJani Nikula goto out_unlock; 1274df0566a6SJani Nikula } 1275df0566a6SJani Nikula 1276df0566a6SJani Nikula ret = check_gamma(attrs); 1277df0566a6SJani Nikula if (ret) 1278df0566a6SJani Nikula goto out_unlock; 1279df0566a6SJani Nikula 128082e1b12eSJani Nikula intel_de_write(dev_priv, OGAMC0, attrs->gamma0); 128182e1b12eSJani Nikula intel_de_write(dev_priv, OGAMC1, attrs->gamma1); 128282e1b12eSJani Nikula intel_de_write(dev_priv, OGAMC2, attrs->gamma2); 128382e1b12eSJani Nikula intel_de_write(dev_priv, OGAMC3, attrs->gamma3); 128482e1b12eSJani Nikula intel_de_write(dev_priv, OGAMC4, attrs->gamma4); 128582e1b12eSJani Nikula intel_de_write(dev_priv, OGAMC5, attrs->gamma5); 1286df0566a6SJani Nikula } 1287df0566a6SJani Nikula } 1288df0566a6SJani Nikula overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1289df0566a6SJani Nikula 1290df0566a6SJani Nikula ret = 0; 1291df0566a6SJani Nikula out_unlock: 1292df0566a6SJani Nikula drm_modeset_unlock_all(dev); 1293df0566a6SJani Nikula 1294df0566a6SJani Nikula return ret; 1295df0566a6SJani Nikula } 1296df0566a6SJani Nikula 1297df0566a6SJani Nikula static int get_registers(struct intel_overlay *overlay, bool use_phys) 1298df0566a6SJani Nikula { 1299df0566a6SJani Nikula struct drm_i915_private *i915 = overlay->i915; 1300df0566a6SJani Nikula struct drm_i915_gem_object *obj; 1301df0566a6SJani Nikula struct i915_vma *vma; 1302df0566a6SJani Nikula int err; 1303df0566a6SJani Nikula 1304df0566a6SJani Nikula obj = i915_gem_object_create_stolen(i915, PAGE_SIZE); 13050e5493caSCQ Tang if (IS_ERR(obj)) 1306df0566a6SJani Nikula obj = i915_gem_object_create_internal(i915, PAGE_SIZE); 13072850748eSChris Wilson if (IS_ERR(obj)) 13082850748eSChris Wilson return PTR_ERR(obj); 1309df0566a6SJani Nikula 1310df0566a6SJani Nikula vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); 1311df0566a6SJani Nikula if (IS_ERR(vma)) { 1312df0566a6SJani Nikula err = PTR_ERR(vma); 1313df0566a6SJani Nikula goto err_put_bo; 1314df0566a6SJani Nikula } 1315df0566a6SJani Nikula 1316df0566a6SJani Nikula if (use_phys) 1317df0566a6SJani Nikula overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl); 1318df0566a6SJani Nikula else 1319df0566a6SJani Nikula overlay->flip_addr = i915_ggtt_offset(vma); 1320df0566a6SJani Nikula overlay->regs = i915_vma_pin_iomap(vma); 1321df0566a6SJani Nikula i915_vma_unpin(vma); 1322df0566a6SJani Nikula 1323df0566a6SJani Nikula if (IS_ERR(overlay->regs)) { 1324df0566a6SJani Nikula err = PTR_ERR(overlay->regs); 1325df0566a6SJani Nikula goto err_put_bo; 1326df0566a6SJani Nikula } 1327df0566a6SJani Nikula 1328df0566a6SJani Nikula overlay->reg_bo = obj; 1329df0566a6SJani Nikula return 0; 1330df0566a6SJani Nikula 1331df0566a6SJani Nikula err_put_bo: 1332df0566a6SJani Nikula i915_gem_object_put(obj); 1333df0566a6SJani Nikula return err; 1334df0566a6SJani Nikula } 1335df0566a6SJani Nikula 1336df0566a6SJani Nikula void intel_overlay_setup(struct drm_i915_private *dev_priv) 1337df0566a6SJani Nikula { 1338df0566a6SJani Nikula struct intel_overlay *overlay; 1339e26b6d43SChris Wilson struct intel_engine_cs *engine; 1340df0566a6SJani Nikula int ret; 1341df0566a6SJani Nikula 1342df0566a6SJani Nikula if (!HAS_OVERLAY(dev_priv)) 1343df0566a6SJani Nikula return; 1344df0566a6SJani Nikula 134573c8bfb7SChris Wilson engine = dev_priv->gt.engine[RCS0]; 1346e26b6d43SChris Wilson if (!engine || !engine->kernel_context) 1347ec22f256SChris Wilson return; 1348ec22f256SChris Wilson 1349df0566a6SJani Nikula overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 1350df0566a6SJani Nikula if (!overlay) 1351df0566a6SJani Nikula return; 1352df0566a6SJani Nikula 1353df0566a6SJani Nikula overlay->i915 = dev_priv; 1354e26b6d43SChris Wilson overlay->context = engine->kernel_context; 1355ec22f256SChris Wilson GEM_BUG_ON(!overlay->context); 1356df0566a6SJani Nikula 1357df0566a6SJani Nikula overlay->color_key = 0x0101fe; 1358df0566a6SJani Nikula overlay->color_key_enabled = true; 1359df0566a6SJani Nikula overlay->brightness = -19; 1360df0566a6SJani Nikula overlay->contrast = 75; 1361df0566a6SJani Nikula overlay->saturation = 146; 1362df0566a6SJani Nikula 1363b1e3177bSChris Wilson i915_active_init(&overlay->last_flip, 1364a21ce8adSChris Wilson NULL, intel_overlay_last_flip_retire); 1365df0566a6SJani Nikula 1366df0566a6SJani Nikula ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv)); 1367df0566a6SJani Nikula if (ret) 1368df0566a6SJani Nikula goto out_free; 1369df0566a6SJani Nikula 1370df0566a6SJani Nikula memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1371df0566a6SJani Nikula update_polyphase_filter(overlay->regs); 1372df0566a6SJani Nikula update_reg_attrs(overlay, overlay->regs); 1373df0566a6SJani Nikula 1374df0566a6SJani Nikula dev_priv->overlay = overlay; 13753c4e93e9SWambui Karuga drm_info(&dev_priv->drm, "Initialized overlay support.\n"); 1376df0566a6SJani Nikula return; 1377df0566a6SJani Nikula 1378df0566a6SJani Nikula out_free: 1379df0566a6SJani Nikula kfree(overlay); 1380df0566a6SJani Nikula } 1381df0566a6SJani Nikula 1382df0566a6SJani Nikula void intel_overlay_cleanup(struct drm_i915_private *dev_priv) 1383df0566a6SJani Nikula { 1384df0566a6SJani Nikula struct intel_overlay *overlay; 1385df0566a6SJani Nikula 1386df0566a6SJani Nikula overlay = fetch_and_zero(&dev_priv->overlay); 1387df0566a6SJani Nikula if (!overlay) 1388df0566a6SJani Nikula return; 1389df0566a6SJani Nikula 1390df0566a6SJani Nikula /* 1391df0566a6SJani Nikula * The bo's should be free'd by the generic code already. 1392df0566a6SJani Nikula * Furthermore modesetting teardown happens beforehand so the 1393df0566a6SJani Nikula * hardware should be off already. 1394df0566a6SJani Nikula */ 1395b0b2ed0cSPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, overlay->active); 1396df0566a6SJani Nikula 1397df0566a6SJani Nikula i915_gem_object_put(overlay->reg_bo); 1398a21ce8adSChris Wilson i915_active_fini(&overlay->last_flip); 1399df0566a6SJani Nikula 1400df0566a6SJani Nikula kfree(overlay); 1401df0566a6SJani Nikula } 1402df0566a6SJani Nikula 1403df0566a6SJani Nikula #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1404df0566a6SJani Nikula 1405df0566a6SJani Nikula struct intel_overlay_error_state { 1406df0566a6SJani Nikula struct overlay_registers regs; 1407df0566a6SJani Nikula unsigned long base; 1408df0566a6SJani Nikula u32 dovsta; 1409df0566a6SJani Nikula u32 isr; 1410df0566a6SJani Nikula }; 1411df0566a6SJani Nikula 1412df0566a6SJani Nikula struct intel_overlay_error_state * 1413df0566a6SJani Nikula intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) 1414df0566a6SJani Nikula { 1415df0566a6SJani Nikula struct intel_overlay *overlay = dev_priv->overlay; 1416df0566a6SJani Nikula struct intel_overlay_error_state *error; 1417df0566a6SJani Nikula 1418df0566a6SJani Nikula if (!overlay || !overlay->active) 1419df0566a6SJani Nikula return NULL; 1420df0566a6SJani Nikula 1421df0566a6SJani Nikula error = kmalloc(sizeof(*error), GFP_ATOMIC); 1422df0566a6SJani Nikula if (error == NULL) 1423df0566a6SJani Nikula return NULL; 1424df0566a6SJani Nikula 142582e1b12eSJani Nikula error->dovsta = intel_de_read(dev_priv, DOVSTA); 142682e1b12eSJani Nikula error->isr = intel_de_read(dev_priv, GEN2_ISR); 1427df0566a6SJani Nikula error->base = overlay->flip_addr; 1428df0566a6SJani Nikula 1429df0566a6SJani Nikula memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs)); 1430df0566a6SJani Nikula 1431df0566a6SJani Nikula return error; 1432df0566a6SJani Nikula } 1433df0566a6SJani Nikula 1434df0566a6SJani Nikula void 1435df0566a6SJani Nikula intel_overlay_print_error_state(struct drm_i915_error_state_buf *m, 1436df0566a6SJani Nikula struct intel_overlay_error_state *error) 1437df0566a6SJani Nikula { 1438df0566a6SJani Nikula i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1439df0566a6SJani Nikula error->dovsta, error->isr); 1440df0566a6SJani Nikula i915_error_printf(m, " Register file at 0x%08lx:\n", 1441df0566a6SJani Nikula error->base); 1442df0566a6SJani Nikula 1443df0566a6SJani Nikula #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) 1444df0566a6SJani Nikula P(OBUF_0Y); 1445df0566a6SJani Nikula P(OBUF_1Y); 1446df0566a6SJani Nikula P(OBUF_0U); 1447df0566a6SJani Nikula P(OBUF_0V); 1448df0566a6SJani Nikula P(OBUF_1U); 1449df0566a6SJani Nikula P(OBUF_1V); 1450df0566a6SJani Nikula P(OSTRIDE); 1451df0566a6SJani Nikula P(YRGB_VPH); 1452df0566a6SJani Nikula P(UV_VPH); 1453df0566a6SJani Nikula P(HORZ_PH); 1454df0566a6SJani Nikula P(INIT_PHS); 1455df0566a6SJani Nikula P(DWINPOS); 1456df0566a6SJani Nikula P(DWINSZ); 1457df0566a6SJani Nikula P(SWIDTH); 1458df0566a6SJani Nikula P(SWIDTHSW); 1459df0566a6SJani Nikula P(SHEIGHT); 1460df0566a6SJani Nikula P(YRGBSCALE); 1461df0566a6SJani Nikula P(UVSCALE); 1462df0566a6SJani Nikula P(OCLRC0); 1463df0566a6SJani Nikula P(OCLRC1); 1464df0566a6SJani Nikula P(DCLRKV); 1465df0566a6SJani Nikula P(DCLRKM); 1466df0566a6SJani Nikula P(SCLRKVH); 1467df0566a6SJani Nikula P(SCLRKVL); 1468df0566a6SJani Nikula P(SCLRKEN); 1469df0566a6SJani Nikula P(OCONFIG); 1470df0566a6SJani Nikula P(OCMD); 1471df0566a6SJani Nikula P(OSTART_0Y); 1472df0566a6SJani Nikula P(OSTART_1Y); 1473df0566a6SJani Nikula P(OSTART_0U); 1474df0566a6SJani Nikula P(OSTART_0V); 1475df0566a6SJani Nikula P(OSTART_1U); 1476df0566a6SJani Nikula P(OSTART_1V); 1477df0566a6SJani Nikula P(OTILEOFF_0Y); 1478df0566a6SJani Nikula P(OTILEOFF_1Y); 1479df0566a6SJani Nikula P(OTILEOFF_0U); 1480df0566a6SJani Nikula P(OTILEOFF_0V); 1481df0566a6SJani Nikula P(OTILEOFF_1U); 1482df0566a6SJani Nikula P(OTILEOFF_1V); 1483df0566a6SJani Nikula P(FASTHSCALE); 1484df0566a6SJani Nikula P(UVSCALEV); 1485df0566a6SJani Nikula #undef P 1486df0566a6SJani Nikula } 1487df0566a6SJani Nikula 1488df0566a6SJani Nikula #endif 1489