1df0566a6SJani Nikula /* 2df0566a6SJani Nikula * Copyright © 2009 3df0566a6SJani Nikula * 4df0566a6SJani Nikula * Permission is hereby granted, free of charge, to any person obtaining a 5df0566a6SJani Nikula * copy of this software and associated documentation files (the "Software"), 6df0566a6SJani Nikula * to deal in the Software without restriction, including without limitation 7df0566a6SJani Nikula * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8df0566a6SJani Nikula * and/or sell copies of the Software, and to permit persons to whom the 9df0566a6SJani Nikula * Software is furnished to do so, subject to the following conditions: 10df0566a6SJani Nikula * 11df0566a6SJani Nikula * The above copyright notice and this permission notice (including the next 12df0566a6SJani Nikula * paragraph) shall be included in all copies or substantial portions of the 13df0566a6SJani Nikula * Software. 14df0566a6SJani Nikula * 15df0566a6SJani Nikula * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16df0566a6SJani Nikula * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17df0566a6SJani Nikula * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18df0566a6SJani Nikula * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19df0566a6SJani Nikula * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20df0566a6SJani Nikula * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21df0566a6SJani Nikula * SOFTWARE. 22df0566a6SJani Nikula * 23df0566a6SJani Nikula * Authors: 24df0566a6SJani Nikula * Daniel Vetter <daniel@ffwll.ch> 25df0566a6SJani Nikula * 26df0566a6SJani Nikula * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27df0566a6SJani Nikula */ 28df0566a6SJani Nikula 29df0566a6SJani Nikula #include <drm/drm_fourcc.h> 30df0566a6SJani Nikula 31df0566a6SJani Nikula #include "gem/i915_gem_pm.h" 322871ea85SChris Wilson #include "gt/intel_ring.h" 33df0566a6SJani Nikula 34df0566a6SJani Nikula #include "i915_drv.h" 35df0566a6SJani Nikula #include "i915_reg.h" 361d455f8dSJani Nikula #include "intel_display_types.h" 37df0566a6SJani Nikula #include "intel_frontbuffer.h" 38df0566a6SJani Nikula #include "intel_overlay.h" 39df0566a6SJani Nikula 40df0566a6SJani Nikula /* Limits for overlay size. According to intel doc, the real limits are: 41df0566a6SJani Nikula * Y width: 4095, UV width (planar): 2047, Y height: 2047, 42df0566a6SJani Nikula * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 43df0566a6SJani Nikula * the mininum of both. */ 44df0566a6SJani Nikula #define IMAGE_MAX_WIDTH 2048 45df0566a6SJani Nikula #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 46df0566a6SJani Nikula /* on 830 and 845 these large limits result in the card hanging */ 47df0566a6SJani Nikula #define IMAGE_MAX_WIDTH_LEGACY 1024 48df0566a6SJani Nikula #define IMAGE_MAX_HEIGHT_LEGACY 1088 49df0566a6SJani Nikula 50df0566a6SJani Nikula /* overlay register definitions */ 51df0566a6SJani Nikula /* OCMD register */ 52df0566a6SJani Nikula #define OCMD_TILED_SURFACE (0x1<<19) 53df0566a6SJani Nikula #define OCMD_MIRROR_MASK (0x3<<17) 54df0566a6SJani Nikula #define OCMD_MIRROR_MODE (0x3<<17) 55df0566a6SJani Nikula #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 56df0566a6SJani Nikula #define OCMD_MIRROR_VERTICAL (0x2<<17) 57df0566a6SJani Nikula #define OCMD_MIRROR_BOTH (0x3<<17) 58df0566a6SJani Nikula #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 59df0566a6SJani Nikula #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 60df0566a6SJani Nikula #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 61df0566a6SJani Nikula #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 62df0566a6SJani Nikula #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 63df0566a6SJani Nikula #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 64df0566a6SJani Nikula #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 65df0566a6SJani Nikula #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 66df0566a6SJani Nikula #define OCMD_YUV_422_PACKED (0x8<<10) 67df0566a6SJani Nikula #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 68df0566a6SJani Nikula #define OCMD_YUV_420_PLANAR (0xc<<10) 69df0566a6SJani Nikula #define OCMD_YUV_422_PLANAR (0xd<<10) 70df0566a6SJani Nikula #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 71df0566a6SJani Nikula #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 72df0566a6SJani Nikula #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 73df0566a6SJani Nikula #define OCMD_BUF_TYPE_MASK (0x1<<5) 74df0566a6SJani Nikula #define OCMD_BUF_TYPE_FRAME (0x0<<5) 75df0566a6SJani Nikula #define OCMD_BUF_TYPE_FIELD (0x1<<5) 76df0566a6SJani Nikula #define OCMD_TEST_MODE (0x1<<4) 77df0566a6SJani Nikula #define OCMD_BUFFER_SELECT (0x3<<2) 78df0566a6SJani Nikula #define OCMD_BUFFER0 (0x0<<2) 79df0566a6SJani Nikula #define OCMD_BUFFER1 (0x1<<2) 80df0566a6SJani Nikula #define OCMD_FIELD_SELECT (0x1<<2) 81df0566a6SJani Nikula #define OCMD_FIELD0 (0x0<<1) 82df0566a6SJani Nikula #define OCMD_FIELD1 (0x1<<1) 83df0566a6SJani Nikula #define OCMD_ENABLE (0x1<<0) 84df0566a6SJani Nikula 85df0566a6SJani Nikula /* OCONFIG register */ 86df0566a6SJani Nikula #define OCONF_PIPE_MASK (0x1<<18) 87df0566a6SJani Nikula #define OCONF_PIPE_A (0x0<<18) 88df0566a6SJani Nikula #define OCONF_PIPE_B (0x1<<18) 89df0566a6SJani Nikula #define OCONF_GAMMA2_ENABLE (0x1<<16) 90df0566a6SJani Nikula #define OCONF_CSC_MODE_BT601 (0x0<<5) 91df0566a6SJani Nikula #define OCONF_CSC_MODE_BT709 (0x1<<5) 92df0566a6SJani Nikula #define OCONF_CSC_BYPASS (0x1<<4) 93df0566a6SJani Nikula #define OCONF_CC_OUT_8BIT (0x1<<3) 94df0566a6SJani Nikula #define OCONF_TEST_MODE (0x1<<2) 95df0566a6SJani Nikula #define OCONF_THREE_LINE_BUFFER (0x1<<0) 96df0566a6SJani Nikula #define OCONF_TWO_LINE_BUFFER (0x0<<0) 97df0566a6SJani Nikula 98df0566a6SJani Nikula /* DCLRKM (dst-key) register */ 99df0566a6SJani Nikula #define DST_KEY_ENABLE (0x1<<31) 100df0566a6SJani Nikula #define CLK_RGB24_MASK 0x0 101df0566a6SJani Nikula #define CLK_RGB16_MASK 0x070307 102df0566a6SJani Nikula #define CLK_RGB15_MASK 0x070707 103df0566a6SJani Nikula 1040e12b4e3SVille Syrjälä #define RGB30_TO_COLORKEY(c) \ 1050e12b4e3SVille Syrjälä (((c & 0x3FC00000) >> 6) | ((c & 0x000FF000) >> 4) | ((c & 0x000003FC) >> 2)) 106df0566a6SJani Nikula #define RGB16_TO_COLORKEY(c) \ 107df0566a6SJani Nikula (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3)) 108df0566a6SJani Nikula #define RGB15_TO_COLORKEY(c) \ 109df0566a6SJani Nikula (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3)) 1100e12b4e3SVille Syrjälä #define RGB8I_TO_COLORKEY(c) \ 1110e12b4e3SVille Syrjälä (((c & 0xFF) << 16) | ((c & 0XFF) << 8) | ((c & 0xFF) << 0)) 112df0566a6SJani Nikula 113df0566a6SJani Nikula /* overlay flip addr flag */ 114df0566a6SJani Nikula #define OFC_UPDATE 0x1 115df0566a6SJani Nikula 116df0566a6SJani Nikula /* polyphase filter coefficients */ 117df0566a6SJani Nikula #define N_HORIZ_Y_TAPS 5 118df0566a6SJani Nikula #define N_VERT_Y_TAPS 3 119df0566a6SJani Nikula #define N_HORIZ_UV_TAPS 3 120df0566a6SJani Nikula #define N_VERT_UV_TAPS 3 121df0566a6SJani Nikula #define N_PHASES 17 122df0566a6SJani Nikula #define MAX_TAPS 5 123df0566a6SJani Nikula 124df0566a6SJani Nikula /* memory bufferd overlay registers */ 125df0566a6SJani Nikula struct overlay_registers { 126df0566a6SJani Nikula u32 OBUF_0Y; 127df0566a6SJani Nikula u32 OBUF_1Y; 128df0566a6SJani Nikula u32 OBUF_0U; 129df0566a6SJani Nikula u32 OBUF_0V; 130df0566a6SJani Nikula u32 OBUF_1U; 131df0566a6SJani Nikula u32 OBUF_1V; 132df0566a6SJani Nikula u32 OSTRIDE; 133df0566a6SJani Nikula u32 YRGB_VPH; 134df0566a6SJani Nikula u32 UV_VPH; 135df0566a6SJani Nikula u32 HORZ_PH; 136df0566a6SJani Nikula u32 INIT_PHS; 137df0566a6SJani Nikula u32 DWINPOS; 138df0566a6SJani Nikula u32 DWINSZ; 139df0566a6SJani Nikula u32 SWIDTH; 140df0566a6SJani Nikula u32 SWIDTHSW; 141df0566a6SJani Nikula u32 SHEIGHT; 142df0566a6SJani Nikula u32 YRGBSCALE; 143df0566a6SJani Nikula u32 UVSCALE; 144df0566a6SJani Nikula u32 OCLRC0; 145df0566a6SJani Nikula u32 OCLRC1; 146df0566a6SJani Nikula u32 DCLRKV; 147df0566a6SJani Nikula u32 DCLRKM; 148df0566a6SJani Nikula u32 SCLRKVH; 149df0566a6SJani Nikula u32 SCLRKVL; 150df0566a6SJani Nikula u32 SCLRKEN; 151df0566a6SJani Nikula u32 OCONFIG; 152df0566a6SJani Nikula u32 OCMD; 153df0566a6SJani Nikula u32 RESERVED1; /* 0x6C */ 154df0566a6SJani Nikula u32 OSTART_0Y; 155df0566a6SJani Nikula u32 OSTART_1Y; 156df0566a6SJani Nikula u32 OSTART_0U; 157df0566a6SJani Nikula u32 OSTART_0V; 158df0566a6SJani Nikula u32 OSTART_1U; 159df0566a6SJani Nikula u32 OSTART_1V; 160df0566a6SJani Nikula u32 OTILEOFF_0Y; 161df0566a6SJani Nikula u32 OTILEOFF_1Y; 162df0566a6SJani Nikula u32 OTILEOFF_0U; 163df0566a6SJani Nikula u32 OTILEOFF_0V; 164df0566a6SJani Nikula u32 OTILEOFF_1U; 165df0566a6SJani Nikula u32 OTILEOFF_1V; 166df0566a6SJani Nikula u32 FASTHSCALE; /* 0xA0 */ 167df0566a6SJani Nikula u32 UVSCALEV; /* 0xA4 */ 168df0566a6SJani Nikula u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 169df0566a6SJani Nikula u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 170df0566a6SJani Nikula u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 171df0566a6SJani Nikula u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 172df0566a6SJani Nikula u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 173df0566a6SJani Nikula u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 174df0566a6SJani Nikula u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 175df0566a6SJani Nikula u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 176df0566a6SJani Nikula u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 177df0566a6SJani Nikula }; 178df0566a6SJani Nikula 179df0566a6SJani Nikula struct intel_overlay { 180df0566a6SJani Nikula struct drm_i915_private *i915; 181ec22f256SChris Wilson struct intel_context *context; 182df0566a6SJani Nikula struct intel_crtc *crtc; 183df0566a6SJani Nikula struct i915_vma *vma; 184df0566a6SJani Nikula struct i915_vma *old_vma; 185df0566a6SJani Nikula bool active; 186df0566a6SJani Nikula bool pfit_active; 187df0566a6SJani Nikula u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 188df0566a6SJani Nikula u32 color_key:24; 189df0566a6SJani Nikula u32 color_key_enabled:1; 190df0566a6SJani Nikula u32 brightness, contrast, saturation; 191df0566a6SJani Nikula u32 old_xscale, old_yscale; 192df0566a6SJani Nikula /* register access */ 193df0566a6SJani Nikula struct drm_i915_gem_object *reg_bo; 194df0566a6SJani Nikula struct overlay_registers __iomem *regs; 195df0566a6SJani Nikula u32 flip_addr; 196df0566a6SJani Nikula /* flip handling */ 197a21ce8adSChris Wilson struct i915_active last_flip; 198a21ce8adSChris Wilson void (*flip_complete)(struct intel_overlay *ovl); 199df0566a6SJani Nikula }; 200df0566a6SJani Nikula 201df0566a6SJani Nikula static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, 202df0566a6SJani Nikula bool enable) 203df0566a6SJani Nikula { 204df0566a6SJani Nikula struct pci_dev *pdev = dev_priv->drm.pdev; 205df0566a6SJani Nikula u8 val; 206df0566a6SJani Nikula 207df0566a6SJani Nikula /* WA_OVERLAY_CLKGATE:alm */ 208df0566a6SJani Nikula if (enable) 20982e1b12eSJani Nikula intel_de_write(dev_priv, DSPCLK_GATE_D, 0); 210df0566a6SJani Nikula else 21182e1b12eSJani Nikula intel_de_write(dev_priv, DSPCLK_GATE_D, 21282e1b12eSJani Nikula OVRUNIT_CLOCK_GATE_DISABLE); 213df0566a6SJani Nikula 214df0566a6SJani Nikula /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 215df0566a6SJani Nikula pci_bus_read_config_byte(pdev->bus, 216df0566a6SJani Nikula PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); 217df0566a6SJani Nikula if (enable) 218df0566a6SJani Nikula val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; 219df0566a6SJani Nikula else 220df0566a6SJani Nikula val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 221df0566a6SJani Nikula pci_bus_write_config_byte(pdev->bus, 222df0566a6SJani Nikula PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 223df0566a6SJani Nikula } 224df0566a6SJani Nikula 225a21ce8adSChris Wilson static struct i915_request * 226a21ce8adSChris Wilson alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *)) 227df0566a6SJani Nikula { 228a21ce8adSChris Wilson struct i915_request *rq; 229a21ce8adSChris Wilson int err; 230a21ce8adSChris Wilson 231a21ce8adSChris Wilson overlay->flip_complete = fn; 232a21ce8adSChris Wilson 233a21ce8adSChris Wilson rq = i915_request_create(overlay->context); 234a21ce8adSChris Wilson if (IS_ERR(rq)) 235a21ce8adSChris Wilson return rq; 236a21ce8adSChris Wilson 237d19d71fcSChris Wilson err = i915_active_add_request(&overlay->last_flip, rq); 238a21ce8adSChris Wilson if (err) { 239df0566a6SJani Nikula i915_request_add(rq); 240a21ce8adSChris Wilson return ERR_PTR(err); 241df0566a6SJani Nikula } 242df0566a6SJani Nikula 243a21ce8adSChris Wilson return rq; 244df0566a6SJani Nikula } 245df0566a6SJani Nikula 246df0566a6SJani Nikula /* overlay needs to be disable in OCMD reg */ 247df0566a6SJani Nikula static int intel_overlay_on(struct intel_overlay *overlay) 248df0566a6SJani Nikula { 249df0566a6SJani Nikula struct drm_i915_private *dev_priv = overlay->i915; 250df0566a6SJani Nikula struct i915_request *rq; 251df0566a6SJani Nikula u32 *cs; 252df0566a6SJani Nikula 253b0b2ed0cSPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, overlay->active); 254df0566a6SJani Nikula 255a21ce8adSChris Wilson rq = alloc_request(overlay, NULL); 256df0566a6SJani Nikula if (IS_ERR(rq)) 257df0566a6SJani Nikula return PTR_ERR(rq); 258df0566a6SJani Nikula 259df0566a6SJani Nikula cs = intel_ring_begin(rq, 4); 260df0566a6SJani Nikula if (IS_ERR(cs)) { 261df0566a6SJani Nikula i915_request_add(rq); 262df0566a6SJani Nikula return PTR_ERR(cs); 263df0566a6SJani Nikula } 264df0566a6SJani Nikula 265df0566a6SJani Nikula overlay->active = true; 266df0566a6SJani Nikula 267df0566a6SJani Nikula if (IS_I830(dev_priv)) 268df0566a6SJani Nikula i830_overlay_clock_gating(dev_priv, false); 269df0566a6SJani Nikula 270df0566a6SJani Nikula *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 271df0566a6SJani Nikula *cs++ = overlay->flip_addr | OFC_UPDATE; 272df0566a6SJani Nikula *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 273df0566a6SJani Nikula *cs++ = MI_NOOP; 274df0566a6SJani Nikula intel_ring_advance(rq, cs); 275df0566a6SJani Nikula 276a21ce8adSChris Wilson i915_request_add(rq); 277a21ce8adSChris Wilson 278a21ce8adSChris Wilson return i915_active_wait(&overlay->last_flip); 279df0566a6SJani Nikula } 280df0566a6SJani Nikula 281df0566a6SJani Nikula static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 282df0566a6SJani Nikula struct i915_vma *vma) 283df0566a6SJani Nikula { 284df0566a6SJani Nikula enum pipe pipe = overlay->crtc->pipe; 285e1f0fbdaSColin Ian King struct intel_frontbuffer *from = NULL, *to = NULL; 286df0566a6SJani Nikula 287e278f076SPankaj Bharadiya drm_WARN_ON(&overlay->i915->drm, overlay->old_vma); 288df0566a6SJani Nikula 289da42104fSChris Wilson if (overlay->vma) 290da42104fSChris Wilson from = intel_frontbuffer_get(overlay->vma->obj); 291da42104fSChris Wilson if (vma) 292da42104fSChris Wilson to = intel_frontbuffer_get(vma->obj); 293da42104fSChris Wilson 294da42104fSChris Wilson intel_frontbuffer_track(from, to, INTEL_FRONTBUFFER_OVERLAY(pipe)); 295da42104fSChris Wilson 296da42104fSChris Wilson if (to) 297da42104fSChris Wilson intel_frontbuffer_put(to); 298da42104fSChris Wilson if (from) 299da42104fSChris Wilson intel_frontbuffer_put(from); 300df0566a6SJani Nikula 301df0566a6SJani Nikula intel_frontbuffer_flip_prepare(overlay->i915, 302df0566a6SJani Nikula INTEL_FRONTBUFFER_OVERLAY(pipe)); 303df0566a6SJani Nikula 304df0566a6SJani Nikula overlay->old_vma = overlay->vma; 305df0566a6SJani Nikula if (vma) 306df0566a6SJani Nikula overlay->vma = i915_vma_get(vma); 307df0566a6SJani Nikula else 308df0566a6SJani Nikula overlay->vma = NULL; 309df0566a6SJani Nikula } 310df0566a6SJani Nikula 311df0566a6SJani Nikula /* overlay needs to be enabled in OCMD reg */ 312df0566a6SJani Nikula static int intel_overlay_continue(struct intel_overlay *overlay, 313df0566a6SJani Nikula struct i915_vma *vma, 314df0566a6SJani Nikula bool load_polyphase_filter) 315df0566a6SJani Nikula { 316df0566a6SJani Nikula struct drm_i915_private *dev_priv = overlay->i915; 317df0566a6SJani Nikula struct i915_request *rq; 318df0566a6SJani Nikula u32 flip_addr = overlay->flip_addr; 319df0566a6SJani Nikula u32 tmp, *cs; 320df0566a6SJani Nikula 321b0b2ed0cSPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, !overlay->active); 322df0566a6SJani Nikula 323df0566a6SJani Nikula if (load_polyphase_filter) 324df0566a6SJani Nikula flip_addr |= OFC_UPDATE; 325df0566a6SJani Nikula 326df0566a6SJani Nikula /* check for underruns */ 32782e1b12eSJani Nikula tmp = intel_de_read(dev_priv, DOVSTA); 328df0566a6SJani Nikula if (tmp & (1 << 17)) 3293c4e93e9SWambui Karuga drm_dbg(&dev_priv->drm, "overlay underrun, DOVSTA: %x\n", tmp); 330df0566a6SJani Nikula 331a21ce8adSChris Wilson rq = alloc_request(overlay, NULL); 332df0566a6SJani Nikula if (IS_ERR(rq)) 333df0566a6SJani Nikula return PTR_ERR(rq); 334df0566a6SJani Nikula 335df0566a6SJani Nikula cs = intel_ring_begin(rq, 2); 336df0566a6SJani Nikula if (IS_ERR(cs)) { 337df0566a6SJani Nikula i915_request_add(rq); 338df0566a6SJani Nikula return PTR_ERR(cs); 339df0566a6SJani Nikula } 340df0566a6SJani Nikula 341df0566a6SJani Nikula *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 342df0566a6SJani Nikula *cs++ = flip_addr; 343df0566a6SJani Nikula intel_ring_advance(rq, cs); 344df0566a6SJani Nikula 345df0566a6SJani Nikula intel_overlay_flip_prepare(overlay, vma); 346a21ce8adSChris Wilson i915_request_add(rq); 347df0566a6SJani Nikula 348df0566a6SJani Nikula return 0; 349df0566a6SJani Nikula } 350df0566a6SJani Nikula 351df0566a6SJani Nikula static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 352df0566a6SJani Nikula { 353df0566a6SJani Nikula struct i915_vma *vma; 354df0566a6SJani Nikula 355df0566a6SJani Nikula vma = fetch_and_zero(&overlay->old_vma); 356e278f076SPankaj Bharadiya if (drm_WARN_ON(&overlay->i915->drm, !vma)) 357df0566a6SJani Nikula return; 358df0566a6SJani Nikula 359df0566a6SJani Nikula intel_frontbuffer_flip_complete(overlay->i915, 360df0566a6SJani Nikula INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 361df0566a6SJani Nikula 362df0566a6SJani Nikula i915_gem_object_unpin_from_display_plane(vma); 363df0566a6SJani Nikula i915_vma_put(vma); 364df0566a6SJani Nikula } 365df0566a6SJani Nikula 366df0566a6SJani Nikula static void 367a21ce8adSChris Wilson intel_overlay_release_old_vid_tail(struct intel_overlay *overlay) 368df0566a6SJani Nikula { 369df0566a6SJani Nikula intel_overlay_release_old_vma(overlay); 370df0566a6SJani Nikula } 371df0566a6SJani Nikula 372a21ce8adSChris Wilson static void intel_overlay_off_tail(struct intel_overlay *overlay) 373df0566a6SJani Nikula { 374df0566a6SJani Nikula struct drm_i915_private *dev_priv = overlay->i915; 375df0566a6SJani Nikula 376df0566a6SJani Nikula intel_overlay_release_old_vma(overlay); 377df0566a6SJani Nikula 378df0566a6SJani Nikula overlay->crtc->overlay = NULL; 379df0566a6SJani Nikula overlay->crtc = NULL; 380df0566a6SJani Nikula overlay->active = false; 381df0566a6SJani Nikula 382df0566a6SJani Nikula if (IS_I830(dev_priv)) 383df0566a6SJani Nikula i830_overlay_clock_gating(dev_priv, true); 384df0566a6SJani Nikula } 385df0566a6SJani Nikula 386a21ce8adSChris Wilson static void 387a21ce8adSChris Wilson intel_overlay_last_flip_retire(struct i915_active *active) 388a21ce8adSChris Wilson { 389a21ce8adSChris Wilson struct intel_overlay *overlay = 390a21ce8adSChris Wilson container_of(active, typeof(*overlay), last_flip); 391a21ce8adSChris Wilson 392a21ce8adSChris Wilson if (overlay->flip_complete) 393a21ce8adSChris Wilson overlay->flip_complete(overlay); 394a21ce8adSChris Wilson } 395a21ce8adSChris Wilson 396df0566a6SJani Nikula /* overlay needs to be disabled in OCMD reg */ 397df0566a6SJani Nikula static int intel_overlay_off(struct intel_overlay *overlay) 398df0566a6SJani Nikula { 399df0566a6SJani Nikula struct i915_request *rq; 400df0566a6SJani Nikula u32 *cs, flip_addr = overlay->flip_addr; 401df0566a6SJani Nikula 402e278f076SPankaj Bharadiya drm_WARN_ON(&overlay->i915->drm, !overlay->active); 403df0566a6SJani Nikula 404df0566a6SJani Nikula /* According to intel docs the overlay hw may hang (when switching 405df0566a6SJani Nikula * off) without loading the filter coeffs. It is however unclear whether 406df0566a6SJani Nikula * this applies to the disabling of the overlay or to the switching off 407df0566a6SJani Nikula * of the hw. Do it in both cases */ 408df0566a6SJani Nikula flip_addr |= OFC_UPDATE; 409df0566a6SJani Nikula 410a21ce8adSChris Wilson rq = alloc_request(overlay, intel_overlay_off_tail); 411df0566a6SJani Nikula if (IS_ERR(rq)) 412df0566a6SJani Nikula return PTR_ERR(rq); 413df0566a6SJani Nikula 414df0566a6SJani Nikula cs = intel_ring_begin(rq, 6); 415df0566a6SJani Nikula if (IS_ERR(cs)) { 416df0566a6SJani Nikula i915_request_add(rq); 417df0566a6SJani Nikula return PTR_ERR(cs); 418df0566a6SJani Nikula } 419df0566a6SJani Nikula 420df0566a6SJani Nikula /* wait for overlay to go idle */ 421df0566a6SJani Nikula *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 422df0566a6SJani Nikula *cs++ = flip_addr; 423df0566a6SJani Nikula *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 424df0566a6SJani Nikula 425df0566a6SJani Nikula /* turn overlay off */ 426df0566a6SJani Nikula *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; 427df0566a6SJani Nikula *cs++ = flip_addr; 428df0566a6SJani Nikula *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 429df0566a6SJani Nikula 430df0566a6SJani Nikula intel_ring_advance(rq, cs); 431df0566a6SJani Nikula 432df0566a6SJani Nikula intel_overlay_flip_prepare(overlay, NULL); 433a21ce8adSChris Wilson i915_request_add(rq); 434df0566a6SJani Nikula 435a21ce8adSChris Wilson return i915_active_wait(&overlay->last_flip); 436df0566a6SJani Nikula } 437df0566a6SJani Nikula 438df0566a6SJani Nikula /* recover from an interruption due to a signal 439df0566a6SJani Nikula * We have to be careful not to repeat work forever an make forward progess. */ 440df0566a6SJani Nikula static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) 441df0566a6SJani Nikula { 442a21ce8adSChris Wilson return i915_active_wait(&overlay->last_flip); 443df0566a6SJani Nikula } 444df0566a6SJani Nikula 445df0566a6SJani Nikula /* Wait for pending overlay flip and release old frame. 446df0566a6SJani Nikula * Needs to be called before the overlay register are changed 447df0566a6SJani Nikula * via intel_overlay_(un)map_regs 448df0566a6SJani Nikula */ 449df0566a6SJani Nikula static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 450df0566a6SJani Nikula { 451df0566a6SJani Nikula struct drm_i915_private *dev_priv = overlay->i915; 452a21ce8adSChris Wilson struct i915_request *rq; 453df0566a6SJani Nikula u32 *cs; 454df0566a6SJani Nikula 455a21ce8adSChris Wilson /* 456a21ce8adSChris Wilson * Only wait if there is actually an old frame to release to 457df0566a6SJani Nikula * guarantee forward progress. 458df0566a6SJani Nikula */ 459df0566a6SJani Nikula if (!overlay->old_vma) 460df0566a6SJani Nikula return 0; 461df0566a6SJani Nikula 46282e1b12eSJani Nikula if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { 463a21ce8adSChris Wilson intel_overlay_release_old_vid_tail(overlay); 464a21ce8adSChris Wilson return 0; 465a21ce8adSChris Wilson } 466df0566a6SJani Nikula 467a21ce8adSChris Wilson rq = alloc_request(overlay, intel_overlay_release_old_vid_tail); 468df0566a6SJani Nikula if (IS_ERR(rq)) 469df0566a6SJani Nikula return PTR_ERR(rq); 470df0566a6SJani Nikula 471df0566a6SJani Nikula cs = intel_ring_begin(rq, 2); 472df0566a6SJani Nikula if (IS_ERR(cs)) { 473df0566a6SJani Nikula i915_request_add(rq); 474df0566a6SJani Nikula return PTR_ERR(cs); 475df0566a6SJani Nikula } 476df0566a6SJani Nikula 477df0566a6SJani Nikula *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 478df0566a6SJani Nikula *cs++ = MI_NOOP; 479df0566a6SJani Nikula intel_ring_advance(rq, cs); 480df0566a6SJani Nikula 481a21ce8adSChris Wilson i915_request_add(rq); 482df0566a6SJani Nikula 483a21ce8adSChris Wilson return i915_active_wait(&overlay->last_flip); 484df0566a6SJani Nikula } 485df0566a6SJani Nikula 486df0566a6SJani Nikula void intel_overlay_reset(struct drm_i915_private *dev_priv) 487df0566a6SJani Nikula { 488df0566a6SJani Nikula struct intel_overlay *overlay = dev_priv->overlay; 489df0566a6SJani Nikula 490df0566a6SJani Nikula if (!overlay) 491df0566a6SJani Nikula return; 492df0566a6SJani Nikula 493df0566a6SJani Nikula overlay->old_xscale = 0; 494df0566a6SJani Nikula overlay->old_yscale = 0; 495df0566a6SJani Nikula overlay->crtc = NULL; 496df0566a6SJani Nikula overlay->active = false; 497df0566a6SJani Nikula } 498df0566a6SJani Nikula 499df0566a6SJani Nikula static int packed_depth_bytes(u32 format) 500df0566a6SJani Nikula { 501df0566a6SJani Nikula switch (format & I915_OVERLAY_DEPTH_MASK) { 502df0566a6SJani Nikula case I915_OVERLAY_YUV422: 503df0566a6SJani Nikula return 4; 504df0566a6SJani Nikula case I915_OVERLAY_YUV411: 505df0566a6SJani Nikula /* return 6; not implemented */ 506df0566a6SJani Nikula default: 507df0566a6SJani Nikula return -EINVAL; 508df0566a6SJani Nikula } 509df0566a6SJani Nikula } 510df0566a6SJani Nikula 511df0566a6SJani Nikula static int packed_width_bytes(u32 format, short width) 512df0566a6SJani Nikula { 513df0566a6SJani Nikula switch (format & I915_OVERLAY_DEPTH_MASK) { 514df0566a6SJani Nikula case I915_OVERLAY_YUV422: 515df0566a6SJani Nikula return width << 1; 516df0566a6SJani Nikula default: 517df0566a6SJani Nikula return -EINVAL; 518df0566a6SJani Nikula } 519df0566a6SJani Nikula } 520df0566a6SJani Nikula 521df0566a6SJani Nikula static int uv_hsubsampling(u32 format) 522df0566a6SJani Nikula { 523df0566a6SJani Nikula switch (format & I915_OVERLAY_DEPTH_MASK) { 524df0566a6SJani Nikula case I915_OVERLAY_YUV422: 525df0566a6SJani Nikula case I915_OVERLAY_YUV420: 526df0566a6SJani Nikula return 2; 527df0566a6SJani Nikula case I915_OVERLAY_YUV411: 528df0566a6SJani Nikula case I915_OVERLAY_YUV410: 529df0566a6SJani Nikula return 4; 530df0566a6SJani Nikula default: 531df0566a6SJani Nikula return -EINVAL; 532df0566a6SJani Nikula } 533df0566a6SJani Nikula } 534df0566a6SJani Nikula 535df0566a6SJani Nikula static int uv_vsubsampling(u32 format) 536df0566a6SJani Nikula { 537df0566a6SJani Nikula switch (format & I915_OVERLAY_DEPTH_MASK) { 538df0566a6SJani Nikula case I915_OVERLAY_YUV420: 539df0566a6SJani Nikula case I915_OVERLAY_YUV410: 540df0566a6SJani Nikula return 2; 541df0566a6SJani Nikula case I915_OVERLAY_YUV422: 542df0566a6SJani Nikula case I915_OVERLAY_YUV411: 543df0566a6SJani Nikula return 1; 544df0566a6SJani Nikula default: 545df0566a6SJani Nikula return -EINVAL; 546df0566a6SJani Nikula } 547df0566a6SJani Nikula } 548df0566a6SJani Nikula 549df0566a6SJani Nikula static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) 550df0566a6SJani Nikula { 551df0566a6SJani Nikula u32 sw; 552df0566a6SJani Nikula 553df0566a6SJani Nikula if (IS_GEN(dev_priv, 2)) 554df0566a6SJani Nikula sw = ALIGN((offset & 31) + width, 32); 555df0566a6SJani Nikula else 556df0566a6SJani Nikula sw = ALIGN((offset & 63) + width, 64); 557df0566a6SJani Nikula 558df0566a6SJani Nikula if (sw == 0) 559df0566a6SJani Nikula return 0; 560df0566a6SJani Nikula 561df0566a6SJani Nikula return (sw - 32) >> 3; 562df0566a6SJani Nikula } 563df0566a6SJani Nikula 564df0566a6SJani Nikula static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 565df0566a6SJani Nikula [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 566df0566a6SJani Nikula [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 567df0566a6SJani Nikula [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 568df0566a6SJani Nikula [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 569df0566a6SJani Nikula [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 570df0566a6SJani Nikula [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 571df0566a6SJani Nikula [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 572df0566a6SJani Nikula [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 573df0566a6SJani Nikula [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 574df0566a6SJani Nikula [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 575df0566a6SJani Nikula [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 576df0566a6SJani Nikula [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 577df0566a6SJani Nikula [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 578df0566a6SJani Nikula [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 579df0566a6SJani Nikula [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 580df0566a6SJani Nikula [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 581df0566a6SJani Nikula [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 582df0566a6SJani Nikula }; 583df0566a6SJani Nikula 584df0566a6SJani Nikula static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 585df0566a6SJani Nikula [ 0] = { 0x3000, 0x1800, 0x1800, }, 586df0566a6SJani Nikula [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 587df0566a6SJani Nikula [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 588df0566a6SJani Nikula [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 589df0566a6SJani Nikula [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 590df0566a6SJani Nikula [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 591df0566a6SJani Nikula [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 592df0566a6SJani Nikula [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 593df0566a6SJani Nikula [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 594df0566a6SJani Nikula [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 595df0566a6SJani Nikula [10] = { 0xb100, 0x1eb8, 0x3620, }, 596df0566a6SJani Nikula [11] = { 0xb100, 0x1f18, 0x34a0, }, 597df0566a6SJani Nikula [12] = { 0xb100, 0x1f68, 0x3360, }, 598df0566a6SJani Nikula [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 599df0566a6SJani Nikula [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 600df0566a6SJani Nikula [15] = { 0xb060, 0x1ff0, 0x30a0, }, 601df0566a6SJani Nikula [16] = { 0x3000, 0x0800, 0x3000, }, 602df0566a6SJani Nikula }; 603df0566a6SJani Nikula 604df0566a6SJani Nikula static void update_polyphase_filter(struct overlay_registers __iomem *regs) 605df0566a6SJani Nikula { 606df0566a6SJani Nikula memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 607df0566a6SJani Nikula memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 608df0566a6SJani Nikula sizeof(uv_static_hcoeffs)); 609df0566a6SJani Nikula } 610df0566a6SJani Nikula 611df0566a6SJani Nikula static bool update_scaling_factors(struct intel_overlay *overlay, 612df0566a6SJani Nikula struct overlay_registers __iomem *regs, 613df0566a6SJani Nikula struct drm_intel_overlay_put_image *params) 614df0566a6SJani Nikula { 615df0566a6SJani Nikula /* fixed point with a 12 bit shift */ 616df0566a6SJani Nikula u32 xscale, yscale, xscale_UV, yscale_UV; 617df0566a6SJani Nikula #define FP_SHIFT 12 618df0566a6SJani Nikula #define FRACT_MASK 0xfff 619df0566a6SJani Nikula bool scale_changed = false; 620df0566a6SJani Nikula int uv_hscale = uv_hsubsampling(params->flags); 621df0566a6SJani Nikula int uv_vscale = uv_vsubsampling(params->flags); 622df0566a6SJani Nikula 623df0566a6SJani Nikula if (params->dst_width > 1) 624df0566a6SJani Nikula xscale = ((params->src_scan_width - 1) << FP_SHIFT) / 625df0566a6SJani Nikula params->dst_width; 626df0566a6SJani Nikula else 627df0566a6SJani Nikula xscale = 1 << FP_SHIFT; 628df0566a6SJani Nikula 629df0566a6SJani Nikula if (params->dst_height > 1) 630df0566a6SJani Nikula yscale = ((params->src_scan_height - 1) << FP_SHIFT) / 631df0566a6SJani Nikula params->dst_height; 632df0566a6SJani Nikula else 633df0566a6SJani Nikula yscale = 1 << FP_SHIFT; 634df0566a6SJani Nikula 635df0566a6SJani Nikula /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 636df0566a6SJani Nikula xscale_UV = xscale/uv_hscale; 637df0566a6SJani Nikula yscale_UV = yscale/uv_vscale; 638df0566a6SJani Nikula /* make the Y scale to UV scale ratio an exact multiply */ 639df0566a6SJani Nikula xscale = xscale_UV * uv_hscale; 640df0566a6SJani Nikula yscale = yscale_UV * uv_vscale; 641df0566a6SJani Nikula /*} else { 642df0566a6SJani Nikula xscale_UV = 0; 643df0566a6SJani Nikula yscale_UV = 0; 644df0566a6SJani Nikula }*/ 645df0566a6SJani Nikula 646df0566a6SJani Nikula if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 647df0566a6SJani Nikula scale_changed = true; 648df0566a6SJani Nikula overlay->old_xscale = xscale; 649df0566a6SJani Nikula overlay->old_yscale = yscale; 650df0566a6SJani Nikula 651df0566a6SJani Nikula iowrite32(((yscale & FRACT_MASK) << 20) | 652df0566a6SJani Nikula ((xscale >> FP_SHIFT) << 16) | 653df0566a6SJani Nikula ((xscale & FRACT_MASK) << 3), 654df0566a6SJani Nikula ®s->YRGBSCALE); 655df0566a6SJani Nikula 656df0566a6SJani Nikula iowrite32(((yscale_UV & FRACT_MASK) << 20) | 657df0566a6SJani Nikula ((xscale_UV >> FP_SHIFT) << 16) | 658df0566a6SJani Nikula ((xscale_UV & FRACT_MASK) << 3), 659df0566a6SJani Nikula ®s->UVSCALE); 660df0566a6SJani Nikula 661df0566a6SJani Nikula iowrite32((((yscale >> FP_SHIFT) << 16) | 662df0566a6SJani Nikula ((yscale_UV >> FP_SHIFT) << 0)), 663df0566a6SJani Nikula ®s->UVSCALEV); 664df0566a6SJani Nikula 665df0566a6SJani Nikula if (scale_changed) 666df0566a6SJani Nikula update_polyphase_filter(regs); 667df0566a6SJani Nikula 668df0566a6SJani Nikula return scale_changed; 669df0566a6SJani Nikula } 670df0566a6SJani Nikula 671df0566a6SJani Nikula static void update_colorkey(struct intel_overlay *overlay, 672df0566a6SJani Nikula struct overlay_registers __iomem *regs) 673df0566a6SJani Nikula { 674df0566a6SJani Nikula const struct intel_plane_state *state = 675df0566a6SJani Nikula to_intel_plane_state(overlay->crtc->base.primary->state); 676df0566a6SJani Nikula u32 key = overlay->color_key; 677df0566a6SJani Nikula u32 format = 0; 678df0566a6SJani Nikula u32 flags = 0; 679df0566a6SJani Nikula 680df0566a6SJani Nikula if (overlay->color_key_enabled) 681df0566a6SJani Nikula flags |= DST_KEY_ENABLE; 682df0566a6SJani Nikula 683f90a85e7SMaarten Lankhorst if (state->uapi.visible) 6847b3cb17aSMaarten Lankhorst format = state->hw.fb->format->format; 685df0566a6SJani Nikula 686df0566a6SJani Nikula switch (format) { 687df0566a6SJani Nikula case DRM_FORMAT_C8: 6880e12b4e3SVille Syrjälä key = RGB8I_TO_COLORKEY(key); 6890e12b4e3SVille Syrjälä flags |= CLK_RGB24_MASK; 690df0566a6SJani Nikula break; 691df0566a6SJani Nikula case DRM_FORMAT_XRGB1555: 692df0566a6SJani Nikula key = RGB15_TO_COLORKEY(key); 693df0566a6SJani Nikula flags |= CLK_RGB15_MASK; 694df0566a6SJani Nikula break; 695df0566a6SJani Nikula case DRM_FORMAT_RGB565: 696df0566a6SJani Nikula key = RGB16_TO_COLORKEY(key); 697df0566a6SJani Nikula flags |= CLK_RGB16_MASK; 698df0566a6SJani Nikula break; 6990e12b4e3SVille Syrjälä case DRM_FORMAT_XRGB2101010: 7000e12b4e3SVille Syrjälä case DRM_FORMAT_XBGR2101010: 7010e12b4e3SVille Syrjälä key = RGB30_TO_COLORKEY(key); 7020e12b4e3SVille Syrjälä flags |= CLK_RGB24_MASK; 7030e12b4e3SVille Syrjälä break; 704df0566a6SJani Nikula default: 705df0566a6SJani Nikula flags |= CLK_RGB24_MASK; 706df0566a6SJani Nikula break; 707df0566a6SJani Nikula } 708df0566a6SJani Nikula 709df0566a6SJani Nikula iowrite32(key, ®s->DCLRKV); 710df0566a6SJani Nikula iowrite32(flags, ®s->DCLRKM); 711df0566a6SJani Nikula } 712df0566a6SJani Nikula 713df0566a6SJani Nikula static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) 714df0566a6SJani Nikula { 715df0566a6SJani Nikula u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 716df0566a6SJani Nikula 717df0566a6SJani Nikula if (params->flags & I915_OVERLAY_YUV_PLANAR) { 718df0566a6SJani Nikula switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 719df0566a6SJani Nikula case I915_OVERLAY_YUV422: 720df0566a6SJani Nikula cmd |= OCMD_YUV_422_PLANAR; 721df0566a6SJani Nikula break; 722df0566a6SJani Nikula case I915_OVERLAY_YUV420: 723df0566a6SJani Nikula cmd |= OCMD_YUV_420_PLANAR; 724df0566a6SJani Nikula break; 725df0566a6SJani Nikula case I915_OVERLAY_YUV411: 726df0566a6SJani Nikula case I915_OVERLAY_YUV410: 727df0566a6SJani Nikula cmd |= OCMD_YUV_410_PLANAR; 728df0566a6SJani Nikula break; 729df0566a6SJani Nikula } 730df0566a6SJani Nikula } else { /* YUV packed */ 731df0566a6SJani Nikula switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 732df0566a6SJani Nikula case I915_OVERLAY_YUV422: 733df0566a6SJani Nikula cmd |= OCMD_YUV_422_PACKED; 734df0566a6SJani Nikula break; 735df0566a6SJani Nikula case I915_OVERLAY_YUV411: 736df0566a6SJani Nikula cmd |= OCMD_YUV_411_PACKED; 737df0566a6SJani Nikula break; 738df0566a6SJani Nikula } 739df0566a6SJani Nikula 740df0566a6SJani Nikula switch (params->flags & I915_OVERLAY_SWAP_MASK) { 741df0566a6SJani Nikula case I915_OVERLAY_NO_SWAP: 742df0566a6SJani Nikula break; 743df0566a6SJani Nikula case I915_OVERLAY_UV_SWAP: 744df0566a6SJani Nikula cmd |= OCMD_UV_SWAP; 745df0566a6SJani Nikula break; 746df0566a6SJani Nikula case I915_OVERLAY_Y_SWAP: 747df0566a6SJani Nikula cmd |= OCMD_Y_SWAP; 748df0566a6SJani Nikula break; 749df0566a6SJani Nikula case I915_OVERLAY_Y_AND_UV_SWAP: 750df0566a6SJani Nikula cmd |= OCMD_Y_AND_UV_SWAP; 751df0566a6SJani Nikula break; 752df0566a6SJani Nikula } 753df0566a6SJani Nikula } 754df0566a6SJani Nikula 755df0566a6SJani Nikula return cmd; 756df0566a6SJani Nikula } 757df0566a6SJani Nikula 758df0566a6SJani Nikula static int intel_overlay_do_put_image(struct intel_overlay *overlay, 759df0566a6SJani Nikula struct drm_i915_gem_object *new_bo, 760df0566a6SJani Nikula struct drm_intel_overlay_put_image *params) 761df0566a6SJani Nikula { 762df0566a6SJani Nikula struct overlay_registers __iomem *regs = overlay->regs; 763df0566a6SJani Nikula struct drm_i915_private *dev_priv = overlay->i915; 764df0566a6SJani Nikula u32 swidth, swidthsw, sheight, ostride; 765df0566a6SJani Nikula enum pipe pipe = overlay->crtc->pipe; 766df0566a6SJani Nikula bool scale_changed = false; 767df0566a6SJani Nikula struct i915_vma *vma; 768df0566a6SJani Nikula int ret, tmp_width; 769df0566a6SJani Nikula 770b0b2ed0cSPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, 771b0b2ed0cSPankaj Bharadiya !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 772df0566a6SJani Nikula 773df0566a6SJani Nikula ret = intel_overlay_release_old_vid(overlay); 774df0566a6SJani Nikula if (ret != 0) 775df0566a6SJani Nikula return ret; 776df0566a6SJani Nikula 777df0566a6SJani Nikula atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 778df0566a6SJani Nikula 779df0566a6SJani Nikula vma = i915_gem_object_pin_to_display_plane(new_bo, 780df0566a6SJani Nikula 0, NULL, PIN_MAPPABLE); 781df0566a6SJani Nikula if (IS_ERR(vma)) { 782df0566a6SJani Nikula ret = PTR_ERR(vma); 783df0566a6SJani Nikula goto out_pin_section; 784df0566a6SJani Nikula } 785da42104fSChris Wilson i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB); 786df0566a6SJani Nikula 787df0566a6SJani Nikula if (!overlay->active) { 788df0566a6SJani Nikula u32 oconfig; 789df0566a6SJani Nikula 790df0566a6SJani Nikula oconfig = OCONF_CC_OUT_8BIT; 791df0566a6SJani Nikula if (IS_GEN(dev_priv, 4)) 792df0566a6SJani Nikula oconfig |= OCONF_CSC_MODE_BT709; 793df0566a6SJani Nikula oconfig |= pipe == 0 ? 794df0566a6SJani Nikula OCONF_PIPE_A : OCONF_PIPE_B; 795df0566a6SJani Nikula iowrite32(oconfig, ®s->OCONFIG); 796df0566a6SJani Nikula 797df0566a6SJani Nikula ret = intel_overlay_on(overlay); 798df0566a6SJani Nikula if (ret != 0) 799df0566a6SJani Nikula goto out_unpin; 800df0566a6SJani Nikula } 801df0566a6SJani Nikula 802df0566a6SJani Nikula iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS); 803df0566a6SJani Nikula iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ); 804df0566a6SJani Nikula 805df0566a6SJani Nikula if (params->flags & I915_OVERLAY_YUV_PACKED) 806df0566a6SJani Nikula tmp_width = packed_width_bytes(params->flags, 807df0566a6SJani Nikula params->src_width); 808df0566a6SJani Nikula else 809df0566a6SJani Nikula tmp_width = params->src_width; 810df0566a6SJani Nikula 811df0566a6SJani Nikula swidth = params->src_width; 812df0566a6SJani Nikula swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width); 813df0566a6SJani Nikula sheight = params->src_height; 814df0566a6SJani Nikula iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); 815df0566a6SJani Nikula ostride = params->stride_Y; 816df0566a6SJani Nikula 817df0566a6SJani Nikula if (params->flags & I915_OVERLAY_YUV_PLANAR) { 818df0566a6SJani Nikula int uv_hscale = uv_hsubsampling(params->flags); 819df0566a6SJani Nikula int uv_vscale = uv_vsubsampling(params->flags); 820df0566a6SJani Nikula u32 tmp_U, tmp_V; 821df0566a6SJani Nikula 822df0566a6SJani Nikula swidth |= (params->src_width / uv_hscale) << 16; 823df0566a6SJani Nikula sheight |= (params->src_height / uv_vscale) << 16; 824df0566a6SJani Nikula 825df0566a6SJani Nikula tmp_U = calc_swidthsw(dev_priv, params->offset_U, 826df0566a6SJani Nikula params->src_width / uv_hscale); 827df0566a6SJani Nikula tmp_V = calc_swidthsw(dev_priv, params->offset_V, 828df0566a6SJani Nikula params->src_width / uv_hscale); 829df0566a6SJani Nikula swidthsw |= max(tmp_U, tmp_V) << 16; 830df0566a6SJani Nikula 831df0566a6SJani Nikula iowrite32(i915_ggtt_offset(vma) + params->offset_U, 832df0566a6SJani Nikula ®s->OBUF_0U); 833df0566a6SJani Nikula iowrite32(i915_ggtt_offset(vma) + params->offset_V, 834df0566a6SJani Nikula ®s->OBUF_0V); 835df0566a6SJani Nikula 836df0566a6SJani Nikula ostride |= params->stride_UV << 16; 837df0566a6SJani Nikula } 838df0566a6SJani Nikula 839df0566a6SJani Nikula iowrite32(swidth, ®s->SWIDTH); 840df0566a6SJani Nikula iowrite32(swidthsw, ®s->SWIDTHSW); 841df0566a6SJani Nikula iowrite32(sheight, ®s->SHEIGHT); 842df0566a6SJani Nikula iowrite32(ostride, ®s->OSTRIDE); 843df0566a6SJani Nikula 844df0566a6SJani Nikula scale_changed = update_scaling_factors(overlay, regs, params); 845df0566a6SJani Nikula 846df0566a6SJani Nikula update_colorkey(overlay, regs); 847df0566a6SJani Nikula 848df0566a6SJani Nikula iowrite32(overlay_cmd_reg(params), ®s->OCMD); 849df0566a6SJani Nikula 850df0566a6SJani Nikula ret = intel_overlay_continue(overlay, vma, scale_changed); 851df0566a6SJani Nikula if (ret) 852df0566a6SJani Nikula goto out_unpin; 853df0566a6SJani Nikula 854df0566a6SJani Nikula return 0; 855df0566a6SJani Nikula 856df0566a6SJani Nikula out_unpin: 857df0566a6SJani Nikula i915_gem_object_unpin_from_display_plane(vma); 858df0566a6SJani Nikula out_pin_section: 859df0566a6SJani Nikula atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 860df0566a6SJani Nikula 861df0566a6SJani Nikula return ret; 862df0566a6SJani Nikula } 863df0566a6SJani Nikula 864df0566a6SJani Nikula int intel_overlay_switch_off(struct intel_overlay *overlay) 865df0566a6SJani Nikula { 866df0566a6SJani Nikula struct drm_i915_private *dev_priv = overlay->i915; 867df0566a6SJani Nikula int ret; 868df0566a6SJani Nikula 869b0b2ed0cSPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, 870b0b2ed0cSPankaj Bharadiya !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 871df0566a6SJani Nikula 872df0566a6SJani Nikula ret = intel_overlay_recover_from_interrupt(overlay); 873df0566a6SJani Nikula if (ret != 0) 874df0566a6SJani Nikula return ret; 875df0566a6SJani Nikula 876df0566a6SJani Nikula if (!overlay->active) 877df0566a6SJani Nikula return 0; 878df0566a6SJani Nikula 879df0566a6SJani Nikula ret = intel_overlay_release_old_vid(overlay); 880df0566a6SJani Nikula if (ret != 0) 881df0566a6SJani Nikula return ret; 882df0566a6SJani Nikula 883df0566a6SJani Nikula iowrite32(0, &overlay->regs->OCMD); 884df0566a6SJani Nikula 885df0566a6SJani Nikula return intel_overlay_off(overlay); 886df0566a6SJani Nikula } 887df0566a6SJani Nikula 888df0566a6SJani Nikula static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 889df0566a6SJani Nikula struct intel_crtc *crtc) 890df0566a6SJani Nikula { 891df0566a6SJani Nikula if (!crtc->active) 892df0566a6SJani Nikula return -EINVAL; 893df0566a6SJani Nikula 894df0566a6SJani Nikula /* can't use the overlay with double wide pipe */ 895df0566a6SJani Nikula if (crtc->config->double_wide) 896df0566a6SJani Nikula return -EINVAL; 897df0566a6SJani Nikula 898df0566a6SJani Nikula return 0; 899df0566a6SJani Nikula } 900df0566a6SJani Nikula 901df0566a6SJani Nikula static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 902df0566a6SJani Nikula { 903df0566a6SJani Nikula struct drm_i915_private *dev_priv = overlay->i915; 90482e1b12eSJani Nikula u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL); 905df0566a6SJani Nikula u32 ratio; 906df0566a6SJani Nikula 907df0566a6SJani Nikula /* XXX: This is not the same logic as in the xorg driver, but more in 908df0566a6SJani Nikula * line with the intel documentation for the i965 909df0566a6SJani Nikula */ 910df0566a6SJani Nikula if (INTEL_GEN(dev_priv) >= 4) { 911df0566a6SJani Nikula /* on i965 use the PGM reg to read out the autoscaler values */ 91282e1b12eSJani Nikula ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; 913df0566a6SJani Nikula } else { 914df0566a6SJani Nikula if (pfit_control & VERT_AUTO_SCALE) 91582e1b12eSJani Nikula ratio = intel_de_read(dev_priv, PFIT_AUTO_RATIOS); 916df0566a6SJani Nikula else 91782e1b12eSJani Nikula ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS); 918df0566a6SJani Nikula ratio >>= PFIT_VERT_SCALE_SHIFT; 919df0566a6SJani Nikula } 920df0566a6SJani Nikula 921df0566a6SJani Nikula overlay->pfit_vscale_ratio = ratio; 922df0566a6SJani Nikula } 923df0566a6SJani Nikula 924df0566a6SJani Nikula static int check_overlay_dst(struct intel_overlay *overlay, 925df0566a6SJani Nikula struct drm_intel_overlay_put_image *rec) 926df0566a6SJani Nikula { 927df0566a6SJani Nikula const struct intel_crtc_state *pipe_config = 928df0566a6SJani Nikula overlay->crtc->config; 929df0566a6SJani Nikula 930df0566a6SJani Nikula if (rec->dst_x < pipe_config->pipe_src_w && 931df0566a6SJani Nikula rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && 932df0566a6SJani Nikula rec->dst_y < pipe_config->pipe_src_h && 933df0566a6SJani Nikula rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) 934df0566a6SJani Nikula return 0; 935df0566a6SJani Nikula else 936df0566a6SJani Nikula return -EINVAL; 937df0566a6SJani Nikula } 938df0566a6SJani Nikula 939df0566a6SJani Nikula static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) 940df0566a6SJani Nikula { 941df0566a6SJani Nikula u32 tmp; 942df0566a6SJani Nikula 943df0566a6SJani Nikula /* downscaling limit is 8.0 */ 944df0566a6SJani Nikula tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16; 945df0566a6SJani Nikula if (tmp > 7) 946df0566a6SJani Nikula return -EINVAL; 947df0566a6SJani Nikula 948df0566a6SJani Nikula tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16; 949df0566a6SJani Nikula if (tmp > 7) 950df0566a6SJani Nikula return -EINVAL; 951df0566a6SJani Nikula 952df0566a6SJani Nikula return 0; 953df0566a6SJani Nikula } 954df0566a6SJani Nikula 955df0566a6SJani Nikula static int check_overlay_src(struct drm_i915_private *dev_priv, 956df0566a6SJani Nikula struct drm_intel_overlay_put_image *rec, 957df0566a6SJani Nikula struct drm_i915_gem_object *new_bo) 958df0566a6SJani Nikula { 959df0566a6SJani Nikula int uv_hscale = uv_hsubsampling(rec->flags); 960df0566a6SJani Nikula int uv_vscale = uv_vsubsampling(rec->flags); 961df0566a6SJani Nikula u32 stride_mask; 962df0566a6SJani Nikula int depth; 963df0566a6SJani Nikula u32 tmp; 964df0566a6SJani Nikula 965df0566a6SJani Nikula /* check src dimensions */ 966df0566a6SJani Nikula if (IS_I845G(dev_priv) || IS_I830(dev_priv)) { 967df0566a6SJani Nikula if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 968df0566a6SJani Nikula rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 969df0566a6SJani Nikula return -EINVAL; 970df0566a6SJani Nikula } else { 971df0566a6SJani Nikula if (rec->src_height > IMAGE_MAX_HEIGHT || 972df0566a6SJani Nikula rec->src_width > IMAGE_MAX_WIDTH) 973df0566a6SJani Nikula return -EINVAL; 974df0566a6SJani Nikula } 975df0566a6SJani Nikula 976df0566a6SJani Nikula /* better safe than sorry, use 4 as the maximal subsampling ratio */ 977df0566a6SJani Nikula if (rec->src_height < N_VERT_Y_TAPS*4 || 978df0566a6SJani Nikula rec->src_width < N_HORIZ_Y_TAPS*4) 979df0566a6SJani Nikula return -EINVAL; 980df0566a6SJani Nikula 981df0566a6SJani Nikula /* check alignment constraints */ 982df0566a6SJani Nikula switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 983df0566a6SJani Nikula case I915_OVERLAY_RGB: 984df0566a6SJani Nikula /* not implemented */ 985df0566a6SJani Nikula return -EINVAL; 986df0566a6SJani Nikula 987df0566a6SJani Nikula case I915_OVERLAY_YUV_PACKED: 988df0566a6SJani Nikula if (uv_vscale != 1) 989df0566a6SJani Nikula return -EINVAL; 990df0566a6SJani Nikula 991df0566a6SJani Nikula depth = packed_depth_bytes(rec->flags); 992df0566a6SJani Nikula if (depth < 0) 993df0566a6SJani Nikula return depth; 994df0566a6SJani Nikula 995df0566a6SJani Nikula /* ignore UV planes */ 996df0566a6SJani Nikula rec->stride_UV = 0; 997df0566a6SJani Nikula rec->offset_U = 0; 998df0566a6SJani Nikula rec->offset_V = 0; 999df0566a6SJani Nikula /* check pixel alignment */ 1000df0566a6SJani Nikula if (rec->offset_Y % depth) 1001df0566a6SJani Nikula return -EINVAL; 1002df0566a6SJani Nikula break; 1003df0566a6SJani Nikula 1004df0566a6SJani Nikula case I915_OVERLAY_YUV_PLANAR: 1005df0566a6SJani Nikula if (uv_vscale < 0 || uv_hscale < 0) 1006df0566a6SJani Nikula return -EINVAL; 1007df0566a6SJani Nikula /* no offset restrictions for planar formats */ 1008df0566a6SJani Nikula break; 1009df0566a6SJani Nikula 1010df0566a6SJani Nikula default: 1011df0566a6SJani Nikula return -EINVAL; 1012df0566a6SJani Nikula } 1013df0566a6SJani Nikula 1014df0566a6SJani Nikula if (rec->src_width % uv_hscale) 1015df0566a6SJani Nikula return -EINVAL; 1016df0566a6SJani Nikula 1017df0566a6SJani Nikula /* stride checking */ 1018df0566a6SJani Nikula if (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1019df0566a6SJani Nikula stride_mask = 255; 1020df0566a6SJani Nikula else 1021df0566a6SJani Nikula stride_mask = 63; 1022df0566a6SJani Nikula 1023df0566a6SJani Nikula if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1024df0566a6SJani Nikula return -EINVAL; 1025df0566a6SJani Nikula if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512) 1026df0566a6SJani Nikula return -EINVAL; 1027df0566a6SJani Nikula 1028df0566a6SJani Nikula tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1029df0566a6SJani Nikula 4096 : 8192; 1030df0566a6SJani Nikula if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 1031df0566a6SJani Nikula return -EINVAL; 1032df0566a6SJani Nikula 1033df0566a6SJani Nikula /* check buffer dimensions */ 1034df0566a6SJani Nikula switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1035df0566a6SJani Nikula case I915_OVERLAY_RGB: 1036df0566a6SJani Nikula case I915_OVERLAY_YUV_PACKED: 1037df0566a6SJani Nikula /* always 4 Y values per depth pixels */ 1038df0566a6SJani Nikula if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 1039df0566a6SJani Nikula return -EINVAL; 1040df0566a6SJani Nikula 1041df0566a6SJani Nikula tmp = rec->stride_Y*rec->src_height; 1042df0566a6SJani Nikula if (rec->offset_Y + tmp > new_bo->base.size) 1043df0566a6SJani Nikula return -EINVAL; 1044df0566a6SJani Nikula break; 1045df0566a6SJani Nikula 1046df0566a6SJani Nikula case I915_OVERLAY_YUV_PLANAR: 1047df0566a6SJani Nikula if (rec->src_width > rec->stride_Y) 1048df0566a6SJani Nikula return -EINVAL; 1049df0566a6SJani Nikula if (rec->src_width/uv_hscale > rec->stride_UV) 1050df0566a6SJani Nikula return -EINVAL; 1051df0566a6SJani Nikula 1052df0566a6SJani Nikula tmp = rec->stride_Y * rec->src_height; 1053df0566a6SJani Nikula if (rec->offset_Y + tmp > new_bo->base.size) 1054df0566a6SJani Nikula return -EINVAL; 1055df0566a6SJani Nikula 1056df0566a6SJani Nikula tmp = rec->stride_UV * (rec->src_height / uv_vscale); 1057df0566a6SJani Nikula if (rec->offset_U + tmp > new_bo->base.size || 1058df0566a6SJani Nikula rec->offset_V + tmp > new_bo->base.size) 1059df0566a6SJani Nikula return -EINVAL; 1060df0566a6SJani Nikula break; 1061df0566a6SJani Nikula } 1062df0566a6SJani Nikula 1063df0566a6SJani Nikula return 0; 1064df0566a6SJani Nikula } 1065df0566a6SJani Nikula 1066df0566a6SJani Nikula int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1067df0566a6SJani Nikula struct drm_file *file_priv) 1068df0566a6SJani Nikula { 1069df0566a6SJani Nikula struct drm_intel_overlay_put_image *params = data; 1070df0566a6SJani Nikula struct drm_i915_private *dev_priv = to_i915(dev); 1071df0566a6SJani Nikula struct intel_overlay *overlay; 1072df0566a6SJani Nikula struct drm_crtc *drmmode_crtc; 1073df0566a6SJani Nikula struct intel_crtc *crtc; 1074df0566a6SJani Nikula struct drm_i915_gem_object *new_bo; 1075df0566a6SJani Nikula int ret; 1076df0566a6SJani Nikula 1077df0566a6SJani Nikula overlay = dev_priv->overlay; 1078df0566a6SJani Nikula if (!overlay) { 10793c4e93e9SWambui Karuga drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n"); 1080df0566a6SJani Nikula return -ENODEV; 1081df0566a6SJani Nikula } 1082df0566a6SJani Nikula 1083df0566a6SJani Nikula if (!(params->flags & I915_OVERLAY_ENABLE)) { 1084df0566a6SJani Nikula drm_modeset_lock_all(dev); 1085df0566a6SJani Nikula ret = intel_overlay_switch_off(overlay); 1086df0566a6SJani Nikula drm_modeset_unlock_all(dev); 1087df0566a6SJani Nikula 1088df0566a6SJani Nikula return ret; 1089df0566a6SJani Nikula } 1090df0566a6SJani Nikula 1091df0566a6SJani Nikula drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id); 1092df0566a6SJani Nikula if (!drmmode_crtc) 1093df0566a6SJani Nikula return -ENOENT; 1094df0566a6SJani Nikula crtc = to_intel_crtc(drmmode_crtc); 1095df0566a6SJani Nikula 1096df0566a6SJani Nikula new_bo = i915_gem_object_lookup(file_priv, params->bo_handle); 1097df0566a6SJani Nikula if (!new_bo) 1098df0566a6SJani Nikula return -ENOENT; 1099df0566a6SJani Nikula 1100df0566a6SJani Nikula drm_modeset_lock_all(dev); 1101df0566a6SJani Nikula 1102df0566a6SJani Nikula if (i915_gem_object_is_tiled(new_bo)) { 11033c4e93e9SWambui Karuga drm_dbg_kms(&dev_priv->drm, 11043c4e93e9SWambui Karuga "buffer used for overlay image can not be tiled\n"); 1105df0566a6SJani Nikula ret = -EINVAL; 1106df0566a6SJani Nikula goto out_unlock; 1107df0566a6SJani Nikula } 1108df0566a6SJani Nikula 1109df0566a6SJani Nikula ret = intel_overlay_recover_from_interrupt(overlay); 1110df0566a6SJani Nikula if (ret != 0) 1111df0566a6SJani Nikula goto out_unlock; 1112df0566a6SJani Nikula 1113df0566a6SJani Nikula if (overlay->crtc != crtc) { 1114df0566a6SJani Nikula ret = intel_overlay_switch_off(overlay); 1115df0566a6SJani Nikula if (ret != 0) 1116df0566a6SJani Nikula goto out_unlock; 1117df0566a6SJani Nikula 1118df0566a6SJani Nikula ret = check_overlay_possible_on_crtc(overlay, crtc); 1119df0566a6SJani Nikula if (ret != 0) 1120df0566a6SJani Nikula goto out_unlock; 1121df0566a6SJani Nikula 1122df0566a6SJani Nikula overlay->crtc = crtc; 1123df0566a6SJani Nikula crtc->overlay = overlay; 1124df0566a6SJani Nikula 1125df0566a6SJani Nikula /* line too wide, i.e. one-line-mode */ 1126df0566a6SJani Nikula if (crtc->config->pipe_src_w > 1024 && 1127df0566a6SJani Nikula crtc->config->gmch_pfit.control & PFIT_ENABLE) { 1128df0566a6SJani Nikula overlay->pfit_active = true; 1129df0566a6SJani Nikula update_pfit_vscale_ratio(overlay); 1130df0566a6SJani Nikula } else 1131df0566a6SJani Nikula overlay->pfit_active = false; 1132df0566a6SJani Nikula } 1133df0566a6SJani Nikula 1134df0566a6SJani Nikula ret = check_overlay_dst(overlay, params); 1135df0566a6SJani Nikula if (ret != 0) 1136df0566a6SJani Nikula goto out_unlock; 1137df0566a6SJani Nikula 1138df0566a6SJani Nikula if (overlay->pfit_active) { 1139df0566a6SJani Nikula params->dst_y = (((u32)params->dst_y << 12) / 1140df0566a6SJani Nikula overlay->pfit_vscale_ratio); 1141df0566a6SJani Nikula /* shifting right rounds downwards, so add 1 */ 1142df0566a6SJani Nikula params->dst_height = (((u32)params->dst_height << 12) / 1143df0566a6SJani Nikula overlay->pfit_vscale_ratio) + 1; 1144df0566a6SJani Nikula } 1145df0566a6SJani Nikula 1146df0566a6SJani Nikula if (params->src_scan_height > params->src_height || 1147df0566a6SJani Nikula params->src_scan_width > params->src_width) { 1148df0566a6SJani Nikula ret = -EINVAL; 1149df0566a6SJani Nikula goto out_unlock; 1150df0566a6SJani Nikula } 1151df0566a6SJani Nikula 1152df0566a6SJani Nikula ret = check_overlay_src(dev_priv, params, new_bo); 1153df0566a6SJani Nikula if (ret != 0) 1154df0566a6SJani Nikula goto out_unlock; 1155df0566a6SJani Nikula 1156df0566a6SJani Nikula /* Check scaling after src size to prevent a divide-by-zero. */ 1157df0566a6SJani Nikula ret = check_overlay_scaling(params); 1158df0566a6SJani Nikula if (ret != 0) 1159df0566a6SJani Nikula goto out_unlock; 1160df0566a6SJani Nikula 1161df0566a6SJani Nikula ret = intel_overlay_do_put_image(overlay, new_bo, params); 1162df0566a6SJani Nikula if (ret != 0) 1163df0566a6SJani Nikula goto out_unlock; 1164df0566a6SJani Nikula 1165df0566a6SJani Nikula drm_modeset_unlock_all(dev); 1166df0566a6SJani Nikula i915_gem_object_put(new_bo); 1167df0566a6SJani Nikula 1168df0566a6SJani Nikula return 0; 1169df0566a6SJani Nikula 1170df0566a6SJani Nikula out_unlock: 1171df0566a6SJani Nikula drm_modeset_unlock_all(dev); 1172df0566a6SJani Nikula i915_gem_object_put(new_bo); 1173df0566a6SJani Nikula 1174df0566a6SJani Nikula return ret; 1175df0566a6SJani Nikula } 1176df0566a6SJani Nikula 1177df0566a6SJani Nikula static void update_reg_attrs(struct intel_overlay *overlay, 1178df0566a6SJani Nikula struct overlay_registers __iomem *regs) 1179df0566a6SJani Nikula { 1180df0566a6SJani Nikula iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 1181df0566a6SJani Nikula ®s->OCLRC0); 1182df0566a6SJani Nikula iowrite32(overlay->saturation, ®s->OCLRC1); 1183df0566a6SJani Nikula } 1184df0566a6SJani Nikula 1185df0566a6SJani Nikula static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 1186df0566a6SJani Nikula { 1187df0566a6SJani Nikula int i; 1188df0566a6SJani Nikula 1189df0566a6SJani Nikula if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 1190df0566a6SJani Nikula return false; 1191df0566a6SJani Nikula 1192df0566a6SJani Nikula for (i = 0; i < 3; i++) { 1193df0566a6SJani Nikula if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 1194df0566a6SJani Nikula return false; 1195df0566a6SJani Nikula } 1196df0566a6SJani Nikula 1197df0566a6SJani Nikula return true; 1198df0566a6SJani Nikula } 1199df0566a6SJani Nikula 1200df0566a6SJani Nikula static bool check_gamma5_errata(u32 gamma5) 1201df0566a6SJani Nikula { 1202df0566a6SJani Nikula int i; 1203df0566a6SJani Nikula 1204df0566a6SJani Nikula for (i = 0; i < 3; i++) { 1205df0566a6SJani Nikula if (((gamma5 >> i*8) & 0xff) == 0x80) 1206df0566a6SJani Nikula return false; 1207df0566a6SJani Nikula } 1208df0566a6SJani Nikula 1209df0566a6SJani Nikula return true; 1210df0566a6SJani Nikula } 1211df0566a6SJani Nikula 1212df0566a6SJani Nikula static int check_gamma(struct drm_intel_overlay_attrs *attrs) 1213df0566a6SJani Nikula { 1214df0566a6SJani Nikula if (!check_gamma_bounds(0, attrs->gamma0) || 1215df0566a6SJani Nikula !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 1216df0566a6SJani Nikula !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 1217df0566a6SJani Nikula !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 1218df0566a6SJani Nikula !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 1219df0566a6SJani Nikula !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 1220df0566a6SJani Nikula !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 1221df0566a6SJani Nikula return -EINVAL; 1222df0566a6SJani Nikula 1223df0566a6SJani Nikula if (!check_gamma5_errata(attrs->gamma5)) 1224df0566a6SJani Nikula return -EINVAL; 1225df0566a6SJani Nikula 1226df0566a6SJani Nikula return 0; 1227df0566a6SJani Nikula } 1228df0566a6SJani Nikula 1229df0566a6SJani Nikula int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1230df0566a6SJani Nikula struct drm_file *file_priv) 1231df0566a6SJani Nikula { 1232df0566a6SJani Nikula struct drm_intel_overlay_attrs *attrs = data; 1233df0566a6SJani Nikula struct drm_i915_private *dev_priv = to_i915(dev); 1234df0566a6SJani Nikula struct intel_overlay *overlay; 1235df0566a6SJani Nikula int ret; 1236df0566a6SJani Nikula 1237df0566a6SJani Nikula overlay = dev_priv->overlay; 1238df0566a6SJani Nikula if (!overlay) { 12393c4e93e9SWambui Karuga drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n"); 1240df0566a6SJani Nikula return -ENODEV; 1241df0566a6SJani Nikula } 1242df0566a6SJani Nikula 1243df0566a6SJani Nikula drm_modeset_lock_all(dev); 1244df0566a6SJani Nikula 1245df0566a6SJani Nikula ret = -EINVAL; 1246df0566a6SJani Nikula if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 1247df0566a6SJani Nikula attrs->color_key = overlay->color_key; 1248df0566a6SJani Nikula attrs->brightness = overlay->brightness; 1249df0566a6SJani Nikula attrs->contrast = overlay->contrast; 1250df0566a6SJani Nikula attrs->saturation = overlay->saturation; 1251df0566a6SJani Nikula 1252df0566a6SJani Nikula if (!IS_GEN(dev_priv, 2)) { 125382e1b12eSJani Nikula attrs->gamma0 = intel_de_read(dev_priv, OGAMC0); 125482e1b12eSJani Nikula attrs->gamma1 = intel_de_read(dev_priv, OGAMC1); 125582e1b12eSJani Nikula attrs->gamma2 = intel_de_read(dev_priv, OGAMC2); 125682e1b12eSJani Nikula attrs->gamma3 = intel_de_read(dev_priv, OGAMC3); 125782e1b12eSJani Nikula attrs->gamma4 = intel_de_read(dev_priv, OGAMC4); 125882e1b12eSJani Nikula attrs->gamma5 = intel_de_read(dev_priv, OGAMC5); 1259df0566a6SJani Nikula } 1260df0566a6SJani Nikula } else { 1261df0566a6SJani Nikula if (attrs->brightness < -128 || attrs->brightness > 127) 1262df0566a6SJani Nikula goto out_unlock; 1263df0566a6SJani Nikula if (attrs->contrast > 255) 1264df0566a6SJani Nikula goto out_unlock; 1265df0566a6SJani Nikula if (attrs->saturation > 1023) 1266df0566a6SJani Nikula goto out_unlock; 1267df0566a6SJani Nikula 1268df0566a6SJani Nikula overlay->color_key = attrs->color_key; 1269df0566a6SJani Nikula overlay->brightness = attrs->brightness; 1270df0566a6SJani Nikula overlay->contrast = attrs->contrast; 1271df0566a6SJani Nikula overlay->saturation = attrs->saturation; 1272df0566a6SJani Nikula 1273df0566a6SJani Nikula update_reg_attrs(overlay, overlay->regs); 1274df0566a6SJani Nikula 1275df0566a6SJani Nikula if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1276df0566a6SJani Nikula if (IS_GEN(dev_priv, 2)) 1277df0566a6SJani Nikula goto out_unlock; 1278df0566a6SJani Nikula 1279df0566a6SJani Nikula if (overlay->active) { 1280df0566a6SJani Nikula ret = -EBUSY; 1281df0566a6SJani Nikula goto out_unlock; 1282df0566a6SJani Nikula } 1283df0566a6SJani Nikula 1284df0566a6SJani Nikula ret = check_gamma(attrs); 1285df0566a6SJani Nikula if (ret) 1286df0566a6SJani Nikula goto out_unlock; 1287df0566a6SJani Nikula 128882e1b12eSJani Nikula intel_de_write(dev_priv, OGAMC0, attrs->gamma0); 128982e1b12eSJani Nikula intel_de_write(dev_priv, OGAMC1, attrs->gamma1); 129082e1b12eSJani Nikula intel_de_write(dev_priv, OGAMC2, attrs->gamma2); 129182e1b12eSJani Nikula intel_de_write(dev_priv, OGAMC3, attrs->gamma3); 129282e1b12eSJani Nikula intel_de_write(dev_priv, OGAMC4, attrs->gamma4); 129382e1b12eSJani Nikula intel_de_write(dev_priv, OGAMC5, attrs->gamma5); 1294df0566a6SJani Nikula } 1295df0566a6SJani Nikula } 1296df0566a6SJani Nikula overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1297df0566a6SJani Nikula 1298df0566a6SJani Nikula ret = 0; 1299df0566a6SJani Nikula out_unlock: 1300df0566a6SJani Nikula drm_modeset_unlock_all(dev); 1301df0566a6SJani Nikula 1302df0566a6SJani Nikula return ret; 1303df0566a6SJani Nikula } 1304df0566a6SJani Nikula 1305df0566a6SJani Nikula static int get_registers(struct intel_overlay *overlay, bool use_phys) 1306df0566a6SJani Nikula { 1307df0566a6SJani Nikula struct drm_i915_private *i915 = overlay->i915; 1308df0566a6SJani Nikula struct drm_i915_gem_object *obj; 1309df0566a6SJani Nikula struct i915_vma *vma; 1310df0566a6SJani Nikula int err; 1311df0566a6SJani Nikula 1312df0566a6SJani Nikula obj = i915_gem_object_create_stolen(i915, PAGE_SIZE); 13130e5493caSCQ Tang if (IS_ERR(obj)) 1314df0566a6SJani Nikula obj = i915_gem_object_create_internal(i915, PAGE_SIZE); 13152850748eSChris Wilson if (IS_ERR(obj)) 13162850748eSChris Wilson return PTR_ERR(obj); 1317df0566a6SJani Nikula 1318df0566a6SJani Nikula vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); 1319df0566a6SJani Nikula if (IS_ERR(vma)) { 1320df0566a6SJani Nikula err = PTR_ERR(vma); 1321df0566a6SJani Nikula goto err_put_bo; 1322df0566a6SJani Nikula } 1323df0566a6SJani Nikula 1324df0566a6SJani Nikula if (use_phys) 1325df0566a6SJani Nikula overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl); 1326df0566a6SJani Nikula else 1327df0566a6SJani Nikula overlay->flip_addr = i915_ggtt_offset(vma); 1328df0566a6SJani Nikula overlay->regs = i915_vma_pin_iomap(vma); 1329df0566a6SJani Nikula i915_vma_unpin(vma); 1330df0566a6SJani Nikula 1331df0566a6SJani Nikula if (IS_ERR(overlay->regs)) { 1332df0566a6SJani Nikula err = PTR_ERR(overlay->regs); 1333df0566a6SJani Nikula goto err_put_bo; 1334df0566a6SJani Nikula } 1335df0566a6SJani Nikula 1336df0566a6SJani Nikula overlay->reg_bo = obj; 1337df0566a6SJani Nikula return 0; 1338df0566a6SJani Nikula 1339df0566a6SJani Nikula err_put_bo: 1340df0566a6SJani Nikula i915_gem_object_put(obj); 1341df0566a6SJani Nikula return err; 1342df0566a6SJani Nikula } 1343df0566a6SJani Nikula 1344df0566a6SJani Nikula void intel_overlay_setup(struct drm_i915_private *dev_priv) 1345df0566a6SJani Nikula { 1346df0566a6SJani Nikula struct intel_overlay *overlay; 1347e26b6d43SChris Wilson struct intel_engine_cs *engine; 1348df0566a6SJani Nikula int ret; 1349df0566a6SJani Nikula 1350df0566a6SJani Nikula if (!HAS_OVERLAY(dev_priv)) 1351df0566a6SJani Nikula return; 1352df0566a6SJani Nikula 135373c8bfb7SChris Wilson engine = dev_priv->gt.engine[RCS0]; 1354e26b6d43SChris Wilson if (!engine || !engine->kernel_context) 1355ec22f256SChris Wilson return; 1356ec22f256SChris Wilson 1357df0566a6SJani Nikula overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 1358df0566a6SJani Nikula if (!overlay) 1359df0566a6SJani Nikula return; 1360df0566a6SJani Nikula 1361df0566a6SJani Nikula overlay->i915 = dev_priv; 1362e26b6d43SChris Wilson overlay->context = engine->kernel_context; 1363ec22f256SChris Wilson GEM_BUG_ON(!overlay->context); 1364df0566a6SJani Nikula 1365df0566a6SJani Nikula overlay->color_key = 0x0101fe; 1366df0566a6SJani Nikula overlay->color_key_enabled = true; 1367df0566a6SJani Nikula overlay->brightness = -19; 1368df0566a6SJani Nikula overlay->contrast = 75; 1369df0566a6SJani Nikula overlay->saturation = 146; 1370df0566a6SJani Nikula 1371b1e3177bSChris Wilson i915_active_init(&overlay->last_flip, 1372a21ce8adSChris Wilson NULL, intel_overlay_last_flip_retire); 1373df0566a6SJani Nikula 1374df0566a6SJani Nikula ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv)); 1375df0566a6SJani Nikula if (ret) 1376df0566a6SJani Nikula goto out_free; 1377df0566a6SJani Nikula 1378df0566a6SJani Nikula memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1379df0566a6SJani Nikula update_polyphase_filter(overlay->regs); 1380df0566a6SJani Nikula update_reg_attrs(overlay, overlay->regs); 1381df0566a6SJani Nikula 1382df0566a6SJani Nikula dev_priv->overlay = overlay; 13833c4e93e9SWambui Karuga drm_info(&dev_priv->drm, "Initialized overlay support.\n"); 1384df0566a6SJani Nikula return; 1385df0566a6SJani Nikula 1386df0566a6SJani Nikula out_free: 1387df0566a6SJani Nikula kfree(overlay); 1388df0566a6SJani Nikula } 1389df0566a6SJani Nikula 1390df0566a6SJani Nikula void intel_overlay_cleanup(struct drm_i915_private *dev_priv) 1391df0566a6SJani Nikula { 1392df0566a6SJani Nikula struct intel_overlay *overlay; 1393df0566a6SJani Nikula 1394df0566a6SJani Nikula overlay = fetch_and_zero(&dev_priv->overlay); 1395df0566a6SJani Nikula if (!overlay) 1396df0566a6SJani Nikula return; 1397df0566a6SJani Nikula 1398df0566a6SJani Nikula /* 1399df0566a6SJani Nikula * The bo's should be free'd by the generic code already. 1400df0566a6SJani Nikula * Furthermore modesetting teardown happens beforehand so the 1401df0566a6SJani Nikula * hardware should be off already. 1402df0566a6SJani Nikula */ 1403b0b2ed0cSPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, overlay->active); 1404df0566a6SJani Nikula 1405df0566a6SJani Nikula i915_gem_object_put(overlay->reg_bo); 1406a21ce8adSChris Wilson i915_active_fini(&overlay->last_flip); 1407df0566a6SJani Nikula 1408df0566a6SJani Nikula kfree(overlay); 1409df0566a6SJani Nikula } 1410df0566a6SJani Nikula 1411df0566a6SJani Nikula #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1412df0566a6SJani Nikula 1413df0566a6SJani Nikula struct intel_overlay_error_state { 1414df0566a6SJani Nikula struct overlay_registers regs; 1415df0566a6SJani Nikula unsigned long base; 1416df0566a6SJani Nikula u32 dovsta; 1417df0566a6SJani Nikula u32 isr; 1418df0566a6SJani Nikula }; 1419df0566a6SJani Nikula 1420df0566a6SJani Nikula struct intel_overlay_error_state * 1421df0566a6SJani Nikula intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) 1422df0566a6SJani Nikula { 1423df0566a6SJani Nikula struct intel_overlay *overlay = dev_priv->overlay; 1424df0566a6SJani Nikula struct intel_overlay_error_state *error; 1425df0566a6SJani Nikula 1426df0566a6SJani Nikula if (!overlay || !overlay->active) 1427df0566a6SJani Nikula return NULL; 1428df0566a6SJani Nikula 1429df0566a6SJani Nikula error = kmalloc(sizeof(*error), GFP_ATOMIC); 1430df0566a6SJani Nikula if (error == NULL) 1431df0566a6SJani Nikula return NULL; 1432df0566a6SJani Nikula 143382e1b12eSJani Nikula error->dovsta = intel_de_read(dev_priv, DOVSTA); 143482e1b12eSJani Nikula error->isr = intel_de_read(dev_priv, GEN2_ISR); 1435df0566a6SJani Nikula error->base = overlay->flip_addr; 1436df0566a6SJani Nikula 1437df0566a6SJani Nikula memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs)); 1438df0566a6SJani Nikula 1439df0566a6SJani Nikula return error; 1440df0566a6SJani Nikula } 1441df0566a6SJani Nikula 1442df0566a6SJani Nikula void 1443df0566a6SJani Nikula intel_overlay_print_error_state(struct drm_i915_error_state_buf *m, 1444df0566a6SJani Nikula struct intel_overlay_error_state *error) 1445df0566a6SJani Nikula { 1446df0566a6SJani Nikula i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1447df0566a6SJani Nikula error->dovsta, error->isr); 1448df0566a6SJani Nikula i915_error_printf(m, " Register file at 0x%08lx:\n", 1449df0566a6SJani Nikula error->base); 1450df0566a6SJani Nikula 1451df0566a6SJani Nikula #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) 1452df0566a6SJani Nikula P(OBUF_0Y); 1453df0566a6SJani Nikula P(OBUF_1Y); 1454df0566a6SJani Nikula P(OBUF_0U); 1455df0566a6SJani Nikula P(OBUF_0V); 1456df0566a6SJani Nikula P(OBUF_1U); 1457df0566a6SJani Nikula P(OBUF_1V); 1458df0566a6SJani Nikula P(OSTRIDE); 1459df0566a6SJani Nikula P(YRGB_VPH); 1460df0566a6SJani Nikula P(UV_VPH); 1461df0566a6SJani Nikula P(HORZ_PH); 1462df0566a6SJani Nikula P(INIT_PHS); 1463df0566a6SJani Nikula P(DWINPOS); 1464df0566a6SJani Nikula P(DWINSZ); 1465df0566a6SJani Nikula P(SWIDTH); 1466df0566a6SJani Nikula P(SWIDTHSW); 1467df0566a6SJani Nikula P(SHEIGHT); 1468df0566a6SJani Nikula P(YRGBSCALE); 1469df0566a6SJani Nikula P(UVSCALE); 1470df0566a6SJani Nikula P(OCLRC0); 1471df0566a6SJani Nikula P(OCLRC1); 1472df0566a6SJani Nikula P(DCLRKV); 1473df0566a6SJani Nikula P(DCLRKM); 1474df0566a6SJani Nikula P(SCLRKVH); 1475df0566a6SJani Nikula P(SCLRKVL); 1476df0566a6SJani Nikula P(SCLRKEN); 1477df0566a6SJani Nikula P(OCONFIG); 1478df0566a6SJani Nikula P(OCMD); 1479df0566a6SJani Nikula P(OSTART_0Y); 1480df0566a6SJani Nikula P(OSTART_1Y); 1481df0566a6SJani Nikula P(OSTART_0U); 1482df0566a6SJani Nikula P(OSTART_0V); 1483df0566a6SJani Nikula P(OSTART_1U); 1484df0566a6SJani Nikula P(OSTART_1V); 1485df0566a6SJani Nikula P(OTILEOFF_0Y); 1486df0566a6SJani Nikula P(OTILEOFF_1Y); 1487df0566a6SJani Nikula P(OTILEOFF_0U); 1488df0566a6SJani Nikula P(OTILEOFF_0V); 1489df0566a6SJani Nikula P(OTILEOFF_1U); 1490df0566a6SJani Nikula P(OTILEOFF_1V); 1491df0566a6SJani Nikula P(FASTHSCALE); 1492df0566a6SJani Nikula P(UVSCALEV); 1493df0566a6SJani Nikula #undef P 1494df0566a6SJani Nikula } 1495df0566a6SJani Nikula 1496df0566a6SJani Nikula #endif 1497