1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 * 5 * Read out the current hardware modeset state, and sanitize it to the current 6 * state. 7 */ 8 9 #include <drm/drm_atomic_uapi.h> 10 #include <drm/drm_atomic_state_helper.h> 11 12 #include "i915_drv.h" 13 #include "i915_reg.h" 14 #include "i9xx_wm.h" 15 #include "intel_atomic.h" 16 #include "intel_bw.h" 17 #include "intel_color.h" 18 #include "intel_crtc.h" 19 #include "intel_crtc_state_dump.h" 20 #include "intel_ddi.h" 21 #include "intel_de.h" 22 #include "intel_display.h" 23 #include "intel_display_power.h" 24 #include "intel_display_types.h" 25 #include "intel_dmc.h" 26 #include "intel_fifo_underrun.h" 27 #include "intel_modeset_setup.h" 28 #include "intel_pch_display.h" 29 #include "intel_vblank.h" 30 #include "intel_wm.h" 31 #include "skl_watermark.h" 32 33 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, 34 struct drm_modeset_acquire_ctx *ctx) 35 { 36 struct intel_encoder *encoder; 37 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 38 struct intel_bw_state *bw_state = 39 to_intel_bw_state(i915->display.bw.obj.state); 40 struct intel_cdclk_state *cdclk_state = 41 to_intel_cdclk_state(i915->display.cdclk.obj.state); 42 struct intel_dbuf_state *dbuf_state = 43 to_intel_dbuf_state(i915->display.dbuf.obj.state); 44 struct intel_crtc_state *crtc_state = 45 to_intel_crtc_state(crtc->base.state); 46 struct intel_plane *plane; 47 struct drm_atomic_state *state; 48 struct intel_crtc_state *temp_crtc_state; 49 enum pipe pipe = crtc->pipe; 50 int ret; 51 52 if (!crtc_state->hw.active) 53 return; 54 55 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 56 const struct intel_plane_state *plane_state = 57 to_intel_plane_state(plane->base.state); 58 59 if (plane_state->uapi.visible) 60 intel_plane_disable_noatomic(crtc, plane); 61 } 62 63 state = drm_atomic_state_alloc(&i915->drm); 64 if (!state) { 65 drm_dbg_kms(&i915->drm, 66 "failed to disable [CRTC:%d:%s], out of memory", 67 crtc->base.base.id, crtc->base.name); 68 return; 69 } 70 71 state->acquire_ctx = ctx; 72 73 /* Everything's already locked, -EDEADLK can't happen. */ 74 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); 75 ret = drm_atomic_add_affected_connectors(state, &crtc->base); 76 77 drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret); 78 79 i915->display.funcs.display->crtc_disable(to_intel_atomic_state(state), crtc); 80 81 drm_atomic_state_put(state); 82 83 drm_dbg_kms(&i915->drm, 84 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", 85 crtc->base.base.id, crtc->base.name); 86 87 crtc->active = false; 88 crtc->base.enabled = false; 89 90 drm_WARN_ON(&i915->drm, 91 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); 92 crtc_state->uapi.active = false; 93 crtc_state->uapi.connector_mask = 0; 94 crtc_state->uapi.encoder_mask = 0; 95 intel_crtc_free_hw_state(crtc_state); 96 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); 97 98 for_each_encoder_on_crtc(&i915->drm, &crtc->base, encoder) 99 encoder->base.crtc = NULL; 100 101 intel_fbc_disable(crtc); 102 intel_update_watermarks(i915); 103 104 intel_display_power_put_all_in_set(i915, &crtc->enabled_power_domains); 105 106 cdclk_state->min_cdclk[pipe] = 0; 107 cdclk_state->min_voltage_level[pipe] = 0; 108 cdclk_state->active_pipes &= ~BIT(pipe); 109 110 dbuf_state->active_pipes &= ~BIT(pipe); 111 112 bw_state->data_rate[pipe] = 0; 113 bw_state->num_active_planes[pipe] = 0; 114 } 115 116 static void intel_modeset_update_connector_atomic_state(struct drm_i915_private *i915) 117 { 118 struct intel_connector *connector; 119 struct drm_connector_list_iter conn_iter; 120 121 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 122 for_each_intel_connector_iter(connector, &conn_iter) { 123 struct drm_connector_state *conn_state = connector->base.state; 124 struct intel_encoder *encoder = 125 to_intel_encoder(connector->base.encoder); 126 127 if (conn_state->crtc) 128 drm_connector_put(&connector->base); 129 130 if (encoder) { 131 struct intel_crtc *crtc = 132 to_intel_crtc(encoder->base.crtc); 133 const struct intel_crtc_state *crtc_state = 134 to_intel_crtc_state(crtc->base.state); 135 136 conn_state->best_encoder = &encoder->base; 137 conn_state->crtc = &crtc->base; 138 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; 139 140 drm_connector_get(&connector->base); 141 } else { 142 conn_state->best_encoder = NULL; 143 conn_state->crtc = NULL; 144 } 145 } 146 drm_connector_list_iter_end(&conn_iter); 147 } 148 149 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) 150 { 151 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 152 return; 153 154 crtc_state->uapi.enable = crtc_state->hw.enable; 155 crtc_state->uapi.active = crtc_state->hw.active; 156 drm_WARN_ON(crtc_state->uapi.crtc->dev, 157 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); 158 159 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; 160 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; 161 162 /* assume 1:1 mapping */ 163 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 164 crtc_state->pre_csc_lut); 165 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 166 crtc_state->post_csc_lut); 167 168 drm_property_replace_blob(&crtc_state->uapi.degamma_lut, 169 crtc_state->hw.degamma_lut); 170 drm_property_replace_blob(&crtc_state->uapi.gamma_lut, 171 crtc_state->hw.gamma_lut); 172 drm_property_replace_blob(&crtc_state->uapi.ctm, 173 crtc_state->hw.ctm); 174 } 175 176 static void 177 intel_sanitize_plane_mapping(struct drm_i915_private *i915) 178 { 179 struct intel_crtc *crtc; 180 181 if (DISPLAY_VER(i915) >= 4) 182 return; 183 184 for_each_intel_crtc(&i915->drm, crtc) { 185 struct intel_plane *plane = 186 to_intel_plane(crtc->base.primary); 187 struct intel_crtc *plane_crtc; 188 enum pipe pipe; 189 190 if (!plane->get_hw_state(plane, &pipe)) 191 continue; 192 193 if (pipe == crtc->pipe) 194 continue; 195 196 drm_dbg_kms(&i915->drm, 197 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", 198 plane->base.base.id, plane->base.name); 199 200 plane_crtc = intel_crtc_for_pipe(i915, pipe); 201 intel_plane_disable_noatomic(plane_crtc, plane); 202 } 203 } 204 205 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) 206 { 207 struct drm_device *dev = crtc->base.dev; 208 struct intel_encoder *encoder; 209 210 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 211 return true; 212 213 return false; 214 } 215 216 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) 217 { 218 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 219 struct drm_connector_list_iter conn_iter; 220 struct intel_connector *connector; 221 struct intel_connector *found_connector = NULL; 222 223 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 224 for_each_intel_connector_iter(connector, &conn_iter) { 225 if (&encoder->base == connector->base.encoder) { 226 found_connector = connector; 227 break; 228 } 229 } 230 drm_connector_list_iter_end(&conn_iter); 231 232 return found_connector; 233 } 234 235 static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state) 236 { 237 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 238 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 239 240 /* 241 * We start out with underrun reporting disabled on active 242 * pipes to avoid races. 243 * 244 * Also on gmch platforms we dont have any hardware bits to 245 * disable the underrun reporting. Which means we need to start 246 * out with underrun reporting disabled also on inactive pipes, 247 * since otherwise we'll complain about the garbage we read when 248 * e.g. coming up after runtime pm. 249 * 250 * No protection against concurrent access is required - at 251 * worst a fifo underrun happens which also sets this to false. 252 */ 253 intel_init_fifo_underrun_reporting(i915, crtc, 254 !crtc_state->hw.active && 255 !HAS_GMCH(i915)); 256 } 257 258 static void intel_sanitize_crtc(struct intel_crtc *crtc, 259 struct drm_modeset_acquire_ctx *ctx) 260 { 261 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 262 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 263 264 if (crtc_state->hw.active) { 265 struct intel_plane *plane; 266 267 /* Disable everything but the primary plane */ 268 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 269 const struct intel_plane_state *plane_state = 270 to_intel_plane_state(plane->base.state); 271 272 if (plane_state->uapi.visible && 273 plane->base.type != DRM_PLANE_TYPE_PRIMARY) 274 intel_plane_disable_noatomic(crtc, plane); 275 } 276 277 /* Disable any background color/etc. set by the BIOS */ 278 intel_color_commit_noarm(crtc_state); 279 intel_color_commit_arm(crtc_state); 280 } 281 282 /* 283 * Adjust the state of the output pipe according to whether we have 284 * active connectors/encoders. 285 */ 286 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) && 287 !intel_crtc_is_bigjoiner_slave(crtc_state)) 288 intel_crtc_disable_noatomic(crtc, ctx); 289 } 290 291 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) 292 { 293 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 294 295 /* 296 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram 297 * the hardware when a high res displays plugged in. DPLL P 298 * divider is zero, and the pipe timings are bonkers. We'll 299 * try to disable everything in that case. 300 * 301 * FIXME would be nice to be able to sanitize this state 302 * without several WARNs, but for now let's take the easy 303 * road. 304 */ 305 return IS_SANDYBRIDGE(i915) && 306 crtc_state->hw.active && 307 crtc_state->shared_dpll && 308 crtc_state->port_clock == 0; 309 } 310 311 static void intel_sanitize_encoder(struct intel_encoder *encoder) 312 { 313 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 314 struct intel_connector *connector; 315 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 316 struct intel_crtc_state *crtc_state = crtc ? 317 to_intel_crtc_state(crtc->base.state) : NULL; 318 319 /* 320 * We need to check both for a crtc link (meaning that the encoder is 321 * active and trying to read from a pipe) and the pipe itself being 322 * active. 323 */ 324 bool has_active_crtc = crtc_state && 325 crtc_state->hw.active; 326 327 if (crtc_state && has_bogus_dpll_config(crtc_state)) { 328 drm_dbg_kms(&i915->drm, 329 "BIOS has misprogrammed the hardware. Disabling pipe %c\n", 330 pipe_name(crtc->pipe)); 331 has_active_crtc = false; 332 } 333 334 connector = intel_encoder_find_connector(encoder); 335 if (connector && !has_active_crtc) { 336 drm_dbg_kms(&i915->drm, 337 "[ENCODER:%d:%s] has active connectors but no active pipe!\n", 338 encoder->base.base.id, 339 encoder->base.name); 340 341 /* 342 * Connector is active, but has no active pipe. This is fallout 343 * from our resume register restoring. Disable the encoder 344 * manually again. 345 */ 346 if (crtc_state) { 347 struct drm_encoder *best_encoder; 348 349 drm_dbg_kms(&i915->drm, 350 "[ENCODER:%d:%s] manually disabled\n", 351 encoder->base.base.id, 352 encoder->base.name); 353 354 /* avoid oopsing in case the hooks consult best_encoder */ 355 best_encoder = connector->base.state->best_encoder; 356 connector->base.state->best_encoder = &encoder->base; 357 358 /* FIXME NULL atomic state passed! */ 359 if (encoder->disable) 360 encoder->disable(NULL, encoder, crtc_state, 361 connector->base.state); 362 if (encoder->post_disable) 363 encoder->post_disable(NULL, encoder, crtc_state, 364 connector->base.state); 365 366 connector->base.state->best_encoder = best_encoder; 367 } 368 encoder->base.crtc = NULL; 369 370 /* 371 * Inconsistent output/port/pipe state happens presumably due to 372 * a bug in one of the get_hw_state functions. Or someplace else 373 * in our code, like the register restore mess on resume. Clamp 374 * things to off as a safer default. 375 */ 376 connector->base.dpms = DRM_MODE_DPMS_OFF; 377 connector->base.encoder = NULL; 378 } 379 380 /* notify opregion of the sanitized encoder state */ 381 intel_opregion_notify_encoder(encoder, connector && has_active_crtc); 382 383 if (HAS_DDI(i915)) 384 intel_ddi_sanitize_encoder_pll_mapping(encoder); 385 } 386 387 /* FIXME read out full plane state for all planes */ 388 static void readout_plane_state(struct drm_i915_private *i915) 389 { 390 struct intel_plane *plane; 391 struct intel_crtc *crtc; 392 393 for_each_intel_plane(&i915->drm, plane) { 394 struct intel_plane_state *plane_state = 395 to_intel_plane_state(plane->base.state); 396 struct intel_crtc_state *crtc_state; 397 enum pipe pipe = PIPE_A; 398 bool visible; 399 400 visible = plane->get_hw_state(plane, &pipe); 401 402 crtc = intel_crtc_for_pipe(i915, pipe); 403 crtc_state = to_intel_crtc_state(crtc->base.state); 404 405 intel_set_plane_visible(crtc_state, plane_state, visible); 406 407 drm_dbg_kms(&i915->drm, 408 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", 409 plane->base.base.id, plane->base.name, 410 str_enabled_disabled(visible), pipe_name(pipe)); 411 } 412 413 for_each_intel_crtc(&i915->drm, crtc) { 414 struct intel_crtc_state *crtc_state = 415 to_intel_crtc_state(crtc->base.state); 416 417 intel_plane_fixup_bitmasks(crtc_state); 418 } 419 } 420 421 static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) 422 { 423 struct intel_cdclk_state *cdclk_state = 424 to_intel_cdclk_state(i915->display.cdclk.obj.state); 425 struct intel_dbuf_state *dbuf_state = 426 to_intel_dbuf_state(i915->display.dbuf.obj.state); 427 enum pipe pipe; 428 struct intel_crtc *crtc; 429 struct intel_encoder *encoder; 430 struct intel_connector *connector; 431 struct drm_connector_list_iter conn_iter; 432 u8 active_pipes = 0; 433 434 for_each_intel_crtc(&i915->drm, crtc) { 435 struct intel_crtc_state *crtc_state = 436 to_intel_crtc_state(crtc->base.state); 437 438 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 439 intel_crtc_free_hw_state(crtc_state); 440 intel_crtc_state_reset(crtc_state, crtc); 441 442 intel_crtc_get_pipe_config(crtc_state); 443 444 crtc_state->hw.enable = crtc_state->hw.active; 445 446 crtc->base.enabled = crtc_state->hw.enable; 447 crtc->active = crtc_state->hw.active; 448 449 if (crtc_state->hw.active) 450 active_pipes |= BIT(crtc->pipe); 451 452 drm_dbg_kms(&i915->drm, 453 "[CRTC:%d:%s] hw state readout: %s\n", 454 crtc->base.base.id, crtc->base.name, 455 str_enabled_disabled(crtc_state->hw.active)); 456 } 457 458 cdclk_state->active_pipes = active_pipes; 459 dbuf_state->active_pipes = active_pipes; 460 461 readout_plane_state(i915); 462 463 for_each_intel_encoder(&i915->drm, encoder) { 464 struct intel_crtc_state *crtc_state = NULL; 465 466 pipe = 0; 467 468 if (encoder->get_hw_state(encoder, &pipe)) { 469 crtc = intel_crtc_for_pipe(i915, pipe); 470 crtc_state = to_intel_crtc_state(crtc->base.state); 471 472 encoder->base.crtc = &crtc->base; 473 intel_encoder_get_config(encoder, crtc_state); 474 475 /* read out to slave crtc as well for bigjoiner */ 476 if (crtc_state->bigjoiner_pipes) { 477 struct intel_crtc *slave_crtc; 478 479 /* encoder should read be linked to bigjoiner master */ 480 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 481 482 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 483 intel_crtc_bigjoiner_slave_pipes(crtc_state)) { 484 struct intel_crtc_state *slave_crtc_state; 485 486 slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state); 487 intel_encoder_get_config(encoder, slave_crtc_state); 488 } 489 } 490 } else { 491 encoder->base.crtc = NULL; 492 } 493 494 if (encoder->sync_state) 495 encoder->sync_state(encoder, crtc_state); 496 497 drm_dbg_kms(&i915->drm, 498 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", 499 encoder->base.base.id, encoder->base.name, 500 str_enabled_disabled(encoder->base.crtc), 501 pipe_name(pipe)); 502 } 503 504 intel_dpll_readout_hw_state(i915); 505 506 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 507 for_each_intel_connector_iter(connector, &conn_iter) { 508 if (connector->get_hw_state(connector)) { 509 struct intel_crtc_state *crtc_state; 510 struct intel_crtc *crtc; 511 512 connector->base.dpms = DRM_MODE_DPMS_ON; 513 514 encoder = intel_attached_encoder(connector); 515 connector->base.encoder = &encoder->base; 516 517 crtc = to_intel_crtc(encoder->base.crtc); 518 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; 519 520 if (crtc_state && crtc_state->hw.active) { 521 /* 522 * This has to be done during hardware readout 523 * because anything calling .crtc_disable may 524 * rely on the connector_mask being accurate. 525 */ 526 crtc_state->uapi.connector_mask |= 527 drm_connector_mask(&connector->base); 528 crtc_state->uapi.encoder_mask |= 529 drm_encoder_mask(&encoder->base); 530 } 531 } else { 532 connector->base.dpms = DRM_MODE_DPMS_OFF; 533 connector->base.encoder = NULL; 534 } 535 drm_dbg_kms(&i915->drm, 536 "[CONNECTOR:%d:%s] hw state readout: %s\n", 537 connector->base.base.id, connector->base.name, 538 str_enabled_disabled(connector->base.encoder)); 539 } 540 drm_connector_list_iter_end(&conn_iter); 541 542 for_each_intel_crtc(&i915->drm, crtc) { 543 struct intel_bw_state *bw_state = 544 to_intel_bw_state(i915->display.bw.obj.state); 545 struct intel_crtc_state *crtc_state = 546 to_intel_crtc_state(crtc->base.state); 547 struct intel_plane *plane; 548 int min_cdclk = 0; 549 550 if (crtc_state->hw.active) { 551 /* 552 * The initial mode needs to be set in order to keep 553 * the atomic core happy. It wants a valid mode if the 554 * crtc's enabled, so we do the above call. 555 * 556 * But we don't set all the derived state fully, hence 557 * set a flag to indicate that a full recalculation is 558 * needed on the next commit. 559 */ 560 crtc_state->inherited = true; 561 562 intel_crtc_update_active_timings(crtc_state); 563 564 intel_crtc_copy_hw_to_uapi_state(crtc_state); 565 } 566 567 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 568 const struct intel_plane_state *plane_state = 569 to_intel_plane_state(plane->base.state); 570 571 /* 572 * FIXME don't have the fb yet, so can't 573 * use intel_plane_data_rate() :( 574 */ 575 if (plane_state->uapi.visible) 576 crtc_state->data_rate[plane->id] = 577 4 * crtc_state->pixel_rate; 578 /* 579 * FIXME don't have the fb yet, so can't 580 * use plane->min_cdclk() :( 581 */ 582 if (plane_state->uapi.visible && plane->min_cdclk) { 583 if (crtc_state->double_wide || DISPLAY_VER(i915) >= 10) 584 crtc_state->min_cdclk[plane->id] = 585 DIV_ROUND_UP(crtc_state->pixel_rate, 2); 586 else 587 crtc_state->min_cdclk[plane->id] = 588 crtc_state->pixel_rate; 589 } 590 drm_dbg_kms(&i915->drm, 591 "[PLANE:%d:%s] min_cdclk %d kHz\n", 592 plane->base.base.id, plane->base.name, 593 crtc_state->min_cdclk[plane->id]); 594 } 595 596 if (crtc_state->hw.active) { 597 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 598 if (drm_WARN_ON(&i915->drm, min_cdclk < 0)) 599 min_cdclk = 0; 600 } 601 602 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 603 cdclk_state->min_voltage_level[crtc->pipe] = 604 crtc_state->min_voltage_level; 605 606 intel_bw_crtc_update(bw_state, crtc_state); 607 } 608 } 609 610 static void 611 get_encoder_power_domains(struct drm_i915_private *i915) 612 { 613 struct intel_encoder *encoder; 614 615 for_each_intel_encoder(&i915->drm, encoder) { 616 struct intel_crtc_state *crtc_state; 617 618 if (!encoder->get_power_domains) 619 continue; 620 621 /* 622 * MST-primary and inactive encoders don't have a crtc state 623 * and neither of these require any power domain references. 624 */ 625 if (!encoder->base.crtc) 626 continue; 627 628 crtc_state = to_intel_crtc_state(encoder->base.crtc->state); 629 encoder->get_power_domains(encoder, crtc_state); 630 } 631 } 632 633 static void intel_early_display_was(struct drm_i915_private *i915) 634 { 635 /* 636 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl 637 * Also known as Wa_14010480278. 638 */ 639 if (IS_DISPLAY_VER(i915, 10, 12)) 640 intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, DARBF_GATING_DIS); 641 642 /* 643 * WaRsPkgCStateDisplayPMReq:hsw 644 * System hang if this isn't done before disabling all planes! 645 */ 646 if (IS_HASWELL(i915)) 647 intel_de_rmw(i915, CHICKEN_PAR1_1, 0, FORCE_ARB_IDLE_PLANES); 648 649 if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) { 650 /* Display WA #1142:kbl,cfl,cml */ 651 intel_de_rmw(i915, CHICKEN_PAR1_1, 652 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22); 653 intel_de_rmw(i915, CHICKEN_MISC_2, 654 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14, 655 KBL_ARB_FILL_SPARE_14); 656 } 657 } 658 659 void intel_modeset_setup_hw_state(struct drm_i915_private *i915, 660 struct drm_modeset_acquire_ctx *ctx) 661 { 662 struct intel_encoder *encoder; 663 struct intel_crtc *crtc; 664 intel_wakeref_t wakeref; 665 666 wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); 667 668 intel_early_display_was(i915); 669 intel_modeset_readout_hw_state(i915); 670 671 /* HW state is read out, now we need to sanitize this mess. */ 672 get_encoder_power_domains(i915); 673 674 intel_pch_sanitize(i915); 675 676 /* 677 * intel_sanitize_plane_mapping() may need to do vblank 678 * waits, so we need vblank interrupts restored beforehand. 679 */ 680 for_each_intel_crtc(&i915->drm, crtc) { 681 struct intel_crtc_state *crtc_state = 682 to_intel_crtc_state(crtc->base.state); 683 684 intel_sanitize_fifo_underrun_reporting(crtc_state); 685 686 drm_crtc_vblank_reset(&crtc->base); 687 688 if (crtc_state->hw.active) { 689 intel_dmc_enable_pipe(i915, crtc->pipe); 690 intel_crtc_vblank_on(crtc_state); 691 } 692 } 693 694 intel_fbc_sanitize(i915); 695 696 intel_sanitize_plane_mapping(i915); 697 698 for_each_intel_encoder(&i915->drm, encoder) 699 intel_sanitize_encoder(encoder); 700 701 for_each_intel_crtc(&i915->drm, crtc) { 702 struct intel_crtc_state *crtc_state = 703 to_intel_crtc_state(crtc->base.state); 704 705 intel_sanitize_crtc(crtc, ctx); 706 intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state"); 707 } 708 709 intel_modeset_update_connector_atomic_state(i915); 710 711 intel_dpll_sanitize_state(i915); 712 713 intel_wm_get_hw_state(i915); 714 715 for_each_intel_crtc(&i915->drm, crtc) { 716 struct intel_crtc_state *crtc_state = 717 to_intel_crtc_state(crtc->base.state); 718 struct intel_power_domain_mask put_domains; 719 720 intel_modeset_get_crtc_power_domains(crtc_state, &put_domains); 721 if (drm_WARN_ON(&i915->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM))) 722 intel_modeset_put_crtc_power_domains(crtc, &put_domains); 723 } 724 725 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 726 727 intel_power_domains_sanitize_state(i915); 728 } 729