1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 * 5 * Read out the current hardware modeset state, and sanitize it to the current 6 * state. 7 */ 8 9 #include <drm/drm_atomic_uapi.h> 10 #include <drm/drm_atomic_state_helper.h> 11 12 #include "i915_drv.h" 13 #include "i915_reg.h" 14 #include "intel_atomic.h" 15 #include "intel_bw.h" 16 #include "intel_color.h" 17 #include "intel_crtc.h" 18 #include "intel_crtc_state_dump.h" 19 #include "intel_ddi.h" 20 #include "intel_de.h" 21 #include "intel_display.h" 22 #include "intel_display_power.h" 23 #include "intel_display_types.h" 24 #include "intel_modeset_setup.h" 25 #include "intel_pch_display.h" 26 #include "intel_pm.h" 27 #include "skl_watermark.h" 28 29 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, 30 struct drm_modeset_acquire_ctx *ctx) 31 { 32 struct intel_encoder *encoder; 33 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 34 struct intel_bw_state *bw_state = 35 to_intel_bw_state(i915->display.bw.obj.state); 36 struct intel_cdclk_state *cdclk_state = 37 to_intel_cdclk_state(i915->display.cdclk.obj.state); 38 struct intel_dbuf_state *dbuf_state = 39 to_intel_dbuf_state(i915->display.dbuf.obj.state); 40 struct intel_crtc_state *crtc_state = 41 to_intel_crtc_state(crtc->base.state); 42 struct intel_plane *plane; 43 struct drm_atomic_state *state; 44 struct intel_crtc_state *temp_crtc_state; 45 enum pipe pipe = crtc->pipe; 46 int ret; 47 48 if (!crtc_state->hw.active) 49 return; 50 51 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 52 const struct intel_plane_state *plane_state = 53 to_intel_plane_state(plane->base.state); 54 55 if (plane_state->uapi.visible) 56 intel_plane_disable_noatomic(crtc, plane); 57 } 58 59 state = drm_atomic_state_alloc(&i915->drm); 60 if (!state) { 61 drm_dbg_kms(&i915->drm, 62 "failed to disable [CRTC:%d:%s], out of memory", 63 crtc->base.base.id, crtc->base.name); 64 return; 65 } 66 67 state->acquire_ctx = ctx; 68 69 /* Everything's already locked, -EDEADLK can't happen. */ 70 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); 71 ret = drm_atomic_add_affected_connectors(state, &crtc->base); 72 73 drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret); 74 75 i915->display.funcs.display->crtc_disable(to_intel_atomic_state(state), crtc); 76 77 drm_atomic_state_put(state); 78 79 drm_dbg_kms(&i915->drm, 80 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", 81 crtc->base.base.id, crtc->base.name); 82 83 crtc->active = false; 84 crtc->base.enabled = false; 85 86 drm_WARN_ON(&i915->drm, 87 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); 88 crtc_state->uapi.active = false; 89 crtc_state->uapi.connector_mask = 0; 90 crtc_state->uapi.encoder_mask = 0; 91 intel_crtc_free_hw_state(crtc_state); 92 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); 93 94 for_each_encoder_on_crtc(&i915->drm, &crtc->base, encoder) 95 encoder->base.crtc = NULL; 96 97 intel_fbc_disable(crtc); 98 intel_update_watermarks(i915); 99 intel_disable_shared_dpll(crtc_state); 100 101 intel_display_power_put_all_in_set(i915, &crtc->enabled_power_domains); 102 103 cdclk_state->min_cdclk[pipe] = 0; 104 cdclk_state->min_voltage_level[pipe] = 0; 105 cdclk_state->active_pipes &= ~BIT(pipe); 106 107 dbuf_state->active_pipes &= ~BIT(pipe); 108 109 bw_state->data_rate[pipe] = 0; 110 bw_state->num_active_planes[pipe] = 0; 111 } 112 113 static void intel_modeset_update_connector_atomic_state(struct drm_i915_private *i915) 114 { 115 struct intel_connector *connector; 116 struct drm_connector_list_iter conn_iter; 117 118 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 119 for_each_intel_connector_iter(connector, &conn_iter) { 120 struct drm_connector_state *conn_state = connector->base.state; 121 struct intel_encoder *encoder = 122 to_intel_encoder(connector->base.encoder); 123 124 if (conn_state->crtc) 125 drm_connector_put(&connector->base); 126 127 if (encoder) { 128 struct intel_crtc *crtc = 129 to_intel_crtc(encoder->base.crtc); 130 const struct intel_crtc_state *crtc_state = 131 to_intel_crtc_state(crtc->base.state); 132 133 conn_state->best_encoder = &encoder->base; 134 conn_state->crtc = &crtc->base; 135 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; 136 137 drm_connector_get(&connector->base); 138 } else { 139 conn_state->best_encoder = NULL; 140 conn_state->crtc = NULL; 141 } 142 } 143 drm_connector_list_iter_end(&conn_iter); 144 } 145 146 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) 147 { 148 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 149 return; 150 151 crtc_state->uapi.enable = crtc_state->hw.enable; 152 crtc_state->uapi.active = crtc_state->hw.active; 153 drm_WARN_ON(crtc_state->uapi.crtc->dev, 154 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); 155 156 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; 157 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; 158 159 /* assume 1:1 mapping */ 160 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 161 crtc_state->pre_csc_lut); 162 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 163 crtc_state->post_csc_lut); 164 165 drm_property_replace_blob(&crtc_state->uapi.degamma_lut, 166 crtc_state->hw.degamma_lut); 167 drm_property_replace_blob(&crtc_state->uapi.gamma_lut, 168 crtc_state->hw.gamma_lut); 169 drm_property_replace_blob(&crtc_state->uapi.ctm, 170 crtc_state->hw.ctm); 171 } 172 173 static void 174 intel_sanitize_plane_mapping(struct drm_i915_private *i915) 175 { 176 struct intel_crtc *crtc; 177 178 if (DISPLAY_VER(i915) >= 4) 179 return; 180 181 for_each_intel_crtc(&i915->drm, crtc) { 182 struct intel_plane *plane = 183 to_intel_plane(crtc->base.primary); 184 struct intel_crtc *plane_crtc; 185 enum pipe pipe; 186 187 if (!plane->get_hw_state(plane, &pipe)) 188 continue; 189 190 if (pipe == crtc->pipe) 191 continue; 192 193 drm_dbg_kms(&i915->drm, 194 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", 195 plane->base.base.id, plane->base.name); 196 197 plane_crtc = intel_crtc_for_pipe(i915, pipe); 198 intel_plane_disable_noatomic(plane_crtc, plane); 199 } 200 } 201 202 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) 203 { 204 struct drm_device *dev = crtc->base.dev; 205 struct intel_encoder *encoder; 206 207 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 208 return true; 209 210 return false; 211 } 212 213 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) 214 { 215 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 216 struct drm_connector_list_iter conn_iter; 217 struct intel_connector *connector; 218 struct intel_connector *found_connector = NULL; 219 220 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 221 for_each_intel_connector_iter(connector, &conn_iter) { 222 if (&encoder->base == connector->base.encoder) { 223 found_connector = connector; 224 break; 225 } 226 } 227 drm_connector_list_iter_end(&conn_iter); 228 229 return found_connector; 230 } 231 232 static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state) 233 { 234 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 235 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 236 237 if (!crtc_state->hw.active && !HAS_GMCH(i915)) 238 return; 239 240 /* 241 * We start out with underrun reporting disabled to avoid races. 242 * For correct bookkeeping mark this on active crtcs. 243 * 244 * Also on gmch platforms we dont have any hardware bits to 245 * disable the underrun reporting. Which means we need to start 246 * out with underrun reporting disabled also on inactive pipes, 247 * since otherwise we'll complain about the garbage we read when 248 * e.g. coming up after runtime pm. 249 * 250 * No protection against concurrent access is required - at 251 * worst a fifo underrun happens which also sets this to false. 252 */ 253 crtc->cpu_fifo_underrun_disabled = true; 254 255 /* 256 * We track the PCH trancoder underrun reporting state 257 * within the crtc. With crtc for pipe A housing the underrun 258 * reporting state for PCH transcoder A, crtc for pipe B housing 259 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, 260 * and marking underrun reporting as disabled for the non-existing 261 * PCH transcoders B and C would prevent enabling the south 262 * error interrupt (see cpt_can_enable_serr_int()). 263 */ 264 if (intel_has_pch_trancoder(i915, crtc->pipe)) 265 crtc->pch_fifo_underrun_disabled = true; 266 } 267 268 static void intel_sanitize_crtc(struct intel_crtc *crtc, 269 struct drm_modeset_acquire_ctx *ctx) 270 { 271 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 272 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 273 274 if (crtc_state->hw.active) { 275 struct intel_plane *plane; 276 277 /* Disable everything but the primary plane */ 278 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 279 const struct intel_plane_state *plane_state = 280 to_intel_plane_state(plane->base.state); 281 282 if (plane_state->uapi.visible && 283 plane->base.type != DRM_PLANE_TYPE_PRIMARY) 284 intel_plane_disable_noatomic(crtc, plane); 285 } 286 287 /* Disable any background color/etc. set by the BIOS */ 288 intel_color_commit_noarm(crtc_state); 289 intel_color_commit_arm(crtc_state); 290 } 291 292 /* 293 * Adjust the state of the output pipe according to whether we have 294 * active connectors/encoders. 295 */ 296 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) && 297 !intel_crtc_is_bigjoiner_slave(crtc_state)) 298 intel_crtc_disable_noatomic(crtc, ctx); 299 } 300 301 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) 302 { 303 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 304 305 /* 306 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram 307 * the hardware when a high res displays plugged in. DPLL P 308 * divider is zero, and the pipe timings are bonkers. We'll 309 * try to disable everything in that case. 310 * 311 * FIXME would be nice to be able to sanitize this state 312 * without several WARNs, but for now let's take the easy 313 * road. 314 */ 315 return IS_SANDYBRIDGE(i915) && 316 crtc_state->hw.active && 317 crtc_state->shared_dpll && 318 crtc_state->port_clock == 0; 319 } 320 321 static void intel_sanitize_encoder(struct intel_encoder *encoder) 322 { 323 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 324 struct intel_connector *connector; 325 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 326 struct intel_crtc_state *crtc_state = crtc ? 327 to_intel_crtc_state(crtc->base.state) : NULL; 328 329 /* 330 * We need to check both for a crtc link (meaning that the encoder is 331 * active and trying to read from a pipe) and the pipe itself being 332 * active. 333 */ 334 bool has_active_crtc = crtc_state && 335 crtc_state->hw.active; 336 337 if (crtc_state && has_bogus_dpll_config(crtc_state)) { 338 drm_dbg_kms(&i915->drm, 339 "BIOS has misprogrammed the hardware. Disabling pipe %c\n", 340 pipe_name(crtc->pipe)); 341 has_active_crtc = false; 342 } 343 344 connector = intel_encoder_find_connector(encoder); 345 if (connector && !has_active_crtc) { 346 drm_dbg_kms(&i915->drm, 347 "[ENCODER:%d:%s] has active connectors but no active pipe!\n", 348 encoder->base.base.id, 349 encoder->base.name); 350 351 /* 352 * Connector is active, but has no active pipe. This is fallout 353 * from our resume register restoring. Disable the encoder 354 * manually again. 355 */ 356 if (crtc_state) { 357 struct drm_encoder *best_encoder; 358 359 drm_dbg_kms(&i915->drm, 360 "[ENCODER:%d:%s] manually disabled\n", 361 encoder->base.base.id, 362 encoder->base.name); 363 364 /* avoid oopsing in case the hooks consult best_encoder */ 365 best_encoder = connector->base.state->best_encoder; 366 connector->base.state->best_encoder = &encoder->base; 367 368 /* FIXME NULL atomic state passed! */ 369 if (encoder->disable) 370 encoder->disable(NULL, encoder, crtc_state, 371 connector->base.state); 372 if (encoder->post_disable) 373 encoder->post_disable(NULL, encoder, crtc_state, 374 connector->base.state); 375 376 connector->base.state->best_encoder = best_encoder; 377 } 378 encoder->base.crtc = NULL; 379 380 /* 381 * Inconsistent output/port/pipe state happens presumably due to 382 * a bug in one of the get_hw_state functions. Or someplace else 383 * in our code, like the register restore mess on resume. Clamp 384 * things to off as a safer default. 385 */ 386 connector->base.dpms = DRM_MODE_DPMS_OFF; 387 connector->base.encoder = NULL; 388 } 389 390 /* notify opregion of the sanitized encoder state */ 391 intel_opregion_notify_encoder(encoder, connector && has_active_crtc); 392 393 if (HAS_DDI(i915)) 394 intel_ddi_sanitize_encoder_pll_mapping(encoder); 395 } 396 397 /* FIXME read out full plane state for all planes */ 398 static void readout_plane_state(struct drm_i915_private *i915) 399 { 400 struct intel_plane *plane; 401 struct intel_crtc *crtc; 402 403 for_each_intel_plane(&i915->drm, plane) { 404 struct intel_plane_state *plane_state = 405 to_intel_plane_state(plane->base.state); 406 struct intel_crtc_state *crtc_state; 407 enum pipe pipe = PIPE_A; 408 bool visible; 409 410 visible = plane->get_hw_state(plane, &pipe); 411 412 crtc = intel_crtc_for_pipe(i915, pipe); 413 crtc_state = to_intel_crtc_state(crtc->base.state); 414 415 intel_set_plane_visible(crtc_state, plane_state, visible); 416 417 drm_dbg_kms(&i915->drm, 418 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", 419 plane->base.base.id, plane->base.name, 420 str_enabled_disabled(visible), pipe_name(pipe)); 421 } 422 423 for_each_intel_crtc(&i915->drm, crtc) { 424 struct intel_crtc_state *crtc_state = 425 to_intel_crtc_state(crtc->base.state); 426 427 intel_plane_fixup_bitmasks(crtc_state); 428 } 429 } 430 431 static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) 432 { 433 struct intel_cdclk_state *cdclk_state = 434 to_intel_cdclk_state(i915->display.cdclk.obj.state); 435 struct intel_dbuf_state *dbuf_state = 436 to_intel_dbuf_state(i915->display.dbuf.obj.state); 437 enum pipe pipe; 438 struct intel_crtc *crtc; 439 struct intel_encoder *encoder; 440 struct intel_connector *connector; 441 struct drm_connector_list_iter conn_iter; 442 u8 active_pipes = 0; 443 444 for_each_intel_crtc(&i915->drm, crtc) { 445 struct intel_crtc_state *crtc_state = 446 to_intel_crtc_state(crtc->base.state); 447 448 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 449 intel_crtc_free_hw_state(crtc_state); 450 intel_crtc_state_reset(crtc_state, crtc); 451 452 intel_crtc_get_pipe_config(crtc_state); 453 454 crtc_state->hw.enable = crtc_state->hw.active; 455 456 crtc->base.enabled = crtc_state->hw.enable; 457 crtc->active = crtc_state->hw.active; 458 459 if (crtc_state->hw.active) 460 active_pipes |= BIT(crtc->pipe); 461 462 drm_dbg_kms(&i915->drm, 463 "[CRTC:%d:%s] hw state readout: %s\n", 464 crtc->base.base.id, crtc->base.name, 465 str_enabled_disabled(crtc_state->hw.active)); 466 } 467 468 cdclk_state->active_pipes = active_pipes; 469 dbuf_state->active_pipes = active_pipes; 470 471 readout_plane_state(i915); 472 473 for_each_intel_encoder(&i915->drm, encoder) { 474 struct intel_crtc_state *crtc_state = NULL; 475 476 pipe = 0; 477 478 if (encoder->get_hw_state(encoder, &pipe)) { 479 crtc = intel_crtc_for_pipe(i915, pipe); 480 crtc_state = to_intel_crtc_state(crtc->base.state); 481 482 encoder->base.crtc = &crtc->base; 483 intel_encoder_get_config(encoder, crtc_state); 484 485 /* read out to slave crtc as well for bigjoiner */ 486 if (crtc_state->bigjoiner_pipes) { 487 struct intel_crtc *slave_crtc; 488 489 /* encoder should read be linked to bigjoiner master */ 490 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 491 492 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 493 intel_crtc_bigjoiner_slave_pipes(crtc_state)) { 494 struct intel_crtc_state *slave_crtc_state; 495 496 slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state); 497 intel_encoder_get_config(encoder, slave_crtc_state); 498 } 499 } 500 } else { 501 encoder->base.crtc = NULL; 502 } 503 504 if (encoder->sync_state) 505 encoder->sync_state(encoder, crtc_state); 506 507 drm_dbg_kms(&i915->drm, 508 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", 509 encoder->base.base.id, encoder->base.name, 510 str_enabled_disabled(encoder->base.crtc), 511 pipe_name(pipe)); 512 } 513 514 intel_dpll_readout_hw_state(i915); 515 516 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 517 for_each_intel_connector_iter(connector, &conn_iter) { 518 if (connector->get_hw_state(connector)) { 519 struct intel_crtc_state *crtc_state; 520 struct intel_crtc *crtc; 521 522 connector->base.dpms = DRM_MODE_DPMS_ON; 523 524 encoder = intel_attached_encoder(connector); 525 connector->base.encoder = &encoder->base; 526 527 crtc = to_intel_crtc(encoder->base.crtc); 528 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; 529 530 if (crtc_state && crtc_state->hw.active) { 531 /* 532 * This has to be done during hardware readout 533 * because anything calling .crtc_disable may 534 * rely on the connector_mask being accurate. 535 */ 536 crtc_state->uapi.connector_mask |= 537 drm_connector_mask(&connector->base); 538 crtc_state->uapi.encoder_mask |= 539 drm_encoder_mask(&encoder->base); 540 } 541 } else { 542 connector->base.dpms = DRM_MODE_DPMS_OFF; 543 connector->base.encoder = NULL; 544 } 545 drm_dbg_kms(&i915->drm, 546 "[CONNECTOR:%d:%s] hw state readout: %s\n", 547 connector->base.base.id, connector->base.name, 548 str_enabled_disabled(connector->base.encoder)); 549 } 550 drm_connector_list_iter_end(&conn_iter); 551 552 for_each_intel_crtc(&i915->drm, crtc) { 553 struct intel_bw_state *bw_state = 554 to_intel_bw_state(i915->display.bw.obj.state); 555 struct intel_crtc_state *crtc_state = 556 to_intel_crtc_state(crtc->base.state); 557 struct intel_plane *plane; 558 int min_cdclk = 0; 559 560 if (crtc_state->hw.active) { 561 /* 562 * The initial mode needs to be set in order to keep 563 * the atomic core happy. It wants a valid mode if the 564 * crtc's enabled, so we do the above call. 565 * 566 * But we don't set all the derived state fully, hence 567 * set a flag to indicate that a full recalculation is 568 * needed on the next commit. 569 */ 570 crtc_state->inherited = true; 571 572 intel_crtc_update_active_timings(crtc_state); 573 574 intel_crtc_copy_hw_to_uapi_state(crtc_state); 575 } 576 577 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 578 const struct intel_plane_state *plane_state = 579 to_intel_plane_state(plane->base.state); 580 581 /* 582 * FIXME don't have the fb yet, so can't 583 * use intel_plane_data_rate() :( 584 */ 585 if (plane_state->uapi.visible) 586 crtc_state->data_rate[plane->id] = 587 4 * crtc_state->pixel_rate; 588 /* 589 * FIXME don't have the fb yet, so can't 590 * use plane->min_cdclk() :( 591 */ 592 if (plane_state->uapi.visible && plane->min_cdclk) { 593 if (crtc_state->double_wide || DISPLAY_VER(i915) >= 10) 594 crtc_state->min_cdclk[plane->id] = 595 DIV_ROUND_UP(crtc_state->pixel_rate, 2); 596 else 597 crtc_state->min_cdclk[plane->id] = 598 crtc_state->pixel_rate; 599 } 600 drm_dbg_kms(&i915->drm, 601 "[PLANE:%d:%s] min_cdclk %d kHz\n", 602 plane->base.base.id, plane->base.name, 603 crtc_state->min_cdclk[plane->id]); 604 } 605 606 if (crtc_state->hw.active) { 607 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 608 if (drm_WARN_ON(&i915->drm, min_cdclk < 0)) 609 min_cdclk = 0; 610 } 611 612 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 613 cdclk_state->min_voltage_level[crtc->pipe] = 614 crtc_state->min_voltage_level; 615 616 intel_bw_crtc_update(bw_state, crtc_state); 617 } 618 } 619 620 static void 621 get_encoder_power_domains(struct drm_i915_private *i915) 622 { 623 struct intel_encoder *encoder; 624 625 for_each_intel_encoder(&i915->drm, encoder) { 626 struct intel_crtc_state *crtc_state; 627 628 if (!encoder->get_power_domains) 629 continue; 630 631 /* 632 * MST-primary and inactive encoders don't have a crtc state 633 * and neither of these require any power domain references. 634 */ 635 if (!encoder->base.crtc) 636 continue; 637 638 crtc_state = to_intel_crtc_state(encoder->base.crtc->state); 639 encoder->get_power_domains(encoder, crtc_state); 640 } 641 } 642 643 static void intel_early_display_was(struct drm_i915_private *i915) 644 { 645 /* 646 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl 647 * Also known as Wa_14010480278. 648 */ 649 if (IS_DISPLAY_VER(i915, 10, 12)) 650 intel_de_write(i915, GEN9_CLKGATE_DIS_0, 651 intel_de_read(i915, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS); 652 653 if (IS_HASWELL(i915)) { 654 /* 655 * WaRsPkgCStateDisplayPMReq:hsw 656 * System hang if this isn't done before disabling all planes! 657 */ 658 intel_de_write(i915, CHICKEN_PAR1_1, 659 intel_de_read(i915, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 660 } 661 662 if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) { 663 /* Display WA #1142:kbl,cfl,cml */ 664 intel_de_rmw(i915, CHICKEN_PAR1_1, 665 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22); 666 intel_de_rmw(i915, CHICKEN_MISC_2, 667 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14, 668 KBL_ARB_FILL_SPARE_14); 669 } 670 } 671 672 void intel_modeset_setup_hw_state(struct drm_i915_private *i915, 673 struct drm_modeset_acquire_ctx *ctx) 674 { 675 struct intel_encoder *encoder; 676 struct intel_crtc *crtc; 677 intel_wakeref_t wakeref; 678 679 wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); 680 681 intel_early_display_was(i915); 682 intel_modeset_readout_hw_state(i915); 683 684 /* HW state is read out, now we need to sanitize this mess. */ 685 get_encoder_power_domains(i915); 686 687 intel_pch_sanitize(i915); 688 689 /* 690 * intel_sanitize_plane_mapping() may need to do vblank 691 * waits, so we need vblank interrupts restored beforehand. 692 */ 693 for_each_intel_crtc(&i915->drm, crtc) { 694 struct intel_crtc_state *crtc_state = 695 to_intel_crtc_state(crtc->base.state); 696 697 intel_sanitize_fifo_underrun_reporting(crtc_state); 698 699 drm_crtc_vblank_reset(&crtc->base); 700 701 if (crtc_state->hw.active) { 702 intel_dmc_enable_pipe(i915, crtc->pipe); 703 intel_crtc_vblank_on(crtc_state); 704 } 705 } 706 707 intel_fbc_sanitize(i915); 708 709 intel_sanitize_plane_mapping(i915); 710 711 for_each_intel_encoder(&i915->drm, encoder) 712 intel_sanitize_encoder(encoder); 713 714 for_each_intel_crtc(&i915->drm, crtc) { 715 struct intel_crtc_state *crtc_state = 716 to_intel_crtc_state(crtc->base.state); 717 718 intel_sanitize_crtc(crtc, ctx); 719 intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state"); 720 } 721 722 intel_modeset_update_connector_atomic_state(i915); 723 724 intel_dpll_sanitize_state(i915); 725 726 if (IS_G4X(i915)) { 727 g4x_wm_get_hw_state(i915); 728 g4x_wm_sanitize(i915); 729 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 730 vlv_wm_get_hw_state(i915); 731 vlv_wm_sanitize(i915); 732 } else if (DISPLAY_VER(i915) >= 9) { 733 skl_wm_get_hw_state(i915); 734 skl_wm_sanitize(i915); 735 } else if (HAS_PCH_SPLIT(i915)) { 736 ilk_wm_get_hw_state(i915); 737 } 738 739 for_each_intel_crtc(&i915->drm, crtc) { 740 struct intel_crtc_state *crtc_state = 741 to_intel_crtc_state(crtc->base.state); 742 struct intel_power_domain_mask put_domains; 743 744 intel_modeset_get_crtc_power_domains(crtc_state, &put_domains); 745 if (drm_WARN_ON(&i915->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM))) 746 intel_modeset_put_crtc_power_domains(crtc, &put_domains); 747 } 748 749 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 750 751 intel_power_domains_sanitize_state(i915); 752 } 753